[llvm-branch-commits] [clang] [HLSL] Add RWBuffer::Load(Index) (PR #117018)

@@ -189,12 +189,28 @@ struct BuiltinTypeDeclBuilder { BuiltinTypeDeclBuilder &addArraySubscriptOperators(Sema &S) { if (Record->isCompleteDefinition()) return *this; -addArraySubscriptOperator(S, true); -addArraySubscriptOperator(S, false); +ASTContext &

[llvm-branch-commits] [clang] [llvm] [RISCV] Support __builtin_cpu_is (PR #116231)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/116231 >From 9686a2c5c5276289e72d9098f497a9f246a1c457 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Thu, 14 Nov 2024 22:06:45 +0800 Subject: [PATCH 1/4] Remove stale CHECKs Created using spr 1.3.6-beta.1 ---

[llvm-branch-commits] [clang] [llvm] [RISCV] Support __builtin_cpu_is (PR #116231)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/116231 >From 9686a2c5c5276289e72d9098f497a9f246a1c457 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Thu, 14 Nov 2024 22:06:45 +0800 Subject: [PATCH 1/4] Remove stale CHECKs Created using spr 1.3.6-beta.1 ---

[llvm-branch-commits] [clang] [llvm] [RISCV] Support __builtin_cpu_is (PR #116231)

https://github.com/lenary approved this pull request. https://github.com/llvm/llvm-project/pull/116231 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [CodeGen][NewPM] Port SpillPlacement analysis to NPM (PR #116618)

https://github.com/optimisan updated https://github.com/llvm/llvm-project/pull/116618 >From d56857683955832290505f6cfed6fd27a07d7a94 Mon Sep 17 00:00:00 2001 From: Akshat Oke Date: Mon, 18 Nov 2024 12:42:00 + Subject: [PATCH 1/4] [CodeGen][NewPM] Port SpillPlacement analysis to NPM --- ll

[llvm-branch-commits] [llvm] [NFC] Use unique_ptr in SparseSet (PR #116617)

https://github.com/optimisan updated https://github.com/llvm/llvm-project/pull/116617 >From 69c604aacd3a71b3559dbc96721eef2ef06200f7 Mon Sep 17 00:00:00 2001 From: Akshat Oke Date: Mon, 18 Nov 2024 10:15:19 + Subject: [PATCH 1/2] [NFC] Use unique_ptr in SparseSet This allows implementing t

[llvm-branch-commits] [llvm] [NFC] Use unique_ptr in SparseSet (PR #116617)

optimisan wrote: ### Merge activity * **Nov 22, 6:17 AM EST**: A user started a stack merge that includes this pull request via [Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/116617). https://github.com/llvm/llvm-project/pull/116617 __

[llvm-branch-commits] [flang] [flang] handle fir.call in AliasAnalysis::getModRef (PR #117164)

@@ -329,14 +341,92 @@ AliasResult AliasAnalysis::alias(Source lhsSrc, Source rhsSrc, mlir::Value lhs, // AliasAnalysis: getModRef //===--===// +static bool isSavedLocal(const fir::AliasAnalysis::Source &src)

[llvm-branch-commits] [flang] [MLIR][OpenMP] Add Lowering support for OpenMP Declare Mapper directive (PR #117046)

https://github.com/TIFitis edited https://github.com/llvm/llvm-project/pull/117046 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [flang] [MLIR][OpenMP] Add Lowering support for OpenMP Declare Mapper directive (PR #117046)

@@ -2701,7 +2702,39 @@ static void genOMP(lower::AbstractConverter &converter, lower::SymMap &symTable, semantics::SemanticsContext &semaCtx, lower::pft::Evaluation &eval, const parser::OpenMPDeclareMapperConstruct &declareMapperConstruct) { - TODO(converter.getC

[llvm-branch-commits] [lldb] 4348c4d - Revert "[lldb] Fix DW_OP_piece-O3 test on AArch64 Windows (#117336)"

Author: Ilia Kuklin Date: 2024-11-22T22:45:42+05:00 New Revision: 4348c4d658a56f45e939190aa1b2b6c698893999 URL: https://github.com/llvm/llvm-project/commit/4348c4d658a56f45e939190aa1b2b6c698893999 DIFF: https://github.com/llvm/llvm-project/commit/4348c4d658a56f45e939190aa1b2b6c698893999.diff L

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scalef32_pk_{fp8|bf8}_f32 of gfx950. (PR #117382)

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/117382 OPSEL[3] selects low/high 16 bits of dest write. Co-authored-by: Pravin Jagtap >From 006e95f01c5de40a1a328c0d74642b8eced70414 Mon Sep 17 00:00:00 2001 From: Pravin Jagtap Date: Sat, 6 Apr 2024 09:17:03 -0400 S

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scalef32_pk_{fp|bf}8_{f|bf}16 of gfx950. (PR #117384)

https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/117384 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Add MC support for gfx950 V_BITOP3_B32/B16 (PR #117379)

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/117379 Co-authored-by: Pravin Jagtap >From 26772728d84c8cd247defa8a73448369ead9032a Mon Sep 17 00:00:00 2001 From: Pravin Jagtap Date: Fri, 26 Jan 2024 01:40:32 -0500 Subject: [PATCH] AMDGPU: Add MC support for gfx950

[llvm-branch-commits] [clang] [llvm] AMDGPU: Add support for load transpose instructions for gfx950 (PR #117378)

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/117378 This patch support for intrinsics in clang, as well as assembly instructions in the backend. Co-authored-by: Sirish Pande >From 5806ee7ef05a77aee37bb93de6eeb223dd0186fa Mon Sep 17 00:00:00 2001 From: Sirish Pan

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scale_[f16|f32]_fp8 of gfx950. (PR #117380)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117380 >From d34c2cc46c6adc0e9ce80ce92f69e755e66774ed Mon Sep 17 00:00:00 2001 From: Pravin Jagtap Date: Sat, 6 Apr 2024 02:35:49 -0400 Subject: [PATCH] AMDGPU: MC support for v_cvt_scale_[f16|f32]_fp8 of gfx950. OPSEL

[llvm-branch-commits] [llvm] AMDGPU: Add MC support for gfx950 V_BITOP3_B32/B16 (PR #117379)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117379 >From 2bb646ca3045532b382a8c6d0db9b5ffe6bd4d2e Mon Sep 17 00:00:00 2001 From: Pravin Jagtap Date: Fri, 26 Jan 2024 01:40:32 -0500 Subject: [PATCH] AMDGPU: Add MC support for gfx950 V_BITOP3_B32/B16 Co-authored-b

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scale_[f16|f32]_bf8 of gfx950. (PR #117381)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117381 >From cff4def955447d2adaff3caebc323f23320a3e73 Mon Sep 17 00:00:00 2001 From: Pravin Jagtap Date: Sat, 6 Apr 2024 07:19:15 -0400 Subject: [PATCH] AMDGPU: MC support for v_cvt_scale_[f16|f32]_bf8 of gfx950. OPSEL

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scalef32_pk_f32_[fp|bf]8 of gfx950. (PR #117383)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117383 >From a009325974e7d0cffbf288d2dd9b4d3d2e392007 Mon Sep 17 00:00:00 2001 From: Pravin Jagtap Date: Sat, 6 Apr 2024 11:08:22 -0400 Subject: [PATCH] AMDGPU: MC support for v_cvt_scalef32_pk_f32_[fp|bf]8 of gfx950.

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scalef32_pk_{fp8|bf8}_f32 of gfx950. (PR #117382)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117382 >From bad2d8e5dcac64128c8e73d0b9752cb6bfe17620 Mon Sep 17 00:00:00 2001 From: Pravin Jagtap Date: Sat, 6 Apr 2024 09:17:03 -0400 Subject: [PATCH] AMDGPU: MC support for v_cvt_scalef32_pk_{fp8|bf8}_f32 of gfx950.

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scalef32_pk_{fp|bf}8_{f|bf}16 of gfx950. (PR #117384)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117384 >From d5c3e0b8dd48841b1b23bb847919683d9a5d8506 Mon Sep 17 00:00:00 2001 From: Pravin Jagtap Date: Sun, 7 Apr 2024 01:57:15 -0400 Subject: [PATCH] AMDGPU: MC support for v_cvt_scalef32_pk_{fp|bf}8_{f|bf}16 of gfx

[llvm-branch-commits] [clang] [llvm] AMDGPU: Add v_smfmac_f32_32x32x32x64_fp8_bf8 for gfx950 (PR #117258)

https://github.com/shiltian approved this pull request. https://github.com/llvm/llvm-project/pull/117258 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] AMDGPU: Add v_smfmac_f32_32x32x64_fp8_fp8 for gfx950 (PR #117259)

https://github.com/shiltian approved this pull request. https://github.com/llvm/llvm-project/pull/117259 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Define new sched model for gfx950 (PR #117261)

https://github.com/shiltian edited https://github.com/llvm/llvm-project/pull/117261 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Define new sched model for gfx950 (PR #117261)

https://github.com/shiltian approved this pull request. https://github.com/llvm/llvm-project/pull/117261 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [compiler-rt] [TySan] A Type Sanitizer (Runtime Library) (PR #76261)

fhahn wrote: The latest version also includes a new test case `compiler-rt/test/tysan/constexpr-subobject.cpp` which had a false positive (IIUC the code should have no strict aliasing violation) + a fix https://github.com/llvm/llvm-project/pull/76261 ___

[llvm-branch-commits] [clang] [compiler-rt] [TySan] A Type Sanitizer (Runtime Library) (PR #76261)

https://github.com/fhahn updated https://github.com/llvm/llvm-project/pull/76261 >From 8e6e62d0dee48a696afd0c7d53d74eaccef97b5e Mon Sep 17 00:00:00 2001 From: Florian Hahn Date: Fri, 22 Nov 2024 15:01:41 + Subject: [PATCH] [TySan] A Type Sanitizer (Runtime Library) --- clang/runtime/CMakeL

[llvm-branch-commits] [clang] [llvm] AMDGPU: Add v_smfmac_f32_32x32x64_fp8_fp8 for gfx950 (PR #117259)

https://github.com/shiltian edited https://github.com/llvm/llvm-project/pull/117259 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] AMDGPU: Add v_smfmac_f32_32x32x32x64_fp8_bf8 for gfx950 (PR #117258)

https://github.com/shiltian edited https://github.com/llvm/llvm-project/pull/117258 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] AMDGPU: Add v_permlane16_swap_b32 and v_permlane32_swap_b32 for gfx950 (PR #117260)

@@ -1319,6 +1321,10 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo, /// \returns true if the target has instructions with xf32 format support. bool hasXF32Insts() const { return HasXF32Insts; } + bool hasPrngInst() const { return HasPrngInst; } --

[llvm-branch-commits] [clang] [llvm] AMDGPU: Add v_smfmac_f32_32x32x32x64_fp8_bf8 for gfx950 (PR #117258)

arsenm wrote: ### Merge activity * **Nov 22, 2:45 PM EST**: A user started a stack merge that includes this pull request via [Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/117258). https://github.com/llvm/llvm-project/pull/117258 _

[llvm-branch-commits] [clang] [llvm] AMDGPU: Add v_smfmac_f32_32x32x64_fp8_fp8 for gfx950 (PR #117259)

arsenm wrote: ### Merge activity * **Nov 22, 2:45 PM EST**: A user started a stack merge that includes this pull request via [Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/117259). https://github.com/llvm/llvm-project/pull/117259 _

[llvm-branch-commits] [clang] [llvm] AMDGPU: Add v_smfmac_f32_32x32x64_bf8_fp8 for gfx950 (PR #117257)

arsenm wrote: ### Merge activity * **Nov 22, 2:45 PM EST**: A user started a stack merge that includes this pull request via [Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/117257). https://github.com/llvm/llvm-project/pull/117257 _

[llvm-branch-commits] [llvm] AMDGPU: Handle gfx950 change in mfma_f64_16x16x4 + valu hazard (PR #117262)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117262 >From 0f57e4c8e3a049c2d887cbc017d1c76dc9c3b155 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Thu, 7 Mar 2024 15:01:08 +0530 Subject: [PATCH] AMDGPU: Handle gfx950 change in mfma_f64_16x16x4 + valu hazard

[llvm-branch-commits] [llvm] AMDGPU: Handle v_mfma_f64_16x16x4_f64 write VGPR read srca/srcb hazard change for gfx950 (PR #117284)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117284 >From 26c86acea9e387b14e081f11ebb09bea004ee694 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Thu, 7 Mar 2024 15:18:59 +0530 Subject: [PATCH] AMDGPU: Handle v_mfma_f64_16x16x4_f64 write VGPR read srca/srcb

[llvm-branch-commits] [llvm] AMDGPU: Handle v_mfma_f64_16x16x4_f64 srcc write VGPR hazard change for gfx950 (PR #117283)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117283 >From ac9fc9da1521e412d31b5ed9acdc3932573d6c7c Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Thu, 7 Mar 2024 14:54:41 +0530 Subject: [PATCH] AMDGPU: Handle v_mfma_f64_16x16x4_f64 srcc write VGPR hazard cha

[llvm-branch-commits] [llvm] AMDGPU: Handle vcmpx+permalane gfx950 hazard (PR #117286)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117286 >From 7c92bcc28e7327c0637caa0d744d1e4d20eace02 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Mon, 18 Mar 2024 13:45:22 +0530 Subject: [PATCH] AMDGPU: Handle vcmpx+permalane gfx950 hazard Confusingly, this

[llvm-branch-commits] [llvm] AMDGPU: Refine gfx950 xdl-write-vgpr hazard cases (PR #117285)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117285 >From ccc271528980d20517142d65373be6db85d0447b Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Tue, 12 Mar 2024 13:29:05 +0530 Subject: [PATCH] AMDGPU: Refine gfx950 xdl-write-vgpr hazard cases The 2-pass XD

[llvm-branch-commits] [llvm] AMDGPU: Handle gfx950 valu write vdst + permlane read hazard (PR #117287)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117287 >From 73457dc7df855747568559c9b9c626f6efef01d1 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Mon, 18 Mar 2024 14:41:11 +0530 Subject: [PATCH] AMDGPU: Handle gfx950 valu write vdst + permlane read hazard --

[llvm-branch-commits] [clang] [TySan] A Type Sanitizer (Clang) (PR #76260)

https://github.com/fhahn updated https://github.com/llvm/llvm-project/pull/76260 >From ab8d005600b99fb62d991bc63c58136576429385 Mon Sep 17 00:00:00 2001 From: Florian Hahn Date: Thu, 18 Apr 2024 23:01:03 +0100 Subject: [PATCH 1/3] [TySan] A Type Sanitizer (Clang) --- clang/include/clang/Basic/

[llvm-branch-commits] [clang] [TySan] A Type Sanitizer (Clang) (PR #76260)

fhahn wrote: > The clang changes are ok, but this needs some level of documentation/release > notes, which I don't see in the clang release. As this is a part of a larger > feature, do we intend to push that later? > > Also, the clang-format suggestion makes sense. Sorry for the long delay! A

[llvm-branch-commits] [llvm] AMDGPU: Handle gfx950 XDL-write-overlapped-smfma-src-c wait state change (PR #117263)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117263 >From c5db8175e880bac604241e150d2990207cef15ef Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 6 Mar 2024 19:51:00 +0530 Subject: [PATCH] AMDGPU: Handle gfx950 XDL-write-overlapped-smfma-src-c wait stat

[llvm-branch-commits] [llvm] AMDGPU: Handle v_mfma_f64_16x16x4_f64 srcc write VGPR hazard change for gfx950 (PR #117283)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117283 >From 9527ef641bf57c88f497785c20ebc24edc472567 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Thu, 7 Mar 2024 14:54:41 +0530 Subject: [PATCH] AMDGPU: Handle v_mfma_f64_16x16x4_f64 srcc write VGPR hazard cha

[llvm-branch-commits] [llvm] AMDGPU: Handle gfx950 valu write vdst + permlane read hazard (PR #117287)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117287 >From b4858a252d18dd63aa3b88c2685b41fa9a604b0c Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Mon, 18 Mar 2024 14:41:11 +0530 Subject: [PATCH] AMDGPU: Handle gfx950 valu write vdst + permlane read hazard --

[llvm-branch-commits] [llvm] AMDGPU: Handle v_mfma_f64_16x16x4_f64 write VGPR read srca/srcb hazard change for gfx950 (PR #117284)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117284 >From 1a4e01fad64f26e3213fda69d14ae6ae606c625b Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Thu, 7 Mar 2024 15:18:59 +0530 Subject: [PATCH] AMDGPU: Handle v_mfma_f64_16x16x4_f64 write VGPR read srca/srcb

[llvm-branch-commits] [llvm] AMDGPU: Handle vcmpx+permalane gfx950 hazard (PR #117286)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117286 >From 05500a03da62e1f7ed41b16e2f036b68ef8d8cc4 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Mon, 18 Mar 2024 13:45:22 +0530 Subject: [PATCH] AMDGPU: Handle vcmpx+permalane gfx950 hazard Confusingly, this

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scale_[f16|f32]_fp8 of gfx950. (PR #117380)

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/117380 OPSEL ASM Syntax: opsel:[x,y,z] where, opsel[x] = Inst{11} = src0_modifier{2} opsel[y] = Inst{12} = src1_modifier{2} opsel[z] = Inst{14} = src0_modifier{3} Note: Conventional Inst{13} i.e. OPSEL[2] is

[llvm-branch-commits] [llvm] AMDGPU: Add MC support for gfx950 V_BITOP3_B32/B16 (PR #117379)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/117379?utm_source=stack-comment-downstack-mergeability-warning";

[llvm-branch-commits] [llvm] AMDGPU: Refine gfx950 xdl-write-vgpr hazard cases (PR #117285)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117285 >From 608d98d7fc7c703d3bf7df5246393e1624d8662c Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Tue, 12 Mar 2024 13:29:05 +0530 Subject: [PATCH] AMDGPU: Refine gfx950 xdl-write-vgpr hazard cases The 2-pass XD

[llvm-branch-commits] [clang] [llvm] AMDGPU: Add support for load transpose instructions for gfx950 (PR #117378)

https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/117378 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] AMDGPU: Add support for load transpose instructions for gfx950 (PR #117378)

llvmbot wrote: @llvm/pr-subscribers-backend-amdgpu Author: Matt Arsenault (arsenm) Changes This patch support for intrinsics in clang, as well as assembly instructions in the backend. Co-authored-by: Sirish Pande --- Patch is 28.39 KiB, truncated to 20.00 KiB belo

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scale_[f16|f32]_fp8 of gfx950. (PR #117380)

llvmbot wrote: @llvm/pr-subscribers-backend-amdgpu Author: Matt Arsenault (arsenm) Changes OPSEL ASM Syntax: opsel:[x,y,z] where, opsel[x] = Inst{11} = src0_modifier{2} opsel[y] = Inst{12} = src1_modifier{2} opsel[z] = Inst{14} = src0_modifier{3} Note: Conventional Inst{13} i.e

[llvm-branch-commits] [clang] [llvm] AMDGPU: Add support for load transpose instructions for gfx950 (PR #117378)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/117378?utm_source=stack-comment-downstack-mergeability-warning";

[llvm-branch-commits] [llvm] AMDGPU: Add MC support for gfx950 V_BITOP3_B32/B16 (PR #117379)

https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/117379 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scale_[f16|f32]_fp8 of gfx950. (PR #117380)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/117380?utm_source=stack-comment-downstack-mergeability-warning";

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scale_[f16|f32]_bf8 of gfx950. (PR #117381)

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/117381 OPSEL ASM Syntax: opsel:[x,y,z] where, opsel[x] = Inst{11} = src0_modifier{2} opsel[y] = Inst{12} = src1_modifier{2} opsel[z] = Inst{14} = src0_modifier{3} Note: Conventional Inst{13} i.e. OPSEL[2] is

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scalef32_pk_{fp|bf}8_{f|bf}16 of gfx950. (PR #117384)

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/117384 OPSEL ASM Syntax: opsel:[x,y,z] where, opsel[z] = Inst{14} = src0_modifier{3} Note: Conventional Inst{13} i.e. OPSEL[2] is ignored in asm syntax. Co-authored-by: Pravin Jagtap >From 7f0c00c5714c8051de48b15

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scalef32_pk_f32_[fp|bf]8 of gfx950. (PR #117383)

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/117383 OPSEL[0] selects srcword to read. Co-authored-by: Pravin Jagtap >From a4c577bce86a5c827fb5e4c215e28189b8c8722e Mon Sep 17 00:00:00 2001 From: Pravin Jagtap Date: Sat, 6 Apr 2024 11:08:22 -0400 Subject: [PATCH]

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scale_[f16|f32]_bf8 of gfx950. (PR #117381)

https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/117381 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scalef32_pk_{fp|bf}8_{f|bf}16 of gfx950. (PR #117384)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/117384?utm_source=stack-comment-downstack-mergeability-warning";

[llvm-branch-commits] [llvm] AMDGPU: Add MC support for gfx950 V_BITOP3_B32/B16 (PR #117379)

github-actions[bot] wrote: :warning: C/C++ code formatter, clang-format found issues in your code. :warning: You can test this locally with the following command: ``bash git-clang-format --diff 5806ee7ef05a77aee37bb93de6eeb223dd0186fa 26772728d84c8cd247defa8a73448369ead9032a --e

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scalef32_pk_{fp8|bf8}_f32 of gfx950. (PR #117382)

https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/117382 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scalef32_pk_f32_[fp|bf]8 of gfx950. (PR #117383)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/117383?utm_source=stack-comment-downstack-mergeability-warning";

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scale_[f16|f32]_bf8 of gfx950. (PR #117381)

llvmbot wrote: @llvm/pr-subscribers-backend-amdgpu Author: Matt Arsenault (arsenm) Changes OPSEL ASM Syntax: opsel:[x,y,z] where, opsel[x] = Inst{11} = src0_modifier{2} opsel[y] = Inst{12} = src1_modifier{2} opsel[z] = Inst{14} = src0_modifier{3} Note: Conventional Inst{13} i.e

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scale_[f16|f32]_bf8 of gfx950. (PR #117381)

llvmbot wrote: @llvm/pr-subscribers-mc Author: Matt Arsenault (arsenm) Changes OPSEL ASM Syntax: opsel:[x,y,z] where, opsel[x] = Inst{11} = src0_modifier{2} opsel[y] = Inst{12} = src1_modifier{2} opsel[z] = Inst{14} = src0_modifier{3} Note: Conventional Inst{13} i.e. OPSEL[2] i

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scalef32_pk_{fp8|bf8}_f32 of gfx950. (PR #117382)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/117382?utm_source=stack-comment-downstack-mergeability-warning";

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scalef32_pk_{fp|bf}8_{f|bf}16 of gfx950. (PR #117384)

llvmbot wrote: @llvm/pr-subscribers-mc Author: Matt Arsenault (arsenm) Changes OPSEL ASM Syntax: opsel:[x,y,z] where, opsel[z] = Inst{14} = src0_modifier{3} Note: Conventional Inst{13} i.e. OPSEL[2] is ignored in asm syntax. Co-authored-by: Pravin Jagtap ---

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scalef32_pk_f32_[fp|bf]8 of gfx950. (PR #117383)

https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/117383 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scale_[f16|f32]_bf8 of gfx950. (PR #117381)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/117381?utm_source=stack-comment-downstack-mergeability-warning";

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scalef32_pk_{fp8|bf8}_f32 of gfx950. (PR #117382)

llvmbot wrote: @llvm/pr-subscribers-backend-amdgpu Author: Matt Arsenault (arsenm) Changes OPSEL[3] selects low/high 16 bits of dest write. Co-authored-by: Pravin Jagtap --- Full diff: https://github.com/llvm/llvm-project/pull/117382.diff 3 Files Affected: - (m

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scalef32_pk_f32_[fp|bf]8 of gfx950. (PR #117383)

llvmbot wrote: @llvm/pr-subscribers-backend-amdgpu Author: Matt Arsenault (arsenm) Changes OPSEL[0] selects srcword to read. Co-authored-by: Pravin Jagtap --- Full diff: https://github.com/llvm/llvm-project/pull/117383.diff 3 Files Affected: - (modified) llvm/l

[llvm-branch-commits] [llvm] AMDGPU: Add MC support for gfx950 V_BITOP3_B32/B16 (PR #117379)

llvmbot wrote: @llvm/pr-subscribers-mc Author: Matt Arsenault (arsenm) Changes Co-authored-by: Pravin Jagtap --- Full diff: https://github.com/llvm/llvm-project/pull/117379.diff 9 Files Affected: - (modified) llvm/lib/Target/AMDGPU/AMDGPU.td (+11-1) - (modified

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scale_[f16|f32]_fp8 of gfx950. (PR #117380)

https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/117380 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Handle gfx950 change in mfma_f64_16x16x4 + valu hazard (PR #117262)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117262 >From a444594bee500951ff23d7745e19abdb22bc1019 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Thu, 7 Mar 2024 15:01:08 +0530 Subject: [PATCH] AMDGPU: Handle gfx950 change in mfma_f64_16x16x4 + valu hazard

[llvm-branch-commits] [compiler-rt] [TySan] Fix struct access with different bases (PR #108385)

fhahn wrote: Thanks for putting up the patch! I just rebased the patches, hopefully we can get them in soon so it is easier to submit bug-fixes iteratively. I noticed that with this patch, I am seeing segfaults when running `llvm-min-tblgen` when built with `-fsanitize=type`, but I wasn't ab

[llvm-branch-commits] [clang] [TySan] A Type Sanitizer (Clang) (PR #76260)

https://github.com/fhahn updated https://github.com/llvm/llvm-project/pull/76260 >From ab8d005600b99fb62d991bc63c58136576429385 Mon Sep 17 00:00:00 2001 From: Florian Hahn Date: Thu, 18 Apr 2024 23:01:03 +0100 Subject: [PATCH 1/2] [TySan] A Type Sanitizer (Clang) --- clang/include/clang/Basic/

[llvm-branch-commits] [llvm] AMDGPU: Handle gfx950 XDL-write-overlapped-smfma-src-c wait state change (PR #117263)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117263 >From 4b8825db29df2e248963f3955729da4ae9d7a9c9 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 6 Mar 2024 19:51:00 +0530 Subject: [PATCH] AMDGPU: Handle gfx950 XDL-write-overlapped-smfma-src-c wait stat

[llvm-branch-commits] [clang] [HLSL] Add RWBuffer::Load(Index) (PR #117018)

@@ -189,12 +189,28 @@ struct BuiltinTypeDeclBuilder { BuiltinTypeDeclBuilder &addArraySubscriptOperators(Sema &S) { if (Record->isCompleteDefinition()) return *this; -addArraySubscriptOperator(S, true); -addArraySubscriptOperator(S, false); +ASTContext &

[llvm-branch-commits] [clang] [HLSL] Add RWBuffer::Load(Index) (PR #117018)

https://github.com/hekota approved this pull request. LGTM! https://github.com/llvm/llvm-project/pull/117018 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [lld] [lld][Hexagon] Fix R_HEX_B22_PCREL range checks (#115925) (PR #116906)

https://github.com/SidManning approved this pull request. https://github.com/llvm/llvm-project/pull/116906 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Use isWave[32|64] instead of comparing size value (PR #117411)

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/117411 None >From 7016169b68c98fbf4e9467483a9c2ca4fe7c6dcc Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Fri, 22 Nov 2024 18:40:25 -0800 Subject: [PATCH] AMDGPU: Use isWave[32|64] instead of comparing size value

[llvm-branch-commits] [llvm] AMDGPU: Use isWave[32|64] instead of comparing size value (PR #117411)

llvmbot wrote: @llvm/pr-subscribers-backend-amdgpu Author: Matt Arsenault (arsenm) Changes --- Full diff: https://github.com/llvm/llvm-project/pull/117411.diff 3 Files Affected: - (modified) llvm/lib/Target/AMDGPU/SIISelLowering.cpp (+2-2) - (modified) llvm/lib/Target/AMDGPU/SIInstrI

[llvm-branch-commits] [llvm] AMDGPU: Use isWave[32|64] instead of comparing size value (PR #117411)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/117411?utm_source=stack-comment-downstack-mergeability-warning";

[llvm-branch-commits] [llvm] AMDGPU: Use isWave[32|64] instead of comparing size value (PR #117411)

https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/117411 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Use isWave[32|64] instead of comparing size value (PR #117411)

https://github.com/jhuber6 approved this pull request. LG https://github.com/llvm/llvm-project/pull/117411 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Handle v_mfma_f64_16x16x4_f64 srcc write VGPR hazard change for gfx950 (PR #117283)

https://github.com/shiltian edited https://github.com/llvm/llvm-project/pull/117283 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Handle v_mfma_f64_16x16x4_f64 srcc write VGPR hazard change for gfx950 (PR #117283)

https://github.com/shiltian approved this pull request. https://github.com/llvm/llvm-project/pull/117283 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Handle gfx950 XDL-write-overlapped-smfma-src-c wait state change (PR #117263)

https://github.com/shiltian edited https://github.com/llvm/llvm-project/pull/117263 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Handle gfx950 change in mfma_f64_16x16x4 + valu hazard (PR #117262)

https://github.com/shiltian edited https://github.com/llvm/llvm-project/pull/117262 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] d69790b - Revert "[MemProf] Use radix tree for alloc contexts in bitcode summaries (#11…"

Author: Teresa Johnson Date: 2024-11-22T14:57:26-08:00 New Revision: d69790b481cea9196b7b59f542c8771f3103b425 URL: https://github.com/llvm/llvm-project/commit/d69790b481cea9196b7b59f542c8771f3103b425 DIFF: https://github.com/llvm/llvm-project/commit/d69790b481cea9196b7b59f542c8771f3103b425.diff

[llvm-branch-commits] [clang] [llvm] AMDGPU: Add support for load transpose instructions for gfx950 (PR #117378)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117378 >From e32d731b9c2c4409f00e1b738f93c7b2407212ca Mon Sep 17 00:00:00 2001 From: Sirish Pande Date: Wed, 7 Feb 2024 10:12:03 -0600 Subject: [PATCH] AMDGPU: Add support for load transpose instructions for gfx950 Th

[llvm-branch-commits] [llvm] AMDGPU: Handle gfx950 valu write vdst + permlane read hazard (PR #117287)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117287 >From 4ad9760c6300afbded15ab14f542f47e02d2efef Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Mon, 18 Mar 2024 14:41:11 +0530 Subject: [PATCH] AMDGPU: Handle gfx950 valu write vdst + permlane read hazard --

[llvm-branch-commits] [llvm] AMDGPU: Handle vcmpx+permalane gfx950 hazard (PR #117286)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117286 >From d3de92249f924b1d518c366d881a0ac59eedc58b Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Mon, 18 Mar 2024 13:45:22 +0530 Subject: [PATCH] AMDGPU: Handle vcmpx+permalane gfx950 hazard Confusingly, this

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scalef32_pk_{fp|bf}8_{f|bf}16 of gfx950. (PR #117384)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117384 >From 58fde3075c3f8d020a181456a5a270231767e4c1 Mon Sep 17 00:00:00 2001 From: Pravin Jagtap Date: Sun, 7 Apr 2024 01:57:15 -0400 Subject: [PATCH] AMDGPU: MC support for v_cvt_scalef32_pk_{fp|bf}8_{f|bf}16 of gfx

[llvm-branch-commits] [llvm] AMDGPU: Handle gfx950 change in mfma_f64_16x16x4 + valu hazard (PR #117262)

https://github.com/shiltian approved this pull request. https://github.com/llvm/llvm-project/pull/117262 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Add MC support for gfx950 V_BITOP3_B32/B16 (PR #117379)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117379 >From 2d7a1ca9803e94d4dda0594f52deb983c40dd14b Mon Sep 17 00:00:00 2001 From: Pravin Jagtap Date: Fri, 26 Jan 2024 01:40:32 -0500 Subject: [PATCH] AMDGPU: Add MC support for gfx950 V_BITOP3_B32/B16 Co-authored-b

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scale_[f16|f32]_fp8 of gfx950. (PR #117380)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117380 >From 2cdbe55dd974940bf89dcecb7bf9a66fb9febe42 Mon Sep 17 00:00:00 2001 From: Pravin Jagtap Date: Sat, 6 Apr 2024 02:35:49 -0400 Subject: [PATCH] AMDGPU: MC support for v_cvt_scale_[f16|f32]_fp8 of gfx950. OPSEL

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scale_[f16|f32]_bf8 of gfx950. (PR #117381)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117381 >From 9f7e7fd55d71afc3b12e1fbb947a29c95b2d1d0d Mon Sep 17 00:00:00 2001 From: Pravin Jagtap Date: Sat, 6 Apr 2024 07:19:15 -0400 Subject: [PATCH] AMDGPU: MC support for v_cvt_scale_[f16|f32]_bf8 of gfx950. OPSEL

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scalef32_pk_{fp8|bf8}_f32 of gfx950. (PR #117382)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117382 >From 68282297a4eddeb5c71c2b0757bfd759f6813f25 Mon Sep 17 00:00:00 2001 From: Pravin Jagtap Date: Sat, 6 Apr 2024 09:17:03 -0400 Subject: [PATCH] AMDGPU: MC support for v_cvt_scalef32_pk_{fp8|bf8}_f32 of gfx950.

[llvm-branch-commits] [llvm] AMDGPU: MC support for v_cvt_scalef32_pk_f32_[fp|bf]8 of gfx950. (PR #117383)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/117383 >From 717812c8de83e42c34c7ceef0eb2dc82980b875f Mon Sep 17 00:00:00 2001 From: Pravin Jagtap Date: Sat, 6 Apr 2024 11:08:22 -0400 Subject: [PATCH] AMDGPU: MC support for v_cvt_scalef32_pk_f32_[fp|bf]8 of gfx950.

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