https://github.com/tblah approved this pull request.
https://github.com/llvm/llvm-project/pull/146025
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https://github.com/inbelic created
https://github.com/llvm/llvm-project/pull/146124
This pr breaks-up `HLSLRootSignatureUtils` into separate orthogonal and
meaningful libraries. This prevents it end up as a dumping grounds of many
different parts.
- Creates a library `RootSignatureMetadata` t
https://github.com/inbelic created
https://github.com/llvm/llvm-project/pull/146150
None
>From 18edab1fc3ab4a137de935abff5bb4716cc9a5fd Mon Sep 17 00:00:00 2001
From: Finn Plummer
Date: Fri, 27 Jun 2025 18:36:38 +
Subject: [PATCH 1/5] nfc: introduce wrapper `RootSignatureElement` around
`
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/145911
>From 7c2efb4eae157acba554923fb81f85fd30647f86 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 5 Jun 2025 12:17:13 +0200
Subject: [PATCH] AMDGPU/GlobalISel: Improve readanylane combines in
reg
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/145912
>From 4c82486cb901855c00a8b6b8de250e96430f9473 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 26 Jun 2025 16:03:56 +0200
Subject: [PATCH] AMDGPU/GlobalISel: Add waterfall lowering in regbankle
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/145910
>From 57e9aeccd735186314a9a57bf1142baaf013738f Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Wed, 4 Jun 2025 17:11:48 +0200
Subject: [PATCH] AMDGPU/GlobalISel: Add tests for missing readanylane co
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/145911
>From 7c2efb4eae157acba554923fb81f85fd30647f86 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 5 Jun 2025 12:17:13 +0200
Subject: [PATCH] AMDGPU/GlobalISel: Improve readanylane combines in
reg
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/145912
>From 4c82486cb901855c00a8b6b8de250e96430f9473 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 26 Jun 2025 16:03:56 +0200
Subject: [PATCH] AMDGPU/GlobalISel: Add waterfall lowering in regbankle
https://github.com/RKSimon approved this pull request.
https://github.com/llvm/llvm-project/pull/146081
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https://github.com/fmayer updated
https://github.com/llvm/llvm-project/pull/145999
>From 6b21e00652860816ac3d7d8969fd34325661df06 Mon Sep 17 00:00:00 2001
From: Florian Mayer
Date: Thu, 26 Jun 2025 18:03:10 -0700
Subject: [PATCH] more testr
Created using spr 1.3.4
---
clang/test/CodeGen/fallo
https://github.com/fmayer updated
https://github.com/llvm/llvm-project/pull/145999
>From 6b21e00652860816ac3d7d8969fd34325661df06 Mon Sep 17 00:00:00 2001
From: Florian Mayer
Date: Thu, 26 Jun 2025 18:03:10 -0700
Subject: [PATCH] more testr
Created using spr 1.3.4
---
clang/test/CodeGen/fallo
@@ -2668,6 +2668,16 @@ def fsanitize_skip_hot_cutoff_EQ
} // end -f[no-]sanitize* flags
+def fallow_runtime_check_skip_hot_cutoff_EQ
+: Joined<["-"], "fallow-runtime-check-skip-hot-cutoff=">,
+ Group,
+ Visibility<[ClangOption, CC1Option]>,
+ HelpText<"Excl
@@ -2668,6 +2668,16 @@ def fsanitize_skip_hot_cutoff_EQ
} // end -f[no-]sanitize* flags
+def fallow_runtime_check_skip_hot_cutoff_EQ
+: Joined<["-"], "fallow-runtime-check-skip-hot-cutoff=">,
+ Group,
+ Visibility<[ClangOption, CC1Option]>,
+ HelpText<"Excl
https://github.com/vitalybuka approved this pull request.
https://github.com/llvm/llvm-project/pull/145999
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@@ -2668,6 +2668,16 @@ def fsanitize_skip_hot_cutoff_EQ
} // end -f[no-]sanitize* flags
+def fallow_runtime_check_skip_hot_cutoff_EQ
+: Joined<["-"], "fallow-runtime-check-skip-hot-cutoff=">,
+ Group,
+ Visibility<[ClangOption, CC1Option]>,
+ HelpText<"Excl
@@ -615,8 +615,14 @@ bool TargetLowering::ShrinkDemandedOp(SDValue Op, unsigned
BitWidth,
// operands on the new node are also disjoint.
SDNodeFlags Flags(Op->getFlags().hasDisjoint() ? SDNodeFlags::Disjoint
: SD
@@ -2230,7 +2230,7 @@ bool AMDGPUDAGToDAGISel::SelectSMRDBaseOffset(SDValue
Addr, SDValue &SBase,
SDValue N0, N1;
// Extract the base and offset if possible.
- if (CurDAG->isBaseWithConstantOffset(Addr) || Addr.getOpcode() == ISD::ADD) {
+ if (CurDAG->isBaseWithConstant
@@ -2960,10 +2971,10 @@ bool TargetLowering::SimplifyDemandedBits(
if (Op.getOpcode() == ISD::MUL) {
Known = KnownBits::mul(KnownOp0, KnownOp1);
-} else { // Op.getOpcode() is either ISD::ADD or ISD::SUB.
+} else { // Op.getOpcode() is either ISD::ADD, ISD::P
https://github.com/Pierre-vh created
https://github.com/llvm/llvm-project/pull/146053
None
>From 3f62ab3beb30abbf8c8c32dd79c0133f7ca122e0 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Thu, 26 Jun 2025 13:08:31 +0200
Subject: [PATCH] [AMDGPU] Add tests for workgroup/workitem intrinsic
optimiza
https://github.com/Pierre-vh created
https://github.com/llvm/llvm-project/pull/146055
Equivalent of the previous DAG patch for GISel.
The shifts are BFXs in GISel, so the canonical form of the entire expression
is different than in the DAG. The mask is not at the root of the expression, it
remai
https://github.com/Pierre-vh created
https://github.com/llvm/llvm-project/pull/146054
Fold sequences where we extract a bunch of contiguous bits from a value,
merge them into the low bit and then check if the low bits are zero or not.
It seems like a strange sequence at first but it's an idiom
Pierre-vh wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/146053?utm_source=stack-comment-downstack-mergeability-warning
Pierre-vh wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/146054?utm_source=stack-comment-downstack-mergeability-warning
Pierre-vh wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/146055?utm_source=stack-comment-downstack-mergeability-warning
llvmbot wrote:
@llvm/pr-subscribers-backend-amdgpu
@llvm/pr-subscribers-llvm-selectiondag
Author: Pierre van Houtryve (Pierre-vh)
Changes
Fold sequences where we extract a bunch of contiguous bits from a value,
merge them into the low bit and then check if the low bits are zero or not.
Us
llvmbot wrote:
@llvm/pr-subscribers-backend-amdgpu
Author: Pierre van Houtryve (Pierre-vh)
Changes
Equivalent of the previous DAG patch for GISel.
The shifts are BFXs in GISel, so the canonical form of the entire expression
is different than in the DAG. The mask is not at the root of the e
llvmbot wrote:
@llvm/pr-subscribers-llvm-globalisel
Author: Pierre van Houtryve (Pierre-vh)
Changes
Equivalent of the previous DAG patch for GISel.
The shifts are BFXs in GISel, so the canonical form of the entire expression
is different than in the DAG. The mask is not at the root of the
llvmbot wrote:
@llvm/pr-subscribers-backend-amdgpu
Author: Pierre van Houtryve (Pierre-vh)
Changes
---
Patch is 24.13 KiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-project/pull/146053.diff
1 Files Affected:
- (added) llvm/test/CodeGen/AMDGPU/workitems
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/145910
>From 57e9aeccd735186314a9a57bf1142baaf013738f Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Wed, 4 Jun 2025 17:11:48 +0200
Subject: [PATCH] AMDGPU/GlobalISel: Add tests for missing readanylane co
https://github.com/Pierre-vh ready_for_review
https://github.com/llvm/llvm-project/pull/146053
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https://github.com/llvm/llvm-project/pull/146055
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https://github.com/Pierre-vh edited
https://github.com/llvm/llvm-project/pull/146054
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https://github.com/RKSimon commented:
Why DAG and not InstCombine for this?
https://github.com/llvm/llvm-project/pull/146054
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https://github.com/ritter-x2a created
https://github.com/llvm/llvm-project/pull/146074
This PR adds a TargetLowering hook, canTransformPtrArithOutOfBounds,
that targets can use to allow transformations to introduce out-of-bounds
pointer arithmetic. It also moves two such transformations from the
https://github.com/ritter-x2a created
https://github.com/llvm/llvm-project/pull/146076
Also removes the command line option to control this feature.
There seem to be mainly two kinds of test changes:
- Some operands of addition instructions are swapped; that is to be expected
since PTRADD is
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/145329
>From ee350dc005a6274b4a3114c85aeafa0d5e83806f Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Tue, 17 Jun 2025 03:51:19 -0400
Subject: [PATCH] [AMDGPU][SDAG] Test ISD::PTRADD handling in various special
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/143881
>From d2ca0b2c1b0d9bb3da82b3dfbf82b74ae2b3f978 Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Thu, 12 Jun 2025 07:44:37 -0400
Subject: [PATCH] [AMDGPU][SDAG] Handle ISD::PTRADD in VOP3 patterns
This patc
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/145329
>From ee350dc005a6274b4a3114c85aeafa0d5e83806f Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Tue, 17 Jun 2025 03:51:19 -0400
Subject: [PATCH] [AMDGPU][SDAG] Test ISD::PTRADD handling in various special
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/145330
>From 083ff661ca6f83339902ebb603a38d53a6f0a695 Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Tue, 17 Jun 2025 04:03:53 -0400
Subject: [PATCH 1/2] [AMDGPU][SDAG] Handle ISD::PTRADD in various special
cas
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/143881
>From d2ca0b2c1b0d9bb3da82b3dfbf82b74ae2b3f978 Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Thu, 12 Jun 2025 07:44:37 -0400
Subject: [PATCH] [AMDGPU][SDAG] Handle ISD::PTRADD in VOP3 patterns
This patc
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/143880
>From 604ad3d39fac13c1abec2b7db46d1e671d842399 Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Thu, 12 Jun 2025 06:13:26 -0400
Subject: [PATCH] [AMDGPU][SDAG] Test ISD::PTRADD handling in VOP3 patterns
Pr
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/143880
>From 604ad3d39fac13c1abec2b7db46d1e671d842399 Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Thu, 12 Jun 2025 06:13:26 -0400
Subject: [PATCH] [AMDGPU][SDAG] Test ISD::PTRADD handling in VOP3 patterns
Pr
https://github.com/erichkeane approved this pull request.
https://github.com/llvm/llvm-project/pull/146045
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https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/145330
>From 083ff661ca6f83339902ebb603a38d53a6f0a695 Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Tue, 17 Jun 2025 04:03:53 -0400
Subject: [PATCH 1/2] [AMDGPU][SDAG] Handle ISD::PTRADD in various special
cas
ritter-x2a wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/146075?utm_source=stack-comment-downstack-mergeability-warnin
https://github.com/ritter-x2a created
https://github.com/llvm/llvm-project/pull/146075
If we can't fold a PTRADD's offset into its users, lowering them to
disjoint ORs is preferable: Often, a 32-bit OR instruction suffices
where we'd otherwise use a pair of 32-bit additions with carry.
This nee
ritter-x2a wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/146074?utm_source=stack-comment-downstack-mergeability-warnin
ritter-x2a wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/146076?utm_source=stack-comment-downstack-mergeability-warnin
@@ -2960,10 +2971,10 @@ bool TargetLowering::SimplifyDemandedBits(
if (Op.getOpcode() == ISD::MUL) {
Known = KnownBits::mul(KnownOp0, KnownOp1);
-} else { // Op.getOpcode() is either ISD::ADD or ISD::SUB.
+} else { // Op.getOpcode() is either ISD::ADD, ISD::P
github-actions[bot] wrote:
:warning: C/C++ code formatter, clang-format found issues in your code.
:warning:
You can test this locally with the following command:
``bash
git-clang-format --diff HEAD~1 HEAD --extensions cpp,h --
llvm/include/llvm/Analysis/TargetTransformInfo.h
l
@@ -2230,7 +2230,7 @@ bool AMDGPUDAGToDAGISel::SelectSMRDBaseOffset(SDValue
Addr, SDValue &SBase,
SDValue N0, N1;
// Extract the base and offset if possible.
- if (CurDAG->isBaseWithConstantOffset(Addr) || Addr.getOpcode() == ISD::ADD) {
+ if (CurDAG->isBaseWithConstant
llvmbot wrote:
@llvm/pr-subscribers-backend-amdgpu
Author: Fabian Ritter (ritter-x2a)
Changes
If we can't fold a PTRADD's offset into its users, lowering them to
disjoint ORs is preferable: Often, a 32-bit OR instruction suffices
where we'd otherwise use a pair of 32-bit additions with car
https://github.com/ritter-x2a ready_for_review
https://github.com/llvm/llvm-project/pull/146074
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llvmbot wrote:
@llvm/pr-subscribers-backend-amdgpu
Author: Fabian Ritter (ritter-x2a)
Changes
This PR adds a TargetLowering hook, canTransformPtrArithOutOfBounds,
that targets can use to allow transformations to introduce out-of-bounds
pointer arithmetic. It also moves two such transformat
https://github.com/xlauko created
https://github.com/llvm/llvm-project/pull/146045
Resolves issues pointed out in
https://github.com/llvm/llvm-project/pull/143960/files#r2164047625 of needing
to update sized list of types on each new type.
This mirrors incubator changes from https://github.co
https://github.com/xlauko ready_for_review
https://github.com/llvm/llvm-project/pull/146045
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xlauko wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/146045?utm_source=stack-comment-downstack-mergeability-warning";
llvmbot wrote:
@llvm/pr-subscribers-clangir
@llvm/pr-subscribers-clang
Author: Henrich Lauko (xlauko)
Changes
Resolves issues pointed out in
https://github.com/llvm/llvm-project/pull/143960/files#r2164047625 of needing
to update sized list of types on each new type.
This mirrors incubat
llvmbot wrote:
@llvm/pr-subscribers-vectorizers
Author: Sam Tebbs (SamTebbs33)
Changes
Partial reductions can easily be represented by the VPReductionRecipe class by
setting their scale factor to something greater than 1. This PR merges the two
together and gives VPReductionRecipe a VFSc
https://github.com/ergawy edited
https://github.com/llvm/llvm-project/pull/146033
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@@ -98,6 +98,45 @@ static void setARMLibcallNames(RuntimeLibcallsInfo &Info,
const Triple &TT,
Info.setLibcallImpl(RTLIB::SDIVREM_I32, RTLIB::__divmodsi4);
Info.setLibcallImpl(RTLIB::UDIVREM_I32, RTLIB::__udivmodsi4);
}
+
+ static const RTLIB::LibcallImpl AAPCS_Libc
https://github.com/efriedma-quic edited
https://github.com/llvm/llvm-project/pull/146083
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https://github.com/efriedma-quic approved this pull request.
Yes, these functions are always AAPCS. LGTM with one minor comment.
https://github.com/llvm/llvm-project/pull/146083
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h
https://github.com/inbelic edited
https://github.com/llvm/llvm-project/pull/145828
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https://github.com/inbelic updated
https://github.com/llvm/llvm-project/pull/145828
>From 471a4a556ad0653792e39c99da2423d5e3ed933f Mon Sep 17 00:00:00 2001
From: Finn Plummer
Date: Fri, 27 Jun 2025 16:39:13 +
Subject: [PATCH 1/7] update `setDefaultFlags`
---
.../llvm/Frontend/HLSL/HLSLRoo
koachan wrote:
Ping?
https://github.com/llvm/llvm-project/pull/139451
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https://github.com/kparzysz approved this pull request.
https://github.com/llvm/llvm-project/pull/146025
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https://github.com/dianqk created
https://github.com/llvm/llvm-project/pull/146191
Backport c43282ab69d7ff1b64f8ef5c84eab46e57553075
Requested by: @dianqk
>From 58b8b35b174fa0a108b7ed1e0b209504e5144cfc Mon Sep 17 00:00:00 2001
From: dianqk
Date: Sat, 28 Jun 2025 06:42:42 +0800
Subject: [PATCH
llvmbot wrote:
@llvm/pr-subscribers-llvm-transforms
Author: dianqk (dianqk)
Changes
Backport c43282ab69d7ff1b64f8ef5c84eab46e57553075
Requested by: @dianqk
---
Full diff: https://github.com/llvm/llvm-project/pull/146191.diff
2 Files Affected:
- (modified) llvm/lib/Transforms/Utils/Rel
llvmbot wrote:
@llvm/pr-subscribers-flang-fir-hlfir
Author: Kareem Ergawy (ergawy)
Changes
Now that we have changes introduced by #145837, mapping reductions from
`do concurrent` to OpenMP is almost trivial. This PR adds such mapping.
TODO: Add tests
---
Full diff: https://github.com/ll
https://github.com/ergawy created
https://github.com/llvm/llvm-project/pull/146033
Now that we have changes introduced by #145837, mapping reductions from `do
concurrent` to OpenMP is almost trivial. This PR adds such mapping.
TODO: Add tests
>From b99122bb337d80d0d7958b6763e1337b3e5d9405 Mon
https://github.com/ergawy updated
https://github.com/llvm/llvm-project/pull/146025
>From 9021dbcf419e189f96e2d88f6db97c9d472dc2b9 Mon Sep 17 00:00:00 2001
From: ergawy
Date: Thu, 26 Jun 2025 23:30:04 -0500
Subject: [PATCH] [NFC][flang] Move `ReductionProcessor` to `Lower/Support`.
With #145837
https://github.com/ergawy updated
https://github.com/llvm/llvm-project/pull/146028
>From 5f665c949781fda9406e67c74c31217dba170a4c Mon Sep 17 00:00:00 2001
From: ergawy
Date: Fri, 27 Jun 2025 00:05:42 -0500
Subject: [PATCH] [flang][fir] Small clean-up in `fir_DoConcurrentLoopOp`'s
defintion
Re
@@ -235,29 +247,57 @@ void
RuntimeLibcallEmitter::emitGetInitRuntimeLibcallNames(
// TODO: Emit libcall names as string offset table.
OS << "#ifdef GET_INIT_RUNTIME_LIBCALL_NAMES\n"
-"const char *const "
+"const RTLIB::LibcallImpl "
"llvm::RTLIB::
https://github.com/nikic edited https://github.com/llvm/llvm-project/pull/144973
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https://github.com/nikic approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/144973
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@@ -882,7 +902,7 @@ def exp10f128 : RuntimeLibcallImpl;
def sinf128 : RuntimeLibcallImpl;
def cosf128 : RuntimeLibcallImpl;
def tanf128 : RuntimeLibcallImpl;
-def tanhf128 : RuntimeLibcallImpl;
+def tanhf128 : RuntimeLibcallImpl;
nikic wrote:
Should probably b
@@ -235,29 +247,57 @@ void
RuntimeLibcallEmitter::emitGetInitRuntimeLibcallNames(
// TODO: Emit libcall names as string offset table.
OS << "#ifdef GET_INIT_RUNTIME_LIBCALL_NAMES\n"
-"const char *const "
+"const RTLIB::LibcallImpl "
"llvm::RTLIB::
@@ -235,29 +247,57 @@ void
RuntimeLibcallEmitter::emitGetInitRuntimeLibcallNames(
// TODO: Emit libcall names as string offset table.
OS << "#ifdef GET_INIT_RUNTIME_LIBCALL_NAMES\n"
-"const char *const "
+"const RTLIB::LibcallImpl "
"llvm::RTLIB::
@@ -720,18 +720,17 @@ SDValue TargetLowering::SimplifyMultipleUseDemandedBits(
unsigned Scale = NumDstEltBits / NumSrcEltBits;
unsigned NumSrcElts = SrcVT.getVectorNumElements();
APInt DemandedSrcBits = APInt::getZero(NumSrcEltBits);
- APInt DemandedSrcEl
https://github.com/ergawy converted_to_draft
https://github.com/llvm/llvm-project/pull/146033
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https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/144974
>From c18ce1989e40ab83ed5da821a72afcab72e8330f Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 16 Jun 2025 15:50:24 +0900
Subject: [PATCH] ARM: Add runtime libcall definitions for eabi memory
functions
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/144978
>From 18a2de65f477924557ec792533e3aa94fa62c532 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Sat, 7 Jun 2025 20:57:31 +0900
Subject: [PATCH] TableGen: Allow defining sets of runtime libraries
Add a way to
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/144977
>From 97b0c49e41ef60286c7f150db1a846eb18f6e7a8 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 16 Jun 2025 14:56:26 +0900
Subject: [PATCH] AArch64: Add libcall impl declarations for __arm_sc* memory
fun
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/144977
>From 97b0c49e41ef60286c7f150db1a846eb18f6e7a8 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 16 Jun 2025 14:56:26 +0900
Subject: [PATCH] AArch64: Add libcall impl declarations for __arm_sc* memory
fun
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/144978
>From 18a2de65f477924557ec792533e3aa94fa62c532 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Sat, 7 Jun 2025 20:57:31 +0900
Subject: [PATCH] TableGen: Allow defining sets of runtime libraries
Add a way to
@@ -235,29 +247,57 @@ void
RuntimeLibcallEmitter::emitGetInitRuntimeLibcallNames(
// TODO: Emit libcall names as string offset table.
OS << "#ifdef GET_INIT_RUNTIME_LIBCALL_NAMES\n"
-"const char *const "
+"const RTLIB::LibcallImpl "
"llvm::RTLIB::
@@ -235,29 +247,57 @@ void
RuntimeLibcallEmitter::emitGetInitRuntimeLibcallNames(
// TODO: Emit libcall names as string offset table.
OS << "#ifdef GET_INIT_RUNTIME_LIBCALL_NAMES\n"
-"const char *const "
+"const RTLIB::LibcallImpl "
"llvm::RTLIB::
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/144976
>From 6854ef6e460f575b211f4d15f2f7dbbfa6513a66 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 16 Jun 2025 16:27:41 +0900
Subject: [PATCH] XCore: Declare libcalls used for align 4 memcpy
This usage was
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/144975
>From d3f44e838be753a2e54c99bb63663d040edbc194 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 16 Jun 2025 16:14:09 +0900
Subject: [PATCH] Hexagon: Add libcall declarations for special memcpy
HexagonSel
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/144974
>From c18ce1989e40ab83ed5da821a72afcab72e8330f Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 16 Jun 2025 15:50:24 +0900
Subject: [PATCH] ARM: Add runtime libcall definitions for eabi memory
functions
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/144980
>From a53a1c9b3c675d9d75aa2b359102faef98262d69 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Fri, 13 Jun 2025 15:54:41 +0900
Subject: [PATCH] TableGen: Handle setting runtime libcall calling conventions
Al
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/144979
>From fb4074a4d188707c22f477c508b00e245406a5f6 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Tue, 17 Jun 2025 16:25:50 +0900
Subject: [PATCH] RuntimeLibcalls: Associate calling convention with libcall
impl
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/144976
>From 6854ef6e460f575b211f4d15f2f7dbbfa6513a66 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 16 Jun 2025 16:27:41 +0900
Subject: [PATCH] XCore: Declare libcalls used for align 4 memcpy
This usage was
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/144975
>From d3f44e838be753a2e54c99bb63663d040edbc194 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 16 Jun 2025 16:14:09 +0900
Subject: [PATCH] Hexagon: Add libcall declarations for special memcpy
HexagonSel
https://github.com/arsenm approved this pull request.
https://github.com/llvm/llvm-project/pull/145910
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@@ -0,0 +1,166 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010
-new-reg-bank-select < %s | FileCheck %s
+
+define amdgpu_ps void @readanylane_to_virtual_vgpr
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