https://github.com/MacDue approved this pull request.
LGTM :+1:
https://github.com/llvm/llvm-project/pull/86098
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@@ -316,6 +317,9 @@ class ValueBoundsConstraintSet {
/// Builder for constructing affine expressions.
Builder builder;
+
+ /// The current stop condition function.
+ StopConditionFn stopCondition = nullptr;
MacDue wrote:
Just wondering if this should be
https://github.com/MacDue approved this pull request.
https://github.com/llvm/llvm-project/pull/86099
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https://github.com/MacDue approved this pull request.
https://github.com/llvm/llvm-project/pull/87976
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@@ -1416,14 +1466,14 @@ void VPlanTransforms::addActiveLaneMask(
auto *FoundWidenCanonicalIVUser =
find_if(Plan.getCanonicalIV()->users(),
[](VPUser *U) { return isa(U); });
- assert(FoundWidenCanonicalIVUser &&
+ assert(FoundWidenCanonicalIVUser && *Fou
@@ -77,9 +77,13 @@ struct VPlanTransforms {
/// creation) and instead it is handled using active-lane-mask. \p
/// DataAndControlFlowWithoutRuntimeCheck implies \p
/// UseActiveLaneMaskForControlFlow.
+ /// RTChecks refers to the pointer pairs that need aliasing elements
@@ -3073,6 +3075,56 @@ struct VPWidenStoreEVLRecipe final : public
VPWidenMemoryRecipe {
}
};
+// Given a pointer A that is being stored to, and pointer B that is being
+// read from, both with unknown lengths, create a mask that disables
+// elements which could overlap ac
@@ -427,6 +428,29 @@ Value *VPInstruction::generate(VPTransformState &State) {
{PredTy, ScalarTC->getType()},
{VIVElem0, ScalarTC}, nullptr, Name);
}
+ // Count the number of bits set in each lane and redu
@@ -1300,14 +1301,38 @@ static VPActiveLaneMaskPHIRecipe
*addVPLaneMaskPhiAndUpdateExitBranch(
cast(CanonicalIVPHI->getBackedgeValue());
// TODO: Check if dropping the flags is needed if
// !DataAndControlFlowWithoutRuntimeCheck.
+ VPValue *IncVal = CanonicalIVIncre
@@ -195,6 +195,13 @@ enum class TailFoldingStyle {
DataWithEVL,
};
+enum class RTCheckStyle {
+ /// Branch to scalar loop if checks fails at runtime.
+ ScalarFallback,
+ /// Form a mask based on elements which won't be a WAR or RAW hazard
MacDue wrote:
u
https://github.com/MacDue edited
https://github.com/llvm/llvm-project/pull/100579
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@@ -1331,14 +1356,37 @@ static VPActiveLaneMaskPHIRecipe
*addVPLaneMaskPhiAndUpdateExitBranch(
"index.part.next");
// Create the active lane mask instruction in the VPlan preheader.
- auto *EntryALM =
+ VPValue *Mask =
Builder.createNaryOp(VPInstruction::Acti
@@ -3235,6 +3263,36 @@ void VPWidenPointerInductionRecipe::print(raw_ostream
&O, const Twine &Indent,
}
#endif
+void VPAliasLaneMaskRecipe::execute(VPTransformState &State) {
+ IRBuilderBase Builder = State.Builder;
+ Value *SinkValue = State.get(getSinkValue(), true);
+ V
@@ -952,7 +952,6 @@ void VPlan::prepareToExecute(Value *TripCountV, Value
*VectorTripCountV,
IRBuilder<> Builder(State.CFG.PrevBB->getTerminator());
// FIXME: Model VF * UF computation completely in VPlan.
- assert(VFxUF.getNumUsers() && "VFxUF expected to always have us
@@ -3235,6 +3263,36 @@ void VPWidenPointerInductionRecipe::print(raw_ostream
&O, const Twine &Indent,
}
#endif
+void VPAliasLaneMaskRecipe::execute(VPTransformState &State) {
+ IRBuilderBase Builder = State.Builder;
+ Value *SinkValue = State.get(getSinkValue(), true);
+ V
https://github.com/MacDue commented:
A bunch of little comments (mostly just nitpicks from a pass over the PR)
:slightly_smiling_face:
https://github.com/llvm/llvm-project/pull/100579
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@@ -418,7 +418,13 @@ class LoopVectorizationPlanner {
/// Build VPlans for the specified \p UserVF and \p UserIC if they are
/// non-zero or all applicable candidate VFs otherwise. If vectorization and
/// interleaving should be avoided up-front, no plans are generated.
-
https://github.com/MacDue edited
https://github.com/llvm/llvm-project/pull/126503
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@@ -253,38 +253,38 @@ define i64 @not_dotp_i8_to_i64_has_neon_dotprod(ptr
readonly %a, ptr readonly %b
; CHECK-MAXBW-SAME: ptr readonly [[A:%.*]], ptr readonly [[B:%.*]])
#[[ATTR1:[0-9]+]] {
; CHECK-MAXBW-NEXT: entry:
; CHECK-MAXBW-NEXT:[[TMP0:%.*]] = call i64 @llvm.vsca
@@ -2376,6 +2327,59 @@ class VPReductionRecipe : public VPRecipeWithIRFlags {
}
};
+/// A recipe for forming partial reductions. In the loop, an accumulator and
+/// vector operand are added together and passed to the next iteration as the
+/// next accumulator. After the lo
https://github.com/MacDue edited
https://github.com/llvm/llvm-project/pull/136173
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https://github.com/MacDue created
https://github.com/llvm/llvm-project/pull/137683
This cherry-picks https://github.com/llvm/llvm-project/pull/132722 and
https://github.com/llvm/llvm-project/pull/136726 (the latter is based on the
former).
These patches are needed to prevent invalid codegen
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MacDue wrote:
@sdesmalen-arm What do you think about merging this PR to the release branch?
https://github.com/llvm/llvm-project/pull/137683
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@@ -4923,9 +4923,7 @@ InstructionCost AArch64TTIImpl::getPartialReductionCost(
return Invalid;
break;
case 16:
- if (AccumEVT == MVT::i64)
-Cost *= 2;
- else if (AccumEVT != MVT::i32)
+ if (AccumEVT != MVT::i32)
MacDue w
@@ -4923,9 +4923,7 @@ InstructionCost AArch64TTIImpl::getPartialReductionCost(
return Invalid;
break;
case 16:
- if (AccumEVT == MVT::i64)
-Cost *= 2;
- else if (AccumEVT != MVT::i32)
+ if (AccumEVT != MVT::i32)
MacDue w
MacDue wrote:
Not sure why the bot is asking me (I think it's fine, but I requested the
backport).
cc @arsenm, @RKSimon
https://github.com/llvm/llvm-project/pull/140703
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