[llvm-branch-commits] [llvm] release/19.x: [RISCV] Fix InsnCI register type (#100113) (PR #100306)

https://github.com/lenary approved this pull request. https://github.com/llvm/llvm-project/pull/100306 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/19.x: [RISCV] Fix InsnCI register type (#100113) (PR #100306)

lenary wrote: The build failures aren't related. I'm going to hit the rebase button in the hope that fixes the build issue. https://github.com/llvm/llvm-project/pull/100306 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https:

[llvm-branch-commits] [llvm] release/19.x: [RISCV] Fix InsnCI register type (#100113) (PR #100306)

https://github.com/lenary updated https://github.com/llvm/llvm-project/pull/100306 >From f9d32a6882749e761e971f9237dde813ddbba2d7 Mon Sep 17 00:00:00 2001 From: Sudharsan Veeravalli Date: Tue, 23 Jul 2024 18:49:57 +0530 Subject: [PATCH] [RISCV] Fix InsnCI register type (#100113) According to t

[llvm-branch-commits] [llvm] release/19.x: [RISCV] Don't outline pcrel_lo when the function has a section prefix (#107943) (PR #108288)

lenary wrote: I believe the risk of bringing this in to be fairly small (we did the smallest fix possible to make it more amenable to back-porting), but I also knew this was fairly close to the 19.1.0 release date. If you think there will be a 19.1.1, then it can probably wait for that. https

[llvm-branch-commits] [llvm] 71ed4b6 - [RISCV] Legalize select when Zbt extension available

Author: Michael Munday Date: 2021-01-12T21:24:38Z New Revision: 71ed4b6ce57d8843ef705af8f98305976a8f107a URL: https://github.com/llvm/llvm-project/commit/71ed4b6ce57d8843ef705af8f98305976a8f107a DIFF: https://github.com/llvm/llvm-project/commit/71ed4b6ce57d8843ef705af8f98305976a8f107a.diff LOG

[llvm-branch-commits] [llvm] 7c9c2a2 - Revert "[RISCV] Legalize select when Zbt extension available"

Author: Sam Elliott Date: 2021-01-14T16:44:34Z New Revision: 7c9c2a2ea5e3760d7310309c96c9a4ce41fa4d9b URL: https://github.com/llvm/llvm-project/commit/7c9c2a2ea5e3760d7310309c96c9a4ce41fa4d9b DIFF: https://github.com/llvm/llvm-project/commit/7c9c2a2ea5e3760d7310309c96c9a4ce41fa4d9b.diff LOG: R

[llvm-branch-commits] [llvm] 8a53a73 - [RISCV][NFC] Regenerate Calling Convention Tests

Author: Sam Elliott Date: 2021-01-14T22:35:17Z New Revision: 8a53a7375a86a5a89ba124de9e17aa5701544104 URL: https://github.com/llvm/llvm-project/commit/8a53a7375a86a5a89ba124de9e17aa5701544104 DIFF: https://github.com/llvm/llvm-project/commit/8a53a7375a86a5a89ba124de9e17aa5701544104.diff LOG: [

[llvm-branch-commits] [llvm] 141e45b - [RISCV] Optimize Branch Comparisons

Author: Sam Elliott Date: 2021-01-15T11:28:19Z New Revision: 141e45b99ca09235b985504e8108dbb3cf210fbd URL: https://github.com/llvm/llvm-project/commit/141e45b99ca09235b985504e8108dbb3cf210fbd DIFF: https://github.com/llvm/llvm-project/commit/141e45b99ca09235b985504e8108dbb3cf210fbd.diff LOG: [

[llvm-branch-commits] [llvm] bf1aa5d - [RISCV][NFC] Fix order of parameters in cmov ge/le tests

Author: Michael Munday Date: 2021-01-15T15:35:13Z New Revision: bf1aa5db5c76d187df8dfef28bc5b8889fb53c4b URL: https://github.com/llvm/llvm-project/commit/bf1aa5db5c76d187df8dfef28bc5b8889fb53c4b DIFF: https://github.com/llvm/llvm-project/commit/bf1aa5db5c76d187df8dfef28bc5b8889fb53c4b.diff LOG

[llvm-branch-commits] [llvm] b42ff9f - [RISCV][NFC] Increase test coverage of Zbt extension

Author: Michael Munday Date: 2021-01-18T17:30:35Z New Revision: b42ff9fb038206c7967e22ceef2c7ea8275dc198 URL: https://github.com/llvm/llvm-project/commit/b42ff9fb038206c7967e22ceef2c7ea8275dc198 DIFF: https://github.com/llvm/llvm-project/commit/b42ff9fb038206c7967e22ceef2c7ea8275dc198.diff LOG

[llvm-branch-commits] [llvm] e2d3d50 - [RISCV][NFC] Add additional cmov tests

Author: Michael Munday Date: 2021-01-04T16:01:40Z New Revision: e2d3d501ef8b49eb8990dd3556948373b023cd48 URL: https://github.com/llvm/llvm-project/commit/e2d3d501ef8b49eb8990dd3556948373b023cd48 DIFF: https://github.com/llvm/llvm-project/commit/e2d3d501ef8b49eb8990dd3556948373b023cd48.diff LOG

[llvm-branch-commits] [llvm] 12406ad - [RISCV] Add (Proposed) Assembler Extend Pseudo-Instructions

Author: Sam Elliott Date: 2020-12-10T19:25:51Z New Revision: 12406ade0625ffa3939e2fa684293e02eb8791ff URL: https://github.com/llvm/llvm-project/commit/12406ade0625ffa3939e2fa684293e02eb8791ff DIFF: https://github.com/llvm/llvm-project/commit/12406ade0625ffa3939e2fa684293e02eb8791ff.diff LOG: [

[llvm-branch-commits] [llvm] b7901e4 - [RISCV][NFC] Fix Sext/Zext Tests

Author: Sam Elliott Date: 2020-12-10T20:10:29Z New Revision: b7901e4c1a2ef0de73f133d5ecc6abbc3f427bdc URL: https://github.com/llvm/llvm-project/commit/b7901e4c1a2ef0de73f133d5ecc6abbc3f427bdc DIFF: https://github.com/llvm/llvm-project/commit/b7901e4c1a2ef0de73f133d5ecc6abbc3f427bdc.diff LOG: [

[llvm-branch-commits] [llvm] 5cfd30a - [RISCV] Add Clang and LLVM Release Notes

Author: Sam Elliott Date: 2020-02-26T18:19:07Z New Revision: 5cfd30add460640264c7d88c4d837a2d4e0ae7b1 URL: https://github.com/llvm/llvm-project/commit/5cfd30add460640264c7d88c4d837a2d4e0ae7b1 DIFF: https://github.com/llvm/llvm-project/commit/5cfd30add460640264c7d88c4d837a2d4e0ae7b1.diff LOG: [

[llvm-branch-commits] [llvm] 7e3ebf3 - [RISCV] Update RISC-V Release Notes for LLVM

Author: Sam Elliott Date: 2020-02-27T13:14:57Z New Revision: 7e3ebf34eb03ddc5fefe8d4fb2ed62a195bcee0e URL: https://github.com/llvm/llvm-project/commit/7e3ebf34eb03ddc5fefe8d4fb2ed62a195bcee0e DIFF: https://github.com/llvm/llvm-project/commit/7e3ebf34eb03ddc5fefe8d4fb2ed62a195bcee0e.diff LOG: [

[llvm-branch-commits] [llvm] [RISCV][NFC] refactor CFI emitting (PR #114227)

https://github.com/lenary commented: This cleanup is going in a nice direction, I think. A few suggestions/questions below. https://github.com/llvm/llvm-project/pull/114227 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https:

[llvm-branch-commits] [llvm] [RISCV][NFC] refactor CFI emitting (PR #114227)

@@ -27,6 +27,102 @@ using namespace llvm; +static unsigned getCaleeSavedRVVNumRegs(const Register &BaseReg) { + return RISCV::VRRegClass.contains(BaseReg) ? 1 + : RISCV::VRM2RegClass.contains(BaseReg) ? 2 + : RISCV::VRM4RegClass.contains(BaseReg) ? 4 +

[llvm-branch-commits] [llvm] [RISCV][NFC] refactor CFI emitting (PR #114227)

@@ -27,6 +27,102 @@ using namespace llvm; +static unsigned getCaleeSavedRVVNumRegs(const Register &BaseReg) { + return RISCV::VRRegClass.contains(BaseReg) ? 1 + : RISCV::VRM2RegClass.contains(BaseReg) ? 2 + : RISCV::VRM4RegClass.contains(BaseReg) ? 4 +

[llvm-branch-commits] [llvm] [RISCV][NFC] refactor CFI emitting (PR #114227)

@@ -1737,39 +1776,14 @@ void RISCVFrameLowering::emitCalleeSavedRVVPrologCFI( for (auto &CS : RVVCSI) { // Insert the spill to the stack frame. int FI = CS.getFrameIdx(); lenary wrote: Is there a reason you didn't replace this loop with a call to `em

[llvm-branch-commits] [llvm] [RISCV][NFC] refactor CFI emitting (PR #114227)

@@ -27,6 +27,102 @@ using namespace llvm; +static unsigned getCaleeSavedRVVNumRegs(const Register &BaseReg) { + return RISCV::VRRegClass.contains(BaseReg) ? 1 + : RISCV::VRM2RegClass.contains(BaseReg) ? 2 + : RISCV::VRM4RegClass.contains(BaseReg) ? 4 +

[llvm-branch-commits] [llvm] [RISCV][NFC] refactor CFI emitting (PR #114227)

@@ -27,6 +27,102 @@ using namespace llvm; +static unsigned getCaleeSavedRVVNumRegs(const Register &BaseReg) { lenary wrote: Typo ```suggestion static unsigned getCalleeSavedRVVNumRegs(const Register &BaseReg) { ``` https://github.com/llvm/llvm-project/pull

[llvm-branch-commits] [llvm] [RISCV][NFC] refactor CFI emitting (PR #114227)

https://github.com/lenary edited https://github.com/llvm/llvm-project/pull/114227 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] [RISCV] Support __builtin_cpu_is (PR #116231)

https://github.com/lenary approved this pull request. https://github.com/llvm/llvm-project/pull/116231 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] [RISCV] Support __builtin_cpu_is (PR #116231)

@@ -58,6 +58,19 @@ bool hasFastVectorUnalignedAccess(StringRef CPU) { return Info && Info->FastVectorUnalignedAccess; } +bool hasValidCPUModel(StringRef CPU) { + const CPUModel CPUModel = getCPUModel(CPU); + return CPUModel.MVendorID != 0 && CPUModel.MArchID != 0 && --

[llvm-branch-commits] [clang] [llvm] [RISCV] Support __builtin_cpu_is (PR #116231)

@@ -22505,6 +22506,57 @@ Value *CodeGenFunction::EmitHexagonBuiltinExpr(unsigned BuiltinID, return nullptr; } +Value *CodeGenFunction::EmitRISCVCpuIs(const CallExpr *E) { + const Expr *CPUExpr = E->getArg(0)->IgnoreParenCasts(); + StringRef CPUStr = cast(CPUExpr)->getStri

[llvm-branch-commits] [clang] [llvm] [RISCV] Support __builtin_cpu_is (PR #116231)

@@ -1,55 +1,131 @@ -// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -emit-llvm < %s| FileCheck %s +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 5 +// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s

[llvm-branch-commits] [llvm] [CodeGen] Use cached version of getRegPressureSetLimit (PR #119194)

https://github.com/lenary approved this pull request. LGTM for the target-independent changes. https://github.com/llvm/llvm-project/pull/119194 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailm

[llvm-branch-commits] [llvm] [CodeGen] Use cached version of getRegPressureSetLimit (PR #119194)

@@ -123,6 +123,7 @@ namespace { const TargetRegisterInfo *TRI = nullptr; const MachineFrameInfo *MFI = nullptr; MachineRegisterInfo *MRI = nullptr; +RegisterClassInfo RegClassInfo; lenary wrote: I was thinking this, especially as it has some sa

[llvm-branch-commits] [clang] [Multilib] Custom flags processing for library selection (PR #110659)

https://github.com/lenary edited https://github.com/llvm/llvm-project/pull/110659 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [Multilib] Custom flags processing for library selection (PR #110659)

@@ -92,12 +93,141 @@ MultilibSet &MultilibSet::FilterOut(FilterCallback F) { void MultilibSet::push_back(const Multilib &M) { Multilibs.push_back(M); } -bool MultilibSet::select(const Driver &D, const Multilib::flags_list &Flags, - llvm::SmallVectorImp

[llvm-branch-commits] [clang] [Multilib] Custom flags processing for library selection (PR #110659)

https://github.com/lenary approved this pull request. LGTM, with one tiny nit. https://github.com/llvm/llvm-project/pull/110659 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm

[llvm-branch-commits] [clang] Add documentation for Multilib custom flags (PR #114998)

@@ -122,6 +122,76 @@ subclass and a suitable base multilib variant is present then the It is the responsibility of layered multilib authors to ensure that headers and libraries in each layer are complete enough to mask any incompatibilities. +Multilib custom flags +==

[llvm-branch-commits] [clang] [Multilib] Add -fmultilib-flag command-line option (PR #110658)

https://github.com/lenary approved this pull request. https://github.com/llvm/llvm-project/pull/110658 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/19.x: [RISCV] Fix typo in CV_SH_rr_inc pattern (#120246) (PR #120296)

https://github.com/lenary approved this pull request. https://github.com/llvm/llvm-project/pull/120296 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] Add documentation for Multilib custom flags (PR #114998)

https://github.com/lenary approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/114998 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] Add documentation for Multilib custom flags (PR #114998)

lenary wrote: I'm still happy with this, and it is for docs, so I don't think the barrier to landing it is very high. https://github.com/llvm/llvm-project/pull/114998 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lis

[llvm-branch-commits] [llvm] release/19.x: [RISCV] Don't create BuildPairF64 or SplitF64 nodes without D or Zdinx. (#116159) (PR #121175)

https://github.com/lenary approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/121175 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [Multilib] Custom flags processing for library selection (PR #110659)

@@ -92,12 +93,141 @@ MultilibSet &MultilibSet::FilterOut(FilterCallback F) { void MultilibSet::push_back(const Multilib &M) { Multilibs.push_back(M); } -bool MultilibSet::select(const Driver &D, const Multilib::flags_list &Flags, - llvm::SmallVectorImp

[llvm-branch-commits] [llvm] release/19.x: [RISCV] Don't create BuildPairF64 or SplitF64 nodes without D or Zdinx. (#116159) (PR #121501)

https://github.com/lenary approved this pull request. LGTM I guess this would have been easier had the original test had `nounwind`, but that's life. I don't think we should change it on the branch. https://github.com/llvm/llvm-project/pull/121501 __

[llvm-branch-commits] [RISCV] Replace @plt/@gotpcrel in data directives with %pltpcrel %gotpcrel (PR #132569)

@@ -2233,8 +2235,17 @@ ParseStatus RISCVAsmParser::parseOperandWithSpecifier(OperandVector &Operands) { SMLoc S = getLoc(); SMLoc E; - if (!parseOptionalToken(AsmToken::Percent) || - getLexer().getKind() != AsmToken::Identifier) + if (!parseOptionalToken(AsmToken::

[llvm-branch-commits] [RISCV] Replace @plt/@gotpcrel in data directives with %pltpcrel %gotpcrel (PR #132569)

@@ -2233,8 +2235,17 @@ ParseStatus RISCVAsmParser::parseOperandWithSpecifier(OperandVector &Operands) { SMLoc S = getLoc(); SMLoc E; - if (!parseOptionalToken(AsmToken::Percent) || - getLexer().getKind() != AsmToken::Identifier) + if (!parseOptionalToken(AsmToken::

[llvm-branch-commits] [RISCV] Replace @plt/@gotpcrel in data directives with %pltpcrel %gotpcrel (PR #132569)

https://github.com/lenary edited https://github.com/llvm/llvm-project/pull/132569 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [RISCV] Replace @plt/@gotpcrel in data directives with %pltpcrel %gotpcrel (PR #132569)

https://github.com/lenary approved this pull request. I am happy with this, but I don't know if Jessica has more feedback. Comments below are nits or for follow-ups https://github.com/llvm/llvm-project/pull/132569 ___ llvm-branch-commits mailing list

[llvm-branch-commits] [RISCV, test] Replace -riscv-no-aliases with -M no-aliases (PR #134879)

https://github.com/lenary approved this pull request. https://github.com/llvm/llvm-project/pull/134879 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] release/20.x: [RISCV] Allow `Zicsr`/`Zifencei` to duplicate with `g` (#136842) (PR #137490)

https://github.com/lenary approved this pull request. https://github.com/llvm/llvm-project/pull/137490 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] RISCVAsmParser: Reject call foo@invalid (PR #135509)

https://github.com/lenary approved this pull request. https://github.com/llvm/llvm-project/pull/135509 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [RISCV] Replace @plt/@gotpcrel in data directives with %plt %gotpcrel (PR #132569)

@@ -18,6 +18,6 @@ .globl _start _start: .data - .word foo@PLT - . - .word foo@PLT - . + 1 - .word foo@PLT - . - 1 + .word %plt(foo - .) lenary wrote: Yeah I don't like `%plt(foo - .)`, because the thing being put into the instruction is really the differe