[llvm-branch-commits] [clang] [llvm] [RISCV] Add subtarget features for profiles (PR #84877)

2024-04-27 Thread Pengcheng Wang via llvm-branch-commits 

https://github.com/wangpc-pp updated 
https://github.com/llvm/llvm-project/pull/84877

>From ec68548a470d6d9032a900a725e95b92691657b2 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng 
Date: Tue, 12 Mar 2024 14:28:09 +0800
Subject: [PATCH 1/7] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
 =?UTF-8?q?itial=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Created using spr 1.3.4
---
 clang/test/Driver/riscv-cpus.c| 319 ++
 clang/test/Misc/target-invalid-cpu-note.c |   8 +-
 llvm/lib/Target/RISCV/RISCVProcessors.td  | 224 ++-
 3 files changed, 539 insertions(+), 12 deletions(-)

diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index ff2bd6f7c8ba34..a285f0f9c41f54 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -302,3 +302,322 @@
 
 // RUN: not %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv32 
-march=rv64i | FileCheck -check-prefix=MISMATCH-ARCH %s
 // MISMATCH-ARCH: cpu 'generic-rv32' does not support rv64
+
+// Check profile CPUs
+
+// RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=generic-rvi20u32 | 
FileCheck -check-prefix=MCPU-GENERIC-RVI20U32 %s
+// MCPU-GENERIC-RVI20U32: "-target-cpu" "generic-rvi20u32"
+// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-a"
+// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-c"
+// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-d"
+// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-f"
+// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-m"
+// MCPU-GENERIC-RVI20U32-SAME: "-target-abi" "ilp32"
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rvi20u64 | 
FileCheck -check-prefix=MCPU-GENERIC-RVI20U64 %s
+// MCPU-GENERIC-RVI20U64: "-target-cpu" "generic-rvi20u64"
+// MCPU-GENERIC-RVI20U64: "-target-feature" "-a"
+// MCPU-GENERIC-RVI20U64: "-target-feature" "-c"
+// MCPU-GENERIC-RVI20U64: "-target-feature" "-d"
+// MCPU-GENERIC-RVI20U64: "-target-feature" "-f"
+// MCPU-GENERIC-RVI20U64: "-target-feature" "-m"
+// MCPU-GENERIC-RVI20U64-SAME: "-target-abi" "lp64"
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva20u64 | 
FileCheck -check-prefix=MCPU-GENERIC-RVA20U64 %s
+// MCPU-GENERIC-RVA20U64: "-target-cpu" "generic-rva20u64"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+m"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+a"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+f"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+d"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+c"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+ziccamoa"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+ziccif"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+zicclsm"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+ziccrse"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+zicntr"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+zicsr"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+za128rs"
+// MCPU-GENERIC-RVA20U64-SAME: "-target-abi" "lp64d"
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva20s64 | 
FileCheck -check-prefix=MCPU-GENERIC-RVA20S64 %s
+// MCPU-GENERIC-RVA20S64: "-target-cpu" "generic-rva20s64"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+m"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+a"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+f"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+d"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+c"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ziccamoa"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ziccif"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zicclsm"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ziccrse"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zicntr"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zicsr"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zifencei"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+za128rs"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ssccptr"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+sstvala"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+sstvecd"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+svade"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+svbare"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-abi" "lp64d"
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva22u64 | 
FileCheck -check-prefix=MCPU-GENERIC-RVA22U64 %s
+// MCPU-GENERIC-RVA22U64: "-target-cpu" "generic-rva22u64"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+m"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+a"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+f"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+d"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+c"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zic64b"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zicbom"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zicbop"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature"

[llvm-branch-commits] [clang] [llvm] [RISCV] Add subtarget features for profiles (PR #84877)

2024-04-26 Thread Philip Reames via llvm-branch-commits 

https://github.com/preames approved this pull request.

LGTM

https://github.com/llvm/llvm-project/pull/84877
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[llvm-branch-commits] [clang] [llvm] [RISCV] Add subtarget features for profiles (PR #84877)

2024-04-26 Thread Pengcheng Wang via llvm-branch-commits 

https://github.com/wangpc-pp updated 
https://github.com/llvm/llvm-project/pull/84877

>From ec68548a470d6d9032a900a725e95b92691657b2 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng 
Date: Tue, 12 Mar 2024 14:28:09 +0800
Subject: [PATCH 1/6] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
 =?UTF-8?q?itial=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Created using spr 1.3.4
---
 clang/test/Driver/riscv-cpus.c| 319 ++
 clang/test/Misc/target-invalid-cpu-note.c |   8 +-
 llvm/lib/Target/RISCV/RISCVProcessors.td  | 224 ++-
 3 files changed, 539 insertions(+), 12 deletions(-)

diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index ff2bd6f7c8ba34..a285f0f9c41f54 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -302,3 +302,322 @@
 
 // RUN: not %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv32 
-march=rv64i | FileCheck -check-prefix=MISMATCH-ARCH %s
 // MISMATCH-ARCH: cpu 'generic-rv32' does not support rv64
+
+// Check profile CPUs
+
+// RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=generic-rvi20u32 | 
FileCheck -check-prefix=MCPU-GENERIC-RVI20U32 %s
+// MCPU-GENERIC-RVI20U32: "-target-cpu" "generic-rvi20u32"
+// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-a"
+// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-c"
+// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-d"
+// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-f"
+// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-m"
+// MCPU-GENERIC-RVI20U32-SAME: "-target-abi" "ilp32"
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rvi20u64 | 
FileCheck -check-prefix=MCPU-GENERIC-RVI20U64 %s
+// MCPU-GENERIC-RVI20U64: "-target-cpu" "generic-rvi20u64"
+// MCPU-GENERIC-RVI20U64: "-target-feature" "-a"
+// MCPU-GENERIC-RVI20U64: "-target-feature" "-c"
+// MCPU-GENERIC-RVI20U64: "-target-feature" "-d"
+// MCPU-GENERIC-RVI20U64: "-target-feature" "-f"
+// MCPU-GENERIC-RVI20U64: "-target-feature" "-m"
+// MCPU-GENERIC-RVI20U64-SAME: "-target-abi" "lp64"
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva20u64 | 
FileCheck -check-prefix=MCPU-GENERIC-RVA20U64 %s
+// MCPU-GENERIC-RVA20U64: "-target-cpu" "generic-rva20u64"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+m"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+a"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+f"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+d"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+c"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+ziccamoa"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+ziccif"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+zicclsm"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+ziccrse"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+zicntr"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+zicsr"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+za128rs"
+// MCPU-GENERIC-RVA20U64-SAME: "-target-abi" "lp64d"
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva20s64 | 
FileCheck -check-prefix=MCPU-GENERIC-RVA20S64 %s
+// MCPU-GENERIC-RVA20S64: "-target-cpu" "generic-rva20s64"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+m"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+a"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+f"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+d"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+c"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ziccamoa"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ziccif"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zicclsm"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ziccrse"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zicntr"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zicsr"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zifencei"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+za128rs"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ssccptr"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+sstvala"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+sstvecd"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+svade"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+svbare"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-abi" "lp64d"
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva22u64 | 
FileCheck -check-prefix=MCPU-GENERIC-RVA22U64 %s
+// MCPU-GENERIC-RVA22U64: "-target-cpu" "generic-rva22u64"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+m"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+a"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+f"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+d"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+c"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zic64b"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zicbom"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zicbop"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature"

[llvm-branch-commits] [clang] [llvm] [RISCV] Add subtarget features for profiles (PR #84877)

2024-04-26 Thread Craig Topper via llvm-branch-commits 


@@ -47,6 +47,12 @@ include "RISCVSchedSiFiveP600.td"
 include "RISCVSchedSyntacoreSCR1.td"
 include "RISCVSchedXiangShanNanHu.td"
 
+//===--===//
+// RISC-V profiles supported.
+//===--===//
+
+include "RISCVProfiles.td"

topperc wrote:

Why not keep this next to RISCVFeatures.td?

https://github.com/llvm/llvm-project/pull/84877
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[llvm-branch-commits] [clang] [llvm] [RISCV] Add subtarget features for profiles (PR #84877)

2024-04-26 Thread Brandon Wu via llvm-branch-commits 

https://github.com/4vtomat approved this pull request.

LGTM~

https://github.com/llvm/llvm-project/pull/84877
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[llvm-branch-commits] [clang] [llvm] [RISCV] Add subtarget features for profiles (PR #84877)

2024-04-26 Thread Pengcheng Wang via llvm-branch-commits 

https://github.com/wangpc-pp updated 
https://github.com/llvm/llvm-project/pull/84877

>From ec68548a470d6d9032a900a725e95b92691657b2 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng 
Date: Tue, 12 Mar 2024 14:28:09 +0800
Subject: [PATCH 1/5] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
 =?UTF-8?q?itial=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Created using spr 1.3.4
---
 clang/test/Driver/riscv-cpus.c| 319 ++
 clang/test/Misc/target-invalid-cpu-note.c |   8 +-
 llvm/lib/Target/RISCV/RISCVProcessors.td  | 224 ++-
 3 files changed, 539 insertions(+), 12 deletions(-)

diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index ff2bd6f7c8ba34..a285f0f9c41f54 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -302,3 +302,322 @@
 
 // RUN: not %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv32 
-march=rv64i | FileCheck -check-prefix=MISMATCH-ARCH %s
 // MISMATCH-ARCH: cpu 'generic-rv32' does not support rv64
+
+// Check profile CPUs
+
+// RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=generic-rvi20u32 | 
FileCheck -check-prefix=MCPU-GENERIC-RVI20U32 %s
+// MCPU-GENERIC-RVI20U32: "-target-cpu" "generic-rvi20u32"
+// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-a"
+// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-c"
+// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-d"
+// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-f"
+// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-m"
+// MCPU-GENERIC-RVI20U32-SAME: "-target-abi" "ilp32"
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rvi20u64 | 
FileCheck -check-prefix=MCPU-GENERIC-RVI20U64 %s
+// MCPU-GENERIC-RVI20U64: "-target-cpu" "generic-rvi20u64"
+// MCPU-GENERIC-RVI20U64: "-target-feature" "-a"
+// MCPU-GENERIC-RVI20U64: "-target-feature" "-c"
+// MCPU-GENERIC-RVI20U64: "-target-feature" "-d"
+// MCPU-GENERIC-RVI20U64: "-target-feature" "-f"
+// MCPU-GENERIC-RVI20U64: "-target-feature" "-m"
+// MCPU-GENERIC-RVI20U64-SAME: "-target-abi" "lp64"
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva20u64 | 
FileCheck -check-prefix=MCPU-GENERIC-RVA20U64 %s
+// MCPU-GENERIC-RVA20U64: "-target-cpu" "generic-rva20u64"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+m"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+a"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+f"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+d"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+c"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+ziccamoa"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+ziccif"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+zicclsm"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+ziccrse"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+zicntr"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+zicsr"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+za128rs"
+// MCPU-GENERIC-RVA20U64-SAME: "-target-abi" "lp64d"
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva20s64 | 
FileCheck -check-prefix=MCPU-GENERIC-RVA20S64 %s
+// MCPU-GENERIC-RVA20S64: "-target-cpu" "generic-rva20s64"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+m"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+a"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+f"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+d"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+c"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ziccamoa"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ziccif"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zicclsm"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ziccrse"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zicntr"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zicsr"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zifencei"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+za128rs"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ssccptr"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+sstvala"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+sstvecd"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+svade"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+svbare"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-abi" "lp64d"
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva22u64 | 
FileCheck -check-prefix=MCPU-GENERIC-RVA22U64 %s
+// MCPU-GENERIC-RVA22U64: "-target-cpu" "generic-rva22u64"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+m"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+a"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+f"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+d"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+c"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zic64b"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zicbom"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zicbop"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature"

[llvm-branch-commits] [clang] [llvm] [RISCV] Add subtarget features for profiles (PR #84877)

2024-04-26 Thread Brandon Wu via llvm-branch-commits 


@@ -0,0 +1,204 @@
+//===-- RISCVProfiles.td - RISC-V Profiles -*- tablegen 
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+class RISCVProfile features>
+: SubtargetFeaturehttps://github.com/llvm/llvm-project/pull/84877
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[llvm-branch-commits] [clang] [llvm] [RISCV] Add subtarget features for profiles (PR #84877)

2024-04-26 Thread Brandon Wu via llvm-branch-commits 

https://github.com/4vtomat deleted 
https://github.com/llvm/llvm-project/pull/84877
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[llvm-branch-commits] [clang] [llvm] [RISCV] Add subtarget features for profiles (PR #84877)

2024-04-26 Thread Brandon Wu via llvm-branch-commits 

https://github.com/4vtomat edited 
https://github.com/llvm/llvm-project/pull/84877
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[llvm-branch-commits] [clang] [llvm] [RISCV] Add subtarget features for profiles (PR #84877)

2024-04-26 Thread Brandon Wu via llvm-branch-commits 


@@ -0,0 +1,204 @@
+//===-- RISCVProfiles.td - RISC-V Profiles -*- tablegen 
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+class RISCVProfile features>
+: SubtargetFeaturehttps://github.com/llvm/llvm-project/pull/84877
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[llvm-branch-commits] [clang] [llvm] [RISCV] Add subtarget features for profiles (PR #84877)

2024-04-26 Thread Brandon Wu via llvm-branch-commits 


@@ -0,0 +1,204 @@
+//===-- RISCVProfiles.td - RISC-V Profiles -*- tablegen 
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+class RISCVProfile features>
+: SubtargetFeaturehttps://github.com/llvm/llvm-project/pull/84877
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[llvm-branch-commits] [clang] [llvm] [RISCV] Add subtarget features for profiles (PR #84877)

2024-04-26 Thread Kito Cheng via llvm-branch-commits 


@@ -65,10 +65,27 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
 VentanaVeyron,
   };
   // clang-format on
+
+  enum RISCVProfileEnum : uint8_t {
+Unspecified,
+RVI20U32,
+RVI20U64,
+RVA20U64,
+RVA20S64,
+RVA22U64,
+RVA22S64,
+RVA23U64,
+RVA23S64,
+RVB23U64,
+RVB23S64,
+RVM23U32,
+  };
+
 private:
   virtual void anchor();
 
   RISCVProcFamilyEnum RISCVProcFamily = Others;
+  RISCVProfileEnum RISCVProfile = Unspecified;

kito-cheng wrote:

Same 

https://github.com/llvm/llvm-project/pull/84877
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[llvm-branch-commits] [clang] [llvm] [RISCV] Add subtarget features for profiles (PR #84877)

2024-04-26 Thread Kito Cheng via llvm-branch-commits 


@@ -65,10 +65,27 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
 VentanaVeyron,
   };
   // clang-format on
+
+  enum RISCVProfileEnum : uint8_t {

kito-cheng wrote:

This can remove 

https://github.com/llvm/llvm-project/pull/84877
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[llvm-branch-commits] [clang] [llvm] [RISCV] Add subtarget features for profiles (PR #84877)

2024-04-26 Thread Pengcheng Wang via llvm-branch-commits 

https://github.com/wangpc-pp updated 
https://github.com/llvm/llvm-project/pull/84877

>From ec68548a470d6d9032a900a725e95b92691657b2 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng 
Date: Tue, 12 Mar 2024 14:28:09 +0800
Subject: [PATCH 1/4] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
 =?UTF-8?q?itial=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Created using spr 1.3.4
---
 clang/test/Driver/riscv-cpus.c| 319 ++
 clang/test/Misc/target-invalid-cpu-note.c |   8 +-
 llvm/lib/Target/RISCV/RISCVProcessors.td  | 224 ++-
 3 files changed, 539 insertions(+), 12 deletions(-)

diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index ff2bd6f7c8ba34..a285f0f9c41f54 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -302,3 +302,322 @@
 
 // RUN: not %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv32 
-march=rv64i | FileCheck -check-prefix=MISMATCH-ARCH %s
 // MISMATCH-ARCH: cpu 'generic-rv32' does not support rv64
+
+// Check profile CPUs
+
+// RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=generic-rvi20u32 | 
FileCheck -check-prefix=MCPU-GENERIC-RVI20U32 %s
+// MCPU-GENERIC-RVI20U32: "-target-cpu" "generic-rvi20u32"
+// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-a"
+// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-c"
+// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-d"
+// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-f"
+// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-m"
+// MCPU-GENERIC-RVI20U32-SAME: "-target-abi" "ilp32"
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rvi20u64 | 
FileCheck -check-prefix=MCPU-GENERIC-RVI20U64 %s
+// MCPU-GENERIC-RVI20U64: "-target-cpu" "generic-rvi20u64"
+// MCPU-GENERIC-RVI20U64: "-target-feature" "-a"
+// MCPU-GENERIC-RVI20U64: "-target-feature" "-c"
+// MCPU-GENERIC-RVI20U64: "-target-feature" "-d"
+// MCPU-GENERIC-RVI20U64: "-target-feature" "-f"
+// MCPU-GENERIC-RVI20U64: "-target-feature" "-m"
+// MCPU-GENERIC-RVI20U64-SAME: "-target-abi" "lp64"
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva20u64 | 
FileCheck -check-prefix=MCPU-GENERIC-RVA20U64 %s
+// MCPU-GENERIC-RVA20U64: "-target-cpu" "generic-rva20u64"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+m"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+a"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+f"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+d"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+c"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+ziccamoa"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+ziccif"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+zicclsm"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+ziccrse"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+zicntr"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+zicsr"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+za128rs"
+// MCPU-GENERIC-RVA20U64-SAME: "-target-abi" "lp64d"
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva20s64 | 
FileCheck -check-prefix=MCPU-GENERIC-RVA20S64 %s
+// MCPU-GENERIC-RVA20S64: "-target-cpu" "generic-rva20s64"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+m"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+a"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+f"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+d"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+c"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ziccamoa"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ziccif"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zicclsm"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ziccrse"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zicntr"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zicsr"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zifencei"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+za128rs"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ssccptr"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+sstvala"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+sstvecd"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+svade"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+svbare"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-abi" "lp64d"
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva22u64 | 
FileCheck -check-prefix=MCPU-GENERIC-RVA22U64 %s
+// MCPU-GENERIC-RVA22U64: "-target-cpu" "generic-rva22u64"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+m"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+a"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+f"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+d"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+c"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zic64b"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zicbom"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zicbop"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature"

[llvm-branch-commits] [clang] [llvm] [RISCV] Add subtarget features for profiles (PR #84877)

2024-04-26 Thread Kito Cheng via llvm-branch-commits 


@@ -138,6 +155,8 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
   /// initializeProperties().
   RISCVProcFamilyEnum getProcFamily() const { return RISCVProcFamily; }
 
+  RISCVProfileEnum getRISCVProfile() const { return RISCVProfile; }
+

kito-cheng wrote:

Yeah, I incline to remove that for now since no user yet :)

https://github.com/llvm/llvm-project/pull/84877
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[llvm-branch-commits] [clang] [llvm] [RISCV] Add subtarget features for profiles (PR #84877)

2024-04-26 Thread Pengcheng Wang via llvm-branch-commits 

https://github.com/wangpc-pp updated 
https://github.com/llvm/llvm-project/pull/84877

>From ec68548a470d6d9032a900a725e95b92691657b2 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng 
Date: Tue, 12 Mar 2024 14:28:09 +0800
Subject: [PATCH 1/3] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
 =?UTF-8?q?itial=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Created using spr 1.3.4
---
 clang/test/Driver/riscv-cpus.c| 319 ++
 clang/test/Misc/target-invalid-cpu-note.c |   8 +-
 llvm/lib/Target/RISCV/RISCVProcessors.td  | 224 ++-
 3 files changed, 539 insertions(+), 12 deletions(-)

diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index ff2bd6f7c8ba34..a285f0f9c41f54 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -302,3 +302,322 @@
 
 // RUN: not %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv32 
-march=rv64i | FileCheck -check-prefix=MISMATCH-ARCH %s
 // MISMATCH-ARCH: cpu 'generic-rv32' does not support rv64
+
+// Check profile CPUs
+
+// RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=generic-rvi20u32 | 
FileCheck -check-prefix=MCPU-GENERIC-RVI20U32 %s
+// MCPU-GENERIC-RVI20U32: "-target-cpu" "generic-rvi20u32"
+// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-a"
+// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-c"
+// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-d"
+// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-f"
+// MCPU-GENERIC-RVI20U32-SAME: "-target-feature" "-m"
+// MCPU-GENERIC-RVI20U32-SAME: "-target-abi" "ilp32"
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rvi20u64 | 
FileCheck -check-prefix=MCPU-GENERIC-RVI20U64 %s
+// MCPU-GENERIC-RVI20U64: "-target-cpu" "generic-rvi20u64"
+// MCPU-GENERIC-RVI20U64: "-target-feature" "-a"
+// MCPU-GENERIC-RVI20U64: "-target-feature" "-c"
+// MCPU-GENERIC-RVI20U64: "-target-feature" "-d"
+// MCPU-GENERIC-RVI20U64: "-target-feature" "-f"
+// MCPU-GENERIC-RVI20U64: "-target-feature" "-m"
+// MCPU-GENERIC-RVI20U64-SAME: "-target-abi" "lp64"
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva20u64 | 
FileCheck -check-prefix=MCPU-GENERIC-RVA20U64 %s
+// MCPU-GENERIC-RVA20U64: "-target-cpu" "generic-rva20u64"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+m"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+a"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+f"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+d"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+c"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+ziccamoa"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+ziccif"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+zicclsm"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+ziccrse"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+zicntr"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+zicsr"
+// MCPU-GENERIC-RVA20U64: "-target-feature" "+za128rs"
+// MCPU-GENERIC-RVA20U64-SAME: "-target-abi" "lp64d"
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva20s64 | 
FileCheck -check-prefix=MCPU-GENERIC-RVA20S64 %s
+// MCPU-GENERIC-RVA20S64: "-target-cpu" "generic-rva20s64"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+m"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+a"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+f"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+d"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+c"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ziccamoa"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ziccif"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zicclsm"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ziccrse"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zicntr"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zicsr"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+zifencei"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+za128rs"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+ssccptr"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+sstvala"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+sstvecd"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+svade"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-feature" "+svbare"
+// MCPU-GENERIC-RVA20S64-SAME: "-target-abi" "lp64d"
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=generic-rva22u64 | 
FileCheck -check-prefix=MCPU-GENERIC-RVA22U64 %s
+// MCPU-GENERIC-RVA22U64: "-target-cpu" "generic-rva22u64"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+m"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+a"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+f"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+d"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+c"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zic64b"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zicbom"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature" "+zicbop"
+// MCPU-GENERIC-RVA22U64-SAME: "-target-feature"

[llvm-branch-commits] [clang] [llvm] [RISCV] Add subtarget features for profiles (PR #84877)

2024-04-26 Thread Pengcheng Wang via llvm-branch-commits 

https://github.com/wangpc-pp edited 
https://github.com/llvm/llvm-project/pull/84877
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