[llvm-branch-commits] [llvm] [AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (PR #187400)
https://github.com/jthackray updated
https://github.com/llvm/llvm-project/pull/187400
>From 84d6359f34146408b02fca179ff2a2a77c4486e0 Mon Sep 17 00:00:00 2001
From: Jonathan Thackray
Date: Wed, 18 Mar 2026 20:54:50 +
Subject: [PATCH 1/7] [AArch64][llvm] Separate TLBI-only feature gating from
TLBIP aliases
Refactor the TLBI system operand definitions so that TLBI and TLBIP
records are emitted through separate helper multiclasses, whilst keeping
the table layout readable.
The feature-scoped wrappers now apply FeatureTLB_RMI, FeatureRME, and
FeatureTLBIW only to TLBI records (it was previously incorrectly also
applied to TLBIP instructions), while TLBIP aliases remain gated only
by FeatureD128, including their nXS forms.
Update testcases accordingly.
---
.../Target/AArch64/AArch64SystemOperands.td | 155 +++---
llvm/test/MC/AArch64/armv9a-tlbip.s | 17 +-
2 files changed, 101 insertions(+), 71 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
index 8129dde0658cf..73478d3491995 100644
--- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
+++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
@@ -924,6 +924,39 @@ multiclass TLBI op1,
bits<4> crn, bits<4> crm
}
}
+multiclass TLBIP_Base op1, bits<4> crn, bits<4> crm,
+ bits<3> op2, int reguse = REG_REQUIRED,
+ list extra_requires = ["AArch64::FeatureD128"]> {
+ foreach nxs = [0, 1] in {
+// TLBIP instructions aren't gated by FeatureXS like TLBI ones
+defvar VariantName = !if(nxs, !strconcat(name, "nXS"), name);
+def : TLBIPEntry {
+ let Encoding{7} = nxs;
+ let ExtraRequires = extra_requires;
+}
+ }
+}
+
+multiclass TLBI op1, bits<4> crn,
+bits<4> crm, bits<3> op2, int reguse = REG_REQUIRED> {
+ defm : TLBI_Base;
+ if !eq(hasTLBIP, true) then {
+defm : TLBIP_Base;
+ }
+}
+
+multiclass TLBI_RMI op1, bits<4> crn,
+bits<4> crm, bits<3> op2, int reguse = REG_REQUIRED> {
+ let Requires = ["AArch64::FeatureTLB_RMI"] in {
+defm : TLBI_Base;
+ }
+ // TLBIP instructions aren't gated by FeatureTLB_RMI
+ if !eq(hasTLBIP, true) then {
+defm : TLBIP_Base;
+ }
+}
+
+// TLBI and TLBIP instructions encodings
// hasTLBIP op1CRn CRm op2reguse
defm : TLBI<"IPAS2E1IS",1, 0b100, 0b1000, 0b, 0b001, REG_REQUIRED>;
defm : TLBI<"IPAS2LE1IS", 1, 0b100, 0b1000, 0b, 0b101, REG_REQUIRED>;
@@ -958,76 +991,74 @@ defm : TLBI<"VALE3",1, 0b110, 0b1000, 0b0111,
0b101, REG_REQUIRED>;
defm : TLBI<"VMALLS12E1", 0, 0b100, 0b1000, 0b0111, 0b110, REG_NONE>;
defm : TLBI<"VAALE1", 1, 0b000, 0b1000, 0b0111, 0b111, REG_REQUIRED>;
-// Armv8.4-A Translation Lookaside Buffer Instructions (TLBI)
-let Requires = ["AArch64::FeatureTLB_RMI"] in {
+// Armv8.4-A Translation Lookaside Buffer Instructions (TLBI and TLBIP)
// Armv8.4-A Outer Sharable TLB Maintenance instructions:
-// hasTLBIP op1CRn CRm op2reguse
-defm : TLBI<"VMALLE1OS",0, 0b000, 0b1000, 0b0001, 0b000, REG_OPTIONAL>;
-defm : TLBI<"VAE1OS", 1, 0b000, 0b1000, 0b0001, 0b001, REG_REQUIRED>;
-defm : TLBI<"ASIDE1OS", 0, 0b000, 0b1000, 0b0001, 0b010, REG_REQUIRED>;
-defm : TLBI<"VAAE1OS", 1, 0b000, 0b1000, 0b0001, 0b011, REG_REQUIRED>;
-defm : TLBI<"VALE1OS", 1, 0b000, 0b1000, 0b0001, 0b101, REG_REQUIRED>;
-defm : TLBI<"VAALE1OS", 1, 0b000, 0b1000, 0b0001, 0b111, REG_REQUIRED>;
-defm : TLBI<"IPAS2E1OS",1, 0b100, 0b1000, 0b0100, 0b000, REG_REQUIRED>;
-defm : TLBI<"IPAS2LE1OS", 1, 0b100, 0b1000, 0b0100, 0b100, REG_REQUIRED>;
-defm : TLBI<"VAE2OS", 1, 0b100, 0b1000, 0b0001, 0b001, REG_REQUIRED>;
-defm : TLBI<"VALE2OS", 1, 0b100, 0b1000, 0b0001, 0b101, REG_REQUIRED>;
-defm : TLBI<"VMALLS12E1OS", 0, 0b100, 0b1000, 0b0001, 0b110, REG_OPTIONAL>;
-defm : TLBI<"VAE3OS", 1, 0b110, 0b1000, 0b0001, 0b001, REG_REQUIRED>;
-defm : TLBI<"VALE3OS", 1, 0b110, 0b1000, 0b0001, 0b101, REG_REQUIRED>;
-defm : TLBI<"ALLE2OS", 0, 0b100, 0b1000, 0b0001, 0b000, REG_OPTIONAL>;
-defm : TLBI<"ALLE1OS", 0, 0b100, 0b1000, 0b0001, 0b100, REG_OPTIONAL>;
-defm : TLBI<"ALLE3OS", 0, 0b110, 0b1000, 0b0001, 0b000, REG_OPTIONAL>;
-
-// Armv8.4-A TLB Range Maintenance instructions:
-// hasTLBIP op1CRn CRm op2
-defm : TLBI<"RVAE1",1, 0b000, 0b1000, 0b0110, 0b001, REG_REQUIRED>;
-defm : TLBI<"RVAAE1", 1, 0b000, 0b1000, 0b0110, 0b011, REG_REQUIRED>;
-defm : TLBI<"RVALE1", 1, 0b000, 0b1000, 0b0110, 0b101, REG_REQUIRED>;
-defm : TLBI<"RVAALE1", 1, 0b000, 0b1000, 0b0110, 0b111, REG_REQUIRED>;
-defm : TLBI<"RVAE1IS", 1, 0b000, 0b1000, 0b0010, 0b001, REG_REQUIRED>;
-defm : TLBI<"RVAAE1IS", 1, 0b000, 0b1000, 0b0010, 0b011, REG_REQUIRED>;
-defm : TLBI<"RVALE1IS", 1, 0b000, 0b1000, 0b0010, 0b101, REG_REQUIRED>;
-defm :
[llvm-branch-commits] [llvm] [AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (PR #187400)
https://github.com/jthackray updated
https://github.com/llvm/llvm-project/pull/187400
>From 84d6359f34146408b02fca179ff2a2a77c4486e0 Mon Sep 17 00:00:00 2001
From: Jonathan Thackray
Date: Wed, 18 Mar 2026 20:54:50 +
Subject: [PATCH 1/7] [AArch64][llvm] Separate TLBI-only feature gating from
TLBIP aliases
Refactor the TLBI system operand definitions so that TLBI and TLBIP
records are emitted through separate helper multiclasses, whilst keeping
the table layout readable.
The feature-scoped wrappers now apply FeatureTLB_RMI, FeatureRME, and
FeatureTLBIW only to TLBI records (it was previously incorrectly also
applied to TLBIP instructions), while TLBIP aliases remain gated only
by FeatureD128, including their nXS forms.
Update testcases accordingly.
---
.../Target/AArch64/AArch64SystemOperands.td | 155 +++---
llvm/test/MC/AArch64/armv9a-tlbip.s | 17 +-
2 files changed, 101 insertions(+), 71 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
index 8129dde0658cf..73478d3491995 100644
--- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
+++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
@@ -924,6 +924,39 @@ multiclass TLBI op1,
bits<4> crn, bits<4> crm
}
}
+multiclass TLBIP_Base op1, bits<4> crn, bits<4> crm,
+ bits<3> op2, int reguse = REG_REQUIRED,
+ list extra_requires = ["AArch64::FeatureD128"]> {
+ foreach nxs = [0, 1] in {
+// TLBIP instructions aren't gated by FeatureXS like TLBI ones
+defvar VariantName = !if(nxs, !strconcat(name, "nXS"), name);
+def : TLBIPEntry {
+ let Encoding{7} = nxs;
+ let ExtraRequires = extra_requires;
+}
+ }
+}
+
+multiclass TLBI op1, bits<4> crn,
+bits<4> crm, bits<3> op2, int reguse = REG_REQUIRED> {
+ defm : TLBI_Base;
+ if !eq(hasTLBIP, true) then {
+defm : TLBIP_Base;
+ }
+}
+
+multiclass TLBI_RMI op1, bits<4> crn,
+bits<4> crm, bits<3> op2, int reguse = REG_REQUIRED> {
+ let Requires = ["AArch64::FeatureTLB_RMI"] in {
+defm : TLBI_Base;
+ }
+ // TLBIP instructions aren't gated by FeatureTLB_RMI
+ if !eq(hasTLBIP, true) then {
+defm : TLBIP_Base;
+ }
+}
+
+// TLBI and TLBIP instructions encodings
// hasTLBIP op1CRn CRm op2reguse
defm : TLBI<"IPAS2E1IS",1, 0b100, 0b1000, 0b, 0b001, REG_REQUIRED>;
defm : TLBI<"IPAS2LE1IS", 1, 0b100, 0b1000, 0b, 0b101, REG_REQUIRED>;
@@ -958,76 +991,74 @@ defm : TLBI<"VALE3",1, 0b110, 0b1000, 0b0111,
0b101, REG_REQUIRED>;
defm : TLBI<"VMALLS12E1", 0, 0b100, 0b1000, 0b0111, 0b110, REG_NONE>;
defm : TLBI<"VAALE1", 1, 0b000, 0b1000, 0b0111, 0b111, REG_REQUIRED>;
-// Armv8.4-A Translation Lookaside Buffer Instructions (TLBI)
-let Requires = ["AArch64::FeatureTLB_RMI"] in {
+// Armv8.4-A Translation Lookaside Buffer Instructions (TLBI and TLBIP)
// Armv8.4-A Outer Sharable TLB Maintenance instructions:
-// hasTLBIP op1CRn CRm op2reguse
-defm : TLBI<"VMALLE1OS",0, 0b000, 0b1000, 0b0001, 0b000, REG_OPTIONAL>;
-defm : TLBI<"VAE1OS", 1, 0b000, 0b1000, 0b0001, 0b001, REG_REQUIRED>;
-defm : TLBI<"ASIDE1OS", 0, 0b000, 0b1000, 0b0001, 0b010, REG_REQUIRED>;
-defm : TLBI<"VAAE1OS", 1, 0b000, 0b1000, 0b0001, 0b011, REG_REQUIRED>;
-defm : TLBI<"VALE1OS", 1, 0b000, 0b1000, 0b0001, 0b101, REG_REQUIRED>;
-defm : TLBI<"VAALE1OS", 1, 0b000, 0b1000, 0b0001, 0b111, REG_REQUIRED>;
-defm : TLBI<"IPAS2E1OS",1, 0b100, 0b1000, 0b0100, 0b000, REG_REQUIRED>;
-defm : TLBI<"IPAS2LE1OS", 1, 0b100, 0b1000, 0b0100, 0b100, REG_REQUIRED>;
-defm : TLBI<"VAE2OS", 1, 0b100, 0b1000, 0b0001, 0b001, REG_REQUIRED>;
-defm : TLBI<"VALE2OS", 1, 0b100, 0b1000, 0b0001, 0b101, REG_REQUIRED>;
-defm : TLBI<"VMALLS12E1OS", 0, 0b100, 0b1000, 0b0001, 0b110, REG_OPTIONAL>;
-defm : TLBI<"VAE3OS", 1, 0b110, 0b1000, 0b0001, 0b001, REG_REQUIRED>;
-defm : TLBI<"VALE3OS", 1, 0b110, 0b1000, 0b0001, 0b101, REG_REQUIRED>;
-defm : TLBI<"ALLE2OS", 0, 0b100, 0b1000, 0b0001, 0b000, REG_OPTIONAL>;
-defm : TLBI<"ALLE1OS", 0, 0b100, 0b1000, 0b0001, 0b100, REG_OPTIONAL>;
-defm : TLBI<"ALLE3OS", 0, 0b110, 0b1000, 0b0001, 0b000, REG_OPTIONAL>;
-
-// Armv8.4-A TLB Range Maintenance instructions:
-// hasTLBIP op1CRn CRm op2
-defm : TLBI<"RVAE1",1, 0b000, 0b1000, 0b0110, 0b001, REG_REQUIRED>;
-defm : TLBI<"RVAAE1", 1, 0b000, 0b1000, 0b0110, 0b011, REG_REQUIRED>;
-defm : TLBI<"RVALE1", 1, 0b000, 0b1000, 0b0110, 0b101, REG_REQUIRED>;
-defm : TLBI<"RVAALE1", 1, 0b000, 0b1000, 0b0110, 0b111, REG_REQUIRED>;
-defm : TLBI<"RVAE1IS", 1, 0b000, 0b1000, 0b0010, 0b001, REG_REQUIRED>;
-defm : TLBI<"RVAAE1IS", 1, 0b000, 0b1000, 0b0010, 0b011, REG_REQUIRED>;
-defm : TLBI<"RVALE1IS", 1, 0b000, 0b1000, 0b0010, 0b101, REG_REQUIRED>;
-defm :
[llvm-branch-commits] [llvm] [AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (PR #187400)
https://github.com/jthackray updated
https://github.com/llvm/llvm-project/pull/187400
>From 1cb2d28037cc9c45ce4f277b290cd3cc9914d8d2 Mon Sep 17 00:00:00 2001
From: Jonathan Thackray
Date: Wed, 18 Mar 2026 20:54:50 +
Subject: [PATCH 1/7] [AArch64][llvm] Separate TLBI-only feature gating from
TLBIP aliases
Refactor the TLBI system operand definitions so that TLBI and TLBIP
records are emitted through separate helper multiclasses, whilst keeping
the table layout readable.
The feature-scoped wrappers now apply FeatureTLB_RMI, FeatureRME, and
FeatureTLBIW only to TLBI records (it was previously incorrectly also
applied to TLBIP instructions), while TLBIP aliases remain gated only
by FeatureD128, including their nXS forms.
Update testcases accordingly.
---
.../Target/AArch64/AArch64SystemOperands.td | 155 +++---
llvm/test/MC/AArch64/armv9a-tlbip.s | 17 +-
2 files changed, 101 insertions(+), 71 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
index 2dfc7f8fbd597..71b3a87c2a1f2 100644
--- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
+++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
@@ -926,6 +926,39 @@ multiclass TLBI op1,
bits<4> crn, bits<4> crm
}
}
+multiclass TLBIP_Base op1, bits<4> crn, bits<4> crm,
+ bits<3> op2, int reguse = REG_REQUIRED,
+ list extra_requires = ["AArch64::FeatureD128"]> {
+ foreach nxs = [0, 1] in {
+// TLBIP instructions aren't gated by FeatureXS like TLBI ones
+defvar VariantName = !if(nxs, !strconcat(name, "nXS"), name);
+def : TLBIPEntry {
+ let Encoding{7} = nxs;
+ let ExtraRequires = extra_requires;
+}
+ }
+}
+
+multiclass TLBI op1, bits<4> crn,
+bits<4> crm, bits<3> op2, int reguse = REG_REQUIRED> {
+ defm : TLBI_Base;
+ if !eq(hasTLBIP, true) then {
+defm : TLBIP_Base;
+ }
+}
+
+multiclass TLBI_RMI op1, bits<4> crn,
+bits<4> crm, bits<3> op2, int reguse = REG_REQUIRED> {
+ let Requires = ["AArch64::FeatureTLB_RMI"] in {
+defm : TLBI_Base;
+ }
+ // TLBIP instructions aren't gated by FeatureTLB_RMI
+ if !eq(hasTLBIP, true) then {
+defm : TLBIP_Base;
+ }
+}
+
+// TLBI and TLBIP instructions encodings
// hasTLBIP op1CRn CRm op2reguse
defm : TLBI<"IPAS2E1IS",1, 0b100, 0b1000, 0b, 0b001, REG_REQUIRED>;
defm : TLBI<"IPAS2LE1IS", 1, 0b100, 0b1000, 0b, 0b101, REG_REQUIRED>;
@@ -960,76 +993,74 @@ defm : TLBI<"VALE3",1, 0b110, 0b1000, 0b0111,
0b101, REG_REQUIRED>;
defm : TLBI<"VMALLS12E1", 0, 0b100, 0b1000, 0b0111, 0b110, REG_NONE>;
defm : TLBI<"VAALE1", 1, 0b000, 0b1000, 0b0111, 0b111, REG_REQUIRED>;
-// Armv8.4-A Translation Lookaside Buffer Instructions (TLBI)
-let Requires = ["AArch64::FeatureTLB_RMI"] in {
+// Armv8.4-A Translation Lookaside Buffer Instructions (TLBI and TLBIP)
// Armv8.4-A Outer Sharable TLB Maintenance instructions:
-// hasTLBIP op1CRn CRm op2reguse
-defm : TLBI<"VMALLE1OS",0, 0b000, 0b1000, 0b0001, 0b000, REG_OPTIONAL>;
-defm : TLBI<"VAE1OS", 1, 0b000, 0b1000, 0b0001, 0b001, REG_REQUIRED>;
-defm : TLBI<"ASIDE1OS", 0, 0b000, 0b1000, 0b0001, 0b010, REG_REQUIRED>;
-defm : TLBI<"VAAE1OS", 1, 0b000, 0b1000, 0b0001, 0b011, REG_REQUIRED>;
-defm : TLBI<"VALE1OS", 1, 0b000, 0b1000, 0b0001, 0b101, REG_REQUIRED>;
-defm : TLBI<"VAALE1OS", 1, 0b000, 0b1000, 0b0001, 0b111, REG_REQUIRED>;
-defm : TLBI<"IPAS2E1OS",1, 0b100, 0b1000, 0b0100, 0b000, REG_REQUIRED>;
-defm : TLBI<"IPAS2LE1OS", 1, 0b100, 0b1000, 0b0100, 0b100, REG_REQUIRED>;
-defm : TLBI<"VAE2OS", 1, 0b100, 0b1000, 0b0001, 0b001, REG_REQUIRED>;
-defm : TLBI<"VALE2OS", 1, 0b100, 0b1000, 0b0001, 0b101, REG_REQUIRED>;
-defm : TLBI<"VMALLS12E1OS", 0, 0b100, 0b1000, 0b0001, 0b110, REG_OPTIONAL>;
-defm : TLBI<"VAE3OS", 1, 0b110, 0b1000, 0b0001, 0b001, REG_REQUIRED>;
-defm : TLBI<"VALE3OS", 1, 0b110, 0b1000, 0b0001, 0b101, REG_REQUIRED>;
-defm : TLBI<"ALLE2OS", 0, 0b100, 0b1000, 0b0001, 0b000, REG_OPTIONAL>;
-defm : TLBI<"ALLE1OS", 0, 0b100, 0b1000, 0b0001, 0b100, REG_OPTIONAL>;
-defm : TLBI<"ALLE3OS", 0, 0b110, 0b1000, 0b0001, 0b000, REG_OPTIONAL>;
-
-// Armv8.4-A TLB Range Maintenance instructions:
-// hasTLBIP op1CRn CRm op2
-defm : TLBI<"RVAE1",1, 0b000, 0b1000, 0b0110, 0b001, REG_REQUIRED>;
-defm : TLBI<"RVAAE1", 1, 0b000, 0b1000, 0b0110, 0b011, REG_REQUIRED>;
-defm : TLBI<"RVALE1", 1, 0b000, 0b1000, 0b0110, 0b101, REG_REQUIRED>;
-defm : TLBI<"RVAALE1", 1, 0b000, 0b1000, 0b0110, 0b111, REG_REQUIRED>;
-defm : TLBI<"RVAE1IS", 1, 0b000, 0b1000, 0b0010, 0b001, REG_REQUIRED>;
-defm : TLBI<"RVAAE1IS", 1, 0b000, 0b1000, 0b0010, 0b011, REG_REQUIRED>;
-defm : TLBI<"RVALE1IS", 1, 0b000, 0b1000, 0b0010, 0b101, REG_REQUIRED>;
-defm :
[llvm-branch-commits] [llvm] [AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (PR #187400)
https://github.com/jthackray updated
https://github.com/llvm/llvm-project/pull/187400
>From 1cb2d28037cc9c45ce4f277b290cd3cc9914d8d2 Mon Sep 17 00:00:00 2001
From: Jonathan Thackray
Date: Wed, 18 Mar 2026 20:54:50 +
Subject: [PATCH 1/7] [AArch64][llvm] Separate TLBI-only feature gating from
TLBIP aliases
Refactor the TLBI system operand definitions so that TLBI and TLBIP
records are emitted through separate helper multiclasses, whilst keeping
the table layout readable.
The feature-scoped wrappers now apply FeatureTLB_RMI, FeatureRME, and
FeatureTLBIW only to TLBI records (it was previously incorrectly also
applied to TLBIP instructions), while TLBIP aliases remain gated only
by FeatureD128, including their nXS forms.
Update testcases accordingly.
---
.../Target/AArch64/AArch64SystemOperands.td | 155 +++---
llvm/test/MC/AArch64/armv9a-tlbip.s | 17 +-
2 files changed, 101 insertions(+), 71 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
index 2dfc7f8fbd597..71b3a87c2a1f2 100644
--- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
+++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
@@ -926,6 +926,39 @@ multiclass TLBI op1,
bits<4> crn, bits<4> crm
}
}
+multiclass TLBIP_Base op1, bits<4> crn, bits<4> crm,
+ bits<3> op2, int reguse = REG_REQUIRED,
+ list extra_requires = ["AArch64::FeatureD128"]> {
+ foreach nxs = [0, 1] in {
+// TLBIP instructions aren't gated by FeatureXS like TLBI ones
+defvar VariantName = !if(nxs, !strconcat(name, "nXS"), name);
+def : TLBIPEntry {
+ let Encoding{7} = nxs;
+ let ExtraRequires = extra_requires;
+}
+ }
+}
+
+multiclass TLBI op1, bits<4> crn,
+bits<4> crm, bits<3> op2, int reguse = REG_REQUIRED> {
+ defm : TLBI_Base;
+ if !eq(hasTLBIP, true) then {
+defm : TLBIP_Base;
+ }
+}
+
+multiclass TLBI_RMI op1, bits<4> crn,
+bits<4> crm, bits<3> op2, int reguse = REG_REQUIRED> {
+ let Requires = ["AArch64::FeatureTLB_RMI"] in {
+defm : TLBI_Base;
+ }
+ // TLBIP instructions aren't gated by FeatureTLB_RMI
+ if !eq(hasTLBIP, true) then {
+defm : TLBIP_Base;
+ }
+}
+
+// TLBI and TLBIP instructions encodings
// hasTLBIP op1CRn CRm op2reguse
defm : TLBI<"IPAS2E1IS",1, 0b100, 0b1000, 0b, 0b001, REG_REQUIRED>;
defm : TLBI<"IPAS2LE1IS", 1, 0b100, 0b1000, 0b, 0b101, REG_REQUIRED>;
@@ -960,76 +993,74 @@ defm : TLBI<"VALE3",1, 0b110, 0b1000, 0b0111,
0b101, REG_REQUIRED>;
defm : TLBI<"VMALLS12E1", 0, 0b100, 0b1000, 0b0111, 0b110, REG_NONE>;
defm : TLBI<"VAALE1", 1, 0b000, 0b1000, 0b0111, 0b111, REG_REQUIRED>;
-// Armv8.4-A Translation Lookaside Buffer Instructions (TLBI)
-let Requires = ["AArch64::FeatureTLB_RMI"] in {
+// Armv8.4-A Translation Lookaside Buffer Instructions (TLBI and TLBIP)
// Armv8.4-A Outer Sharable TLB Maintenance instructions:
-// hasTLBIP op1CRn CRm op2reguse
-defm : TLBI<"VMALLE1OS",0, 0b000, 0b1000, 0b0001, 0b000, REG_OPTIONAL>;
-defm : TLBI<"VAE1OS", 1, 0b000, 0b1000, 0b0001, 0b001, REG_REQUIRED>;
-defm : TLBI<"ASIDE1OS", 0, 0b000, 0b1000, 0b0001, 0b010, REG_REQUIRED>;
-defm : TLBI<"VAAE1OS", 1, 0b000, 0b1000, 0b0001, 0b011, REG_REQUIRED>;
-defm : TLBI<"VALE1OS", 1, 0b000, 0b1000, 0b0001, 0b101, REG_REQUIRED>;
-defm : TLBI<"VAALE1OS", 1, 0b000, 0b1000, 0b0001, 0b111, REG_REQUIRED>;
-defm : TLBI<"IPAS2E1OS",1, 0b100, 0b1000, 0b0100, 0b000, REG_REQUIRED>;
-defm : TLBI<"IPAS2LE1OS", 1, 0b100, 0b1000, 0b0100, 0b100, REG_REQUIRED>;
-defm : TLBI<"VAE2OS", 1, 0b100, 0b1000, 0b0001, 0b001, REG_REQUIRED>;
-defm : TLBI<"VALE2OS", 1, 0b100, 0b1000, 0b0001, 0b101, REG_REQUIRED>;
-defm : TLBI<"VMALLS12E1OS", 0, 0b100, 0b1000, 0b0001, 0b110, REG_OPTIONAL>;
-defm : TLBI<"VAE3OS", 1, 0b110, 0b1000, 0b0001, 0b001, REG_REQUIRED>;
-defm : TLBI<"VALE3OS", 1, 0b110, 0b1000, 0b0001, 0b101, REG_REQUIRED>;
-defm : TLBI<"ALLE2OS", 0, 0b100, 0b1000, 0b0001, 0b000, REG_OPTIONAL>;
-defm : TLBI<"ALLE1OS", 0, 0b100, 0b1000, 0b0001, 0b100, REG_OPTIONAL>;
-defm : TLBI<"ALLE3OS", 0, 0b110, 0b1000, 0b0001, 0b000, REG_OPTIONAL>;
-
-// Armv8.4-A TLB Range Maintenance instructions:
-// hasTLBIP op1CRn CRm op2
-defm : TLBI<"RVAE1",1, 0b000, 0b1000, 0b0110, 0b001, REG_REQUIRED>;
-defm : TLBI<"RVAAE1", 1, 0b000, 0b1000, 0b0110, 0b011, REG_REQUIRED>;
-defm : TLBI<"RVALE1", 1, 0b000, 0b1000, 0b0110, 0b101, REG_REQUIRED>;
-defm : TLBI<"RVAALE1", 1, 0b000, 0b1000, 0b0110, 0b111, REG_REQUIRED>;
-defm : TLBI<"RVAE1IS", 1, 0b000, 0b1000, 0b0010, 0b001, REG_REQUIRED>;
-defm : TLBI<"RVAAE1IS", 1, 0b000, 0b1000, 0b0010, 0b011, REG_REQUIRED>;
-defm : TLBI<"RVALE1IS", 1, 0b000, 0b1000, 0b0010, 0b101, REG_REQUIRED>;
-defm :
[llvm-branch-commits] [llvm] [AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (PR #187400)
https://github.com/jthackray updated
https://github.com/llvm/llvm-project/pull/187400
>From c1b4fa214945965774b92d324215bdca87e2e832 Mon Sep 17 00:00:00 2001
From: Jonathan Thackray
Date: Wed, 18 Mar 2026 20:54:50 +
Subject: [PATCH 1/7] [AArch64][llvm] Separate TLBI-only feature gating from
TLBIP aliases
Refactor the TLBI system operand definitions so that TLBI and TLBIP
records are emitted through separate helper multiclasses, whilst keeping
the table layout readable.
The feature-scoped wrappers now apply FeatureTLB_RMI, FeatureRME, and
FeatureTLBIW only to TLBI records (it was previously incorrectly also
applied to TLBIP instructions), while TLBIP aliases remain gated only
by FeatureD128, including their nXS forms.
Update testcases accordingly.
---
.../Target/AArch64/AArch64SystemOperands.td | 155 +++---
llvm/test/MC/AArch64/armv9a-tlbip.s | 17 +-
2 files changed, 101 insertions(+), 71 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
index 2dfc7f8fbd597..71b3a87c2a1f2 100644
--- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
+++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
@@ -926,6 +926,39 @@ multiclass TLBI op1,
bits<4> crn, bits<4> crm
}
}
+multiclass TLBIP_Base op1, bits<4> crn, bits<4> crm,
+ bits<3> op2, int reguse = REG_REQUIRED,
+ list extra_requires = ["AArch64::FeatureD128"]> {
+ foreach nxs = [0, 1] in {
+// TLBIP instructions aren't gated by FeatureXS like TLBI ones
+defvar VariantName = !if(nxs, !strconcat(name, "nXS"), name);
+def : TLBIPEntry {
+ let Encoding{7} = nxs;
+ let ExtraRequires = extra_requires;
+}
+ }
+}
+
+multiclass TLBI op1, bits<4> crn,
+bits<4> crm, bits<3> op2, int reguse = REG_REQUIRED> {
+ defm : TLBI_Base;
+ if !eq(hasTLBIP, true) then {
+defm : TLBIP_Base;
+ }
+}
+
+multiclass TLBI_RMI op1, bits<4> crn,
+bits<4> crm, bits<3> op2, int reguse = REG_REQUIRED> {
+ let Requires = ["AArch64::FeatureTLB_RMI"] in {
+defm : TLBI_Base;
+ }
+ // TLBIP instructions aren't gated by FeatureTLB_RMI
+ if !eq(hasTLBIP, true) then {
+defm : TLBIP_Base;
+ }
+}
+
+// TLBI and TLBIP instructions encodings
// hasTLBIP op1CRn CRm op2reguse
defm : TLBI<"IPAS2E1IS",1, 0b100, 0b1000, 0b, 0b001, REG_REQUIRED>;
defm : TLBI<"IPAS2LE1IS", 1, 0b100, 0b1000, 0b, 0b101, REG_REQUIRED>;
@@ -960,76 +993,74 @@ defm : TLBI<"VALE3",1, 0b110, 0b1000, 0b0111,
0b101, REG_REQUIRED>;
defm : TLBI<"VMALLS12E1", 0, 0b100, 0b1000, 0b0111, 0b110, REG_NONE>;
defm : TLBI<"VAALE1", 1, 0b000, 0b1000, 0b0111, 0b111, REG_REQUIRED>;
-// Armv8.4-A Translation Lookaside Buffer Instructions (TLBI)
-let Requires = ["AArch64::FeatureTLB_RMI"] in {
+// Armv8.4-A Translation Lookaside Buffer Instructions (TLBI and TLBIP)
// Armv8.4-A Outer Sharable TLB Maintenance instructions:
-// hasTLBIP op1CRn CRm op2reguse
-defm : TLBI<"VMALLE1OS",0, 0b000, 0b1000, 0b0001, 0b000, REG_OPTIONAL>;
-defm : TLBI<"VAE1OS", 1, 0b000, 0b1000, 0b0001, 0b001, REG_REQUIRED>;
-defm : TLBI<"ASIDE1OS", 0, 0b000, 0b1000, 0b0001, 0b010, REG_REQUIRED>;
-defm : TLBI<"VAAE1OS", 1, 0b000, 0b1000, 0b0001, 0b011, REG_REQUIRED>;
-defm : TLBI<"VALE1OS", 1, 0b000, 0b1000, 0b0001, 0b101, REG_REQUIRED>;
-defm : TLBI<"VAALE1OS", 1, 0b000, 0b1000, 0b0001, 0b111, REG_REQUIRED>;
-defm : TLBI<"IPAS2E1OS",1, 0b100, 0b1000, 0b0100, 0b000, REG_REQUIRED>;
-defm : TLBI<"IPAS2LE1OS", 1, 0b100, 0b1000, 0b0100, 0b100, REG_REQUIRED>;
-defm : TLBI<"VAE2OS", 1, 0b100, 0b1000, 0b0001, 0b001, REG_REQUIRED>;
-defm : TLBI<"VALE2OS", 1, 0b100, 0b1000, 0b0001, 0b101, REG_REQUIRED>;
-defm : TLBI<"VMALLS12E1OS", 0, 0b100, 0b1000, 0b0001, 0b110, REG_OPTIONAL>;
-defm : TLBI<"VAE3OS", 1, 0b110, 0b1000, 0b0001, 0b001, REG_REQUIRED>;
-defm : TLBI<"VALE3OS", 1, 0b110, 0b1000, 0b0001, 0b101, REG_REQUIRED>;
-defm : TLBI<"ALLE2OS", 0, 0b100, 0b1000, 0b0001, 0b000, REG_OPTIONAL>;
-defm : TLBI<"ALLE1OS", 0, 0b100, 0b1000, 0b0001, 0b100, REG_OPTIONAL>;
-defm : TLBI<"ALLE3OS", 0, 0b110, 0b1000, 0b0001, 0b000, REG_OPTIONAL>;
-
-// Armv8.4-A TLB Range Maintenance instructions:
-// hasTLBIP op1CRn CRm op2
-defm : TLBI<"RVAE1",1, 0b000, 0b1000, 0b0110, 0b001, REG_REQUIRED>;
-defm : TLBI<"RVAAE1", 1, 0b000, 0b1000, 0b0110, 0b011, REG_REQUIRED>;
-defm : TLBI<"RVALE1", 1, 0b000, 0b1000, 0b0110, 0b101, REG_REQUIRED>;
-defm : TLBI<"RVAALE1", 1, 0b000, 0b1000, 0b0110, 0b111, REG_REQUIRED>;
-defm : TLBI<"RVAE1IS", 1, 0b000, 0b1000, 0b0010, 0b001, REG_REQUIRED>;
-defm : TLBI<"RVAAE1IS", 1, 0b000, 0b1000, 0b0010, 0b011, REG_REQUIRED>;
-defm : TLBI<"RVALE1IS", 1, 0b000, 0b1000, 0b0010, 0b101, REG_REQUIRED>;
-defm :
[llvm-branch-commits] [llvm] [AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (PR #187400)
https://github.com/jthackray updated
https://github.com/llvm/llvm-project/pull/187400
>From c1b4fa214945965774b92d324215bdca87e2e832 Mon Sep 17 00:00:00 2001
From: Jonathan Thackray
Date: Wed, 18 Mar 2026 20:54:50 +
Subject: [PATCH 1/7] [AArch64][llvm] Separate TLBI-only feature gating from
TLBIP aliases
Refactor the TLBI system operand definitions so that TLBI and TLBIP
records are emitted through separate helper multiclasses, whilst keeping
the table layout readable.
The feature-scoped wrappers now apply FeatureTLB_RMI, FeatureRME, and
FeatureTLBIW only to TLBI records (it was previously incorrectly also
applied to TLBIP instructions), while TLBIP aliases remain gated only
by FeatureD128, including their nXS forms.
Update testcases accordingly.
---
.../Target/AArch64/AArch64SystemOperands.td | 155 +++---
llvm/test/MC/AArch64/armv9a-tlbip.s | 17 +-
2 files changed, 101 insertions(+), 71 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
index 2dfc7f8fbd597..71b3a87c2a1f2 100644
--- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
+++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
@@ -926,6 +926,39 @@ multiclass TLBI op1,
bits<4> crn, bits<4> crm
}
}
+multiclass TLBIP_Base op1, bits<4> crn, bits<4> crm,
+ bits<3> op2, int reguse = REG_REQUIRED,
+ list extra_requires = ["AArch64::FeatureD128"]> {
+ foreach nxs = [0, 1] in {
+// TLBIP instructions aren't gated by FeatureXS like TLBI ones
+defvar VariantName = !if(nxs, !strconcat(name, "nXS"), name);
+def : TLBIPEntry {
+ let Encoding{7} = nxs;
+ let ExtraRequires = extra_requires;
+}
+ }
+}
+
+multiclass TLBI op1, bits<4> crn,
+bits<4> crm, bits<3> op2, int reguse = REG_REQUIRED> {
+ defm : TLBI_Base;
+ if !eq(hasTLBIP, true) then {
+defm : TLBIP_Base;
+ }
+}
+
+multiclass TLBI_RMI op1, bits<4> crn,
+bits<4> crm, bits<3> op2, int reguse = REG_REQUIRED> {
+ let Requires = ["AArch64::FeatureTLB_RMI"] in {
+defm : TLBI_Base;
+ }
+ // TLBIP instructions aren't gated by FeatureTLB_RMI
+ if !eq(hasTLBIP, true) then {
+defm : TLBIP_Base;
+ }
+}
+
+// TLBI and TLBIP instructions encodings
// hasTLBIP op1CRn CRm op2reguse
defm : TLBI<"IPAS2E1IS",1, 0b100, 0b1000, 0b, 0b001, REG_REQUIRED>;
defm : TLBI<"IPAS2LE1IS", 1, 0b100, 0b1000, 0b, 0b101, REG_REQUIRED>;
@@ -960,76 +993,74 @@ defm : TLBI<"VALE3",1, 0b110, 0b1000, 0b0111,
0b101, REG_REQUIRED>;
defm : TLBI<"VMALLS12E1", 0, 0b100, 0b1000, 0b0111, 0b110, REG_NONE>;
defm : TLBI<"VAALE1", 1, 0b000, 0b1000, 0b0111, 0b111, REG_REQUIRED>;
-// Armv8.4-A Translation Lookaside Buffer Instructions (TLBI)
-let Requires = ["AArch64::FeatureTLB_RMI"] in {
+// Armv8.4-A Translation Lookaside Buffer Instructions (TLBI and TLBIP)
// Armv8.4-A Outer Sharable TLB Maintenance instructions:
-// hasTLBIP op1CRn CRm op2reguse
-defm : TLBI<"VMALLE1OS",0, 0b000, 0b1000, 0b0001, 0b000, REG_OPTIONAL>;
-defm : TLBI<"VAE1OS", 1, 0b000, 0b1000, 0b0001, 0b001, REG_REQUIRED>;
-defm : TLBI<"ASIDE1OS", 0, 0b000, 0b1000, 0b0001, 0b010, REG_REQUIRED>;
-defm : TLBI<"VAAE1OS", 1, 0b000, 0b1000, 0b0001, 0b011, REG_REQUIRED>;
-defm : TLBI<"VALE1OS", 1, 0b000, 0b1000, 0b0001, 0b101, REG_REQUIRED>;
-defm : TLBI<"VAALE1OS", 1, 0b000, 0b1000, 0b0001, 0b111, REG_REQUIRED>;
-defm : TLBI<"IPAS2E1OS",1, 0b100, 0b1000, 0b0100, 0b000, REG_REQUIRED>;
-defm : TLBI<"IPAS2LE1OS", 1, 0b100, 0b1000, 0b0100, 0b100, REG_REQUIRED>;
-defm : TLBI<"VAE2OS", 1, 0b100, 0b1000, 0b0001, 0b001, REG_REQUIRED>;
-defm : TLBI<"VALE2OS", 1, 0b100, 0b1000, 0b0001, 0b101, REG_REQUIRED>;
-defm : TLBI<"VMALLS12E1OS", 0, 0b100, 0b1000, 0b0001, 0b110, REG_OPTIONAL>;
-defm : TLBI<"VAE3OS", 1, 0b110, 0b1000, 0b0001, 0b001, REG_REQUIRED>;
-defm : TLBI<"VALE3OS", 1, 0b110, 0b1000, 0b0001, 0b101, REG_REQUIRED>;
-defm : TLBI<"ALLE2OS", 0, 0b100, 0b1000, 0b0001, 0b000, REG_OPTIONAL>;
-defm : TLBI<"ALLE1OS", 0, 0b100, 0b1000, 0b0001, 0b100, REG_OPTIONAL>;
-defm : TLBI<"ALLE3OS", 0, 0b110, 0b1000, 0b0001, 0b000, REG_OPTIONAL>;
-
-// Armv8.4-A TLB Range Maintenance instructions:
-// hasTLBIP op1CRn CRm op2
-defm : TLBI<"RVAE1",1, 0b000, 0b1000, 0b0110, 0b001, REG_REQUIRED>;
-defm : TLBI<"RVAAE1", 1, 0b000, 0b1000, 0b0110, 0b011, REG_REQUIRED>;
-defm : TLBI<"RVALE1", 1, 0b000, 0b1000, 0b0110, 0b101, REG_REQUIRED>;
-defm : TLBI<"RVAALE1", 1, 0b000, 0b1000, 0b0110, 0b111, REG_REQUIRED>;
-defm : TLBI<"RVAE1IS", 1, 0b000, 0b1000, 0b0010, 0b001, REG_REQUIRED>;
-defm : TLBI<"RVAAE1IS", 1, 0b000, 0b1000, 0b0010, 0b011, REG_REQUIRED>;
-defm : TLBI<"RVALE1IS", 1, 0b000, 0b1000, 0b0010, 0b101, REG_REQUIRED>;
-defm :
[llvm-branch-commits] [llvm] [AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (PR #187400)
https://github.com/jthackray updated
https://github.com/llvm/llvm-project/pull/187400
>From 0e0b8fb65d3b010d19bc723b54b97ebc9baeb42a Mon Sep 17 00:00:00 2001
From: Jonathan Thackray
Date: Wed, 18 Mar 2026 20:54:50 +
Subject: [PATCH 1/7] [AArch64][llvm] Separate TLBI-only feature gating from
TLBIP aliases
Refactor the TLBI system operand definitions so that TLBI and TLBIP
records are emitted through separate helper multiclasses, whilst keeping
the table layout readable.
The feature-scoped wrappers now apply FeatureTLB_RMI, FeatureRME, and
FeatureTLBIW only to TLBI records (it was previously incorrectly also
applied to TLBIP instructions), while TLBIP aliases remain gated only
by FeatureD128, including their nXS forms.
Update testcases accordingly.
---
.../Target/AArch64/AArch64SystemOperands.td | 155 +++---
llvm/test/MC/AArch64/armv9a-tlbip.s | 17 +-
2 files changed, 101 insertions(+), 71 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
index 2dfc7f8fbd597..71b3a87c2a1f2 100644
--- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
+++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
@@ -926,6 +926,39 @@ multiclass TLBI op1,
bits<4> crn, bits<4> crm
}
}
+multiclass TLBIP_Base op1, bits<4> crn, bits<4> crm,
+ bits<3> op2, int reguse = REG_REQUIRED,
+ list extra_requires = ["AArch64::FeatureD128"]> {
+ foreach nxs = [0, 1] in {
+// TLBIP instructions aren't gated by FeatureXS like TLBI ones
+defvar VariantName = !if(nxs, !strconcat(name, "nXS"), name);
+def : TLBIPEntry {
+ let Encoding{7} = nxs;
+ let ExtraRequires = extra_requires;
+}
+ }
+}
+
+multiclass TLBI op1, bits<4> crn,
+bits<4> crm, bits<3> op2, int reguse = REG_REQUIRED> {
+ defm : TLBI_Base;
+ if !eq(hasTLBIP, true) then {
+defm : TLBIP_Base;
+ }
+}
+
+multiclass TLBI_RMI op1, bits<4> crn,
+bits<4> crm, bits<3> op2, int reguse = REG_REQUIRED> {
+ let Requires = ["AArch64::FeatureTLB_RMI"] in {
+defm : TLBI_Base;
+ }
+ // TLBIP instructions aren't gated by FeatureTLB_RMI
+ if !eq(hasTLBIP, true) then {
+defm : TLBIP_Base;
+ }
+}
+
+// TLBI and TLBIP instructions encodings
// hasTLBIP op1CRn CRm op2reguse
defm : TLBI<"IPAS2E1IS",1, 0b100, 0b1000, 0b, 0b001, REG_REQUIRED>;
defm : TLBI<"IPAS2LE1IS", 1, 0b100, 0b1000, 0b, 0b101, REG_REQUIRED>;
@@ -960,76 +993,74 @@ defm : TLBI<"VALE3",1, 0b110, 0b1000, 0b0111,
0b101, REG_REQUIRED>;
defm : TLBI<"VMALLS12E1", 0, 0b100, 0b1000, 0b0111, 0b110, REG_NONE>;
defm : TLBI<"VAALE1", 1, 0b000, 0b1000, 0b0111, 0b111, REG_REQUIRED>;
-// Armv8.4-A Translation Lookaside Buffer Instructions (TLBI)
-let Requires = ["AArch64::FeatureTLB_RMI"] in {
+// Armv8.4-A Translation Lookaside Buffer Instructions (TLBI and TLBIP)
// Armv8.4-A Outer Sharable TLB Maintenance instructions:
-// hasTLBIP op1CRn CRm op2reguse
-defm : TLBI<"VMALLE1OS",0, 0b000, 0b1000, 0b0001, 0b000, REG_OPTIONAL>;
-defm : TLBI<"VAE1OS", 1, 0b000, 0b1000, 0b0001, 0b001, REG_REQUIRED>;
-defm : TLBI<"ASIDE1OS", 0, 0b000, 0b1000, 0b0001, 0b010, REG_REQUIRED>;
-defm : TLBI<"VAAE1OS", 1, 0b000, 0b1000, 0b0001, 0b011, REG_REQUIRED>;
-defm : TLBI<"VALE1OS", 1, 0b000, 0b1000, 0b0001, 0b101, REG_REQUIRED>;
-defm : TLBI<"VAALE1OS", 1, 0b000, 0b1000, 0b0001, 0b111, REG_REQUIRED>;
-defm : TLBI<"IPAS2E1OS",1, 0b100, 0b1000, 0b0100, 0b000, REG_REQUIRED>;
-defm : TLBI<"IPAS2LE1OS", 1, 0b100, 0b1000, 0b0100, 0b100, REG_REQUIRED>;
-defm : TLBI<"VAE2OS", 1, 0b100, 0b1000, 0b0001, 0b001, REG_REQUIRED>;
-defm : TLBI<"VALE2OS", 1, 0b100, 0b1000, 0b0001, 0b101, REG_REQUIRED>;
-defm : TLBI<"VMALLS12E1OS", 0, 0b100, 0b1000, 0b0001, 0b110, REG_OPTIONAL>;
-defm : TLBI<"VAE3OS", 1, 0b110, 0b1000, 0b0001, 0b001, REG_REQUIRED>;
-defm : TLBI<"VALE3OS", 1, 0b110, 0b1000, 0b0001, 0b101, REG_REQUIRED>;
-defm : TLBI<"ALLE2OS", 0, 0b100, 0b1000, 0b0001, 0b000, REG_OPTIONAL>;
-defm : TLBI<"ALLE1OS", 0, 0b100, 0b1000, 0b0001, 0b100, REG_OPTIONAL>;
-defm : TLBI<"ALLE3OS", 0, 0b110, 0b1000, 0b0001, 0b000, REG_OPTIONAL>;
-
-// Armv8.4-A TLB Range Maintenance instructions:
-// hasTLBIP op1CRn CRm op2
-defm : TLBI<"RVAE1",1, 0b000, 0b1000, 0b0110, 0b001, REG_REQUIRED>;
-defm : TLBI<"RVAAE1", 1, 0b000, 0b1000, 0b0110, 0b011, REG_REQUIRED>;
-defm : TLBI<"RVALE1", 1, 0b000, 0b1000, 0b0110, 0b101, REG_REQUIRED>;
-defm : TLBI<"RVAALE1", 1, 0b000, 0b1000, 0b0110, 0b111, REG_REQUIRED>;
-defm : TLBI<"RVAE1IS", 1, 0b000, 0b1000, 0b0010, 0b001, REG_REQUIRED>;
-defm : TLBI<"RVAAE1IS", 1, 0b000, 0b1000, 0b0010, 0b011, REG_REQUIRED>;
-defm : TLBI<"RVALE1IS", 1, 0b000, 0b1000, 0b0010, 0b101, REG_REQUIRED>;
-defm :
[llvm-branch-commits] [llvm] [AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (PR #187400)
https://github.com/jthackray updated
https://github.com/llvm/llvm-project/pull/187400
>From 0e0b8fb65d3b010d19bc723b54b97ebc9baeb42a Mon Sep 17 00:00:00 2001
From: Jonathan Thackray
Date: Wed, 18 Mar 2026 20:54:50 +
Subject: [PATCH 1/7] [AArch64][llvm] Separate TLBI-only feature gating from
TLBIP aliases
Refactor the TLBI system operand definitions so that TLBI and TLBIP
records are emitted through separate helper multiclasses, whilst keeping
the table layout readable.
The feature-scoped wrappers now apply FeatureTLB_RMI, FeatureRME, and
FeatureTLBIW only to TLBI records (it was previously incorrectly also
applied to TLBIP instructions), while TLBIP aliases remain gated only
by FeatureD128, including their nXS forms.
Update testcases accordingly.
---
.../Target/AArch64/AArch64SystemOperands.td | 155 +++---
llvm/test/MC/AArch64/armv9a-tlbip.s | 17 +-
2 files changed, 101 insertions(+), 71 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
index 2dfc7f8fbd597..71b3a87c2a1f2 100644
--- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
+++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
@@ -926,6 +926,39 @@ multiclass TLBI op1,
bits<4> crn, bits<4> crm
}
}
+multiclass TLBIP_Base op1, bits<4> crn, bits<4> crm,
+ bits<3> op2, int reguse = REG_REQUIRED,
+ list extra_requires = ["AArch64::FeatureD128"]> {
+ foreach nxs = [0, 1] in {
+// TLBIP instructions aren't gated by FeatureXS like TLBI ones
+defvar VariantName = !if(nxs, !strconcat(name, "nXS"), name);
+def : TLBIPEntry {
+ let Encoding{7} = nxs;
+ let ExtraRequires = extra_requires;
+}
+ }
+}
+
+multiclass TLBI op1, bits<4> crn,
+bits<4> crm, bits<3> op2, int reguse = REG_REQUIRED> {
+ defm : TLBI_Base;
+ if !eq(hasTLBIP, true) then {
+defm : TLBIP_Base;
+ }
+}
+
+multiclass TLBI_RMI op1, bits<4> crn,
+bits<4> crm, bits<3> op2, int reguse = REG_REQUIRED> {
+ let Requires = ["AArch64::FeatureTLB_RMI"] in {
+defm : TLBI_Base;
+ }
+ // TLBIP instructions aren't gated by FeatureTLB_RMI
+ if !eq(hasTLBIP, true) then {
+defm : TLBIP_Base;
+ }
+}
+
+// TLBI and TLBIP instructions encodings
// hasTLBIP op1CRn CRm op2reguse
defm : TLBI<"IPAS2E1IS",1, 0b100, 0b1000, 0b, 0b001, REG_REQUIRED>;
defm : TLBI<"IPAS2LE1IS", 1, 0b100, 0b1000, 0b, 0b101, REG_REQUIRED>;
@@ -960,76 +993,74 @@ defm : TLBI<"VALE3",1, 0b110, 0b1000, 0b0111,
0b101, REG_REQUIRED>;
defm : TLBI<"VMALLS12E1", 0, 0b100, 0b1000, 0b0111, 0b110, REG_NONE>;
defm : TLBI<"VAALE1", 1, 0b000, 0b1000, 0b0111, 0b111, REG_REQUIRED>;
-// Armv8.4-A Translation Lookaside Buffer Instructions (TLBI)
-let Requires = ["AArch64::FeatureTLB_RMI"] in {
+// Armv8.4-A Translation Lookaside Buffer Instructions (TLBI and TLBIP)
// Armv8.4-A Outer Sharable TLB Maintenance instructions:
-// hasTLBIP op1CRn CRm op2reguse
-defm : TLBI<"VMALLE1OS",0, 0b000, 0b1000, 0b0001, 0b000, REG_OPTIONAL>;
-defm : TLBI<"VAE1OS", 1, 0b000, 0b1000, 0b0001, 0b001, REG_REQUIRED>;
-defm : TLBI<"ASIDE1OS", 0, 0b000, 0b1000, 0b0001, 0b010, REG_REQUIRED>;
-defm : TLBI<"VAAE1OS", 1, 0b000, 0b1000, 0b0001, 0b011, REG_REQUIRED>;
-defm : TLBI<"VALE1OS", 1, 0b000, 0b1000, 0b0001, 0b101, REG_REQUIRED>;
-defm : TLBI<"VAALE1OS", 1, 0b000, 0b1000, 0b0001, 0b111, REG_REQUIRED>;
-defm : TLBI<"IPAS2E1OS",1, 0b100, 0b1000, 0b0100, 0b000, REG_REQUIRED>;
-defm : TLBI<"IPAS2LE1OS", 1, 0b100, 0b1000, 0b0100, 0b100, REG_REQUIRED>;
-defm : TLBI<"VAE2OS", 1, 0b100, 0b1000, 0b0001, 0b001, REG_REQUIRED>;
-defm : TLBI<"VALE2OS", 1, 0b100, 0b1000, 0b0001, 0b101, REG_REQUIRED>;
-defm : TLBI<"VMALLS12E1OS", 0, 0b100, 0b1000, 0b0001, 0b110, REG_OPTIONAL>;
-defm : TLBI<"VAE3OS", 1, 0b110, 0b1000, 0b0001, 0b001, REG_REQUIRED>;
-defm : TLBI<"VALE3OS", 1, 0b110, 0b1000, 0b0001, 0b101, REG_REQUIRED>;
-defm : TLBI<"ALLE2OS", 0, 0b100, 0b1000, 0b0001, 0b000, REG_OPTIONAL>;
-defm : TLBI<"ALLE1OS", 0, 0b100, 0b1000, 0b0001, 0b100, REG_OPTIONAL>;
-defm : TLBI<"ALLE3OS", 0, 0b110, 0b1000, 0b0001, 0b000, REG_OPTIONAL>;
-
-// Armv8.4-A TLB Range Maintenance instructions:
-// hasTLBIP op1CRn CRm op2
-defm : TLBI<"RVAE1",1, 0b000, 0b1000, 0b0110, 0b001, REG_REQUIRED>;
-defm : TLBI<"RVAAE1", 1, 0b000, 0b1000, 0b0110, 0b011, REG_REQUIRED>;
-defm : TLBI<"RVALE1", 1, 0b000, 0b1000, 0b0110, 0b101, REG_REQUIRED>;
-defm : TLBI<"RVAALE1", 1, 0b000, 0b1000, 0b0110, 0b111, REG_REQUIRED>;
-defm : TLBI<"RVAE1IS", 1, 0b000, 0b1000, 0b0010, 0b001, REG_REQUIRED>;
-defm : TLBI<"RVAAE1IS", 1, 0b000, 0b1000, 0b0010, 0b011, REG_REQUIRED>;
-defm : TLBI<"RVALE1IS", 1, 0b000, 0b1000, 0b0010, 0b101, REG_REQUIRED>;
-defm :
[llvm-branch-commits] [llvm] [AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (PR #187400)
@@ -1,9 +1,11 @@ +// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+xs < %s 2>%t | FileCheck %s +// RUN: FileCheck --check-prefix=CHECK-ERR %s < %t // RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.4a,+xs < %s 2>%t | FileCheck %s // RUN: FileCheck --check-prefix=CHECK-ERR %s < %t // RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.7a < %s 2>%t | FileCheck %s // RUN: FileCheck --check-prefix=CHECK-ERR %s < %t // RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.4a < %s 2> %t -// RUN: FileCheck --check-prefixes=CHECK-ERR,CHECK-NO-XS-ERR %s < %t Lukacma wrote: Ah I see. That's not good. It means those tests were not testing anything... https://github.com/llvm/llvm-project/pull/187400 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (PR #187400)
@@ -866,11 +866,12 @@ class SysAliasRegUse {
}
class TLBICommon op1, bits<4> crn, bits<4> crm,
- bits<3> op2, int reguse> : SysAliasRegUse {
+ bits<3> op2, bit nxs, int reguse> : SysAliasRegUse {
string Name = name;
bits<14> Encoding;
let Encoding{13-11} = op1;
let Encoding{10-7} = crn;
Lukacma wrote:
This is unnecessarily general encoding here. The only modifiable bit for crn is
the last which is 0 for base and 1 for nxs from what I can see in spec.
https://github.com/llvm/llvm-project/pull/187400
___
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[llvm-branch-commits] [llvm] [AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (PR #187400)
@@ -903,128 +904,175 @@ multiclass TLBITableBase {
defm TLBI : TLBITableBase;
defm TLBIP : TLBITableBase;
-multiclass TLBI op1, bits<4> crn, bits<4>
crm,
- bits<3> op2, int reguse = REG_REQUIRED> {
- def : TLBIEntry;
- def : TLBIEntry {
-let Encoding{7} = 1;
+class TLBI op1, bits<4> crn,
+ bits<4> crm, bits<3> op2, int reguse = REG_REQUIRED> {
+ string Name = name;
+ bit HasTLBIP = hasTLBIP;
+ bits<3> Op1 = op1;
+ bits<4> CRn = crn;
+ bits<4> CRm = crm;
+ bits<3> Op2 = op2;
+ int RegUse = reguse;
+}
+
+// TLBI and TLBIP instructions encodings.
+defvar TLBIBase = [
+ //namehasTLBIP op1CRn CRm op2reguse
+ TLBI<"IPAS2E1IS",1, 0b100, 0b1000, 0b, 0b001, REG_REQUIRED>,
+ TLBI<"IPAS2LE1IS", 1, 0b100, 0b1000, 0b, 0b101, REG_REQUIRED>,
+ TLBI<"VMALLE1IS",0, 0b000, 0b1000, 0b0011, 0b000, REG_OPTIONAL>,
+ TLBI<"ALLE2IS", 0, 0b100, 0b1000, 0b0011, 0b000, REG_OPTIONAL>,
+ TLBI<"ALLE3IS", 0, 0b110, 0b1000, 0b0011, 0b000, REG_OPTIONAL>,
+ TLBI<"VAE1IS", 1, 0b000, 0b1000, 0b0011, 0b001, REG_REQUIRED>,
+ TLBI<"VAE2IS", 1, 0b100, 0b1000, 0b0011, 0b001, REG_REQUIRED>,
+ TLBI<"VAE3IS", 1, 0b110, 0b1000, 0b0011, 0b001, REG_REQUIRED>,
+ TLBI<"ASIDE1IS", 0, 0b000, 0b1000, 0b0011, 0b010, REG_REQUIRED>,
+ TLBI<"VAAE1IS", 1, 0b000, 0b1000, 0b0011, 0b011, REG_REQUIRED>,
+ TLBI<"ALLE1IS", 0, 0b100, 0b1000, 0b0011, 0b100, REG_OPTIONAL>,
+ TLBI<"VALE1IS", 1, 0b000, 0b1000, 0b0011, 0b101, REG_REQUIRED>,
+ TLBI<"VALE2IS", 1, 0b100, 0b1000, 0b0011, 0b101, REG_REQUIRED>,
+ TLBI<"VALE3IS", 1, 0b110, 0b1000, 0b0011, 0b101, REG_REQUIRED>,
+ TLBI<"VMALLS12E1IS", 0, 0b100, 0b1000, 0b0011, 0b110, REG_OPTIONAL>,
+ TLBI<"VAALE1IS", 1, 0b000, 0b1000, 0b0011, 0b111, REG_REQUIRED>,
+ TLBI<"IPAS2E1", 1, 0b100, 0b1000, 0b0100, 0b001, REG_REQUIRED>,
+ TLBI<"IPAS2LE1", 1, 0b100, 0b1000, 0b0100, 0b101, REG_REQUIRED>,
+ TLBI<"VMALLE1", 0, 0b000, 0b1000, 0b0111, 0b000, REG_NONE>,
+ TLBI<"ALLE2",0, 0b100, 0b1000, 0b0111, 0b000, REG_NONE>,
+ TLBI<"ALLE3",0, 0b110, 0b1000, 0b0111, 0b000, REG_NONE>,
+ TLBI<"VAE1", 1, 0b000, 0b1000, 0b0111, 0b001, REG_REQUIRED>,
+ TLBI<"VAE2", 1, 0b100, 0b1000, 0b0111, 0b001, REG_REQUIRED>,
+ TLBI<"VAE3", 1, 0b110, 0b1000, 0b0111, 0b001, REG_REQUIRED>,
+ TLBI<"ASIDE1", 0, 0b000, 0b1000, 0b0111, 0b010, REG_REQUIRED>,
+ TLBI<"VAAE1",1, 0b000, 0b1000, 0b0111, 0b011, REG_REQUIRED>,
+ TLBI<"ALLE1",0, 0b100, 0b1000, 0b0111, 0b100, REG_NONE>,
+ TLBI<"VALE1",1, 0b000, 0b1000, 0b0111, 0b101, REG_REQUIRED>,
+ TLBI<"VALE2",1, 0b100, 0b1000, 0b0111, 0b101, REG_REQUIRED>,
+ TLBI<"VALE3",1, 0b110, 0b1000, 0b0111, 0b101, REG_REQUIRED>,
+ TLBI<"VMALLS12E1", 0, 0b100, 0b1000, 0b0111, 0b110, REG_NONE>,
+ TLBI<"VAALE1", 1, 0b000, 0b1000, 0b0111, 0b111, REG_REQUIRED>
+];
+
+foreach I = TLBIBase in {
+ def : TLBIEntry;
+
+ def : TLBIEntry {
let ExtraRequires = ["AArch64::FeatureXS"];
}
- if !eq(hasTLBIP, true) then {
-def : TLBIPEntry {
- let ExtraRequires = ["AArch64::FeatureD128"];
+
+ if !eq(I.HasTLBIP, true) then {
Lukacma wrote:
```suggestion
if I.HasTLBIP then {
```
Same everywhere
https://github.com/llvm/llvm-project/pull/187400
___
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[llvm-branch-commits] [llvm] [AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (PR #187400)
@@ -903,128 +904,175 @@ multiclass TLBITableBase {
defm TLBI : TLBITableBase;
defm TLBIP : TLBITableBase;
-multiclass TLBI op1, bits<4> crn, bits<4>
crm,
- bits<3> op2, int reguse = REG_REQUIRED> {
- def : TLBIEntry;
- def : TLBIEntry {
-let Encoding{7} = 1;
+class TLBI op1, bits<4> crn,
+ bits<4> crm, bits<3> op2, int reguse = REG_REQUIRED> {
+ string Name = name;
+ bit HasTLBIP = hasTLBIP;
+ bits<3> Op1 = op1;
+ bits<4> CRn = crn;
+ bits<4> CRm = crm;
+ bits<3> Op2 = op2;
+ int RegUse = reguse;
+}
+
+// TLBI and TLBIP instructions encodings.
+defvar TLBIBase = [
+ //namehasTLBIP op1CRn CRm op2reguse
+ TLBI<"IPAS2E1IS",1, 0b100, 0b1000, 0b, 0b001, REG_REQUIRED>,
+ TLBI<"IPAS2LE1IS", 1, 0b100, 0b1000, 0b, 0b101, REG_REQUIRED>,
+ TLBI<"VMALLE1IS",0, 0b000, 0b1000, 0b0011, 0b000, REG_OPTIONAL>,
+ TLBI<"ALLE2IS", 0, 0b100, 0b1000, 0b0011, 0b000, REG_OPTIONAL>,
+ TLBI<"ALLE3IS", 0, 0b110, 0b1000, 0b0011, 0b000, REG_OPTIONAL>,
+ TLBI<"VAE1IS", 1, 0b000, 0b1000, 0b0011, 0b001, REG_REQUIRED>,
+ TLBI<"VAE2IS", 1, 0b100, 0b1000, 0b0011, 0b001, REG_REQUIRED>,
+ TLBI<"VAE3IS", 1, 0b110, 0b1000, 0b0011, 0b001, REG_REQUIRED>,
+ TLBI<"ASIDE1IS", 0, 0b000, 0b1000, 0b0011, 0b010, REG_REQUIRED>,
+ TLBI<"VAAE1IS", 1, 0b000, 0b1000, 0b0011, 0b011, REG_REQUIRED>,
+ TLBI<"ALLE1IS", 0, 0b100, 0b1000, 0b0011, 0b100, REG_OPTIONAL>,
+ TLBI<"VALE1IS", 1, 0b000, 0b1000, 0b0011, 0b101, REG_REQUIRED>,
+ TLBI<"VALE2IS", 1, 0b100, 0b1000, 0b0011, 0b101, REG_REQUIRED>,
+ TLBI<"VALE3IS", 1, 0b110, 0b1000, 0b0011, 0b101, REG_REQUIRED>,
+ TLBI<"VMALLS12E1IS", 0, 0b100, 0b1000, 0b0011, 0b110, REG_OPTIONAL>,
+ TLBI<"VAALE1IS", 1, 0b000, 0b1000, 0b0011, 0b111, REG_REQUIRED>,
+ TLBI<"IPAS2E1", 1, 0b100, 0b1000, 0b0100, 0b001, REG_REQUIRED>,
+ TLBI<"IPAS2LE1", 1, 0b100, 0b1000, 0b0100, 0b101, REG_REQUIRED>,
+ TLBI<"VMALLE1", 0, 0b000, 0b1000, 0b0111, 0b000, REG_NONE>,
+ TLBI<"ALLE2",0, 0b100, 0b1000, 0b0111, 0b000, REG_NONE>,
+ TLBI<"ALLE3",0, 0b110, 0b1000, 0b0111, 0b000, REG_NONE>,
+ TLBI<"VAE1", 1, 0b000, 0b1000, 0b0111, 0b001, REG_REQUIRED>,
+ TLBI<"VAE2", 1, 0b100, 0b1000, 0b0111, 0b001, REG_REQUIRED>,
+ TLBI<"VAE3", 1, 0b110, 0b1000, 0b0111, 0b001, REG_REQUIRED>,
+ TLBI<"ASIDE1", 0, 0b000, 0b1000, 0b0111, 0b010, REG_REQUIRED>,
+ TLBI<"VAAE1",1, 0b000, 0b1000, 0b0111, 0b011, REG_REQUIRED>,
+ TLBI<"ALLE1",0, 0b100, 0b1000, 0b0111, 0b100, REG_NONE>,
+ TLBI<"VALE1",1, 0b000, 0b1000, 0b0111, 0b101, REG_REQUIRED>,
+ TLBI<"VALE2",1, 0b100, 0b1000, 0b0111, 0b101, REG_REQUIRED>,
+ TLBI<"VALE3",1, 0b110, 0b1000, 0b0111, 0b101, REG_REQUIRED>,
+ TLBI<"VMALLS12E1", 0, 0b100, 0b1000, 0b0111, 0b110, REG_NONE>,
+ TLBI<"VAALE1", 1, 0b000, 0b1000, 0b0111, 0b111, REG_REQUIRED>
+];
+
+foreach I = TLBIBase in {
+ def : TLBIEntry;
+
+ def : TLBIEntry {
let ExtraRequires = ["AArch64::FeatureXS"];
}
- if !eq(hasTLBIP, true) then {
-def : TLBIPEntry {
- let ExtraRequires = ["AArch64::FeatureD128"];
+
+ if !eq(I.HasTLBIP, true) then {
+def : TLBIPEntry {
+ let Requires = ["AArch64::FeatureD128"];
}
-def : TLBIPEntry {
- let Encoding{7} = 1;
- let ExtraRequires = ["AArch64::FeatureD128"];
+
+// *nxs variants are gated by `FEAT_D128` not `FEAT_XS`
+def : TLBIPEntry {
+ let Requires = ["AArch64::FeatureD128"];
}
}
}
-// hasTLBIP op1CRn CRm op2reguse
-defm : TLBI<"IPAS2E1IS",1, 0b100, 0b1000, 0b, 0b001, REG_REQUIRED>;
-defm : TLBI<"IPAS2LE1IS", 1, 0b100, 0b1000, 0b, 0b101, REG_REQUIRED>;
-defm : TLBI<"VMALLE1IS",0, 0b000, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
-defm : TLBI<"ALLE2IS", 0, 0b100, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
-defm : TLBI<"ALLE3IS", 0, 0b110, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
-defm : TLBI<"VAE1IS", 1, 0b000, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
-defm : TLBI<"VAE2IS", 1, 0b100, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
-defm : TLBI<"VAE3IS", 1, 0b110, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
-defm : TLBI<"ASIDE1IS", 0, 0b000, 0b1000, 0b0011, 0b010, REG_REQUIRED>;
-defm : TLBI<"VAAE1IS", 1, 0b000, 0b1000, 0b0011, 0b011, REG_REQUIRED>;
-defm : TLBI<"ALLE1IS", 0, 0b100, 0b1000, 0b0011, 0b100, REG_OPTIONAL>;
-defm : TLBI<"VALE1IS", 1, 0b000, 0b1000, 0b0011, 0b101, REG_REQUIRED>;
-defm : TLBI<"VALE2IS", 1, 0b100, 0b1000, 0b0011, 0b101, REG_REQUIRED>;
-defm : TLBI<"VALE3IS", 1, 0b110, 0b1000, 0b0011, 0b101, REG_REQUIRED>;
-defm : TLBI<"VMALLS12E1IS", 0, 0b100, 0b1000, 0b0011, 0b110, REG_OPTIONAL>;
-defm : TLBI<"VAALE1IS", 1, 0b000, 0b1000, 0b0011, 0b111, REG_REQUIRED>;
-defm : TLBI<"IPAS2E1", 1, 0b100, 0b1000, 0b0100, 0b001, REG_REQUIRED>;
-defm : TLBI<"IPAS2LE1",
[llvm-branch-commits] [llvm] [AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (PR #187400)
@@ -866,11 +866,12 @@ class SysAliasRegUse {
}
class TLBICommon op1, bits<4> crn, bits<4> crm,
- bits<3> op2, int reguse> : SysAliasRegUse {
+ bits<3> op2, bit nxs, int reguse> : SysAliasRegUse {
string Name = name;
bits<14> Encoding;
let Encoding{13-11} = op1;
let Encoding{10-7} = crn;
jthackray wrote:
Ok, gone.
https://github.com/llvm/llvm-project/pull/187400
___
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[llvm-branch-commits] [llvm] [AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (PR #187400)
@@ -903,128 +904,175 @@ multiclass TLBITableBase {
defm TLBI : TLBITableBase;
defm TLBIP : TLBITableBase;
-multiclass TLBI op1, bits<4> crn, bits<4>
crm,
- bits<3> op2, int reguse = REG_REQUIRED> {
- def : TLBIEntry;
- def : TLBIEntry {
-let Encoding{7} = 1;
+class TLBI op1, bits<4> crn,
+ bits<4> crm, bits<3> op2, int reguse = REG_REQUIRED> {
+ string Name = name;
+ bit HasTLBIP = hasTLBIP;
+ bits<3> Op1 = op1;
+ bits<4> CRn = crn;
+ bits<4> CRm = crm;
+ bits<3> Op2 = op2;
+ int RegUse = reguse;
+}
+
+// TLBI and TLBIP instructions encodings.
+defvar TLBIBase = [
+ //namehasTLBIP op1CRn CRm op2reguse
+ TLBI<"IPAS2E1IS",1, 0b100, 0b1000, 0b, 0b001, REG_REQUIRED>,
+ TLBI<"IPAS2LE1IS", 1, 0b100, 0b1000, 0b, 0b101, REG_REQUIRED>,
+ TLBI<"VMALLE1IS",0, 0b000, 0b1000, 0b0011, 0b000, REG_OPTIONAL>,
+ TLBI<"ALLE2IS", 0, 0b100, 0b1000, 0b0011, 0b000, REG_OPTIONAL>,
+ TLBI<"ALLE3IS", 0, 0b110, 0b1000, 0b0011, 0b000, REG_OPTIONAL>,
+ TLBI<"VAE1IS", 1, 0b000, 0b1000, 0b0011, 0b001, REG_REQUIRED>,
+ TLBI<"VAE2IS", 1, 0b100, 0b1000, 0b0011, 0b001, REG_REQUIRED>,
+ TLBI<"VAE3IS", 1, 0b110, 0b1000, 0b0011, 0b001, REG_REQUIRED>,
+ TLBI<"ASIDE1IS", 0, 0b000, 0b1000, 0b0011, 0b010, REG_REQUIRED>,
+ TLBI<"VAAE1IS", 1, 0b000, 0b1000, 0b0011, 0b011, REG_REQUIRED>,
+ TLBI<"ALLE1IS", 0, 0b100, 0b1000, 0b0011, 0b100, REG_OPTIONAL>,
+ TLBI<"VALE1IS", 1, 0b000, 0b1000, 0b0011, 0b101, REG_REQUIRED>,
+ TLBI<"VALE2IS", 1, 0b100, 0b1000, 0b0011, 0b101, REG_REQUIRED>,
+ TLBI<"VALE3IS", 1, 0b110, 0b1000, 0b0011, 0b101, REG_REQUIRED>,
+ TLBI<"VMALLS12E1IS", 0, 0b100, 0b1000, 0b0011, 0b110, REG_OPTIONAL>,
+ TLBI<"VAALE1IS", 1, 0b000, 0b1000, 0b0011, 0b111, REG_REQUIRED>,
+ TLBI<"IPAS2E1", 1, 0b100, 0b1000, 0b0100, 0b001, REG_REQUIRED>,
+ TLBI<"IPAS2LE1", 1, 0b100, 0b1000, 0b0100, 0b101, REG_REQUIRED>,
+ TLBI<"VMALLE1", 0, 0b000, 0b1000, 0b0111, 0b000, REG_NONE>,
+ TLBI<"ALLE2",0, 0b100, 0b1000, 0b0111, 0b000, REG_NONE>,
+ TLBI<"ALLE3",0, 0b110, 0b1000, 0b0111, 0b000, REG_NONE>,
+ TLBI<"VAE1", 1, 0b000, 0b1000, 0b0111, 0b001, REG_REQUIRED>,
+ TLBI<"VAE2", 1, 0b100, 0b1000, 0b0111, 0b001, REG_REQUIRED>,
+ TLBI<"VAE3", 1, 0b110, 0b1000, 0b0111, 0b001, REG_REQUIRED>,
+ TLBI<"ASIDE1", 0, 0b000, 0b1000, 0b0111, 0b010, REG_REQUIRED>,
+ TLBI<"VAAE1",1, 0b000, 0b1000, 0b0111, 0b011, REG_REQUIRED>,
+ TLBI<"ALLE1",0, 0b100, 0b1000, 0b0111, 0b100, REG_NONE>,
+ TLBI<"VALE1",1, 0b000, 0b1000, 0b0111, 0b101, REG_REQUIRED>,
+ TLBI<"VALE2",1, 0b100, 0b1000, 0b0111, 0b101, REG_REQUIRED>,
+ TLBI<"VALE3",1, 0b110, 0b1000, 0b0111, 0b101, REG_REQUIRED>,
+ TLBI<"VMALLS12E1", 0, 0b100, 0b1000, 0b0111, 0b110, REG_NONE>,
+ TLBI<"VAALE1", 1, 0b000, 0b1000, 0b0111, 0b111, REG_REQUIRED>
+];
+
+foreach I = TLBIBase in {
+ def : TLBIEntry;
+
+ def : TLBIEntry {
let ExtraRequires = ["AArch64::FeatureXS"];
}
- if !eq(hasTLBIP, true) then {
-def : TLBIPEntry {
- let ExtraRequires = ["AArch64::FeatureD128"];
+
+ if !eq(I.HasTLBIP, true) then {
+def : TLBIPEntry {
+ let Requires = ["AArch64::FeatureD128"];
}
-def : TLBIPEntry {
- let Encoding{7} = 1;
- let ExtraRequires = ["AArch64::FeatureD128"];
+
+// *nxs variants are gated by `FEAT_D128` not `FEAT_XS`
jthackray wrote:
Removed.
https://github.com/llvm/llvm-project/pull/187400
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[llvm-branch-commits] [llvm] [AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (PR #187400)
@@ -903,128 +904,175 @@ multiclass TLBITableBase {
defm TLBI : TLBITableBase;
defm TLBIP : TLBITableBase;
-multiclass TLBI op1, bits<4> crn, bits<4>
crm,
- bits<3> op2, int reguse = REG_REQUIRED> {
- def : TLBIEntry;
- def : TLBIEntry {
-let Encoding{7} = 1;
+class TLBI op1, bits<4> crn,
+ bits<4> crm, bits<3> op2, int reguse = REG_REQUIRED> {
+ string Name = name;
+ bit HasTLBIP = hasTLBIP;
+ bits<3> Op1 = op1;
+ bits<4> CRn = crn;
+ bits<4> CRm = crm;
+ bits<3> Op2 = op2;
+ int RegUse = reguse;
+}
+
+// TLBI and TLBIP instructions encodings.
+defvar TLBIBase = [
+ //namehasTLBIP op1CRn CRm op2reguse
+ TLBI<"IPAS2E1IS",1, 0b100, 0b1000, 0b, 0b001, REG_REQUIRED>,
+ TLBI<"IPAS2LE1IS", 1, 0b100, 0b1000, 0b, 0b101, REG_REQUIRED>,
+ TLBI<"VMALLE1IS",0, 0b000, 0b1000, 0b0011, 0b000, REG_OPTIONAL>,
+ TLBI<"ALLE2IS", 0, 0b100, 0b1000, 0b0011, 0b000, REG_OPTIONAL>,
+ TLBI<"ALLE3IS", 0, 0b110, 0b1000, 0b0011, 0b000, REG_OPTIONAL>,
+ TLBI<"VAE1IS", 1, 0b000, 0b1000, 0b0011, 0b001, REG_REQUIRED>,
+ TLBI<"VAE2IS", 1, 0b100, 0b1000, 0b0011, 0b001, REG_REQUIRED>,
+ TLBI<"VAE3IS", 1, 0b110, 0b1000, 0b0011, 0b001, REG_REQUIRED>,
+ TLBI<"ASIDE1IS", 0, 0b000, 0b1000, 0b0011, 0b010, REG_REQUIRED>,
+ TLBI<"VAAE1IS", 1, 0b000, 0b1000, 0b0011, 0b011, REG_REQUIRED>,
+ TLBI<"ALLE1IS", 0, 0b100, 0b1000, 0b0011, 0b100, REG_OPTIONAL>,
+ TLBI<"VALE1IS", 1, 0b000, 0b1000, 0b0011, 0b101, REG_REQUIRED>,
+ TLBI<"VALE2IS", 1, 0b100, 0b1000, 0b0011, 0b101, REG_REQUIRED>,
+ TLBI<"VALE3IS", 1, 0b110, 0b1000, 0b0011, 0b101, REG_REQUIRED>,
+ TLBI<"VMALLS12E1IS", 0, 0b100, 0b1000, 0b0011, 0b110, REG_OPTIONAL>,
+ TLBI<"VAALE1IS", 1, 0b000, 0b1000, 0b0011, 0b111, REG_REQUIRED>,
+ TLBI<"IPAS2E1", 1, 0b100, 0b1000, 0b0100, 0b001, REG_REQUIRED>,
+ TLBI<"IPAS2LE1", 1, 0b100, 0b1000, 0b0100, 0b101, REG_REQUIRED>,
+ TLBI<"VMALLE1", 0, 0b000, 0b1000, 0b0111, 0b000, REG_NONE>,
+ TLBI<"ALLE2",0, 0b100, 0b1000, 0b0111, 0b000, REG_NONE>,
+ TLBI<"ALLE3",0, 0b110, 0b1000, 0b0111, 0b000, REG_NONE>,
+ TLBI<"VAE1", 1, 0b000, 0b1000, 0b0111, 0b001, REG_REQUIRED>,
+ TLBI<"VAE2", 1, 0b100, 0b1000, 0b0111, 0b001, REG_REQUIRED>,
+ TLBI<"VAE3", 1, 0b110, 0b1000, 0b0111, 0b001, REG_REQUIRED>,
+ TLBI<"ASIDE1", 0, 0b000, 0b1000, 0b0111, 0b010, REG_REQUIRED>,
+ TLBI<"VAAE1",1, 0b000, 0b1000, 0b0111, 0b011, REG_REQUIRED>,
+ TLBI<"ALLE1",0, 0b100, 0b1000, 0b0111, 0b100, REG_NONE>,
+ TLBI<"VALE1",1, 0b000, 0b1000, 0b0111, 0b101, REG_REQUIRED>,
+ TLBI<"VALE2",1, 0b100, 0b1000, 0b0111, 0b101, REG_REQUIRED>,
+ TLBI<"VALE3",1, 0b110, 0b1000, 0b0111, 0b101, REG_REQUIRED>,
+ TLBI<"VMALLS12E1", 0, 0b100, 0b1000, 0b0111, 0b110, REG_NONE>,
+ TLBI<"VAALE1", 1, 0b000, 0b1000, 0b0111, 0b111, REG_REQUIRED>
+];
+
+foreach I = TLBIBase in {
+ def : TLBIEntry;
+
+ def : TLBIEntry {
let ExtraRequires = ["AArch64::FeatureXS"];
}
- if !eq(hasTLBIP, true) then {
-def : TLBIPEntry {
- let ExtraRequires = ["AArch64::FeatureD128"];
+
+ if !eq(I.HasTLBIP, true) then {
+def : TLBIPEntry {
+ let Requires = ["AArch64::FeatureD128"];
}
-def : TLBIPEntry {
- let Encoding{7} = 1;
- let ExtraRequires = ["AArch64::FeatureD128"];
+
+// *nxs variants are gated by `FEAT_D128` not `FEAT_XS`
+def : TLBIPEntry {
+ let Requires = ["AArch64::FeatureD128"];
jthackray wrote:
Re-arranged.
https://github.com/llvm/llvm-project/pull/187400
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[llvm-branch-commits] [llvm] [AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (PR #187400)
@@ -903,128 +904,175 @@ multiclass TLBITableBase {
defm TLBI : TLBITableBase;
defm TLBIP : TLBITableBase;
-multiclass TLBI op1, bits<4> crn, bits<4>
crm,
- bits<3> op2, int reguse = REG_REQUIRED> {
- def : TLBIEntry;
- def : TLBIEntry {
-let Encoding{7} = 1;
+class TLBI op1, bits<4> crn,
+ bits<4> crm, bits<3> op2, int reguse = REG_REQUIRED> {
+ string Name = name;
+ bit HasTLBIP = hasTLBIP;
+ bits<3> Op1 = op1;
+ bits<4> CRn = crn;
+ bits<4> CRm = crm;
+ bits<3> Op2 = op2;
+ int RegUse = reguse;
+}
+
+// TLBI and TLBIP instructions encodings.
+defvar TLBIBase = [
+ //namehasTLBIP op1CRn CRm op2reguse
jthackray wrote:
Sure, done.
https://github.com/llvm/llvm-project/pull/187400
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[llvm-branch-commits] [llvm] [AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (PR #187400)
@@ -903,128 +904,175 @@ multiclass TLBITableBase {
defm TLBI : TLBITableBase;
defm TLBIP : TLBITableBase;
-multiclass TLBI op1, bits<4> crn, bits<4>
crm,
- bits<3> op2, int reguse = REG_REQUIRED> {
- def : TLBIEntry;
- def : TLBIEntry {
-let Encoding{7} = 1;
+class TLBI op1, bits<4> crn,
+ bits<4> crm, bits<3> op2, int reguse = REG_REQUIRED> {
+ string Name = name;
+ bit HasTLBIP = hasTLBIP;
+ bits<3> Op1 = op1;
+ bits<4> CRn = crn;
+ bits<4> CRm = crm;
+ bits<3> Op2 = op2;
+ int RegUse = reguse;
+}
+
+// TLBI and TLBIP instructions encodings.
+defvar TLBIBase = [
+ //namehasTLBIP op1CRn CRm op2reguse
+ TLBI<"IPAS2E1IS",1, 0b100, 0b1000, 0b, 0b001, REG_REQUIRED>,
+ TLBI<"IPAS2LE1IS", 1, 0b100, 0b1000, 0b, 0b101, REG_REQUIRED>,
+ TLBI<"VMALLE1IS",0, 0b000, 0b1000, 0b0011, 0b000, REG_OPTIONAL>,
+ TLBI<"ALLE2IS", 0, 0b100, 0b1000, 0b0011, 0b000, REG_OPTIONAL>,
+ TLBI<"ALLE3IS", 0, 0b110, 0b1000, 0b0011, 0b000, REG_OPTIONAL>,
+ TLBI<"VAE1IS", 1, 0b000, 0b1000, 0b0011, 0b001, REG_REQUIRED>,
+ TLBI<"VAE2IS", 1, 0b100, 0b1000, 0b0011, 0b001, REG_REQUIRED>,
+ TLBI<"VAE3IS", 1, 0b110, 0b1000, 0b0011, 0b001, REG_REQUIRED>,
+ TLBI<"ASIDE1IS", 0, 0b000, 0b1000, 0b0011, 0b010, REG_REQUIRED>,
+ TLBI<"VAAE1IS", 1, 0b000, 0b1000, 0b0011, 0b011, REG_REQUIRED>,
+ TLBI<"ALLE1IS", 0, 0b100, 0b1000, 0b0011, 0b100, REG_OPTIONAL>,
+ TLBI<"VALE1IS", 1, 0b000, 0b1000, 0b0011, 0b101, REG_REQUIRED>,
+ TLBI<"VALE2IS", 1, 0b100, 0b1000, 0b0011, 0b101, REG_REQUIRED>,
+ TLBI<"VALE3IS", 1, 0b110, 0b1000, 0b0011, 0b101, REG_REQUIRED>,
+ TLBI<"VMALLS12E1IS", 0, 0b100, 0b1000, 0b0011, 0b110, REG_OPTIONAL>,
+ TLBI<"VAALE1IS", 1, 0b000, 0b1000, 0b0011, 0b111, REG_REQUIRED>,
+ TLBI<"IPAS2E1", 1, 0b100, 0b1000, 0b0100, 0b001, REG_REQUIRED>,
+ TLBI<"IPAS2LE1", 1, 0b100, 0b1000, 0b0100, 0b101, REG_REQUIRED>,
+ TLBI<"VMALLE1", 0, 0b000, 0b1000, 0b0111, 0b000, REG_NONE>,
+ TLBI<"ALLE2",0, 0b100, 0b1000, 0b0111, 0b000, REG_NONE>,
+ TLBI<"ALLE3",0, 0b110, 0b1000, 0b0111, 0b000, REG_NONE>,
+ TLBI<"VAE1", 1, 0b000, 0b1000, 0b0111, 0b001, REG_REQUIRED>,
+ TLBI<"VAE2", 1, 0b100, 0b1000, 0b0111, 0b001, REG_REQUIRED>,
+ TLBI<"VAE3", 1, 0b110, 0b1000, 0b0111, 0b001, REG_REQUIRED>,
+ TLBI<"ASIDE1", 0, 0b000, 0b1000, 0b0111, 0b010, REG_REQUIRED>,
+ TLBI<"VAAE1",1, 0b000, 0b1000, 0b0111, 0b011, REG_REQUIRED>,
+ TLBI<"ALLE1",0, 0b100, 0b1000, 0b0111, 0b100, REG_NONE>,
+ TLBI<"VALE1",1, 0b000, 0b1000, 0b0111, 0b101, REG_REQUIRED>,
+ TLBI<"VALE2",1, 0b100, 0b1000, 0b0111, 0b101, REG_REQUIRED>,
+ TLBI<"VALE3",1, 0b110, 0b1000, 0b0111, 0b101, REG_REQUIRED>,
+ TLBI<"VMALLS12E1", 0, 0b100, 0b1000, 0b0111, 0b110, REG_NONE>,
+ TLBI<"VAALE1", 1, 0b000, 0b1000, 0b0111, 0b111, REG_REQUIRED>
+];
+
+foreach I = TLBIBase in {
+ def : TLBIEntry;
+
+ def : TLBIEntry {
let ExtraRequires = ["AArch64::FeatureXS"];
}
- if !eq(hasTLBIP, true) then {
-def : TLBIPEntry {
- let ExtraRequires = ["AArch64::FeatureD128"];
+
+ if !eq(I.HasTLBIP, true) then {
jthackray wrote:
Good idea, done.
https://github.com/llvm/llvm-project/pull/187400
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[llvm-branch-commits] [llvm] [AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (PR #187400)
@@ -903,128 +904,175 @@ multiclass TLBITableBase {
defm TLBI : TLBITableBase;
defm TLBIP : TLBITableBase;
-multiclass TLBI op1, bits<4> crn, bits<4>
crm,
- bits<3> op2, int reguse = REG_REQUIRED> {
- def : TLBIEntry;
- def : TLBIEntry {
-let Encoding{7} = 1;
+class TLBI op1, bits<4> crn,
+ bits<4> crm, bits<3> op2, int reguse = REG_REQUIRED> {
+ string Name = name;
+ bit HasTLBIP = hasTLBIP;
+ bits<3> Op1 = op1;
+ bits<4> CRn = crn;
+ bits<4> CRm = crm;
+ bits<3> Op2 = op2;
+ int RegUse = reguse;
+}
+
+// TLBI and TLBIP instructions encodings.
+defvar TLBIBase = [
+ //namehasTLBIP op1CRn CRm op2reguse
+ TLBI<"IPAS2E1IS",1, 0b100, 0b1000, 0b, 0b001, REG_REQUIRED>,
+ TLBI<"IPAS2LE1IS", 1, 0b100, 0b1000, 0b, 0b101, REG_REQUIRED>,
+ TLBI<"VMALLE1IS",0, 0b000, 0b1000, 0b0011, 0b000, REG_OPTIONAL>,
+ TLBI<"ALLE2IS", 0, 0b100, 0b1000, 0b0011, 0b000, REG_OPTIONAL>,
+ TLBI<"ALLE3IS", 0, 0b110, 0b1000, 0b0011, 0b000, REG_OPTIONAL>,
+ TLBI<"VAE1IS", 1, 0b000, 0b1000, 0b0011, 0b001, REG_REQUIRED>,
+ TLBI<"VAE2IS", 1, 0b100, 0b1000, 0b0011, 0b001, REG_REQUIRED>,
+ TLBI<"VAE3IS", 1, 0b110, 0b1000, 0b0011, 0b001, REG_REQUIRED>,
+ TLBI<"ASIDE1IS", 0, 0b000, 0b1000, 0b0011, 0b010, REG_REQUIRED>,
+ TLBI<"VAAE1IS", 1, 0b000, 0b1000, 0b0011, 0b011, REG_REQUIRED>,
+ TLBI<"ALLE1IS", 0, 0b100, 0b1000, 0b0011, 0b100, REG_OPTIONAL>,
+ TLBI<"VALE1IS", 1, 0b000, 0b1000, 0b0011, 0b101, REG_REQUIRED>,
+ TLBI<"VALE2IS", 1, 0b100, 0b1000, 0b0011, 0b101, REG_REQUIRED>,
+ TLBI<"VALE3IS", 1, 0b110, 0b1000, 0b0011, 0b101, REG_REQUIRED>,
+ TLBI<"VMALLS12E1IS", 0, 0b100, 0b1000, 0b0011, 0b110, REG_OPTIONAL>,
+ TLBI<"VAALE1IS", 1, 0b000, 0b1000, 0b0011, 0b111, REG_REQUIRED>,
+ TLBI<"IPAS2E1", 1, 0b100, 0b1000, 0b0100, 0b001, REG_REQUIRED>,
+ TLBI<"IPAS2LE1", 1, 0b100, 0b1000, 0b0100, 0b101, REG_REQUIRED>,
+ TLBI<"VMALLE1", 0, 0b000, 0b1000, 0b0111, 0b000, REG_NONE>,
+ TLBI<"ALLE2",0, 0b100, 0b1000, 0b0111, 0b000, REG_NONE>,
+ TLBI<"ALLE3",0, 0b110, 0b1000, 0b0111, 0b000, REG_NONE>,
+ TLBI<"VAE1", 1, 0b000, 0b1000, 0b0111, 0b001, REG_REQUIRED>,
+ TLBI<"VAE2", 1, 0b100, 0b1000, 0b0111, 0b001, REG_REQUIRED>,
+ TLBI<"VAE3", 1, 0b110, 0b1000, 0b0111, 0b001, REG_REQUIRED>,
+ TLBI<"ASIDE1", 0, 0b000, 0b1000, 0b0111, 0b010, REG_REQUIRED>,
+ TLBI<"VAAE1",1, 0b000, 0b1000, 0b0111, 0b011, REG_REQUIRED>,
+ TLBI<"ALLE1",0, 0b100, 0b1000, 0b0111, 0b100, REG_NONE>,
+ TLBI<"VALE1",1, 0b000, 0b1000, 0b0111, 0b101, REG_REQUIRED>,
+ TLBI<"VALE2",1, 0b100, 0b1000, 0b0111, 0b101, REG_REQUIRED>,
+ TLBI<"VALE3",1, 0b110, 0b1000, 0b0111, 0b101, REG_REQUIRED>,
+ TLBI<"VMALLS12E1", 0, 0b100, 0b1000, 0b0111, 0b110, REG_NONE>,
+ TLBI<"VAALE1", 1, 0b000, 0b1000, 0b0111, 0b111, REG_REQUIRED>
+];
+
+foreach I = TLBIBase in {
+ def : TLBIEntry;
+
+ def : TLBIEntry {
let ExtraRequires = ["AArch64::FeatureXS"];
}
- if !eq(hasTLBIP, true) then {
-def : TLBIPEntry {
- let ExtraRequires = ["AArch64::FeatureD128"];
+
+ if !eq(I.HasTLBIP, true) then {
+def : TLBIPEntry {
+ let Requires = ["AArch64::FeatureD128"];
}
-def : TLBIPEntry {
- let Encoding{7} = 1;
- let ExtraRequires = ["AArch64::FeatureD128"];
+
+// *nxs variants are gated by `FEAT_D128` not `FEAT_XS`
+def : TLBIPEntry {
+ let Requires = ["AArch64::FeatureD128"];
}
}
}
-// hasTLBIP op1CRn CRm op2reguse
-defm : TLBI<"IPAS2E1IS",1, 0b100, 0b1000, 0b, 0b001, REG_REQUIRED>;
-defm : TLBI<"IPAS2LE1IS", 1, 0b100, 0b1000, 0b, 0b101, REG_REQUIRED>;
-defm : TLBI<"VMALLE1IS",0, 0b000, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
-defm : TLBI<"ALLE2IS", 0, 0b100, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
-defm : TLBI<"ALLE3IS", 0, 0b110, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
-defm : TLBI<"VAE1IS", 1, 0b000, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
-defm : TLBI<"VAE2IS", 1, 0b100, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
-defm : TLBI<"VAE3IS", 1, 0b110, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
-defm : TLBI<"ASIDE1IS", 0, 0b000, 0b1000, 0b0011, 0b010, REG_REQUIRED>;
-defm : TLBI<"VAAE1IS", 1, 0b000, 0b1000, 0b0011, 0b011, REG_REQUIRED>;
-defm : TLBI<"ALLE1IS", 0, 0b100, 0b1000, 0b0011, 0b100, REG_OPTIONAL>;
-defm : TLBI<"VALE1IS", 1, 0b000, 0b1000, 0b0011, 0b101, REG_REQUIRED>;
-defm : TLBI<"VALE2IS", 1, 0b100, 0b1000, 0b0011, 0b101, REG_REQUIRED>;
-defm : TLBI<"VALE3IS", 1, 0b110, 0b1000, 0b0011, 0b101, REG_REQUIRED>;
-defm : TLBI<"VMALLS12E1IS", 0, 0b100, 0b1000, 0b0011, 0b110, REG_OPTIONAL>;
-defm : TLBI<"VAALE1IS", 1, 0b000, 0b1000, 0b0011, 0b111, REG_REQUIRED>;
-defm : TLBI<"IPAS2E1", 1, 0b100, 0b1000, 0b0100, 0b001, REG_REQUIRED>;
-defm : TLBI<"IPAS2LE1",
[llvm-branch-commits] [llvm] [AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (PR #187400)
https://github.com/jthackray updated
https://github.com/llvm/llvm-project/pull/187400
>From 0ea39f7eb7ec564f1281ec398f690ac3e8468f63 Mon Sep 17 00:00:00 2001
From: Jonathan Thackray
Date: Wed, 18 Mar 2026 20:54:50 +
Subject: [PATCH 1/7] [AArch64][llvm] Separate TLBI-only feature gating from
TLBIP aliases
Refactor the TLBI system operand definitions so that TLBI and TLBIP
records are emitted through separate helper multiclasses, whilst keeping
the table layout readable.
The feature-scoped wrappers now apply FeatureTLB_RMI, FeatureRME, and
FeatureTLBIW only to TLBI records (it was previously incorrectly also
applied to TLBIP instructions), while TLBIP aliases remain gated only
by FeatureD128, including their nXS forms.
Update testcases accordingly.
---
.../Target/AArch64/AArch64SystemOperands.td | 178 ++
llvm/test/MC/AArch64/armv9a-tlbip.s | 17 +-
2 files changed, 111 insertions(+), 84 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
index 257a4958e8305..d914b253c5358 100644
--- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
+++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
@@ -903,24 +903,54 @@ multiclass TLBITableBase {
defm TLBI : TLBITableBase;
defm TLBIP : TLBITableBase;
-multiclass TLBI op1, bits<4> crn, bits<4>
crm,
- bits<3> op2, int reguse = REG_REQUIRED> {
- def : TLBIEntry;
- def : TLBIEntry {
-let Encoding{7} = 1;
-let ExtraRequires = ["AArch64::FeatureXS"];
- }
- if !eq(hasTLBIP, true) then {
-def : TLBIPEntry {
- let ExtraRequires = ["AArch64::FeatureD128"];
+multiclass TLBI_Base op1, bits<4> crn, bits<4> crm,
+ bits<3> op2, int reguse = REG_REQUIRED,
+ list extra_requires = []> {
+ foreach nxs = [0, 1] in {
+defvar VariantName = !if(nxs, !strconcat(name, "nXS"), name);
+defvar VariantRequires = !if(nxs,
+ extra_requires # ["AArch64::FeatureXS"],
+ extra_requires);
+def : TLBIEntry {
+ let Encoding{7} = nxs;
+ let ExtraRequires = VariantRequires;
}
-def : TLBIPEntry {
- let Encoding{7} = 1;
- let ExtraRequires = ["AArch64::FeatureD128"];
+ }
+}
+
+multiclass TLBIP_Base op1, bits<4> crn, bits<4> crm,
+ bits<3> op2, int reguse = REG_REQUIRED,
+ list extra_requires = ["AArch64::FeatureD128"]> {
+ foreach nxs = [0, 1] in {
+// TLBIP instructions aren't gated by FeatureXS like TLBI ones
+defvar VariantName = !if(nxs, !strconcat(name, "nXS"), name);
+def : TLBIPEntry {
+ let Encoding{7} = nxs;
+ let ExtraRequires = extra_requires;
}
}
}
+multiclass TLBI op1, bits<4> crn,
+bits<4> crm, bits<3> op2, int reguse = REG_REQUIRED> {
+ defm : TLBI_Base;
+ if !eq(hasTLBIP, true) then {
+defm : TLBIP_Base;
+ }
+}
+
+multiclass TLBI_RMI op1, bits<4> crn,
+bits<4> crm, bits<3> op2, int reguse = REG_REQUIRED> {
+ let Requires = ["AArch64::FeatureTLB_RMI"] in {
+defm : TLBI_Base;
+ }
+ // TLBIP instructions aren't gated by FeatureTLB_RMI
+ if !eq(hasTLBIP, true) then {
+defm : TLBIP_Base;
+ }
+}
+
+// TLBI and TLBIP instructions encodings
// hasTLBIP op1CRn CRm op2reguse
defm : TLBI<"IPAS2E1IS",1, 0b100, 0b1000, 0b, 0b001, REG_REQUIRED>;
defm : TLBI<"IPAS2LE1IS", 1, 0b100, 0b1000, 0b, 0b101, REG_REQUIRED>;
@@ -955,76 +985,74 @@ defm : TLBI<"VALE3",1, 0b110, 0b1000, 0b0111,
0b101, REG_REQUIRED>;
defm : TLBI<"VMALLS12E1", 0, 0b100, 0b1000, 0b0111, 0b110, REG_NONE>;
defm : TLBI<"VAALE1", 1, 0b000, 0b1000, 0b0111, 0b111, REG_REQUIRED>;
-// Armv8.4-A Translation Lookaside Buffer Instructions (TLBI)
-let Requires = ["AArch64::FeatureTLB_RMI"] in {
+// Armv8.4-A Translation Lookaside Buffer Instructions (TLBI and TLBIP)
// Armv8.4-A Outer Sharable TLB Maintenance instructions:
-// hasTLBIP op1CRn CRm op2reguse
-defm : TLBI<"VMALLE1OS",0, 0b000, 0b1000, 0b0001, 0b000, REG_OPTIONAL>;
-defm : TLBI<"VAE1OS", 1, 0b000, 0b1000, 0b0001, 0b001, REG_REQUIRED>;
-defm : TLBI<"ASIDE1OS", 0, 0b000, 0b1000, 0b0001, 0b010, REG_REQUIRED>;
-defm : TLBI<"VAAE1OS", 1, 0b000, 0b1000, 0b0001, 0b011, REG_REQUIRED>;
-defm : TLBI<"VALE1OS", 1, 0b000, 0b1000, 0b0001, 0b101, REG_REQUIRED>;
-defm : TLBI<"VAALE1OS", 1, 0b000, 0b1000, 0b0001, 0b111, REG_REQUIRED>;
-defm : TLBI<"IPAS2E1OS",1, 0b100, 0b1000, 0b0100, 0b000, REG_REQUIRED>;
-defm : TLBI<"IPAS2LE1OS", 1, 0b100, 0b1000, 0b0100, 0b100, REG_REQUIRED>;
-defm : TLBI<"VAE2OS", 1, 0b100, 0b1000, 0b0001, 0b001, REG_REQUIRED>;
-defm : TLBI<"VALE2OS", 1, 0b100, 0b1000, 0b0001, 0b101, REG_REQUIRED>;
-defm : TLBI<"VMALLS12E1OS", 0, 0b100, 0b1000, 0b0001, 0b110, REG_OPTIONAL>;
-defm : TLBI<"VAE3OS", 1,
[llvm-branch-commits] [llvm] [AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (PR #187400)
@@ -903,128 +904,175 @@ multiclass TLBITableBase {
defm TLBI : TLBITableBase;
defm TLBIP : TLBITableBase;
-multiclass TLBI op1, bits<4> crn, bits<4>
crm,
- bits<3> op2, int reguse = REG_REQUIRED> {
- def : TLBIEntry;
- def : TLBIEntry {
-let Encoding{7} = 1;
+class TLBI op1, bits<4> crn,
+ bits<4> crm, bits<3> op2, int reguse = REG_REQUIRED> {
+ string Name = name;
+ bit HasTLBIP = hasTLBIP;
+ bits<3> Op1 = op1;
+ bits<4> CRn = crn;
+ bits<4> CRm = crm;
+ bits<3> Op2 = op2;
+ int RegUse = reguse;
+}
+
+// TLBI and TLBIP instructions encodings.
+defvar TLBIBase = [
+ //namehasTLBIP op1CRn CRm op2reguse
+ TLBI<"IPAS2E1IS",1, 0b100, 0b1000, 0b, 0b001, REG_REQUIRED>,
+ TLBI<"IPAS2LE1IS", 1, 0b100, 0b1000, 0b, 0b101, REG_REQUIRED>,
+ TLBI<"VMALLE1IS",0, 0b000, 0b1000, 0b0011, 0b000, REG_OPTIONAL>,
+ TLBI<"ALLE2IS", 0, 0b100, 0b1000, 0b0011, 0b000, REG_OPTIONAL>,
+ TLBI<"ALLE3IS", 0, 0b110, 0b1000, 0b0011, 0b000, REG_OPTIONAL>,
+ TLBI<"VAE1IS", 1, 0b000, 0b1000, 0b0011, 0b001, REG_REQUIRED>,
+ TLBI<"VAE2IS", 1, 0b100, 0b1000, 0b0011, 0b001, REG_REQUIRED>,
+ TLBI<"VAE3IS", 1, 0b110, 0b1000, 0b0011, 0b001, REG_REQUIRED>,
+ TLBI<"ASIDE1IS", 0, 0b000, 0b1000, 0b0011, 0b010, REG_REQUIRED>,
+ TLBI<"VAAE1IS", 1, 0b000, 0b1000, 0b0011, 0b011, REG_REQUIRED>,
+ TLBI<"ALLE1IS", 0, 0b100, 0b1000, 0b0011, 0b100, REG_OPTIONAL>,
+ TLBI<"VALE1IS", 1, 0b000, 0b1000, 0b0011, 0b101, REG_REQUIRED>,
+ TLBI<"VALE2IS", 1, 0b100, 0b1000, 0b0011, 0b101, REG_REQUIRED>,
+ TLBI<"VALE3IS", 1, 0b110, 0b1000, 0b0011, 0b101, REG_REQUIRED>,
+ TLBI<"VMALLS12E1IS", 0, 0b100, 0b1000, 0b0011, 0b110, REG_OPTIONAL>,
+ TLBI<"VAALE1IS", 1, 0b000, 0b1000, 0b0011, 0b111, REG_REQUIRED>,
+ TLBI<"IPAS2E1", 1, 0b100, 0b1000, 0b0100, 0b001, REG_REQUIRED>,
+ TLBI<"IPAS2LE1", 1, 0b100, 0b1000, 0b0100, 0b101, REG_REQUIRED>,
+ TLBI<"VMALLE1", 0, 0b000, 0b1000, 0b0111, 0b000, REG_NONE>,
+ TLBI<"ALLE2",0, 0b100, 0b1000, 0b0111, 0b000, REG_NONE>,
+ TLBI<"ALLE3",0, 0b110, 0b1000, 0b0111, 0b000, REG_NONE>,
+ TLBI<"VAE1", 1, 0b000, 0b1000, 0b0111, 0b001, REG_REQUIRED>,
+ TLBI<"VAE2", 1, 0b100, 0b1000, 0b0111, 0b001, REG_REQUIRED>,
+ TLBI<"VAE3", 1, 0b110, 0b1000, 0b0111, 0b001, REG_REQUIRED>,
+ TLBI<"ASIDE1", 0, 0b000, 0b1000, 0b0111, 0b010, REG_REQUIRED>,
+ TLBI<"VAAE1",1, 0b000, 0b1000, 0b0111, 0b011, REG_REQUIRED>,
+ TLBI<"ALLE1",0, 0b100, 0b1000, 0b0111, 0b100, REG_NONE>,
+ TLBI<"VALE1",1, 0b000, 0b1000, 0b0111, 0b101, REG_REQUIRED>,
+ TLBI<"VALE2",1, 0b100, 0b1000, 0b0111, 0b101, REG_REQUIRED>,
+ TLBI<"VALE3",1, 0b110, 0b1000, 0b0111, 0b101, REG_REQUIRED>,
+ TLBI<"VMALLS12E1", 0, 0b100, 0b1000, 0b0111, 0b110, REG_NONE>,
+ TLBI<"VAALE1", 1, 0b000, 0b1000, 0b0111, 0b111, REG_REQUIRED>
+];
+
+foreach I = TLBIBase in {
+ def : TLBIEntry;
+
+ def : TLBIEntry {
let ExtraRequires = ["AArch64::FeatureXS"];
}
- if !eq(hasTLBIP, true) then {
-def : TLBIPEntry {
- let ExtraRequires = ["AArch64::FeatureD128"];
+
+ if !eq(I.HasTLBIP, true) then {
+def : TLBIPEntry {
+ let Requires = ["AArch64::FeatureD128"];
}
-def : TLBIPEntry {
- let Encoding{7} = 1;
- let ExtraRequires = ["AArch64::FeatureD128"];
+
+// *nxs variants are gated by `FEAT_D128` not `FEAT_XS`
+def : TLBIPEntry {
+ let Requires = ["AArch64::FeatureD128"];
}
}
}
-// hasTLBIP op1CRn CRm op2reguse
-defm : TLBI<"IPAS2E1IS",1, 0b100, 0b1000, 0b, 0b001, REG_REQUIRED>;
-defm : TLBI<"IPAS2LE1IS", 1, 0b100, 0b1000, 0b, 0b101, REG_REQUIRED>;
-defm : TLBI<"VMALLE1IS",0, 0b000, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
-defm : TLBI<"ALLE2IS", 0, 0b100, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
-defm : TLBI<"ALLE3IS", 0, 0b110, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
-defm : TLBI<"VAE1IS", 1, 0b000, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
-defm : TLBI<"VAE2IS", 1, 0b100, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
-defm : TLBI<"VAE3IS", 1, 0b110, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
-defm : TLBI<"ASIDE1IS", 0, 0b000, 0b1000, 0b0011, 0b010, REG_REQUIRED>;
-defm : TLBI<"VAAE1IS", 1, 0b000, 0b1000, 0b0011, 0b011, REG_REQUIRED>;
-defm : TLBI<"ALLE1IS", 0, 0b100, 0b1000, 0b0011, 0b100, REG_OPTIONAL>;
-defm : TLBI<"VALE1IS", 1, 0b000, 0b1000, 0b0011, 0b101, REG_REQUIRED>;
-defm : TLBI<"VALE2IS", 1, 0b100, 0b1000, 0b0011, 0b101, REG_REQUIRED>;
-defm : TLBI<"VALE3IS", 1, 0b110, 0b1000, 0b0011, 0b101, REG_REQUIRED>;
-defm : TLBI<"VMALLS12E1IS", 0, 0b100, 0b1000, 0b0011, 0b110, REG_OPTIONAL>;
-defm : TLBI<"VAALE1IS", 1, 0b000, 0b1000, 0b0011, 0b111, REG_REQUIRED>;
-defm : TLBI<"IPAS2E1", 1, 0b100, 0b1000, 0b0100, 0b001, REG_REQUIRED>;
-defm : TLBI<"IPAS2LE1",
[llvm-branch-commits] [llvm] [AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (PR #187400)
https://github.com/jthackray updated
https://github.com/llvm/llvm-project/pull/187400
>From 0ea39f7eb7ec564f1281ec398f690ac3e8468f63 Mon Sep 17 00:00:00 2001
From: Jonathan Thackray
Date: Wed, 18 Mar 2026 20:54:50 +
Subject: [PATCH 1/7] [AArch64][llvm] Separate TLBI-only feature gating from
TLBIP aliases
Refactor the TLBI system operand definitions so that TLBI and TLBIP
records are emitted through separate helper multiclasses, whilst keeping
the table layout readable.
The feature-scoped wrappers now apply FeatureTLB_RMI, FeatureRME, and
FeatureTLBIW only to TLBI records (it was previously incorrectly also
applied to TLBIP instructions), while TLBIP aliases remain gated only
by FeatureD128, including their nXS forms.
Update testcases accordingly.
---
.../Target/AArch64/AArch64SystemOperands.td | 178 ++
llvm/test/MC/AArch64/armv9a-tlbip.s | 17 +-
2 files changed, 111 insertions(+), 84 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
index 257a4958e8305..d914b253c5358 100644
--- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
+++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
@@ -903,24 +903,54 @@ multiclass TLBITableBase {
defm TLBI : TLBITableBase;
defm TLBIP : TLBITableBase;
-multiclass TLBI op1, bits<4> crn, bits<4>
crm,
- bits<3> op2, int reguse = REG_REQUIRED> {
- def : TLBIEntry;
- def : TLBIEntry {
-let Encoding{7} = 1;
-let ExtraRequires = ["AArch64::FeatureXS"];
- }
- if !eq(hasTLBIP, true) then {
-def : TLBIPEntry {
- let ExtraRequires = ["AArch64::FeatureD128"];
+multiclass TLBI_Base op1, bits<4> crn, bits<4> crm,
+ bits<3> op2, int reguse = REG_REQUIRED,
+ list extra_requires = []> {
+ foreach nxs = [0, 1] in {
+defvar VariantName = !if(nxs, !strconcat(name, "nXS"), name);
+defvar VariantRequires = !if(nxs,
+ extra_requires # ["AArch64::FeatureXS"],
+ extra_requires);
+def : TLBIEntry {
+ let Encoding{7} = nxs;
+ let ExtraRequires = VariantRequires;
}
-def : TLBIPEntry {
- let Encoding{7} = 1;
- let ExtraRequires = ["AArch64::FeatureD128"];
+ }
+}
+
+multiclass TLBIP_Base op1, bits<4> crn, bits<4> crm,
+ bits<3> op2, int reguse = REG_REQUIRED,
+ list extra_requires = ["AArch64::FeatureD128"]> {
+ foreach nxs = [0, 1] in {
+// TLBIP instructions aren't gated by FeatureXS like TLBI ones
+defvar VariantName = !if(nxs, !strconcat(name, "nXS"), name);
+def : TLBIPEntry {
+ let Encoding{7} = nxs;
+ let ExtraRequires = extra_requires;
}
}
}
+multiclass TLBI op1, bits<4> crn,
+bits<4> crm, bits<3> op2, int reguse = REG_REQUIRED> {
+ defm : TLBI_Base;
+ if !eq(hasTLBIP, true) then {
+defm : TLBIP_Base;
+ }
+}
+
+multiclass TLBI_RMI op1, bits<4> crn,
+bits<4> crm, bits<3> op2, int reguse = REG_REQUIRED> {
+ let Requires = ["AArch64::FeatureTLB_RMI"] in {
+defm : TLBI_Base;
+ }
+ // TLBIP instructions aren't gated by FeatureTLB_RMI
+ if !eq(hasTLBIP, true) then {
+defm : TLBIP_Base;
+ }
+}
+
+// TLBI and TLBIP instructions encodings
// hasTLBIP op1CRn CRm op2reguse
defm : TLBI<"IPAS2E1IS",1, 0b100, 0b1000, 0b, 0b001, REG_REQUIRED>;
defm : TLBI<"IPAS2LE1IS", 1, 0b100, 0b1000, 0b, 0b101, REG_REQUIRED>;
@@ -955,76 +985,74 @@ defm : TLBI<"VALE3",1, 0b110, 0b1000, 0b0111,
0b101, REG_REQUIRED>;
defm : TLBI<"VMALLS12E1", 0, 0b100, 0b1000, 0b0111, 0b110, REG_NONE>;
defm : TLBI<"VAALE1", 1, 0b000, 0b1000, 0b0111, 0b111, REG_REQUIRED>;
-// Armv8.4-A Translation Lookaside Buffer Instructions (TLBI)
-let Requires = ["AArch64::FeatureTLB_RMI"] in {
+// Armv8.4-A Translation Lookaside Buffer Instructions (TLBI and TLBIP)
// Armv8.4-A Outer Sharable TLB Maintenance instructions:
-// hasTLBIP op1CRn CRm op2reguse
-defm : TLBI<"VMALLE1OS",0, 0b000, 0b1000, 0b0001, 0b000, REG_OPTIONAL>;
-defm : TLBI<"VAE1OS", 1, 0b000, 0b1000, 0b0001, 0b001, REG_REQUIRED>;
-defm : TLBI<"ASIDE1OS", 0, 0b000, 0b1000, 0b0001, 0b010, REG_REQUIRED>;
-defm : TLBI<"VAAE1OS", 1, 0b000, 0b1000, 0b0001, 0b011, REG_REQUIRED>;
-defm : TLBI<"VALE1OS", 1, 0b000, 0b1000, 0b0001, 0b101, REG_REQUIRED>;
-defm : TLBI<"VAALE1OS", 1, 0b000, 0b1000, 0b0001, 0b111, REG_REQUIRED>;
-defm : TLBI<"IPAS2E1OS",1, 0b100, 0b1000, 0b0100, 0b000, REG_REQUIRED>;
-defm : TLBI<"IPAS2LE1OS", 1, 0b100, 0b1000, 0b0100, 0b100, REG_REQUIRED>;
-defm : TLBI<"VAE2OS", 1, 0b100, 0b1000, 0b0001, 0b001, REG_REQUIRED>;
-defm : TLBI<"VALE2OS", 1, 0b100, 0b1000, 0b0001, 0b101, REG_REQUIRED>;
-defm : TLBI<"VMALLS12E1OS", 0, 0b100, 0b1000, 0b0001, 0b110, REG_OPTIONAL>;
-defm : TLBI<"VAE3OS", 1,
[llvm-branch-commits] [llvm] [AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (PR #187400)
@@ -903,128 +904,175 @@ multiclass TLBITableBase {
defm TLBI : TLBITableBase;
defm TLBIP : TLBITableBase;
-multiclass TLBI op1, bits<4> crn, bits<4>
crm,
- bits<3> op2, int reguse = REG_REQUIRED> {
- def : TLBIEntry;
- def : TLBIEntry {
-let Encoding{7} = 1;
+class TLBI op1, bits<4> crn,
+ bits<4> crm, bits<3> op2, int reguse = REG_REQUIRED> {
+ string Name = name;
+ bit HasTLBIP = hasTLBIP;
+ bits<3> Op1 = op1;
+ bits<4> CRn = crn;
+ bits<4> CRm = crm;
+ bits<3> Op2 = op2;
+ int RegUse = reguse;
+}
+
+// TLBI and TLBIP instructions encodings.
+defvar TLBIBase = [
+ //namehasTLBIP op1CRn CRm op2reguse
+ TLBI<"IPAS2E1IS",1, 0b100, 0b1000, 0b, 0b001, REG_REQUIRED>,
+ TLBI<"IPAS2LE1IS", 1, 0b100, 0b1000, 0b, 0b101, REG_REQUIRED>,
+ TLBI<"VMALLE1IS",0, 0b000, 0b1000, 0b0011, 0b000, REG_OPTIONAL>,
+ TLBI<"ALLE2IS", 0, 0b100, 0b1000, 0b0011, 0b000, REG_OPTIONAL>,
+ TLBI<"ALLE3IS", 0, 0b110, 0b1000, 0b0011, 0b000, REG_OPTIONAL>,
+ TLBI<"VAE1IS", 1, 0b000, 0b1000, 0b0011, 0b001, REG_REQUIRED>,
+ TLBI<"VAE2IS", 1, 0b100, 0b1000, 0b0011, 0b001, REG_REQUIRED>,
+ TLBI<"VAE3IS", 1, 0b110, 0b1000, 0b0011, 0b001, REG_REQUIRED>,
+ TLBI<"ASIDE1IS", 0, 0b000, 0b1000, 0b0011, 0b010, REG_REQUIRED>,
+ TLBI<"VAAE1IS", 1, 0b000, 0b1000, 0b0011, 0b011, REG_REQUIRED>,
+ TLBI<"ALLE1IS", 0, 0b100, 0b1000, 0b0011, 0b100, REG_OPTIONAL>,
+ TLBI<"VALE1IS", 1, 0b000, 0b1000, 0b0011, 0b101, REG_REQUIRED>,
+ TLBI<"VALE2IS", 1, 0b100, 0b1000, 0b0011, 0b101, REG_REQUIRED>,
+ TLBI<"VALE3IS", 1, 0b110, 0b1000, 0b0011, 0b101, REG_REQUIRED>,
+ TLBI<"VMALLS12E1IS", 0, 0b100, 0b1000, 0b0011, 0b110, REG_OPTIONAL>,
+ TLBI<"VAALE1IS", 1, 0b000, 0b1000, 0b0011, 0b111, REG_REQUIRED>,
+ TLBI<"IPAS2E1", 1, 0b100, 0b1000, 0b0100, 0b001, REG_REQUIRED>,
+ TLBI<"IPAS2LE1", 1, 0b100, 0b1000, 0b0100, 0b101, REG_REQUIRED>,
+ TLBI<"VMALLE1", 0, 0b000, 0b1000, 0b0111, 0b000, REG_NONE>,
+ TLBI<"ALLE2",0, 0b100, 0b1000, 0b0111, 0b000, REG_NONE>,
+ TLBI<"ALLE3",0, 0b110, 0b1000, 0b0111, 0b000, REG_NONE>,
+ TLBI<"VAE1", 1, 0b000, 0b1000, 0b0111, 0b001, REG_REQUIRED>,
+ TLBI<"VAE2", 1, 0b100, 0b1000, 0b0111, 0b001, REG_REQUIRED>,
+ TLBI<"VAE3", 1, 0b110, 0b1000, 0b0111, 0b001, REG_REQUIRED>,
+ TLBI<"ASIDE1", 0, 0b000, 0b1000, 0b0111, 0b010, REG_REQUIRED>,
+ TLBI<"VAAE1",1, 0b000, 0b1000, 0b0111, 0b011, REG_REQUIRED>,
+ TLBI<"ALLE1",0, 0b100, 0b1000, 0b0111, 0b100, REG_NONE>,
+ TLBI<"VALE1",1, 0b000, 0b1000, 0b0111, 0b101, REG_REQUIRED>,
+ TLBI<"VALE2",1, 0b100, 0b1000, 0b0111, 0b101, REG_REQUIRED>,
+ TLBI<"VALE3",1, 0b110, 0b1000, 0b0111, 0b101, REG_REQUIRED>,
+ TLBI<"VMALLS12E1", 0, 0b100, 0b1000, 0b0111, 0b110, REG_NONE>,
+ TLBI<"VAALE1", 1, 0b000, 0b1000, 0b0111, 0b111, REG_REQUIRED>
+];
+
+foreach I = TLBIBase in {
+ def : TLBIEntry;
+
+ def : TLBIEntry {
let ExtraRequires = ["AArch64::FeatureXS"];
}
- if !eq(hasTLBIP, true) then {
-def : TLBIPEntry {
- let ExtraRequires = ["AArch64::FeatureD128"];
+
+ if !eq(I.HasTLBIP, true) then {
+def : TLBIPEntry {
+ let Requires = ["AArch64::FeatureD128"];
}
-def : TLBIPEntry {
- let Encoding{7} = 1;
- let ExtraRequires = ["AArch64::FeatureD128"];
+
+// *nxs variants are gated by `FEAT_D128` not `FEAT_XS`
+def : TLBIPEntry {
+ let Requires = ["AArch64::FeatureD128"];
}
}
}
-// hasTLBIP op1CRn CRm op2reguse
-defm : TLBI<"IPAS2E1IS",1, 0b100, 0b1000, 0b, 0b001, REG_REQUIRED>;
-defm : TLBI<"IPAS2LE1IS", 1, 0b100, 0b1000, 0b, 0b101, REG_REQUIRED>;
-defm : TLBI<"VMALLE1IS",0, 0b000, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
-defm : TLBI<"ALLE2IS", 0, 0b100, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
-defm : TLBI<"ALLE3IS", 0, 0b110, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
-defm : TLBI<"VAE1IS", 1, 0b000, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
-defm : TLBI<"VAE2IS", 1, 0b100, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
-defm : TLBI<"VAE3IS", 1, 0b110, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
-defm : TLBI<"ASIDE1IS", 0, 0b000, 0b1000, 0b0011, 0b010, REG_REQUIRED>;
-defm : TLBI<"VAAE1IS", 1, 0b000, 0b1000, 0b0011, 0b011, REG_REQUIRED>;
-defm : TLBI<"ALLE1IS", 0, 0b100, 0b1000, 0b0011, 0b100, REG_OPTIONAL>;
-defm : TLBI<"VALE1IS", 1, 0b000, 0b1000, 0b0011, 0b101, REG_REQUIRED>;
-defm : TLBI<"VALE2IS", 1, 0b100, 0b1000, 0b0011, 0b101, REG_REQUIRED>;
-defm : TLBI<"VALE3IS", 1, 0b110, 0b1000, 0b0011, 0b101, REG_REQUIRED>;
-defm : TLBI<"VMALLS12E1IS", 0, 0b100, 0b1000, 0b0011, 0b110, REG_OPTIONAL>;
-defm : TLBI<"VAALE1IS", 1, 0b000, 0b1000, 0b0011, 0b111, REG_REQUIRED>;
-defm : TLBI<"IPAS2E1", 1, 0b100, 0b1000, 0b0100, 0b001, REG_REQUIRED>;
-defm : TLBI<"IPAS2LE1",
[llvm-branch-commits] [llvm] [AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (PR #187400)
@@ -903,128 +904,175 @@ multiclass TLBITableBase {
defm TLBI : TLBITableBase;
defm TLBIP : TLBITableBase;
-multiclass TLBI op1, bits<4> crn, bits<4>
crm,
- bits<3> op2, int reguse = REG_REQUIRED> {
- def : TLBIEntry;
- def : TLBIEntry {
-let Encoding{7} = 1;
+class TLBI op1, bits<4> crn,
+ bits<4> crm, bits<3> op2, int reguse = REG_REQUIRED> {
+ string Name = name;
+ bit HasTLBIP = hasTLBIP;
+ bits<3> Op1 = op1;
+ bits<4> CRn = crn;
+ bits<4> CRm = crm;
+ bits<3> Op2 = op2;
+ int RegUse = reguse;
+}
+
+// TLBI and TLBIP instructions encodings.
+defvar TLBIBase = [
+ //namehasTLBIP op1CRn CRm op2reguse
Lukacma wrote:
After proposed changes above, CRn field becomes unnecessary in all tables
https://github.com/llvm/llvm-project/pull/187400
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[llvm-branch-commits] [llvm] [AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (PR #187400)
@@ -903,128 +904,175 @@ multiclass TLBITableBase {
defm TLBI : TLBITableBase;
defm TLBIP : TLBITableBase;
-multiclass TLBI op1, bits<4> crn, bits<4>
crm,
- bits<3> op2, int reguse = REG_REQUIRED> {
- def : TLBIEntry;
- def : TLBIEntry {
-let Encoding{7} = 1;
+class TLBI op1, bits<4> crn,
+ bits<4> crm, bits<3> op2, int reguse = REG_REQUIRED> {
+ string Name = name;
+ bit HasTLBIP = hasTLBIP;
+ bits<3> Op1 = op1;
+ bits<4> CRn = crn;
+ bits<4> CRm = crm;
+ bits<3> Op2 = op2;
+ int RegUse = reguse;
+}
+
+// TLBI and TLBIP instructions encodings.
+defvar TLBIBase = [
+ //namehasTLBIP op1CRn CRm op2reguse
+ TLBI<"IPAS2E1IS",1, 0b100, 0b1000, 0b, 0b001, REG_REQUIRED>,
+ TLBI<"IPAS2LE1IS", 1, 0b100, 0b1000, 0b, 0b101, REG_REQUIRED>,
+ TLBI<"VMALLE1IS",0, 0b000, 0b1000, 0b0011, 0b000, REG_OPTIONAL>,
+ TLBI<"ALLE2IS", 0, 0b100, 0b1000, 0b0011, 0b000, REG_OPTIONAL>,
+ TLBI<"ALLE3IS", 0, 0b110, 0b1000, 0b0011, 0b000, REG_OPTIONAL>,
+ TLBI<"VAE1IS", 1, 0b000, 0b1000, 0b0011, 0b001, REG_REQUIRED>,
+ TLBI<"VAE2IS", 1, 0b100, 0b1000, 0b0011, 0b001, REG_REQUIRED>,
+ TLBI<"VAE3IS", 1, 0b110, 0b1000, 0b0011, 0b001, REG_REQUIRED>,
+ TLBI<"ASIDE1IS", 0, 0b000, 0b1000, 0b0011, 0b010, REG_REQUIRED>,
+ TLBI<"VAAE1IS", 1, 0b000, 0b1000, 0b0011, 0b011, REG_REQUIRED>,
+ TLBI<"ALLE1IS", 0, 0b100, 0b1000, 0b0011, 0b100, REG_OPTIONAL>,
+ TLBI<"VALE1IS", 1, 0b000, 0b1000, 0b0011, 0b101, REG_REQUIRED>,
+ TLBI<"VALE2IS", 1, 0b100, 0b1000, 0b0011, 0b101, REG_REQUIRED>,
+ TLBI<"VALE3IS", 1, 0b110, 0b1000, 0b0011, 0b101, REG_REQUIRED>,
+ TLBI<"VMALLS12E1IS", 0, 0b100, 0b1000, 0b0011, 0b110, REG_OPTIONAL>,
+ TLBI<"VAALE1IS", 1, 0b000, 0b1000, 0b0011, 0b111, REG_REQUIRED>,
+ TLBI<"IPAS2E1", 1, 0b100, 0b1000, 0b0100, 0b001, REG_REQUIRED>,
+ TLBI<"IPAS2LE1", 1, 0b100, 0b1000, 0b0100, 0b101, REG_REQUIRED>,
+ TLBI<"VMALLE1", 0, 0b000, 0b1000, 0b0111, 0b000, REG_NONE>,
+ TLBI<"ALLE2",0, 0b100, 0b1000, 0b0111, 0b000, REG_NONE>,
+ TLBI<"ALLE3",0, 0b110, 0b1000, 0b0111, 0b000, REG_NONE>,
+ TLBI<"VAE1", 1, 0b000, 0b1000, 0b0111, 0b001, REG_REQUIRED>,
+ TLBI<"VAE2", 1, 0b100, 0b1000, 0b0111, 0b001, REG_REQUIRED>,
+ TLBI<"VAE3", 1, 0b110, 0b1000, 0b0111, 0b001, REG_REQUIRED>,
+ TLBI<"ASIDE1", 0, 0b000, 0b1000, 0b0111, 0b010, REG_REQUIRED>,
+ TLBI<"VAAE1",1, 0b000, 0b1000, 0b0111, 0b011, REG_REQUIRED>,
+ TLBI<"ALLE1",0, 0b100, 0b1000, 0b0111, 0b100, REG_NONE>,
+ TLBI<"VALE1",1, 0b000, 0b1000, 0b0111, 0b101, REG_REQUIRED>,
+ TLBI<"VALE2",1, 0b100, 0b1000, 0b0111, 0b101, REG_REQUIRED>,
+ TLBI<"VALE3",1, 0b110, 0b1000, 0b0111, 0b101, REG_REQUIRED>,
+ TLBI<"VMALLS12E1", 0, 0b100, 0b1000, 0b0111, 0b110, REG_NONE>,
+ TLBI<"VAALE1", 1, 0b000, 0b1000, 0b0111, 0b111, REG_REQUIRED>
+];
+
+foreach I = TLBIBase in {
+ def : TLBIEntry;
+
+ def : TLBIEntry {
let ExtraRequires = ["AArch64::FeatureXS"];
}
- if !eq(hasTLBIP, true) then {
-def : TLBIPEntry {
- let ExtraRequires = ["AArch64::FeatureD128"];
+
+ if !eq(I.HasTLBIP, true) then {
+def : TLBIPEntry {
+ let Requires = ["AArch64::FeatureD128"];
}
-def : TLBIPEntry {
- let Encoding{7} = 1;
- let ExtraRequires = ["AArch64::FeatureD128"];
+
+// *nxs variants are gated by `FEAT_D128` not `FEAT_XS`
+def : TLBIPEntry {
+ let Requires = ["AArch64::FeatureD128"];
}
}
}
-// hasTLBIP op1CRn CRm op2reguse
-defm : TLBI<"IPAS2E1IS",1, 0b100, 0b1000, 0b, 0b001, REG_REQUIRED>;
-defm : TLBI<"IPAS2LE1IS", 1, 0b100, 0b1000, 0b, 0b101, REG_REQUIRED>;
-defm : TLBI<"VMALLE1IS",0, 0b000, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
-defm : TLBI<"ALLE2IS", 0, 0b100, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
-defm : TLBI<"ALLE3IS", 0, 0b110, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
-defm : TLBI<"VAE1IS", 1, 0b000, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
-defm : TLBI<"VAE2IS", 1, 0b100, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
-defm : TLBI<"VAE3IS", 1, 0b110, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
-defm : TLBI<"ASIDE1IS", 0, 0b000, 0b1000, 0b0011, 0b010, REG_REQUIRED>;
-defm : TLBI<"VAAE1IS", 1, 0b000, 0b1000, 0b0011, 0b011, REG_REQUIRED>;
-defm : TLBI<"ALLE1IS", 0, 0b100, 0b1000, 0b0011, 0b100, REG_OPTIONAL>;
-defm : TLBI<"VALE1IS", 1, 0b000, 0b1000, 0b0011, 0b101, REG_REQUIRED>;
-defm : TLBI<"VALE2IS", 1, 0b100, 0b1000, 0b0011, 0b101, REG_REQUIRED>;
-defm : TLBI<"VALE3IS", 1, 0b110, 0b1000, 0b0011, 0b101, REG_REQUIRED>;
-defm : TLBI<"VMALLS12E1IS", 0, 0b100, 0b1000, 0b0011, 0b110, REG_OPTIONAL>;
-defm : TLBI<"VAALE1IS", 1, 0b000, 0b1000, 0b0011, 0b111, REG_REQUIRED>;
-defm : TLBI<"IPAS2E1", 1, 0b100, 0b1000, 0b0100, 0b001, REG_REQUIRED>;
-defm : TLBI<"IPAS2LE1",
[llvm-branch-commits] [llvm] [AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (PR #187400)
@@ -903,128 +904,175 @@ multiclass TLBITableBase {
defm TLBI : TLBITableBase;
defm TLBIP : TLBITableBase;
-multiclass TLBI op1, bits<4> crn, bits<4>
crm,
- bits<3> op2, int reguse = REG_REQUIRED> {
- def : TLBIEntry;
- def : TLBIEntry {
-let Encoding{7} = 1;
+class TLBI op1, bits<4> crn,
+ bits<4> crm, bits<3> op2, int reguse = REG_REQUIRED> {
+ string Name = name;
+ bit HasTLBIP = hasTLBIP;
+ bits<3> Op1 = op1;
+ bits<4> CRn = crn;
+ bits<4> CRm = crm;
+ bits<3> Op2 = op2;
+ int RegUse = reguse;
+}
+
+// TLBI and TLBIP instructions encodings.
+defvar TLBIBase = [
+ //namehasTLBIP op1CRn CRm op2reguse
+ TLBI<"IPAS2E1IS",1, 0b100, 0b1000, 0b, 0b001, REG_REQUIRED>,
+ TLBI<"IPAS2LE1IS", 1, 0b100, 0b1000, 0b, 0b101, REG_REQUIRED>,
+ TLBI<"VMALLE1IS",0, 0b000, 0b1000, 0b0011, 0b000, REG_OPTIONAL>,
+ TLBI<"ALLE2IS", 0, 0b100, 0b1000, 0b0011, 0b000, REG_OPTIONAL>,
+ TLBI<"ALLE3IS", 0, 0b110, 0b1000, 0b0011, 0b000, REG_OPTIONAL>,
+ TLBI<"VAE1IS", 1, 0b000, 0b1000, 0b0011, 0b001, REG_REQUIRED>,
+ TLBI<"VAE2IS", 1, 0b100, 0b1000, 0b0011, 0b001, REG_REQUIRED>,
+ TLBI<"VAE3IS", 1, 0b110, 0b1000, 0b0011, 0b001, REG_REQUIRED>,
+ TLBI<"ASIDE1IS", 0, 0b000, 0b1000, 0b0011, 0b010, REG_REQUIRED>,
+ TLBI<"VAAE1IS", 1, 0b000, 0b1000, 0b0011, 0b011, REG_REQUIRED>,
+ TLBI<"ALLE1IS", 0, 0b100, 0b1000, 0b0011, 0b100, REG_OPTIONAL>,
+ TLBI<"VALE1IS", 1, 0b000, 0b1000, 0b0011, 0b101, REG_REQUIRED>,
+ TLBI<"VALE2IS", 1, 0b100, 0b1000, 0b0011, 0b101, REG_REQUIRED>,
+ TLBI<"VALE3IS", 1, 0b110, 0b1000, 0b0011, 0b101, REG_REQUIRED>,
+ TLBI<"VMALLS12E1IS", 0, 0b100, 0b1000, 0b0011, 0b110, REG_OPTIONAL>,
+ TLBI<"VAALE1IS", 1, 0b000, 0b1000, 0b0011, 0b111, REG_REQUIRED>,
+ TLBI<"IPAS2E1", 1, 0b100, 0b1000, 0b0100, 0b001, REG_REQUIRED>,
+ TLBI<"IPAS2LE1", 1, 0b100, 0b1000, 0b0100, 0b101, REG_REQUIRED>,
+ TLBI<"VMALLE1", 0, 0b000, 0b1000, 0b0111, 0b000, REG_NONE>,
+ TLBI<"ALLE2",0, 0b100, 0b1000, 0b0111, 0b000, REG_NONE>,
+ TLBI<"ALLE3",0, 0b110, 0b1000, 0b0111, 0b000, REG_NONE>,
+ TLBI<"VAE1", 1, 0b000, 0b1000, 0b0111, 0b001, REG_REQUIRED>,
+ TLBI<"VAE2", 1, 0b100, 0b1000, 0b0111, 0b001, REG_REQUIRED>,
+ TLBI<"VAE3", 1, 0b110, 0b1000, 0b0111, 0b001, REG_REQUIRED>,
+ TLBI<"ASIDE1", 0, 0b000, 0b1000, 0b0111, 0b010, REG_REQUIRED>,
+ TLBI<"VAAE1",1, 0b000, 0b1000, 0b0111, 0b011, REG_REQUIRED>,
+ TLBI<"ALLE1",0, 0b100, 0b1000, 0b0111, 0b100, REG_NONE>,
+ TLBI<"VALE1",1, 0b000, 0b1000, 0b0111, 0b101, REG_REQUIRED>,
+ TLBI<"VALE2",1, 0b100, 0b1000, 0b0111, 0b101, REG_REQUIRED>,
+ TLBI<"VALE3",1, 0b110, 0b1000, 0b0111, 0b101, REG_REQUIRED>,
+ TLBI<"VMALLS12E1", 0, 0b100, 0b1000, 0b0111, 0b110, REG_NONE>,
+ TLBI<"VAALE1", 1, 0b000, 0b1000, 0b0111, 0b111, REG_REQUIRED>
+];
+
+foreach I = TLBIBase in {
+ def : TLBIEntry;
+
+ def : TLBIEntry {
let ExtraRequires = ["AArch64::FeatureXS"];
}
- if !eq(hasTLBIP, true) then {
-def : TLBIPEntry {
- let ExtraRequires = ["AArch64::FeatureD128"];
+
+ if !eq(I.HasTLBIP, true) then {
+def : TLBIPEntry {
+ let Requires = ["AArch64::FeatureD128"];
}
-def : TLBIPEntry {
- let Encoding{7} = 1;
- let ExtraRequires = ["AArch64::FeatureD128"];
+
+// *nxs variants are gated by `FEAT_D128` not `FEAT_XS`
Lukacma wrote:
Not sure this comment is necessary.
https://github.com/llvm/llvm-project/pull/187400
___
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[llvm-branch-commits] [llvm] [AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (PR #187400)
@@ -903,128 +904,175 @@ multiclass TLBITableBase {
defm TLBI : TLBITableBase;
defm TLBIP : TLBITableBase;
-multiclass TLBI op1, bits<4> crn, bits<4>
crm,
- bits<3> op2, int reguse = REG_REQUIRED> {
- def : TLBIEntry;
- def : TLBIEntry {
-let Encoding{7} = 1;
+class TLBI op1, bits<4> crn,
+ bits<4> crm, bits<3> op2, int reguse = REG_REQUIRED> {
+ string Name = name;
+ bit HasTLBIP = hasTLBIP;
+ bits<3> Op1 = op1;
+ bits<4> CRn = crn;
+ bits<4> CRm = crm;
+ bits<3> Op2 = op2;
+ int RegUse = reguse;
+}
+
+// TLBI and TLBIP instructions encodings.
+defvar TLBIBase = [
+ //namehasTLBIP op1CRn CRm op2reguse
+ TLBI<"IPAS2E1IS",1, 0b100, 0b1000, 0b, 0b001, REG_REQUIRED>,
+ TLBI<"IPAS2LE1IS", 1, 0b100, 0b1000, 0b, 0b101, REG_REQUIRED>,
+ TLBI<"VMALLE1IS",0, 0b000, 0b1000, 0b0011, 0b000, REG_OPTIONAL>,
+ TLBI<"ALLE2IS", 0, 0b100, 0b1000, 0b0011, 0b000, REG_OPTIONAL>,
+ TLBI<"ALLE3IS", 0, 0b110, 0b1000, 0b0011, 0b000, REG_OPTIONAL>,
+ TLBI<"VAE1IS", 1, 0b000, 0b1000, 0b0011, 0b001, REG_REQUIRED>,
+ TLBI<"VAE2IS", 1, 0b100, 0b1000, 0b0011, 0b001, REG_REQUIRED>,
+ TLBI<"VAE3IS", 1, 0b110, 0b1000, 0b0011, 0b001, REG_REQUIRED>,
+ TLBI<"ASIDE1IS", 0, 0b000, 0b1000, 0b0011, 0b010, REG_REQUIRED>,
+ TLBI<"VAAE1IS", 1, 0b000, 0b1000, 0b0011, 0b011, REG_REQUIRED>,
+ TLBI<"ALLE1IS", 0, 0b100, 0b1000, 0b0011, 0b100, REG_OPTIONAL>,
+ TLBI<"VALE1IS", 1, 0b000, 0b1000, 0b0011, 0b101, REG_REQUIRED>,
+ TLBI<"VALE2IS", 1, 0b100, 0b1000, 0b0011, 0b101, REG_REQUIRED>,
+ TLBI<"VALE3IS", 1, 0b110, 0b1000, 0b0011, 0b101, REG_REQUIRED>,
+ TLBI<"VMALLS12E1IS", 0, 0b100, 0b1000, 0b0011, 0b110, REG_OPTIONAL>,
+ TLBI<"VAALE1IS", 1, 0b000, 0b1000, 0b0011, 0b111, REG_REQUIRED>,
+ TLBI<"IPAS2E1", 1, 0b100, 0b1000, 0b0100, 0b001, REG_REQUIRED>,
+ TLBI<"IPAS2LE1", 1, 0b100, 0b1000, 0b0100, 0b101, REG_REQUIRED>,
+ TLBI<"VMALLE1", 0, 0b000, 0b1000, 0b0111, 0b000, REG_NONE>,
+ TLBI<"ALLE2",0, 0b100, 0b1000, 0b0111, 0b000, REG_NONE>,
+ TLBI<"ALLE3",0, 0b110, 0b1000, 0b0111, 0b000, REG_NONE>,
+ TLBI<"VAE1", 1, 0b000, 0b1000, 0b0111, 0b001, REG_REQUIRED>,
+ TLBI<"VAE2", 1, 0b100, 0b1000, 0b0111, 0b001, REG_REQUIRED>,
+ TLBI<"VAE3", 1, 0b110, 0b1000, 0b0111, 0b001, REG_REQUIRED>,
+ TLBI<"ASIDE1", 0, 0b000, 0b1000, 0b0111, 0b010, REG_REQUIRED>,
+ TLBI<"VAAE1",1, 0b000, 0b1000, 0b0111, 0b011, REG_REQUIRED>,
+ TLBI<"ALLE1",0, 0b100, 0b1000, 0b0111, 0b100, REG_NONE>,
+ TLBI<"VALE1",1, 0b000, 0b1000, 0b0111, 0b101, REG_REQUIRED>,
+ TLBI<"VALE2",1, 0b100, 0b1000, 0b0111, 0b101, REG_REQUIRED>,
+ TLBI<"VALE3",1, 0b110, 0b1000, 0b0111, 0b101, REG_REQUIRED>,
+ TLBI<"VMALLS12E1", 0, 0b100, 0b1000, 0b0111, 0b110, REG_NONE>,
+ TLBI<"VAALE1", 1, 0b000, 0b1000, 0b0111, 0b111, REG_REQUIRED>
+];
+
+foreach I = TLBIBase in {
+ def : TLBIEntry;
+
+ def : TLBIEntry {
let ExtraRequires = ["AArch64::FeatureXS"];
}
- if !eq(hasTLBIP, true) then {
-def : TLBIPEntry {
- let ExtraRequires = ["AArch64::FeatureD128"];
+
+ if !eq(I.HasTLBIP, true) then {
+def : TLBIPEntry {
+ let Requires = ["AArch64::FeatureD128"];
}
-def : TLBIPEntry {
- let Encoding{7} = 1;
- let ExtraRequires = ["AArch64::FeatureD128"];
+
+// *nxs variants are gated by `FEAT_D128` not `FEAT_XS`
+def : TLBIPEntry {
+ let Requires = ["AArch64::FeatureD128"];
}
}
}
-// hasTLBIP op1CRn CRm op2reguse
-defm : TLBI<"IPAS2E1IS",1, 0b100, 0b1000, 0b, 0b001, REG_REQUIRED>;
-defm : TLBI<"IPAS2LE1IS", 1, 0b100, 0b1000, 0b, 0b101, REG_REQUIRED>;
-defm : TLBI<"VMALLE1IS",0, 0b000, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
-defm : TLBI<"ALLE2IS", 0, 0b100, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
-defm : TLBI<"ALLE3IS", 0, 0b110, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
-defm : TLBI<"VAE1IS", 1, 0b000, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
-defm : TLBI<"VAE2IS", 1, 0b100, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
-defm : TLBI<"VAE3IS", 1, 0b110, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
-defm : TLBI<"ASIDE1IS", 0, 0b000, 0b1000, 0b0011, 0b010, REG_REQUIRED>;
-defm : TLBI<"VAAE1IS", 1, 0b000, 0b1000, 0b0011, 0b011, REG_REQUIRED>;
-defm : TLBI<"ALLE1IS", 0, 0b100, 0b1000, 0b0011, 0b100, REG_OPTIONAL>;
-defm : TLBI<"VALE1IS", 1, 0b000, 0b1000, 0b0011, 0b101, REG_REQUIRED>;
-defm : TLBI<"VALE2IS", 1, 0b100, 0b1000, 0b0011, 0b101, REG_REQUIRED>;
-defm : TLBI<"VALE3IS", 1, 0b110, 0b1000, 0b0011, 0b101, REG_REQUIRED>;
-defm : TLBI<"VMALLS12E1IS", 0, 0b100, 0b1000, 0b0011, 0b110, REG_OPTIONAL>;
-defm : TLBI<"VAALE1IS", 1, 0b000, 0b1000, 0b0011, 0b111, REG_REQUIRED>;
-defm : TLBI<"IPAS2E1", 1, 0b100, 0b1000, 0b0100, 0b001, REG_REQUIRED>;
-defm : TLBI<"IPAS2LE1",
[llvm-branch-commits] [llvm] [AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (PR #187400)
@@ -903,128 +904,175 @@ multiclass TLBITableBase {
defm TLBI : TLBITableBase;
defm TLBIP : TLBITableBase;
-multiclass TLBI op1, bits<4> crn, bits<4>
crm,
- bits<3> op2, int reguse = REG_REQUIRED> {
- def : TLBIEntry;
- def : TLBIEntry {
-let Encoding{7} = 1;
+class TLBI op1, bits<4> crn,
+ bits<4> crm, bits<3> op2, int reguse = REG_REQUIRED> {
+ string Name = name;
+ bit HasTLBIP = hasTLBIP;
+ bits<3> Op1 = op1;
+ bits<4> CRn = crn;
+ bits<4> CRm = crm;
+ bits<3> Op2 = op2;
+ int RegUse = reguse;
+}
+
+// TLBI and TLBIP instructions encodings.
+defvar TLBIBase = [
+ //namehasTLBIP op1CRn CRm op2reguse
+ TLBI<"IPAS2E1IS",1, 0b100, 0b1000, 0b, 0b001, REG_REQUIRED>,
+ TLBI<"IPAS2LE1IS", 1, 0b100, 0b1000, 0b, 0b101, REG_REQUIRED>,
+ TLBI<"VMALLE1IS",0, 0b000, 0b1000, 0b0011, 0b000, REG_OPTIONAL>,
+ TLBI<"ALLE2IS", 0, 0b100, 0b1000, 0b0011, 0b000, REG_OPTIONAL>,
+ TLBI<"ALLE3IS", 0, 0b110, 0b1000, 0b0011, 0b000, REG_OPTIONAL>,
+ TLBI<"VAE1IS", 1, 0b000, 0b1000, 0b0011, 0b001, REG_REQUIRED>,
+ TLBI<"VAE2IS", 1, 0b100, 0b1000, 0b0011, 0b001, REG_REQUIRED>,
+ TLBI<"VAE3IS", 1, 0b110, 0b1000, 0b0011, 0b001, REG_REQUIRED>,
+ TLBI<"ASIDE1IS", 0, 0b000, 0b1000, 0b0011, 0b010, REG_REQUIRED>,
+ TLBI<"VAAE1IS", 1, 0b000, 0b1000, 0b0011, 0b011, REG_REQUIRED>,
+ TLBI<"ALLE1IS", 0, 0b100, 0b1000, 0b0011, 0b100, REG_OPTIONAL>,
+ TLBI<"VALE1IS", 1, 0b000, 0b1000, 0b0011, 0b101, REG_REQUIRED>,
+ TLBI<"VALE2IS", 1, 0b100, 0b1000, 0b0011, 0b101, REG_REQUIRED>,
+ TLBI<"VALE3IS", 1, 0b110, 0b1000, 0b0011, 0b101, REG_REQUIRED>,
+ TLBI<"VMALLS12E1IS", 0, 0b100, 0b1000, 0b0011, 0b110, REG_OPTIONAL>,
+ TLBI<"VAALE1IS", 1, 0b000, 0b1000, 0b0011, 0b111, REG_REQUIRED>,
+ TLBI<"IPAS2E1", 1, 0b100, 0b1000, 0b0100, 0b001, REG_REQUIRED>,
+ TLBI<"IPAS2LE1", 1, 0b100, 0b1000, 0b0100, 0b101, REG_REQUIRED>,
+ TLBI<"VMALLE1", 0, 0b000, 0b1000, 0b0111, 0b000, REG_NONE>,
+ TLBI<"ALLE2",0, 0b100, 0b1000, 0b0111, 0b000, REG_NONE>,
+ TLBI<"ALLE3",0, 0b110, 0b1000, 0b0111, 0b000, REG_NONE>,
+ TLBI<"VAE1", 1, 0b000, 0b1000, 0b0111, 0b001, REG_REQUIRED>,
+ TLBI<"VAE2", 1, 0b100, 0b1000, 0b0111, 0b001, REG_REQUIRED>,
+ TLBI<"VAE3", 1, 0b110, 0b1000, 0b0111, 0b001, REG_REQUIRED>,
+ TLBI<"ASIDE1", 0, 0b000, 0b1000, 0b0111, 0b010, REG_REQUIRED>,
+ TLBI<"VAAE1",1, 0b000, 0b1000, 0b0111, 0b011, REG_REQUIRED>,
+ TLBI<"ALLE1",0, 0b100, 0b1000, 0b0111, 0b100, REG_NONE>,
+ TLBI<"VALE1",1, 0b000, 0b1000, 0b0111, 0b101, REG_REQUIRED>,
+ TLBI<"VALE2",1, 0b100, 0b1000, 0b0111, 0b101, REG_REQUIRED>,
+ TLBI<"VALE3",1, 0b110, 0b1000, 0b0111, 0b101, REG_REQUIRED>,
+ TLBI<"VMALLS12E1", 0, 0b100, 0b1000, 0b0111, 0b110, REG_NONE>,
+ TLBI<"VAALE1", 1, 0b000, 0b1000, 0b0111, 0b111, REG_REQUIRED>
+];
+
+foreach I = TLBIBase in {
+ def : TLBIEntry;
+
+ def : TLBIEntry {
let ExtraRequires = ["AArch64::FeatureXS"];
}
- if !eq(hasTLBIP, true) then {
-def : TLBIPEntry {
- let ExtraRequires = ["AArch64::FeatureD128"];
+
+ if !eq(I.HasTLBIP, true) then {
+def : TLBIPEntry {
+ let Requires = ["AArch64::FeatureD128"];
}
-def : TLBIPEntry {
- let Encoding{7} = 1;
- let ExtraRequires = ["AArch64::FeatureD128"];
+
+// *nxs variants are gated by `FEAT_D128` not `FEAT_XS`
+def : TLBIPEntry {
+ let Requires = ["AArch64::FeatureD128"];
Lukacma wrote:
```suggestion
let Requires = ["AArch64::FeatureD128"] in {
def : TLBIPEntry;
def : TLBIPEntry;
}
```
same in the rest of the file
https://github.com/llvm/llvm-project/pull/187400
___
llvm-branch-commits mailing list
[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (PR #187400)
@@ -903,128 +904,175 @@ multiclass TLBITableBase {
defm TLBI : TLBITableBase;
defm TLBIP : TLBITableBase;
-multiclass TLBI op1, bits<4> crn, bits<4>
crm,
- bits<3> op2, int reguse = REG_REQUIRED> {
- def : TLBIEntry;
- def : TLBIEntry {
-let Encoding{7} = 1;
+class TLBI op1, bits<4> crn,
+ bits<4> crm, bits<3> op2, int reguse = REG_REQUIRED> {
+ string Name = name;
+ bit HasTLBIP = hasTLBIP;
+ bits<3> Op1 = op1;
+ bits<4> CRn = crn;
+ bits<4> CRm = crm;
+ bits<3> Op2 = op2;
+ int RegUse = reguse;
+}
+
+// TLBI and TLBIP instructions encodings.
+defvar TLBIBase = [
+ //namehasTLBIP op1CRn CRm op2reguse
+ TLBI<"IPAS2E1IS",1, 0b100, 0b1000, 0b, 0b001, REG_REQUIRED>,
+ TLBI<"IPAS2LE1IS", 1, 0b100, 0b1000, 0b, 0b101, REG_REQUIRED>,
+ TLBI<"VMALLE1IS",0, 0b000, 0b1000, 0b0011, 0b000, REG_OPTIONAL>,
+ TLBI<"ALLE2IS", 0, 0b100, 0b1000, 0b0011, 0b000, REG_OPTIONAL>,
+ TLBI<"ALLE3IS", 0, 0b110, 0b1000, 0b0011, 0b000, REG_OPTIONAL>,
+ TLBI<"VAE1IS", 1, 0b000, 0b1000, 0b0011, 0b001, REG_REQUIRED>,
+ TLBI<"VAE2IS", 1, 0b100, 0b1000, 0b0011, 0b001, REG_REQUIRED>,
+ TLBI<"VAE3IS", 1, 0b110, 0b1000, 0b0011, 0b001, REG_REQUIRED>,
+ TLBI<"ASIDE1IS", 0, 0b000, 0b1000, 0b0011, 0b010, REG_REQUIRED>,
+ TLBI<"VAAE1IS", 1, 0b000, 0b1000, 0b0011, 0b011, REG_REQUIRED>,
+ TLBI<"ALLE1IS", 0, 0b100, 0b1000, 0b0011, 0b100, REG_OPTIONAL>,
+ TLBI<"VALE1IS", 1, 0b000, 0b1000, 0b0011, 0b101, REG_REQUIRED>,
+ TLBI<"VALE2IS", 1, 0b100, 0b1000, 0b0011, 0b101, REG_REQUIRED>,
+ TLBI<"VALE3IS", 1, 0b110, 0b1000, 0b0011, 0b101, REG_REQUIRED>,
+ TLBI<"VMALLS12E1IS", 0, 0b100, 0b1000, 0b0011, 0b110, REG_OPTIONAL>,
+ TLBI<"VAALE1IS", 1, 0b000, 0b1000, 0b0011, 0b111, REG_REQUIRED>,
+ TLBI<"IPAS2E1", 1, 0b100, 0b1000, 0b0100, 0b001, REG_REQUIRED>,
+ TLBI<"IPAS2LE1", 1, 0b100, 0b1000, 0b0100, 0b101, REG_REQUIRED>,
+ TLBI<"VMALLE1", 0, 0b000, 0b1000, 0b0111, 0b000, REG_NONE>,
+ TLBI<"ALLE2",0, 0b100, 0b1000, 0b0111, 0b000, REG_NONE>,
+ TLBI<"ALLE3",0, 0b110, 0b1000, 0b0111, 0b000, REG_NONE>,
+ TLBI<"VAE1", 1, 0b000, 0b1000, 0b0111, 0b001, REG_REQUIRED>,
+ TLBI<"VAE2", 1, 0b100, 0b1000, 0b0111, 0b001, REG_REQUIRED>,
+ TLBI<"VAE3", 1, 0b110, 0b1000, 0b0111, 0b001, REG_REQUIRED>,
+ TLBI<"ASIDE1", 0, 0b000, 0b1000, 0b0111, 0b010, REG_REQUIRED>,
+ TLBI<"VAAE1",1, 0b000, 0b1000, 0b0111, 0b011, REG_REQUIRED>,
+ TLBI<"ALLE1",0, 0b100, 0b1000, 0b0111, 0b100, REG_NONE>,
+ TLBI<"VALE1",1, 0b000, 0b1000, 0b0111, 0b101, REG_REQUIRED>,
+ TLBI<"VALE2",1, 0b100, 0b1000, 0b0111, 0b101, REG_REQUIRED>,
+ TLBI<"VALE3",1, 0b110, 0b1000, 0b0111, 0b101, REG_REQUIRED>,
+ TLBI<"VMALLS12E1", 0, 0b100, 0b1000, 0b0111, 0b110, REG_NONE>,
+ TLBI<"VAALE1", 1, 0b000, 0b1000, 0b0111, 0b111, REG_REQUIRED>
+];
+
+foreach I = TLBIBase in {
+ def : TLBIEntry;
+
+ def : TLBIEntry {
let ExtraRequires = ["AArch64::FeatureXS"];
}
- if !eq(hasTLBIP, true) then {
-def : TLBIPEntry {
- let ExtraRequires = ["AArch64::FeatureD128"];
+
+ if !eq(I.HasTLBIP, true) then {
+def : TLBIPEntry {
+ let Requires = ["AArch64::FeatureD128"];
}
-def : TLBIPEntry {
- let Encoding{7} = 1;
- let ExtraRequires = ["AArch64::FeatureD128"];
+
+// *nxs variants are gated by `FEAT_D128` not `FEAT_XS`
+def : TLBIPEntry {
+ let Requires = ["AArch64::FeatureD128"];
}
}
}
-// hasTLBIP op1CRn CRm op2reguse
-defm : TLBI<"IPAS2E1IS",1, 0b100, 0b1000, 0b, 0b001, REG_REQUIRED>;
-defm : TLBI<"IPAS2LE1IS", 1, 0b100, 0b1000, 0b, 0b101, REG_REQUIRED>;
-defm : TLBI<"VMALLE1IS",0, 0b000, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
-defm : TLBI<"ALLE2IS", 0, 0b100, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
-defm : TLBI<"ALLE3IS", 0, 0b110, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
-defm : TLBI<"VAE1IS", 1, 0b000, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
-defm : TLBI<"VAE2IS", 1, 0b100, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
-defm : TLBI<"VAE3IS", 1, 0b110, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
-defm : TLBI<"ASIDE1IS", 0, 0b000, 0b1000, 0b0011, 0b010, REG_REQUIRED>;
-defm : TLBI<"VAAE1IS", 1, 0b000, 0b1000, 0b0011, 0b011, REG_REQUIRED>;
-defm : TLBI<"ALLE1IS", 0, 0b100, 0b1000, 0b0011, 0b100, REG_OPTIONAL>;
-defm : TLBI<"VALE1IS", 1, 0b000, 0b1000, 0b0011, 0b101, REG_REQUIRED>;
-defm : TLBI<"VALE2IS", 1, 0b100, 0b1000, 0b0011, 0b101, REG_REQUIRED>;
-defm : TLBI<"VALE3IS", 1, 0b110, 0b1000, 0b0011, 0b101, REG_REQUIRED>;
-defm : TLBI<"VMALLS12E1IS", 0, 0b100, 0b1000, 0b0011, 0b110, REG_OPTIONAL>;
-defm : TLBI<"VAALE1IS", 1, 0b000, 0b1000, 0b0011, 0b111, REG_REQUIRED>;
-defm : TLBI<"IPAS2E1", 1, 0b100, 0b1000, 0b0100, 0b001, REG_REQUIRED>;
-defm : TLBI<"IPAS2LE1",
[llvm-branch-commits] [llvm] [AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (PR #187400)
@@ -903,128 +904,175 @@ multiclass TLBITableBase {
defm TLBI : TLBITableBase;
defm TLBIP : TLBITableBase;
-multiclass TLBI op1, bits<4> crn, bits<4>
crm,
- bits<3> op2, int reguse = REG_REQUIRED> {
- def : TLBIEntry;
- def : TLBIEntry {
-let Encoding{7} = 1;
+class TLBI op1, bits<4> crn,
+ bits<4> crm, bits<3> op2, int reguse = REG_REQUIRED> {
+ string Name = name;
+ bit HasTLBIP = hasTLBIP;
+ bits<3> Op1 = op1;
+ bits<4> CRn = crn;
+ bits<4> CRm = crm;
+ bits<3> Op2 = op2;
+ int RegUse = reguse;
+}
+
+// TLBI and TLBIP instructions encodings.
+defvar TLBIBase = [
+ //namehasTLBIP op1CRn CRm op2reguse
+ TLBI<"IPAS2E1IS",1, 0b100, 0b1000, 0b, 0b001, REG_REQUIRED>,
+ TLBI<"IPAS2LE1IS", 1, 0b100, 0b1000, 0b, 0b101, REG_REQUIRED>,
+ TLBI<"VMALLE1IS",0, 0b000, 0b1000, 0b0011, 0b000, REG_OPTIONAL>,
+ TLBI<"ALLE2IS", 0, 0b100, 0b1000, 0b0011, 0b000, REG_OPTIONAL>,
+ TLBI<"ALLE3IS", 0, 0b110, 0b1000, 0b0011, 0b000, REG_OPTIONAL>,
+ TLBI<"VAE1IS", 1, 0b000, 0b1000, 0b0011, 0b001, REG_REQUIRED>,
+ TLBI<"VAE2IS", 1, 0b100, 0b1000, 0b0011, 0b001, REG_REQUIRED>,
+ TLBI<"VAE3IS", 1, 0b110, 0b1000, 0b0011, 0b001, REG_REQUIRED>,
+ TLBI<"ASIDE1IS", 0, 0b000, 0b1000, 0b0011, 0b010, REG_REQUIRED>,
+ TLBI<"VAAE1IS", 1, 0b000, 0b1000, 0b0011, 0b011, REG_REQUIRED>,
+ TLBI<"ALLE1IS", 0, 0b100, 0b1000, 0b0011, 0b100, REG_OPTIONAL>,
+ TLBI<"VALE1IS", 1, 0b000, 0b1000, 0b0011, 0b101, REG_REQUIRED>,
+ TLBI<"VALE2IS", 1, 0b100, 0b1000, 0b0011, 0b101, REG_REQUIRED>,
+ TLBI<"VALE3IS", 1, 0b110, 0b1000, 0b0011, 0b101, REG_REQUIRED>,
+ TLBI<"VMALLS12E1IS", 0, 0b100, 0b1000, 0b0011, 0b110, REG_OPTIONAL>,
+ TLBI<"VAALE1IS", 1, 0b000, 0b1000, 0b0011, 0b111, REG_REQUIRED>,
+ TLBI<"IPAS2E1", 1, 0b100, 0b1000, 0b0100, 0b001, REG_REQUIRED>,
+ TLBI<"IPAS2LE1", 1, 0b100, 0b1000, 0b0100, 0b101, REG_REQUIRED>,
+ TLBI<"VMALLE1", 0, 0b000, 0b1000, 0b0111, 0b000, REG_NONE>,
+ TLBI<"ALLE2",0, 0b100, 0b1000, 0b0111, 0b000, REG_NONE>,
+ TLBI<"ALLE3",0, 0b110, 0b1000, 0b0111, 0b000, REG_NONE>,
+ TLBI<"VAE1", 1, 0b000, 0b1000, 0b0111, 0b001, REG_REQUIRED>,
+ TLBI<"VAE2", 1, 0b100, 0b1000, 0b0111, 0b001, REG_REQUIRED>,
+ TLBI<"VAE3", 1, 0b110, 0b1000, 0b0111, 0b001, REG_REQUIRED>,
+ TLBI<"ASIDE1", 0, 0b000, 0b1000, 0b0111, 0b010, REG_REQUIRED>,
+ TLBI<"VAAE1",1, 0b000, 0b1000, 0b0111, 0b011, REG_REQUIRED>,
+ TLBI<"ALLE1",0, 0b100, 0b1000, 0b0111, 0b100, REG_NONE>,
+ TLBI<"VALE1",1, 0b000, 0b1000, 0b0111, 0b101, REG_REQUIRED>,
+ TLBI<"VALE2",1, 0b100, 0b1000, 0b0111, 0b101, REG_REQUIRED>,
+ TLBI<"VALE3",1, 0b110, 0b1000, 0b0111, 0b101, REG_REQUIRED>,
+ TLBI<"VMALLS12E1", 0, 0b100, 0b1000, 0b0111, 0b110, REG_NONE>,
+ TLBI<"VAALE1", 1, 0b000, 0b1000, 0b0111, 0b111, REG_REQUIRED>
+];
+
+foreach I = TLBIBase in {
+ def : TLBIEntry;
+
+ def : TLBIEntry {
let ExtraRequires = ["AArch64::FeatureXS"];
}
- if !eq(hasTLBIP, true) then {
-def : TLBIPEntry {
- let ExtraRequires = ["AArch64::FeatureD128"];
+
+ if !eq(I.HasTLBIP, true) then {
+def : TLBIPEntry {
+ let Requires = ["AArch64::FeatureD128"];
}
-def : TLBIPEntry {
- let Encoding{7} = 1;
- let ExtraRequires = ["AArch64::FeatureD128"];
+
+// *nxs variants are gated by `FEAT_D128` not `FEAT_XS`
+def : TLBIPEntry {
+ let Requires = ["AArch64::FeatureD128"];
}
}
}
-// hasTLBIP op1CRn CRm op2reguse
-defm : TLBI<"IPAS2E1IS",1, 0b100, 0b1000, 0b, 0b001, REG_REQUIRED>;
-defm : TLBI<"IPAS2LE1IS", 1, 0b100, 0b1000, 0b, 0b101, REG_REQUIRED>;
-defm : TLBI<"VMALLE1IS",0, 0b000, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
-defm : TLBI<"ALLE2IS", 0, 0b100, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
-defm : TLBI<"ALLE3IS", 0, 0b110, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
-defm : TLBI<"VAE1IS", 1, 0b000, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
-defm : TLBI<"VAE2IS", 1, 0b100, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
-defm : TLBI<"VAE3IS", 1, 0b110, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
-defm : TLBI<"ASIDE1IS", 0, 0b000, 0b1000, 0b0011, 0b010, REG_REQUIRED>;
-defm : TLBI<"VAAE1IS", 1, 0b000, 0b1000, 0b0011, 0b011, REG_REQUIRED>;
-defm : TLBI<"ALLE1IS", 0, 0b100, 0b1000, 0b0011, 0b100, REG_OPTIONAL>;
-defm : TLBI<"VALE1IS", 1, 0b000, 0b1000, 0b0011, 0b101, REG_REQUIRED>;
-defm : TLBI<"VALE2IS", 1, 0b100, 0b1000, 0b0011, 0b101, REG_REQUIRED>;
-defm : TLBI<"VALE3IS", 1, 0b110, 0b1000, 0b0011, 0b101, REG_REQUIRED>;
-defm : TLBI<"VMALLS12E1IS", 0, 0b100, 0b1000, 0b0011, 0b110, REG_OPTIONAL>;
-defm : TLBI<"VAALE1IS", 1, 0b000, 0b1000, 0b0011, 0b111, REG_REQUIRED>;
-defm : TLBI<"IPAS2E1", 1, 0b100, 0b1000, 0b0100, 0b001, REG_REQUIRED>;
-defm : TLBI<"IPAS2LE1",
[llvm-branch-commits] [llvm] [AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (PR #187400)
@@ -1,9 +1,11 @@ +// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+xs < %s 2>%t | FileCheck %s +// RUN: FileCheck --check-prefix=CHECK-ERR %s < %t // RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.4a,+xs < %s 2>%t | FileCheck %s // RUN: FileCheck --check-prefix=CHECK-ERR %s < %t // RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.7a < %s 2>%t | FileCheck %s // RUN: FileCheck --check-prefix=CHECK-ERR %s < %t // RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.4a < %s 2> %t -// RUN: FileCheck --check-prefixes=CHECK-ERR,CHECK-NO-XS-ERR %s < %t Lukacma wrote: What's the purpose of this change ? https://github.com/llvm/llvm-project/pull/187400 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (PR #187400)
@@ -903,128 +904,175 @@ multiclass TLBITableBase {
defm TLBI : TLBITableBase;
defm TLBIP : TLBITableBase;
-multiclass TLBI op1, bits<4> crn, bits<4>
crm,
- bits<3> op2, int reguse = REG_REQUIRED> {
- def : TLBIEntry;
- def : TLBIEntry {
-let Encoding{7} = 1;
+class TLBI op1, bits<4> crn,
+ bits<4> crm, bits<3> op2, int reguse = REG_REQUIRED> {
+ string Name = name;
+ bit HasTLBIP = hasTLBIP;
+ bits<3> Op1 = op1;
+ bits<4> CRn = crn;
+ bits<4> CRm = crm;
+ bits<3> Op2 = op2;
+ int RegUse = reguse;
+}
+
+// TLBI and TLBIP instructions encodings.
+defvar TLBIBase = [
+ //namehasTLBIP op1CRn CRm op2reguse
+ TLBI<"IPAS2E1IS",1, 0b100, 0b1000, 0b, 0b001, REG_REQUIRED>,
+ TLBI<"IPAS2LE1IS", 1, 0b100, 0b1000, 0b, 0b101, REG_REQUIRED>,
+ TLBI<"VMALLE1IS",0, 0b000, 0b1000, 0b0011, 0b000, REG_OPTIONAL>,
+ TLBI<"ALLE2IS", 0, 0b100, 0b1000, 0b0011, 0b000, REG_OPTIONAL>,
+ TLBI<"ALLE3IS", 0, 0b110, 0b1000, 0b0011, 0b000, REG_OPTIONAL>,
+ TLBI<"VAE1IS", 1, 0b000, 0b1000, 0b0011, 0b001, REG_REQUIRED>,
+ TLBI<"VAE2IS", 1, 0b100, 0b1000, 0b0011, 0b001, REG_REQUIRED>,
+ TLBI<"VAE3IS", 1, 0b110, 0b1000, 0b0011, 0b001, REG_REQUIRED>,
+ TLBI<"ASIDE1IS", 0, 0b000, 0b1000, 0b0011, 0b010, REG_REQUIRED>,
+ TLBI<"VAAE1IS", 1, 0b000, 0b1000, 0b0011, 0b011, REG_REQUIRED>,
+ TLBI<"ALLE1IS", 0, 0b100, 0b1000, 0b0011, 0b100, REG_OPTIONAL>,
+ TLBI<"VALE1IS", 1, 0b000, 0b1000, 0b0011, 0b101, REG_REQUIRED>,
+ TLBI<"VALE2IS", 1, 0b100, 0b1000, 0b0011, 0b101, REG_REQUIRED>,
+ TLBI<"VALE3IS", 1, 0b110, 0b1000, 0b0011, 0b101, REG_REQUIRED>,
+ TLBI<"VMALLS12E1IS", 0, 0b100, 0b1000, 0b0011, 0b110, REG_OPTIONAL>,
+ TLBI<"VAALE1IS", 1, 0b000, 0b1000, 0b0011, 0b111, REG_REQUIRED>,
+ TLBI<"IPAS2E1", 1, 0b100, 0b1000, 0b0100, 0b001, REG_REQUIRED>,
+ TLBI<"IPAS2LE1", 1, 0b100, 0b1000, 0b0100, 0b101, REG_REQUIRED>,
+ TLBI<"VMALLE1", 0, 0b000, 0b1000, 0b0111, 0b000, REG_NONE>,
+ TLBI<"ALLE2",0, 0b100, 0b1000, 0b0111, 0b000, REG_NONE>,
+ TLBI<"ALLE3",0, 0b110, 0b1000, 0b0111, 0b000, REG_NONE>,
+ TLBI<"VAE1", 1, 0b000, 0b1000, 0b0111, 0b001, REG_REQUIRED>,
+ TLBI<"VAE2", 1, 0b100, 0b1000, 0b0111, 0b001, REG_REQUIRED>,
+ TLBI<"VAE3", 1, 0b110, 0b1000, 0b0111, 0b001, REG_REQUIRED>,
+ TLBI<"ASIDE1", 0, 0b000, 0b1000, 0b0111, 0b010, REG_REQUIRED>,
+ TLBI<"VAAE1",1, 0b000, 0b1000, 0b0111, 0b011, REG_REQUIRED>,
+ TLBI<"ALLE1",0, 0b100, 0b1000, 0b0111, 0b100, REG_NONE>,
+ TLBI<"VALE1",1, 0b000, 0b1000, 0b0111, 0b101, REG_REQUIRED>,
+ TLBI<"VALE2",1, 0b100, 0b1000, 0b0111, 0b101, REG_REQUIRED>,
+ TLBI<"VALE3",1, 0b110, 0b1000, 0b0111, 0b101, REG_REQUIRED>,
+ TLBI<"VMALLS12E1", 0, 0b100, 0b1000, 0b0111, 0b110, REG_NONE>,
+ TLBI<"VAALE1", 1, 0b000, 0b1000, 0b0111, 0b111, REG_REQUIRED>
+];
+
+foreach I = TLBIBase in {
+ def : TLBIEntry;
+
+ def : TLBIEntry {
let ExtraRequires = ["AArch64::FeatureXS"];
}
- if !eq(hasTLBIP, true) then {
-def : TLBIPEntry {
- let ExtraRequires = ["AArch64::FeatureD128"];
+
+ if !eq(I.HasTLBIP, true) then {
+def : TLBIPEntry {
+ let Requires = ["AArch64::FeatureD128"];
}
-def : TLBIPEntry {
- let Encoding{7} = 1;
- let ExtraRequires = ["AArch64::FeatureD128"];
+
+// *nxs variants are gated by `FEAT_D128` not `FEAT_XS`
+def : TLBIPEntry {
+ let Requires = ["AArch64::FeatureD128"];
}
}
}
-// hasTLBIP op1CRn CRm op2reguse
-defm : TLBI<"IPAS2E1IS",1, 0b100, 0b1000, 0b, 0b001, REG_REQUIRED>;
-defm : TLBI<"IPAS2LE1IS", 1, 0b100, 0b1000, 0b, 0b101, REG_REQUIRED>;
-defm : TLBI<"VMALLE1IS",0, 0b000, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
-defm : TLBI<"ALLE2IS", 0, 0b100, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
-defm : TLBI<"ALLE3IS", 0, 0b110, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
-defm : TLBI<"VAE1IS", 1, 0b000, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
-defm : TLBI<"VAE2IS", 1, 0b100, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
-defm : TLBI<"VAE3IS", 1, 0b110, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
-defm : TLBI<"ASIDE1IS", 0, 0b000, 0b1000, 0b0011, 0b010, REG_REQUIRED>;
-defm : TLBI<"VAAE1IS", 1, 0b000, 0b1000, 0b0011, 0b011, REG_REQUIRED>;
-defm : TLBI<"ALLE1IS", 0, 0b100, 0b1000, 0b0011, 0b100, REG_OPTIONAL>;
-defm : TLBI<"VALE1IS", 1, 0b000, 0b1000, 0b0011, 0b101, REG_REQUIRED>;
-defm : TLBI<"VALE2IS", 1, 0b100, 0b1000, 0b0011, 0b101, REG_REQUIRED>;
-defm : TLBI<"VALE3IS", 1, 0b110, 0b1000, 0b0011, 0b101, REG_REQUIRED>;
-defm : TLBI<"VMALLS12E1IS", 0, 0b100, 0b1000, 0b0011, 0b110, REG_OPTIONAL>;
-defm : TLBI<"VAALE1IS", 1, 0b000, 0b1000, 0b0011, 0b111, REG_REQUIRED>;
-defm : TLBI<"IPAS2E1", 1, 0b100, 0b1000, 0b0100, 0b001, REG_REQUIRED>;
-defm : TLBI<"IPAS2LE1",
[llvm-branch-commits] [llvm] [AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (PR #187400)
https://github.com/jthackray edited https://github.com/llvm/llvm-project/pull/187400 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (PR #187400)
https://github.com/jthackray edited https://github.com/llvm/llvm-project/pull/187400 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (PR #187400)
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[llvm-branch-commits] [llvm] [AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (PR #187400)
https://github.com/jthackray edited https://github.com/llvm/llvm-project/pull/187400 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (PR #187400)
https://github.com/jthackray edited https://github.com/llvm/llvm-project/pull/187400 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (PR #187400)
https://github.com/jthackray updated
https://github.com/llvm/llvm-project/pull/187400
>From 027040218c7682a512c6011e2b87e1ff4757146d Mon Sep 17 00:00:00 2001
From: Jonathan Thackray
Date: Wed, 18 Mar 2026 20:54:50 +
Subject: [PATCH 1/6] [AArch64][llvm] Separate TLBI-only feature gating from
TLBIP aliases
Refactor the TLBI system operand definitions so that TLBI and TLBIP
records are emitted through separate helper multiclasses, whilst keeping
the table layout readable.
The feature-scoped wrappers now apply FeatureTLB_RMI, FeatureRME, and
FeatureTLBIW only to TLBI records (it was previously incorrectly also
applied to TLBIP instructions), while TLBIP aliases remain gated only
by FeatureD128, including their nXS forms.
Update testcases accordingly.
---
.../Target/AArch64/AArch64SystemOperands.td | 178 ++
llvm/test/MC/AArch64/armv9a-tlbip.s | 17 +-
2 files changed, 111 insertions(+), 84 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
index 257a4958e8305..d914b253c5358 100644
--- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
+++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
@@ -903,24 +903,54 @@ multiclass TLBITableBase {
defm TLBI : TLBITableBase;
defm TLBIP : TLBITableBase;
-multiclass TLBI op1, bits<4> crn, bits<4>
crm,
- bits<3> op2, int reguse = REG_REQUIRED> {
- def : TLBIEntry;
- def : TLBIEntry {
-let Encoding{7} = 1;
-let ExtraRequires = ["AArch64::FeatureXS"];
- }
- if !eq(hasTLBIP, true) then {
-def : TLBIPEntry {
- let ExtraRequires = ["AArch64::FeatureD128"];
+multiclass TLBI_Base op1, bits<4> crn, bits<4> crm,
+ bits<3> op2, int reguse = REG_REQUIRED,
+ list extra_requires = []> {
+ foreach nxs = [0, 1] in {
+defvar VariantName = !if(nxs, !strconcat(name, "nXS"), name);
+defvar VariantRequires = !if(nxs,
+ extra_requires # ["AArch64::FeatureXS"],
+ extra_requires);
+def : TLBIEntry {
+ let Encoding{7} = nxs;
+ let ExtraRequires = VariantRequires;
}
-def : TLBIPEntry {
- let Encoding{7} = 1;
- let ExtraRequires = ["AArch64::FeatureD128"];
+ }
+}
+
+multiclass TLBIP_Base op1, bits<4> crn, bits<4> crm,
+ bits<3> op2, int reguse = REG_REQUIRED,
+ list extra_requires = ["AArch64::FeatureD128"]> {
+ foreach nxs = [0, 1] in {
+// TLBIP instructions aren't gated by FeatureXS like TLBI ones
+defvar VariantName = !if(nxs, !strconcat(name, "nXS"), name);
+def : TLBIPEntry {
+ let Encoding{7} = nxs;
+ let ExtraRequires = extra_requires;
}
}
}
+multiclass TLBI op1, bits<4> crn,
+bits<4> crm, bits<3> op2, int reguse = REG_REQUIRED> {
+ defm : TLBI_Base;
+ if !eq(hasTLBIP, true) then {
+defm : TLBIP_Base;
+ }
+}
+
+multiclass TLBI_RMI op1, bits<4> crn,
+bits<4> crm, bits<3> op2, int reguse = REG_REQUIRED> {
+ let Requires = ["AArch64::FeatureTLB_RMI"] in {
+defm : TLBI_Base;
+ }
+ // TLBIP instructions aren't gated by FeatureTLB_RMI
+ if !eq(hasTLBIP, true) then {
+defm : TLBIP_Base;
+ }
+}
+
+// TLBI and TLBIP instructions encodings
// hasTLBIP op1CRn CRm op2reguse
defm : TLBI<"IPAS2E1IS",1, 0b100, 0b1000, 0b, 0b001, REG_REQUIRED>;
defm : TLBI<"IPAS2LE1IS", 1, 0b100, 0b1000, 0b, 0b101, REG_REQUIRED>;
@@ -955,76 +985,74 @@ defm : TLBI<"VALE3",1, 0b110, 0b1000, 0b0111,
0b101, REG_REQUIRED>;
defm : TLBI<"VMALLS12E1", 0, 0b100, 0b1000, 0b0111, 0b110, REG_NONE>;
defm : TLBI<"VAALE1", 1, 0b000, 0b1000, 0b0111, 0b111, REG_REQUIRED>;
-// Armv8.4-A Translation Lookaside Buffer Instructions (TLBI)
-let Requires = ["AArch64::FeatureTLB_RMI"] in {
+// Armv8.4-A Translation Lookaside Buffer Instructions (TLBI and TLBIP)
// Armv8.4-A Outer Sharable TLB Maintenance instructions:
-// hasTLBIP op1CRn CRm op2reguse
-defm : TLBI<"VMALLE1OS",0, 0b000, 0b1000, 0b0001, 0b000, REG_OPTIONAL>;
-defm : TLBI<"VAE1OS", 1, 0b000, 0b1000, 0b0001, 0b001, REG_REQUIRED>;
-defm : TLBI<"ASIDE1OS", 0, 0b000, 0b1000, 0b0001, 0b010, REG_REQUIRED>;
-defm : TLBI<"VAAE1OS", 1, 0b000, 0b1000, 0b0001, 0b011, REG_REQUIRED>;
-defm : TLBI<"VALE1OS", 1, 0b000, 0b1000, 0b0001, 0b101, REG_REQUIRED>;
-defm : TLBI<"VAALE1OS", 1, 0b000, 0b1000, 0b0001, 0b111, REG_REQUIRED>;
-defm : TLBI<"IPAS2E1OS",1, 0b100, 0b1000, 0b0100, 0b000, REG_REQUIRED>;
-defm : TLBI<"IPAS2LE1OS", 1, 0b100, 0b1000, 0b0100, 0b100, REG_REQUIRED>;
-defm : TLBI<"VAE2OS", 1, 0b100, 0b1000, 0b0001, 0b001, REG_REQUIRED>;
-defm : TLBI<"VALE2OS", 1, 0b100, 0b1000, 0b0001, 0b101, REG_REQUIRED>;
-defm : TLBI<"VMALLS12E1OS", 0, 0b100, 0b1000, 0b0001, 0b110, REG_OPTIONAL>;
-defm : TLBI<"VAE3OS", 1,
[llvm-branch-commits] [llvm] [AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (PR #187400)
@@ -903,128 +903,250 @@ multiclass TLBITableBase {
defm TLBI : TLBITableBase;
defm TLBIP : TLBITableBase;
-multiclass TLBI op1, bits<4> crn, bits<4>
crm,
- bits<3> op2, int reguse = REG_REQUIRED> {
- def : TLBIEntry;
- def : TLBIEntry {
+class TLBI op1, bits<4> crn,
+ bits<4> crm, bits<3> op2, int reguse = REG_REQUIRED> {
+ string Name = NAME;
+ bit HasTLBIP = hasTLBIP;
+ bits<3> Op1 = op1;
+ bits<4> CRn = crn;
+ bits<4> CRm = crm;
+ bits<3> Op2 = op2;
+ int RegUse = reguse;
+}
+
+// TLBI and TLBIP instructions encodings
+// hasTLBIP op1CRn CRm op2reguse
+def IPAS2E1IS: TLBI<1, 0b100, 0b1000, 0b, 0b001, REG_REQUIRED>;
+def IPAS2LE1IS : TLBI<1, 0b100, 0b1000, 0b, 0b101, REG_REQUIRED>;
+def VMALLE1IS: TLBI<0, 0b000, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
+def ALLE2IS : TLBI<0, 0b100, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
+def ALLE3IS : TLBI<0, 0b110, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
+def VAE1IS : TLBI<1, 0b000, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
+def VAE2IS : TLBI<1, 0b100, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
+def VAE3IS : TLBI<1, 0b110, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
+def ASIDE1IS : TLBI<0, 0b000, 0b1000, 0b0011, 0b010, REG_REQUIRED>;
+def VAAE1IS : TLBI<1, 0b000, 0b1000, 0b0011, 0b011, REG_REQUIRED>;
+def ALLE1IS : TLBI<0, 0b100, 0b1000, 0b0011, 0b100, REG_OPTIONAL>;
+def VALE1IS : TLBI<1, 0b000, 0b1000, 0b0011, 0b101, REG_REQUIRED>;
+def VALE2IS : TLBI<1, 0b100, 0b1000, 0b0011, 0b101, REG_REQUIRED>;
+def VALE3IS : TLBI<1, 0b110, 0b1000, 0b0011, 0b101, REG_REQUIRED>;
+def VMALLS12E1IS : TLBI<0, 0b100, 0b1000, 0b0011, 0b110, REG_OPTIONAL>;
+def VAALE1IS : TLBI<1, 0b000, 0b1000, 0b0011, 0b111, REG_REQUIRED>;
+def IPAS2E1 : TLBI<1, 0b100, 0b1000, 0b0100, 0b001, REG_REQUIRED>;
+def IPAS2LE1 : TLBI<1, 0b100, 0b1000, 0b0100, 0b101, REG_REQUIRED>;
+def VMALLE1 : TLBI<0, 0b000, 0b1000, 0b0111, 0b000, REG_NONE>;
+def ALLE2: TLBI<0, 0b100, 0b1000, 0b0111, 0b000, REG_NONE>;
+def ALLE3: TLBI<0, 0b110, 0b1000, 0b0111, 0b000, REG_NONE>;
+def VAE1 : TLBI<1, 0b000, 0b1000, 0b0111, 0b001, REG_REQUIRED>;
+def VAE2 : TLBI<1, 0b100, 0b1000, 0b0111, 0b001, REG_REQUIRED>;
+def VAE3 : TLBI<1, 0b110, 0b1000, 0b0111, 0b001, REG_REQUIRED>;
+def ASIDE1 : TLBI<0, 0b000, 0b1000, 0b0111, 0b010, REG_REQUIRED>;
+def VAAE1: TLBI<1, 0b000, 0b1000, 0b0111, 0b011, REG_REQUIRED>;
+def ALLE1: TLBI<0, 0b100, 0b1000, 0b0111, 0b100, REG_NONE>;
+def VALE1: TLBI<1, 0b000, 0b1000, 0b0111, 0b101, REG_REQUIRED>;
+def VALE2: TLBI<1, 0b100, 0b1000, 0b0111, 0b101, REG_REQUIRED>;
+def VALE3: TLBI<1, 0b110, 0b1000, 0b0111, 0b101, REG_REQUIRED>;
+def VMALLS12E1 : TLBI<0, 0b100, 0b1000, 0b0111, 0b110, REG_NONE>;
+def VAALE1 : TLBI<1, 0b000, 0b1000, 0b0111, 0b111, REG_REQUIRED>;
+
+defvar TLBINames = [
jthackray wrote:
Ok, done.
https://github.com/llvm/llvm-project/pull/187400
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[llvm-branch-commits] [llvm] [AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (PR #187400)
@@ -903,128 +903,250 @@ multiclass TLBITableBase {
defm TLBI : TLBITableBase;
defm TLBIP : TLBITableBase;
-multiclass TLBI op1, bits<4> crn, bits<4>
crm,
- bits<3> op2, int reguse = REG_REQUIRED> {
- def : TLBIEntry;
- def : TLBIEntry {
+class TLBI op1, bits<4> crn,
+ bits<4> crm, bits<3> op2, int reguse = REG_REQUIRED> {
+ string Name = NAME;
+ bit HasTLBIP = hasTLBIP;
+ bits<3> Op1 = op1;
+ bits<4> CRn = crn;
+ bits<4> CRm = crm;
+ bits<3> Op2 = op2;
+ int RegUse = reguse;
+}
+
+// TLBI and TLBIP instructions encodings
+// hasTLBIP op1CRn CRm op2reguse
+def IPAS2E1IS: TLBI<1, 0b100, 0b1000, 0b, 0b001, REG_REQUIRED>;
+def IPAS2LE1IS : TLBI<1, 0b100, 0b1000, 0b, 0b101, REG_REQUIRED>;
+def VMALLE1IS: TLBI<0, 0b000, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
+def ALLE2IS : TLBI<0, 0b100, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
+def ALLE3IS : TLBI<0, 0b110, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
+def VAE1IS : TLBI<1, 0b000, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
+def VAE2IS : TLBI<1, 0b100, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
+def VAE3IS : TLBI<1, 0b110, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
+def ASIDE1IS : TLBI<0, 0b000, 0b1000, 0b0011, 0b010, REG_REQUIRED>;
+def VAAE1IS : TLBI<1, 0b000, 0b1000, 0b0011, 0b011, REG_REQUIRED>;
+def ALLE1IS : TLBI<0, 0b100, 0b1000, 0b0011, 0b100, REG_OPTIONAL>;
+def VALE1IS : TLBI<1, 0b000, 0b1000, 0b0011, 0b101, REG_REQUIRED>;
+def VALE2IS : TLBI<1, 0b100, 0b1000, 0b0011, 0b101, REG_REQUIRED>;
+def VALE3IS : TLBI<1, 0b110, 0b1000, 0b0011, 0b101, REG_REQUIRED>;
+def VMALLS12E1IS : TLBI<0, 0b100, 0b1000, 0b0011, 0b110, REG_OPTIONAL>;
+def VAALE1IS : TLBI<1, 0b000, 0b1000, 0b0011, 0b111, REG_REQUIRED>;
+def IPAS2E1 : TLBI<1, 0b100, 0b1000, 0b0100, 0b001, REG_REQUIRED>;
+def IPAS2LE1 : TLBI<1, 0b100, 0b1000, 0b0100, 0b101, REG_REQUIRED>;
+def VMALLE1 : TLBI<0, 0b000, 0b1000, 0b0111, 0b000, REG_NONE>;
+def ALLE2: TLBI<0, 0b100, 0b1000, 0b0111, 0b000, REG_NONE>;
+def ALLE3: TLBI<0, 0b110, 0b1000, 0b0111, 0b000, REG_NONE>;
+def VAE1 : TLBI<1, 0b000, 0b1000, 0b0111, 0b001, REG_REQUIRED>;
+def VAE2 : TLBI<1, 0b100, 0b1000, 0b0111, 0b001, REG_REQUIRED>;
+def VAE3 : TLBI<1, 0b110, 0b1000, 0b0111, 0b001, REG_REQUIRED>;
+def ASIDE1 : TLBI<0, 0b000, 0b1000, 0b0111, 0b010, REG_REQUIRED>;
+def VAAE1: TLBI<1, 0b000, 0b1000, 0b0111, 0b011, REG_REQUIRED>;
+def ALLE1: TLBI<0, 0b100, 0b1000, 0b0111, 0b100, REG_NONE>;
+def VALE1: TLBI<1, 0b000, 0b1000, 0b0111, 0b101, REG_REQUIRED>;
+def VALE2: TLBI<1, 0b100, 0b1000, 0b0111, 0b101, REG_REQUIRED>;
+def VALE3: TLBI<1, 0b110, 0b1000, 0b0111, 0b101, REG_REQUIRED>;
+def VMALLS12E1 : TLBI<0, 0b100, 0b1000, 0b0111, 0b110, REG_NONE>;
+def VAALE1 : TLBI<1, 0b000, 0b1000, 0b0111, 0b111, REG_REQUIRED>;
+
+defvar TLBINames = [
+ "IPAS2E1IS", "IPAS2LE1IS", "VMALLE1IS", "ALLE2IS", "ALLE3IS",
+ "VAE1IS", "VAE2IS", "VAE3IS", "ASIDE1IS", "VAAE1IS",
+ "ALLE1IS", "VALE1IS", "VALE2IS", "VALE3IS", "VMALLS12E1IS",
+ "VAALE1IS", "IPAS2E1", "IPAS2LE1", "VMALLE1", "ALLE2",
+ "ALLE3", "VAE1", "VAE2", "VAE3", "ASIDE1", "VAAE1",
+ "ALLE1", "VALE1", "VALE2", "VALE3", "VMALLS12E1", "VAALE1"
+];
+
+foreach I = TLBINames in {
+ defvar Info = !cast(I);
+ def : TLBIEntry {
+let Encoding{7} = 0;
+ }
+
+ def : TLBIEntry {
let Encoding{7} = 1;
let ExtraRequires = ["AArch64::FeatureXS"];
}
- if !eq(hasTLBIP, true) then {
-def : TLBIPEntry {
- let ExtraRequires = ["AArch64::FeatureD128"];
-}
-def : TLBIPEntry {
- let Encoding{7} = 1;
- let ExtraRequires = ["AArch64::FeatureD128"];
+
+ if !eq(Info.HasTLBIP, true) then {
+foreach nxs = [0, 1] in {
jthackray wrote:
Fixed.
https://github.com/llvm/llvm-project/pull/187400
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[llvm-branch-commits] [llvm] [AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (PR #187400)
@@ -903,128 +903,250 @@ multiclass TLBITableBase {
defm TLBI : TLBITableBase;
defm TLBIP : TLBITableBase;
-multiclass TLBI op1, bits<4> crn, bits<4>
crm,
- bits<3> op2, int reguse = REG_REQUIRED> {
- def : TLBIEntry;
- def : TLBIEntry {
+class TLBI op1, bits<4> crn,
+ bits<4> crm, bits<3> op2, int reguse = REG_REQUIRED> {
+ string Name = NAME;
+ bit HasTLBIP = hasTLBIP;
+ bits<3> Op1 = op1;
+ bits<4> CRn = crn;
+ bits<4> CRm = crm;
+ bits<3> Op2 = op2;
+ int RegUse = reguse;
+}
+
+// TLBI and TLBIP instructions encodings
+// hasTLBIP op1CRn CRm op2reguse
+def IPAS2E1IS: TLBI<1, 0b100, 0b1000, 0b, 0b001, REG_REQUIRED>;
+def IPAS2LE1IS : TLBI<1, 0b100, 0b1000, 0b, 0b101, REG_REQUIRED>;
+def VMALLE1IS: TLBI<0, 0b000, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
+def ALLE2IS : TLBI<0, 0b100, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
+def ALLE3IS : TLBI<0, 0b110, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
+def VAE1IS : TLBI<1, 0b000, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
+def VAE2IS : TLBI<1, 0b100, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
+def VAE3IS : TLBI<1, 0b110, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
+def ASIDE1IS : TLBI<0, 0b000, 0b1000, 0b0011, 0b010, REG_REQUIRED>;
+def VAAE1IS : TLBI<1, 0b000, 0b1000, 0b0011, 0b011, REG_REQUIRED>;
+def ALLE1IS : TLBI<0, 0b100, 0b1000, 0b0011, 0b100, REG_OPTIONAL>;
+def VALE1IS : TLBI<1, 0b000, 0b1000, 0b0011, 0b101, REG_REQUIRED>;
+def VALE2IS : TLBI<1, 0b100, 0b1000, 0b0011, 0b101, REG_REQUIRED>;
+def VALE3IS : TLBI<1, 0b110, 0b1000, 0b0011, 0b101, REG_REQUIRED>;
+def VMALLS12E1IS : TLBI<0, 0b100, 0b1000, 0b0011, 0b110, REG_OPTIONAL>;
+def VAALE1IS : TLBI<1, 0b000, 0b1000, 0b0011, 0b111, REG_REQUIRED>;
+def IPAS2E1 : TLBI<1, 0b100, 0b1000, 0b0100, 0b001, REG_REQUIRED>;
+def IPAS2LE1 : TLBI<1, 0b100, 0b1000, 0b0100, 0b101, REG_REQUIRED>;
+def VMALLE1 : TLBI<0, 0b000, 0b1000, 0b0111, 0b000, REG_NONE>;
+def ALLE2: TLBI<0, 0b100, 0b1000, 0b0111, 0b000, REG_NONE>;
+def ALLE3: TLBI<0, 0b110, 0b1000, 0b0111, 0b000, REG_NONE>;
+def VAE1 : TLBI<1, 0b000, 0b1000, 0b0111, 0b001, REG_REQUIRED>;
+def VAE2 : TLBI<1, 0b100, 0b1000, 0b0111, 0b001, REG_REQUIRED>;
+def VAE3 : TLBI<1, 0b110, 0b1000, 0b0111, 0b001, REG_REQUIRED>;
+def ASIDE1 : TLBI<0, 0b000, 0b1000, 0b0111, 0b010, REG_REQUIRED>;
+def VAAE1: TLBI<1, 0b000, 0b1000, 0b0111, 0b011, REG_REQUIRED>;
+def ALLE1: TLBI<0, 0b100, 0b1000, 0b0111, 0b100, REG_NONE>;
+def VALE1: TLBI<1, 0b000, 0b1000, 0b0111, 0b101, REG_REQUIRED>;
+def VALE2: TLBI<1, 0b100, 0b1000, 0b0111, 0b101, REG_REQUIRED>;
+def VALE3: TLBI<1, 0b110, 0b1000, 0b0111, 0b101, REG_REQUIRED>;
+def VMALLS12E1 : TLBI<0, 0b100, 0b1000, 0b0111, 0b110, REG_NONE>;
+def VAALE1 : TLBI<1, 0b000, 0b1000, 0b0111, 0b111, REG_REQUIRED>;
+
+defvar TLBINames = [
+ "IPAS2E1IS", "IPAS2LE1IS", "VMALLE1IS", "ALLE2IS", "ALLE3IS",
+ "VAE1IS", "VAE2IS", "VAE3IS", "ASIDE1IS", "VAAE1IS",
+ "ALLE1IS", "VALE1IS", "VALE2IS", "VALE3IS", "VMALLS12E1IS",
+ "VAALE1IS", "IPAS2E1", "IPAS2LE1", "VMALLE1", "ALLE2",
+ "ALLE3", "VAE1", "VAE2", "VAE3", "ASIDE1", "VAAE1",
+ "ALLE1", "VALE1", "VALE2", "VALE3", "VMALLS12E1", "VAALE1"
+];
+
+foreach I = TLBINames in {
+ defvar Info = !cast(I);
+ def : TLBIEntry {
+let Encoding{7} = 0;
+ }
+
+ def : TLBIEntry {
let Encoding{7} = 1;
let ExtraRequires = ["AArch64::FeatureXS"];
}
- if !eq(hasTLBIP, true) then {
-def : TLBIPEntry {
- let ExtraRequires = ["AArch64::FeatureD128"];
-}
-def : TLBIPEntry {
- let Encoding{7} = 1;
- let ExtraRequires = ["AArch64::FeatureD128"];
+
+ if !eq(Info.HasTLBIP, true) then {
+foreach nxs = [0, 1] in {
+ defvar VariantName = !if(nxs, !strconcat(I, "nXS"), I);
+ def : TLBIPEntry {
+let Encoding{7} = nxs;
+let Requires = ["AArch64::FeatureD128"];
+ }
}
}
}
-// hasTLBIP op1CRn CRm op2reguse
-defm : TLBI<"IPAS2E1IS",1, 0b100, 0b1000, 0b, 0b001, REG_REQUIRED>;
-defm : TLBI<"IPAS2LE1IS", 1, 0b100, 0b1000, 0b, 0b101, REG_REQUIRED>;
-defm : TLBI<"VMALLE1IS",0, 0b000, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
-defm : TLBI<"ALLE2IS", 0, 0b100, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
-defm : TLBI<"ALLE3IS", 0, 0b110, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
-defm : TLBI<"VAE1IS", 1, 0b000, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
-defm : TLBI<"VAE2IS", 1, 0b100, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
-defm : TLBI<"VAE3IS", 1, 0b110, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
-defm : TLBI<"ASIDE1IS", 0, 0b000, 0b1000, 0b0011, 0b010, REG_REQUIRED>;
-defm : TLBI<"VAAE1IS", 1, 0b000, 0b1000, 0b0011, 0b011, REG_REQUIRED>;
-defm : TLBI<"ALLE1IS", 0, 0b100, 0b1000, 0b0011, 0b100, REG_OPTIONAL>;
-defm : TLBI<"VALE1IS",
[llvm-branch-commits] [llvm] [AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (PR #187400)
@@ -903,128 +903,250 @@ multiclass TLBITableBase {
defm TLBI : TLBITableBase;
defm TLBIP : TLBITableBase;
-multiclass TLBI op1, bits<4> crn, bits<4>
crm,
- bits<3> op2, int reguse = REG_REQUIRED> {
- def : TLBIEntry;
- def : TLBIEntry {
+class TLBI op1, bits<4> crn,
+ bits<4> crm, bits<3> op2, int reguse = REG_REQUIRED> {
+ string Name = NAME;
+ bit HasTLBIP = hasTLBIP;
+ bits<3> Op1 = op1;
+ bits<4> CRn = crn;
+ bits<4> CRm = crm;
+ bits<3> Op2 = op2;
+ int RegUse = reguse;
+}
+
+// TLBI and TLBIP instructions encodings
+// hasTLBIP op1CRn CRm op2reguse
+def IPAS2E1IS: TLBI<1, 0b100, 0b1000, 0b, 0b001, REG_REQUIRED>;
+def IPAS2LE1IS : TLBI<1, 0b100, 0b1000, 0b, 0b101, REG_REQUIRED>;
+def VMALLE1IS: TLBI<0, 0b000, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
+def ALLE2IS : TLBI<0, 0b100, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
+def ALLE3IS : TLBI<0, 0b110, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
+def VAE1IS : TLBI<1, 0b000, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
+def VAE2IS : TLBI<1, 0b100, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
+def VAE3IS : TLBI<1, 0b110, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
+def ASIDE1IS : TLBI<0, 0b000, 0b1000, 0b0011, 0b010, REG_REQUIRED>;
+def VAAE1IS : TLBI<1, 0b000, 0b1000, 0b0011, 0b011, REG_REQUIRED>;
+def ALLE1IS : TLBI<0, 0b100, 0b1000, 0b0011, 0b100, REG_OPTIONAL>;
+def VALE1IS : TLBI<1, 0b000, 0b1000, 0b0011, 0b101, REG_REQUIRED>;
+def VALE2IS : TLBI<1, 0b100, 0b1000, 0b0011, 0b101, REG_REQUIRED>;
+def VALE3IS : TLBI<1, 0b110, 0b1000, 0b0011, 0b101, REG_REQUIRED>;
+def VMALLS12E1IS : TLBI<0, 0b100, 0b1000, 0b0011, 0b110, REG_OPTIONAL>;
+def VAALE1IS : TLBI<1, 0b000, 0b1000, 0b0011, 0b111, REG_REQUIRED>;
+def IPAS2E1 : TLBI<1, 0b100, 0b1000, 0b0100, 0b001, REG_REQUIRED>;
+def IPAS2LE1 : TLBI<1, 0b100, 0b1000, 0b0100, 0b101, REG_REQUIRED>;
+def VMALLE1 : TLBI<0, 0b000, 0b1000, 0b0111, 0b000, REG_NONE>;
+def ALLE2: TLBI<0, 0b100, 0b1000, 0b0111, 0b000, REG_NONE>;
+def ALLE3: TLBI<0, 0b110, 0b1000, 0b0111, 0b000, REG_NONE>;
+def VAE1 : TLBI<1, 0b000, 0b1000, 0b0111, 0b001, REG_REQUIRED>;
+def VAE2 : TLBI<1, 0b100, 0b1000, 0b0111, 0b001, REG_REQUIRED>;
+def VAE3 : TLBI<1, 0b110, 0b1000, 0b0111, 0b001, REG_REQUIRED>;
+def ASIDE1 : TLBI<0, 0b000, 0b1000, 0b0111, 0b010, REG_REQUIRED>;
+def VAAE1: TLBI<1, 0b000, 0b1000, 0b0111, 0b011, REG_REQUIRED>;
+def ALLE1: TLBI<0, 0b100, 0b1000, 0b0111, 0b100, REG_NONE>;
+def VALE1: TLBI<1, 0b000, 0b1000, 0b0111, 0b101, REG_REQUIRED>;
+def VALE2: TLBI<1, 0b100, 0b1000, 0b0111, 0b101, REG_REQUIRED>;
+def VALE3: TLBI<1, 0b110, 0b1000, 0b0111, 0b101, REG_REQUIRED>;
+def VMALLS12E1 : TLBI<0, 0b100, 0b1000, 0b0111, 0b110, REG_NONE>;
+def VAALE1 : TLBI<1, 0b000, 0b1000, 0b0111, 0b111, REG_REQUIRED>;
+
+defvar TLBINames = [
+ "IPAS2E1IS", "IPAS2LE1IS", "VMALLE1IS", "ALLE2IS", "ALLE3IS",
+ "VAE1IS", "VAE2IS", "VAE3IS", "ASIDE1IS", "VAAE1IS",
+ "ALLE1IS", "VALE1IS", "VALE2IS", "VALE3IS", "VMALLS12E1IS",
+ "VAALE1IS", "IPAS2E1", "IPAS2LE1", "VMALLE1", "ALLE2",
+ "ALLE3", "VAE1", "VAE2", "VAE3", "ASIDE1", "VAAE1",
+ "ALLE1", "VALE1", "VALE2", "VALE3", "VMALLS12E1", "VAALE1"
+];
+
+foreach I = TLBINames in {
+ defvar Info = !cast(I);
+ def : TLBIEntry {
+let Encoding{7} = 0;
+ }
+
+ def : TLBIEntry {
let Encoding{7} = 1;
let ExtraRequires = ["AArch64::FeatureXS"];
}
- if !eq(hasTLBIP, true) then {
-def : TLBIPEntry {
- let ExtraRequires = ["AArch64::FeatureD128"];
-}
-def : TLBIPEntry {
- let Encoding{7} = 1;
- let ExtraRequires = ["AArch64::FeatureD128"];
+
+ if !eq(Info.HasTLBIP, true) then {
+foreach nxs = [0, 1] in {
+ defvar VariantName = !if(nxs, !strconcat(I, "nXS"), I);
+ def : TLBIPEntry {
+let Encoding{7} = nxs;
+let Requires = ["AArch64::FeatureD128"];
+ }
}
}
}
-// hasTLBIP op1CRn CRm op2reguse
-defm : TLBI<"IPAS2E1IS",1, 0b100, 0b1000, 0b, 0b001, REG_REQUIRED>;
-defm : TLBI<"IPAS2LE1IS", 1, 0b100, 0b1000, 0b, 0b101, REG_REQUIRED>;
-defm : TLBI<"VMALLE1IS",0, 0b000, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
-defm : TLBI<"ALLE2IS", 0, 0b100, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
-defm : TLBI<"ALLE3IS", 0, 0b110, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
-defm : TLBI<"VAE1IS", 1, 0b000, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
-defm : TLBI<"VAE2IS", 1, 0b100, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
-defm : TLBI<"VAE3IS", 1, 0b110, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
-defm : TLBI<"ASIDE1IS", 0, 0b000, 0b1000, 0b0011, 0b010, REG_REQUIRED>;
-defm : TLBI<"VAAE1IS", 1, 0b000, 0b1000, 0b0011, 0b011, REG_REQUIRED>;
-defm : TLBI<"ALLE1IS", 0, 0b100, 0b1000, 0b0011, 0b100, REG_OPTIONAL>;
-defm : TLBI<"VALE1IS",
[llvm-branch-commits] [llvm] [AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (PR #187400)
@@ -903,128 +903,250 @@ multiclass TLBITableBase {
defm TLBI : TLBITableBase;
defm TLBIP : TLBITableBase;
-multiclass TLBI op1, bits<4> crn, bits<4>
crm,
- bits<3> op2, int reguse = REG_REQUIRED> {
- def : TLBIEntry;
- def : TLBIEntry {
+class TLBI op1, bits<4> crn,
+ bits<4> crm, bits<3> op2, int reguse = REG_REQUIRED> {
+ string Name = NAME;
+ bit HasTLBIP = hasTLBIP;
+ bits<3> Op1 = op1;
+ bits<4> CRn = crn;
+ bits<4> CRm = crm;
+ bits<3> Op2 = op2;
+ int RegUse = reguse;
+}
+
+// TLBI and TLBIP instructions encodings
+// hasTLBIP op1CRn CRm op2reguse
+def IPAS2E1IS: TLBI<1, 0b100, 0b1000, 0b, 0b001, REG_REQUIRED>;
+def IPAS2LE1IS : TLBI<1, 0b100, 0b1000, 0b, 0b101, REG_REQUIRED>;
+def VMALLE1IS: TLBI<0, 0b000, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
+def ALLE2IS : TLBI<0, 0b100, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
+def ALLE3IS : TLBI<0, 0b110, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
+def VAE1IS : TLBI<1, 0b000, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
+def VAE2IS : TLBI<1, 0b100, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
+def VAE3IS : TLBI<1, 0b110, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
+def ASIDE1IS : TLBI<0, 0b000, 0b1000, 0b0011, 0b010, REG_REQUIRED>;
+def VAAE1IS : TLBI<1, 0b000, 0b1000, 0b0011, 0b011, REG_REQUIRED>;
+def ALLE1IS : TLBI<0, 0b100, 0b1000, 0b0011, 0b100, REG_OPTIONAL>;
+def VALE1IS : TLBI<1, 0b000, 0b1000, 0b0011, 0b101, REG_REQUIRED>;
+def VALE2IS : TLBI<1, 0b100, 0b1000, 0b0011, 0b101, REG_REQUIRED>;
+def VALE3IS : TLBI<1, 0b110, 0b1000, 0b0011, 0b101, REG_REQUIRED>;
+def VMALLS12E1IS : TLBI<0, 0b100, 0b1000, 0b0011, 0b110, REG_OPTIONAL>;
+def VAALE1IS : TLBI<1, 0b000, 0b1000, 0b0011, 0b111, REG_REQUIRED>;
+def IPAS2E1 : TLBI<1, 0b100, 0b1000, 0b0100, 0b001, REG_REQUIRED>;
+def IPAS2LE1 : TLBI<1, 0b100, 0b1000, 0b0100, 0b101, REG_REQUIRED>;
+def VMALLE1 : TLBI<0, 0b000, 0b1000, 0b0111, 0b000, REG_NONE>;
+def ALLE2: TLBI<0, 0b100, 0b1000, 0b0111, 0b000, REG_NONE>;
+def ALLE3: TLBI<0, 0b110, 0b1000, 0b0111, 0b000, REG_NONE>;
+def VAE1 : TLBI<1, 0b000, 0b1000, 0b0111, 0b001, REG_REQUIRED>;
+def VAE2 : TLBI<1, 0b100, 0b1000, 0b0111, 0b001, REG_REQUIRED>;
+def VAE3 : TLBI<1, 0b110, 0b1000, 0b0111, 0b001, REG_REQUIRED>;
+def ASIDE1 : TLBI<0, 0b000, 0b1000, 0b0111, 0b010, REG_REQUIRED>;
+def VAAE1: TLBI<1, 0b000, 0b1000, 0b0111, 0b011, REG_REQUIRED>;
+def ALLE1: TLBI<0, 0b100, 0b1000, 0b0111, 0b100, REG_NONE>;
+def VALE1: TLBI<1, 0b000, 0b1000, 0b0111, 0b101, REG_REQUIRED>;
+def VALE2: TLBI<1, 0b100, 0b1000, 0b0111, 0b101, REG_REQUIRED>;
+def VALE3: TLBI<1, 0b110, 0b1000, 0b0111, 0b101, REG_REQUIRED>;
+def VMALLS12E1 : TLBI<0, 0b100, 0b1000, 0b0111, 0b110, REG_NONE>;
+def VAALE1 : TLBI<1, 0b000, 0b1000, 0b0111, 0b111, REG_REQUIRED>;
+
+defvar TLBINames = [
+ "IPAS2E1IS", "IPAS2LE1IS", "VMALLE1IS", "ALLE2IS", "ALLE3IS",
+ "VAE1IS", "VAE2IS", "VAE3IS", "ASIDE1IS", "VAAE1IS",
+ "ALLE1IS", "VALE1IS", "VALE2IS", "VALE3IS", "VMALLS12E1IS",
+ "VAALE1IS", "IPAS2E1", "IPAS2LE1", "VMALLE1", "ALLE2",
+ "ALLE3", "VAE1", "VAE2", "VAE3", "ASIDE1", "VAAE1",
+ "ALLE1", "VALE1", "VALE2", "VALE3", "VMALLS12E1", "VAALE1"
+];
+
+foreach I = TLBINames in {
+ defvar Info = !cast(I);
+ def : TLBIEntry {
+let Encoding{7} = 0;
+ }
+
+ def : TLBIEntry {
let Encoding{7} = 1;
let ExtraRequires = ["AArch64::FeatureXS"];
}
- if !eq(hasTLBIP, true) then {
-def : TLBIPEntry {
- let ExtraRequires = ["AArch64::FeatureD128"];
-}
-def : TLBIPEntry {
- let Encoding{7} = 1;
- let ExtraRequires = ["AArch64::FeatureD128"];
+
+ if !eq(Info.HasTLBIP, true) then {
+foreach nxs = [0, 1] in {
+ defvar VariantName = !if(nxs, !strconcat(I, "nXS"), I);
+ def : TLBIPEntry {
+let Encoding{7} = nxs;
+let Requires = ["AArch64::FeatureD128"];
+ }
}
}
}
-// hasTLBIP op1CRn CRm op2reguse
-defm : TLBI<"IPAS2E1IS",1, 0b100, 0b1000, 0b, 0b001, REG_REQUIRED>;
-defm : TLBI<"IPAS2LE1IS", 1, 0b100, 0b1000, 0b, 0b101, REG_REQUIRED>;
-defm : TLBI<"VMALLE1IS",0, 0b000, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
-defm : TLBI<"ALLE2IS", 0, 0b100, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
-defm : TLBI<"ALLE3IS", 0, 0b110, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
-defm : TLBI<"VAE1IS", 1, 0b000, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
-defm : TLBI<"VAE2IS", 1, 0b100, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
-defm : TLBI<"VAE3IS", 1, 0b110, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
-defm : TLBI<"ASIDE1IS", 0, 0b000, 0b1000, 0b0011, 0b010, REG_REQUIRED>;
-defm : TLBI<"VAAE1IS", 1, 0b000, 0b1000, 0b0011, 0b011, REG_REQUIRED>;
-defm : TLBI<"ALLE1IS", 0, 0b100, 0b1000, 0b0011, 0b100, REG_OPTIONAL>;
-defm : TLBI<"VALE1IS",
[llvm-branch-commits] [llvm] [AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (PR #187400)
https://github.com/jthackray updated
https://github.com/llvm/llvm-project/pull/187400
>From 7a74c1de4e939ad8097341da35f689cc4be77edf Mon Sep 17 00:00:00 2001
From: Jonathan Thackray
Date: Wed, 18 Mar 2026 20:54:50 +
Subject: [PATCH 1/4] [AArch64][llvm] Separate TLBI-only feature gating from
TLBIP aliases
Refactor the TLBI system operand definitions so that TLBI and TLBIP
records are emitted through separate helper multiclasses, whilst keeping
the table layout readable.
The feature-scoped wrappers now apply FeatureTLB_RMI, FeatureRME, and
FeatureTLBIW only to TLBI records (it was previously incorrectly also
applied to TLBIP instructions), while TLBIP aliases remain gated only
by FeatureD128, including their nXS forms.
Update testcases accordingly.
---
.../Target/AArch64/AArch64SystemOperands.td | 178 ++
llvm/test/MC/AArch64/armv9a-tlbip.s | 17 +-
2 files changed, 111 insertions(+), 84 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
index 257a4958e8305..d914b253c5358 100644
--- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
+++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
@@ -903,24 +903,54 @@ multiclass TLBITableBase {
defm TLBI : TLBITableBase;
defm TLBIP : TLBITableBase;
-multiclass TLBI op1, bits<4> crn, bits<4>
crm,
- bits<3> op2, int reguse = REG_REQUIRED> {
- def : TLBIEntry;
- def : TLBIEntry {
-let Encoding{7} = 1;
-let ExtraRequires = ["AArch64::FeatureXS"];
- }
- if !eq(hasTLBIP, true) then {
-def : TLBIPEntry {
- let ExtraRequires = ["AArch64::FeatureD128"];
+multiclass TLBI_Base op1, bits<4> crn, bits<4> crm,
+ bits<3> op2, int reguse = REG_REQUIRED,
+ list extra_requires = []> {
+ foreach nxs = [0, 1] in {
+defvar VariantName = !if(nxs, !strconcat(name, "nXS"), name);
+defvar VariantRequires = !if(nxs,
+ extra_requires # ["AArch64::FeatureXS"],
+ extra_requires);
+def : TLBIEntry {
+ let Encoding{7} = nxs;
+ let ExtraRequires = VariantRequires;
}
-def : TLBIPEntry {
- let Encoding{7} = 1;
- let ExtraRequires = ["AArch64::FeatureD128"];
+ }
+}
+
+multiclass TLBIP_Base op1, bits<4> crn, bits<4> crm,
+ bits<3> op2, int reguse = REG_REQUIRED,
+ list extra_requires = ["AArch64::FeatureD128"]> {
+ foreach nxs = [0, 1] in {
+// TLBIP instructions aren't gated by FeatureXS like TLBI ones
+defvar VariantName = !if(nxs, !strconcat(name, "nXS"), name);
+def : TLBIPEntry {
+ let Encoding{7} = nxs;
+ let ExtraRequires = extra_requires;
}
}
}
+multiclass TLBI op1, bits<4> crn,
+bits<4> crm, bits<3> op2, int reguse = REG_REQUIRED> {
+ defm : TLBI_Base;
+ if !eq(hasTLBIP, true) then {
+defm : TLBIP_Base;
+ }
+}
+
+multiclass TLBI_RMI op1, bits<4> crn,
+bits<4> crm, bits<3> op2, int reguse = REG_REQUIRED> {
+ let Requires = ["AArch64::FeatureTLB_RMI"] in {
+defm : TLBI_Base;
+ }
+ // TLBIP instructions aren't gated by FeatureTLB_RMI
+ if !eq(hasTLBIP, true) then {
+defm : TLBIP_Base;
+ }
+}
+
+// TLBI and TLBIP instructions encodings
// hasTLBIP op1CRn CRm op2reguse
defm : TLBI<"IPAS2E1IS",1, 0b100, 0b1000, 0b, 0b001, REG_REQUIRED>;
defm : TLBI<"IPAS2LE1IS", 1, 0b100, 0b1000, 0b, 0b101, REG_REQUIRED>;
@@ -955,76 +985,74 @@ defm : TLBI<"VALE3",1, 0b110, 0b1000, 0b0111,
0b101, REG_REQUIRED>;
defm : TLBI<"VMALLS12E1", 0, 0b100, 0b1000, 0b0111, 0b110, REG_NONE>;
defm : TLBI<"VAALE1", 1, 0b000, 0b1000, 0b0111, 0b111, REG_REQUIRED>;
-// Armv8.4-A Translation Lookaside Buffer Instructions (TLBI)
-let Requires = ["AArch64::FeatureTLB_RMI"] in {
+// Armv8.4-A Translation Lookaside Buffer Instructions (TLBI and TLBIP)
// Armv8.4-A Outer Sharable TLB Maintenance instructions:
-// hasTLBIP op1CRn CRm op2reguse
-defm : TLBI<"VMALLE1OS",0, 0b000, 0b1000, 0b0001, 0b000, REG_OPTIONAL>;
-defm : TLBI<"VAE1OS", 1, 0b000, 0b1000, 0b0001, 0b001, REG_REQUIRED>;
-defm : TLBI<"ASIDE1OS", 0, 0b000, 0b1000, 0b0001, 0b010, REG_REQUIRED>;
-defm : TLBI<"VAAE1OS", 1, 0b000, 0b1000, 0b0001, 0b011, REG_REQUIRED>;
-defm : TLBI<"VALE1OS", 1, 0b000, 0b1000, 0b0001, 0b101, REG_REQUIRED>;
-defm : TLBI<"VAALE1OS", 1, 0b000, 0b1000, 0b0001, 0b111, REG_REQUIRED>;
-defm : TLBI<"IPAS2E1OS",1, 0b100, 0b1000, 0b0100, 0b000, REG_REQUIRED>;
-defm : TLBI<"IPAS2LE1OS", 1, 0b100, 0b1000, 0b0100, 0b100, REG_REQUIRED>;
-defm : TLBI<"VAE2OS", 1, 0b100, 0b1000, 0b0001, 0b001, REG_REQUIRED>;
-defm : TLBI<"VALE2OS", 1, 0b100, 0b1000, 0b0001, 0b101, REG_REQUIRED>;
-defm : TLBI<"VMALLS12E1OS", 0, 0b100, 0b1000, 0b0001, 0b110, REG_OPTIONAL>;
-defm : TLBI<"VAE3OS", 1,
[llvm-branch-commits] [llvm] [AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (PR #187400)
@@ -903,128 +903,250 @@ multiclass TLBITableBase {
defm TLBI : TLBITableBase;
defm TLBIP : TLBITableBase;
-multiclass TLBI op1, bits<4> crn, bits<4>
crm,
- bits<3> op2, int reguse = REG_REQUIRED> {
- def : TLBIEntry;
- def : TLBIEntry {
+class TLBI op1, bits<4> crn,
+ bits<4> crm, bits<3> op2, int reguse = REG_REQUIRED> {
+ string Name = NAME;
+ bit HasTLBIP = hasTLBIP;
+ bits<3> Op1 = op1;
+ bits<4> CRn = crn;
+ bits<4> CRm = crm;
+ bits<3> Op2 = op2;
+ int RegUse = reguse;
+}
+
+// TLBI and TLBIP instructions encodings
+// hasTLBIP op1CRn CRm op2reguse
+def IPAS2E1IS: TLBI<1, 0b100, 0b1000, 0b, 0b001, REG_REQUIRED>;
+def IPAS2LE1IS : TLBI<1, 0b100, 0b1000, 0b, 0b101, REG_REQUIRED>;
+def VMALLE1IS: TLBI<0, 0b000, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
+def ALLE2IS : TLBI<0, 0b100, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
+def ALLE3IS : TLBI<0, 0b110, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
+def VAE1IS : TLBI<1, 0b000, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
+def VAE2IS : TLBI<1, 0b100, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
+def VAE3IS : TLBI<1, 0b110, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
+def ASIDE1IS : TLBI<0, 0b000, 0b1000, 0b0011, 0b010, REG_REQUIRED>;
+def VAAE1IS : TLBI<1, 0b000, 0b1000, 0b0011, 0b011, REG_REQUIRED>;
+def ALLE1IS : TLBI<0, 0b100, 0b1000, 0b0011, 0b100, REG_OPTIONAL>;
+def VALE1IS : TLBI<1, 0b000, 0b1000, 0b0011, 0b101, REG_REQUIRED>;
+def VALE2IS : TLBI<1, 0b100, 0b1000, 0b0011, 0b101, REG_REQUIRED>;
+def VALE3IS : TLBI<1, 0b110, 0b1000, 0b0011, 0b101, REG_REQUIRED>;
+def VMALLS12E1IS : TLBI<0, 0b100, 0b1000, 0b0011, 0b110, REG_OPTIONAL>;
+def VAALE1IS : TLBI<1, 0b000, 0b1000, 0b0011, 0b111, REG_REQUIRED>;
+def IPAS2E1 : TLBI<1, 0b100, 0b1000, 0b0100, 0b001, REG_REQUIRED>;
+def IPAS2LE1 : TLBI<1, 0b100, 0b1000, 0b0100, 0b101, REG_REQUIRED>;
+def VMALLE1 : TLBI<0, 0b000, 0b1000, 0b0111, 0b000, REG_NONE>;
+def ALLE2: TLBI<0, 0b100, 0b1000, 0b0111, 0b000, REG_NONE>;
+def ALLE3: TLBI<0, 0b110, 0b1000, 0b0111, 0b000, REG_NONE>;
+def VAE1 : TLBI<1, 0b000, 0b1000, 0b0111, 0b001, REG_REQUIRED>;
+def VAE2 : TLBI<1, 0b100, 0b1000, 0b0111, 0b001, REG_REQUIRED>;
+def VAE3 : TLBI<1, 0b110, 0b1000, 0b0111, 0b001, REG_REQUIRED>;
+def ASIDE1 : TLBI<0, 0b000, 0b1000, 0b0111, 0b010, REG_REQUIRED>;
+def VAAE1: TLBI<1, 0b000, 0b1000, 0b0111, 0b011, REG_REQUIRED>;
+def ALLE1: TLBI<0, 0b100, 0b1000, 0b0111, 0b100, REG_NONE>;
+def VALE1: TLBI<1, 0b000, 0b1000, 0b0111, 0b101, REG_REQUIRED>;
+def VALE2: TLBI<1, 0b100, 0b1000, 0b0111, 0b101, REG_REQUIRED>;
+def VALE3: TLBI<1, 0b110, 0b1000, 0b0111, 0b101, REG_REQUIRED>;
+def VMALLS12E1 : TLBI<0, 0b100, 0b1000, 0b0111, 0b110, REG_NONE>;
+def VAALE1 : TLBI<1, 0b000, 0b1000, 0b0111, 0b111, REG_REQUIRED>;
+
+defvar TLBINames = [
+ "IPAS2E1IS", "IPAS2LE1IS", "VMALLE1IS", "ALLE2IS", "ALLE3IS",
+ "VAE1IS", "VAE2IS", "VAE3IS", "ASIDE1IS", "VAAE1IS",
+ "ALLE1IS", "VALE1IS", "VALE2IS", "VALE3IS", "VMALLS12E1IS",
+ "VAALE1IS", "IPAS2E1", "IPAS2LE1", "VMALLE1", "ALLE2",
+ "ALLE3", "VAE1", "VAE2", "VAE3", "ASIDE1", "VAAE1",
+ "ALLE1", "VALE1", "VALE2", "VALE3", "VMALLS12E1", "VAALE1"
+];
+
+foreach I = TLBINames in {
+ defvar Info = !cast(I);
+ def : TLBIEntry {
+let Encoding{7} = 0;
+ }
+
+ def : TLBIEntry {
let Encoding{7} = 1;
let ExtraRequires = ["AArch64::FeatureXS"];
}
- if !eq(hasTLBIP, true) then {
-def : TLBIPEntry {
- let ExtraRequires = ["AArch64::FeatureD128"];
-}
-def : TLBIPEntry {
- let Encoding{7} = 1;
- let ExtraRequires = ["AArch64::FeatureD128"];
+
+ if !eq(Info.HasTLBIP, true) then {
+foreach nxs = [0, 1] in {
+ defvar VariantName = !if(nxs, !strconcat(I, "nXS"), I);
+ def : TLBIPEntry {
+let Encoding{7} = nxs;
+let Requires = ["AArch64::FeatureD128"];
+ }
}
}
}
-// hasTLBIP op1CRn CRm op2reguse
-defm : TLBI<"IPAS2E1IS",1, 0b100, 0b1000, 0b, 0b001, REG_REQUIRED>;
-defm : TLBI<"IPAS2LE1IS", 1, 0b100, 0b1000, 0b, 0b101, REG_REQUIRED>;
-defm : TLBI<"VMALLE1IS",0, 0b000, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
-defm : TLBI<"ALLE2IS", 0, 0b100, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
-defm : TLBI<"ALLE3IS", 0, 0b110, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
-defm : TLBI<"VAE1IS", 1, 0b000, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
-defm : TLBI<"VAE2IS", 1, 0b100, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
-defm : TLBI<"VAE3IS", 1, 0b110, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
-defm : TLBI<"ASIDE1IS", 0, 0b000, 0b1000, 0b0011, 0b010, REG_REQUIRED>;
-defm : TLBI<"VAAE1IS", 1, 0b000, 0b1000, 0b0011, 0b011, REG_REQUIRED>;
-defm : TLBI<"ALLE1IS", 0, 0b100, 0b1000, 0b0011, 0b100, REG_OPTIONAL>;
-defm : TLBI<"VALE1IS",
[llvm-branch-commits] [llvm] [AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (PR #187400)
@@ -903,128 +903,250 @@ multiclass TLBITableBase {
defm TLBI : TLBITableBase;
defm TLBIP : TLBITableBase;
-multiclass TLBI op1, bits<4> crn, bits<4>
crm,
- bits<3> op2, int reguse = REG_REQUIRED> {
- def : TLBIEntry;
- def : TLBIEntry {
+class TLBI op1, bits<4> crn,
+ bits<4> crm, bits<3> op2, int reguse = REG_REQUIRED> {
+ string Name = NAME;
+ bit HasTLBIP = hasTLBIP;
+ bits<3> Op1 = op1;
+ bits<4> CRn = crn;
+ bits<4> CRm = crm;
+ bits<3> Op2 = op2;
+ int RegUse = reguse;
+}
+
+// TLBI and TLBIP instructions encodings
+// hasTLBIP op1CRn CRm op2reguse
+def IPAS2E1IS: TLBI<1, 0b100, 0b1000, 0b, 0b001, REG_REQUIRED>;
+def IPAS2LE1IS : TLBI<1, 0b100, 0b1000, 0b, 0b101, REG_REQUIRED>;
+def VMALLE1IS: TLBI<0, 0b000, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
+def ALLE2IS : TLBI<0, 0b100, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
+def ALLE3IS : TLBI<0, 0b110, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
+def VAE1IS : TLBI<1, 0b000, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
+def VAE2IS : TLBI<1, 0b100, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
+def VAE3IS : TLBI<1, 0b110, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
+def ASIDE1IS : TLBI<0, 0b000, 0b1000, 0b0011, 0b010, REG_REQUIRED>;
+def VAAE1IS : TLBI<1, 0b000, 0b1000, 0b0011, 0b011, REG_REQUIRED>;
+def ALLE1IS : TLBI<0, 0b100, 0b1000, 0b0011, 0b100, REG_OPTIONAL>;
+def VALE1IS : TLBI<1, 0b000, 0b1000, 0b0011, 0b101, REG_REQUIRED>;
+def VALE2IS : TLBI<1, 0b100, 0b1000, 0b0011, 0b101, REG_REQUIRED>;
+def VALE3IS : TLBI<1, 0b110, 0b1000, 0b0011, 0b101, REG_REQUIRED>;
+def VMALLS12E1IS : TLBI<0, 0b100, 0b1000, 0b0011, 0b110, REG_OPTIONAL>;
+def VAALE1IS : TLBI<1, 0b000, 0b1000, 0b0011, 0b111, REG_REQUIRED>;
+def IPAS2E1 : TLBI<1, 0b100, 0b1000, 0b0100, 0b001, REG_REQUIRED>;
+def IPAS2LE1 : TLBI<1, 0b100, 0b1000, 0b0100, 0b101, REG_REQUIRED>;
+def VMALLE1 : TLBI<0, 0b000, 0b1000, 0b0111, 0b000, REG_NONE>;
+def ALLE2: TLBI<0, 0b100, 0b1000, 0b0111, 0b000, REG_NONE>;
+def ALLE3: TLBI<0, 0b110, 0b1000, 0b0111, 0b000, REG_NONE>;
+def VAE1 : TLBI<1, 0b000, 0b1000, 0b0111, 0b001, REG_REQUIRED>;
+def VAE2 : TLBI<1, 0b100, 0b1000, 0b0111, 0b001, REG_REQUIRED>;
+def VAE3 : TLBI<1, 0b110, 0b1000, 0b0111, 0b001, REG_REQUIRED>;
+def ASIDE1 : TLBI<0, 0b000, 0b1000, 0b0111, 0b010, REG_REQUIRED>;
+def VAAE1: TLBI<1, 0b000, 0b1000, 0b0111, 0b011, REG_REQUIRED>;
+def ALLE1: TLBI<0, 0b100, 0b1000, 0b0111, 0b100, REG_NONE>;
+def VALE1: TLBI<1, 0b000, 0b1000, 0b0111, 0b101, REG_REQUIRED>;
+def VALE2: TLBI<1, 0b100, 0b1000, 0b0111, 0b101, REG_REQUIRED>;
+def VALE3: TLBI<1, 0b110, 0b1000, 0b0111, 0b101, REG_REQUIRED>;
+def VMALLS12E1 : TLBI<0, 0b100, 0b1000, 0b0111, 0b110, REG_NONE>;
+def VAALE1 : TLBI<1, 0b000, 0b1000, 0b0111, 0b111, REG_REQUIRED>;
+
+defvar TLBINames = [
jthackray wrote:
You mean wrap them into the `foreach i in ["IPAS2E1IS", ... ]` presumably. I
considered that although it looks more dense on screen. I'll see if I can make
it look readable.
https://github.com/llvm/llvm-project/pull/187400
___
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[llvm-branch-commits] [llvm] [AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (PR #187400)
@@ -903,128 +903,250 @@ multiclass TLBITableBase {
defm TLBI : TLBITableBase;
defm TLBIP : TLBITableBase;
-multiclass TLBI op1, bits<4> crn, bits<4>
crm,
- bits<3> op2, int reguse = REG_REQUIRED> {
- def : TLBIEntry;
- def : TLBIEntry {
+class TLBI op1, bits<4> crn,
+ bits<4> crm, bits<3> op2, int reguse = REG_REQUIRED> {
+ string Name = NAME;
+ bit HasTLBIP = hasTLBIP;
+ bits<3> Op1 = op1;
+ bits<4> CRn = crn;
+ bits<4> CRm = crm;
+ bits<3> Op2 = op2;
+ int RegUse = reguse;
+}
+
+// TLBI and TLBIP instructions encodings
+// hasTLBIP op1CRn CRm op2reguse
+def IPAS2E1IS: TLBI<1, 0b100, 0b1000, 0b, 0b001, REG_REQUIRED>;
+def IPAS2LE1IS : TLBI<1, 0b100, 0b1000, 0b, 0b101, REG_REQUIRED>;
+def VMALLE1IS: TLBI<0, 0b000, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
+def ALLE2IS : TLBI<0, 0b100, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
+def ALLE3IS : TLBI<0, 0b110, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
+def VAE1IS : TLBI<1, 0b000, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
+def VAE2IS : TLBI<1, 0b100, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
+def VAE3IS : TLBI<1, 0b110, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
+def ASIDE1IS : TLBI<0, 0b000, 0b1000, 0b0011, 0b010, REG_REQUIRED>;
+def VAAE1IS : TLBI<1, 0b000, 0b1000, 0b0011, 0b011, REG_REQUIRED>;
+def ALLE1IS : TLBI<0, 0b100, 0b1000, 0b0011, 0b100, REG_OPTIONAL>;
+def VALE1IS : TLBI<1, 0b000, 0b1000, 0b0011, 0b101, REG_REQUIRED>;
+def VALE2IS : TLBI<1, 0b100, 0b1000, 0b0011, 0b101, REG_REQUIRED>;
+def VALE3IS : TLBI<1, 0b110, 0b1000, 0b0011, 0b101, REG_REQUIRED>;
+def VMALLS12E1IS : TLBI<0, 0b100, 0b1000, 0b0011, 0b110, REG_OPTIONAL>;
+def VAALE1IS : TLBI<1, 0b000, 0b1000, 0b0011, 0b111, REG_REQUIRED>;
+def IPAS2E1 : TLBI<1, 0b100, 0b1000, 0b0100, 0b001, REG_REQUIRED>;
+def IPAS2LE1 : TLBI<1, 0b100, 0b1000, 0b0100, 0b101, REG_REQUIRED>;
+def VMALLE1 : TLBI<0, 0b000, 0b1000, 0b0111, 0b000, REG_NONE>;
+def ALLE2: TLBI<0, 0b100, 0b1000, 0b0111, 0b000, REG_NONE>;
+def ALLE3: TLBI<0, 0b110, 0b1000, 0b0111, 0b000, REG_NONE>;
+def VAE1 : TLBI<1, 0b000, 0b1000, 0b0111, 0b001, REG_REQUIRED>;
+def VAE2 : TLBI<1, 0b100, 0b1000, 0b0111, 0b001, REG_REQUIRED>;
+def VAE3 : TLBI<1, 0b110, 0b1000, 0b0111, 0b001, REG_REQUIRED>;
+def ASIDE1 : TLBI<0, 0b000, 0b1000, 0b0111, 0b010, REG_REQUIRED>;
+def VAAE1: TLBI<1, 0b000, 0b1000, 0b0111, 0b011, REG_REQUIRED>;
+def ALLE1: TLBI<0, 0b100, 0b1000, 0b0111, 0b100, REG_NONE>;
+def VALE1: TLBI<1, 0b000, 0b1000, 0b0111, 0b101, REG_REQUIRED>;
+def VALE2: TLBI<1, 0b100, 0b1000, 0b0111, 0b101, REG_REQUIRED>;
+def VALE3: TLBI<1, 0b110, 0b1000, 0b0111, 0b101, REG_REQUIRED>;
+def VMALLS12E1 : TLBI<0, 0b100, 0b1000, 0b0111, 0b110, REG_NONE>;
+def VAALE1 : TLBI<1, 0b000, 0b1000, 0b0111, 0b111, REG_REQUIRED>;
+
+defvar TLBINames = [
+ "IPAS2E1IS", "IPAS2LE1IS", "VMALLE1IS", "ALLE2IS", "ALLE3IS",
+ "VAE1IS", "VAE2IS", "VAE3IS", "ASIDE1IS", "VAAE1IS",
+ "ALLE1IS", "VALE1IS", "VALE2IS", "VALE3IS", "VMALLS12E1IS",
+ "VAALE1IS", "IPAS2E1", "IPAS2LE1", "VMALLE1", "ALLE2",
+ "ALLE3", "VAE1", "VAE2", "VAE3", "ASIDE1", "VAAE1",
+ "ALLE1", "VALE1", "VALE2", "VALE3", "VMALLS12E1", "VAALE1"
+];
+
+foreach I = TLBINames in {
+ defvar Info = !cast(I);
+ def : TLBIEntry {
+let Encoding{7} = 0;
+ }
+
+ def : TLBIEntry {
let Encoding{7} = 1;
let ExtraRequires = ["AArch64::FeatureXS"];
}
- if !eq(hasTLBIP, true) then {
-def : TLBIPEntry {
- let ExtraRequires = ["AArch64::FeatureD128"];
-}
-def : TLBIPEntry {
- let Encoding{7} = 1;
- let ExtraRequires = ["AArch64::FeatureD128"];
+
+ if !eq(Info.HasTLBIP, true) then {
+foreach nxs = [0, 1] in {
+ defvar VariantName = !if(nxs, !strconcat(I, "nXS"), I);
+ def : TLBIPEntry {
+let Encoding{7} = nxs;
+let Requires = ["AArch64::FeatureD128"];
+ }
}
}
}
-// hasTLBIP op1CRn CRm op2reguse
-defm : TLBI<"IPAS2E1IS",1, 0b100, 0b1000, 0b, 0b001, REG_REQUIRED>;
-defm : TLBI<"IPAS2LE1IS", 1, 0b100, 0b1000, 0b, 0b101, REG_REQUIRED>;
-defm : TLBI<"VMALLE1IS",0, 0b000, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
-defm : TLBI<"ALLE2IS", 0, 0b100, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
-defm : TLBI<"ALLE3IS", 0, 0b110, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
-defm : TLBI<"VAE1IS", 1, 0b000, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
-defm : TLBI<"VAE2IS", 1, 0b100, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
-defm : TLBI<"VAE3IS", 1, 0b110, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
-defm : TLBI<"ASIDE1IS", 0, 0b000, 0b1000, 0b0011, 0b010, REG_REQUIRED>;
-defm : TLBI<"VAAE1IS", 1, 0b000, 0b1000, 0b0011, 0b011, REG_REQUIRED>;
-defm : TLBI<"ALLE1IS", 0, 0b100, 0b1000, 0b0011, 0b100, REG_OPTIONAL>;
-defm : TLBI<"VALE1IS",
[llvm-branch-commits] [llvm] [AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (PR #187400)
@@ -903,128 +903,250 @@ multiclass TLBITableBase {
defm TLBI : TLBITableBase;
defm TLBIP : TLBITableBase;
-multiclass TLBI op1, bits<4> crn, bits<4>
crm,
- bits<3> op2, int reguse = REG_REQUIRED> {
- def : TLBIEntry;
- def : TLBIEntry {
+class TLBI op1, bits<4> crn,
+ bits<4> crm, bits<3> op2, int reguse = REG_REQUIRED> {
+ string Name = NAME;
+ bit HasTLBIP = hasTLBIP;
+ bits<3> Op1 = op1;
+ bits<4> CRn = crn;
+ bits<4> CRm = crm;
+ bits<3> Op2 = op2;
+ int RegUse = reguse;
+}
+
+// TLBI and TLBIP instructions encodings
+// hasTLBIP op1CRn CRm op2reguse
+def IPAS2E1IS: TLBI<1, 0b100, 0b1000, 0b, 0b001, REG_REQUIRED>;
+def IPAS2LE1IS : TLBI<1, 0b100, 0b1000, 0b, 0b101, REG_REQUIRED>;
+def VMALLE1IS: TLBI<0, 0b000, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
+def ALLE2IS : TLBI<0, 0b100, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
+def ALLE3IS : TLBI<0, 0b110, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
+def VAE1IS : TLBI<1, 0b000, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
+def VAE2IS : TLBI<1, 0b100, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
+def VAE3IS : TLBI<1, 0b110, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
+def ASIDE1IS : TLBI<0, 0b000, 0b1000, 0b0011, 0b010, REG_REQUIRED>;
+def VAAE1IS : TLBI<1, 0b000, 0b1000, 0b0011, 0b011, REG_REQUIRED>;
+def ALLE1IS : TLBI<0, 0b100, 0b1000, 0b0011, 0b100, REG_OPTIONAL>;
+def VALE1IS : TLBI<1, 0b000, 0b1000, 0b0011, 0b101, REG_REQUIRED>;
+def VALE2IS : TLBI<1, 0b100, 0b1000, 0b0011, 0b101, REG_REQUIRED>;
+def VALE3IS : TLBI<1, 0b110, 0b1000, 0b0011, 0b101, REG_REQUIRED>;
+def VMALLS12E1IS : TLBI<0, 0b100, 0b1000, 0b0011, 0b110, REG_OPTIONAL>;
+def VAALE1IS : TLBI<1, 0b000, 0b1000, 0b0011, 0b111, REG_REQUIRED>;
+def IPAS2E1 : TLBI<1, 0b100, 0b1000, 0b0100, 0b001, REG_REQUIRED>;
+def IPAS2LE1 : TLBI<1, 0b100, 0b1000, 0b0100, 0b101, REG_REQUIRED>;
+def VMALLE1 : TLBI<0, 0b000, 0b1000, 0b0111, 0b000, REG_NONE>;
+def ALLE2: TLBI<0, 0b100, 0b1000, 0b0111, 0b000, REG_NONE>;
+def ALLE3: TLBI<0, 0b110, 0b1000, 0b0111, 0b000, REG_NONE>;
+def VAE1 : TLBI<1, 0b000, 0b1000, 0b0111, 0b001, REG_REQUIRED>;
+def VAE2 : TLBI<1, 0b100, 0b1000, 0b0111, 0b001, REG_REQUIRED>;
+def VAE3 : TLBI<1, 0b110, 0b1000, 0b0111, 0b001, REG_REQUIRED>;
+def ASIDE1 : TLBI<0, 0b000, 0b1000, 0b0111, 0b010, REG_REQUIRED>;
+def VAAE1: TLBI<1, 0b000, 0b1000, 0b0111, 0b011, REG_REQUIRED>;
+def ALLE1: TLBI<0, 0b100, 0b1000, 0b0111, 0b100, REG_NONE>;
+def VALE1: TLBI<1, 0b000, 0b1000, 0b0111, 0b101, REG_REQUIRED>;
+def VALE2: TLBI<1, 0b100, 0b1000, 0b0111, 0b101, REG_REQUIRED>;
+def VALE3: TLBI<1, 0b110, 0b1000, 0b0111, 0b101, REG_REQUIRED>;
+def VMALLS12E1 : TLBI<0, 0b100, 0b1000, 0b0111, 0b110, REG_NONE>;
+def VAALE1 : TLBI<1, 0b000, 0b1000, 0b0111, 0b111, REG_REQUIRED>;
+
+defvar TLBINames = [
+ "IPAS2E1IS", "IPAS2LE1IS", "VMALLE1IS", "ALLE2IS", "ALLE3IS",
+ "VAE1IS", "VAE2IS", "VAE3IS", "ASIDE1IS", "VAAE1IS",
+ "ALLE1IS", "VALE1IS", "VALE2IS", "VALE3IS", "VMALLS12E1IS",
+ "VAALE1IS", "IPAS2E1", "IPAS2LE1", "VMALLE1", "ALLE2",
+ "ALLE3", "VAE1", "VAE2", "VAE3", "ASIDE1", "VAAE1",
+ "ALLE1", "VALE1", "VALE2", "VALE3", "VMALLS12E1", "VAALE1"
+];
+
+foreach I = TLBINames in {
+ defvar Info = !cast(I);
+ def : TLBIEntry {
+let Encoding{7} = 0;
+ }
+
+ def : TLBIEntry {
let Encoding{7} = 1;
let ExtraRequires = ["AArch64::FeatureXS"];
}
- if !eq(hasTLBIP, true) then {
-def : TLBIPEntry {
- let ExtraRequires = ["AArch64::FeatureD128"];
-}
-def : TLBIPEntry {
- let Encoding{7} = 1;
- let ExtraRequires = ["AArch64::FeatureD128"];
+
+ if !eq(Info.HasTLBIP, true) then {
+foreach nxs = [0, 1] in {
+ defvar VariantName = !if(nxs, !strconcat(I, "nXS"), I);
+ def : TLBIPEntry {
+let Encoding{7} = nxs;
+let Requires = ["AArch64::FeatureD128"];
+ }
}
}
}
-// hasTLBIP op1CRn CRm op2reguse
-defm : TLBI<"IPAS2E1IS",1, 0b100, 0b1000, 0b, 0b001, REG_REQUIRED>;
-defm : TLBI<"IPAS2LE1IS", 1, 0b100, 0b1000, 0b, 0b101, REG_REQUIRED>;
-defm : TLBI<"VMALLE1IS",0, 0b000, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
-defm : TLBI<"ALLE2IS", 0, 0b100, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
-defm : TLBI<"ALLE3IS", 0, 0b110, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
-defm : TLBI<"VAE1IS", 1, 0b000, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
-defm : TLBI<"VAE2IS", 1, 0b100, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
-defm : TLBI<"VAE3IS", 1, 0b110, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
-defm : TLBI<"ASIDE1IS", 0, 0b000, 0b1000, 0b0011, 0b010, REG_REQUIRED>;
-defm : TLBI<"VAAE1IS", 1, 0b000, 0b1000, 0b0011, 0b011, REG_REQUIRED>;
-defm : TLBI<"ALLE1IS", 0, 0b100, 0b1000, 0b0011, 0b100, REG_OPTIONAL>;
-defm : TLBI<"VALE1IS",
[llvm-branch-commits] [llvm] [AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (PR #187400)
@@ -903,128 +903,250 @@ multiclass TLBITableBase {
defm TLBI : TLBITableBase;
defm TLBIP : TLBITableBase;
-multiclass TLBI op1, bits<4> crn, bits<4>
crm,
- bits<3> op2, int reguse = REG_REQUIRED> {
- def : TLBIEntry;
- def : TLBIEntry {
+class TLBI op1, bits<4> crn,
+ bits<4> crm, bits<3> op2, int reguse = REG_REQUIRED> {
+ string Name = NAME;
+ bit HasTLBIP = hasTLBIP;
+ bits<3> Op1 = op1;
+ bits<4> CRn = crn;
+ bits<4> CRm = crm;
+ bits<3> Op2 = op2;
+ int RegUse = reguse;
+}
+
+// TLBI and TLBIP instructions encodings
+// hasTLBIP op1CRn CRm op2reguse
+def IPAS2E1IS: TLBI<1, 0b100, 0b1000, 0b, 0b001, REG_REQUIRED>;
+def IPAS2LE1IS : TLBI<1, 0b100, 0b1000, 0b, 0b101, REG_REQUIRED>;
+def VMALLE1IS: TLBI<0, 0b000, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
+def ALLE2IS : TLBI<0, 0b100, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
+def ALLE3IS : TLBI<0, 0b110, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
+def VAE1IS : TLBI<1, 0b000, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
+def VAE2IS : TLBI<1, 0b100, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
+def VAE3IS : TLBI<1, 0b110, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
+def ASIDE1IS : TLBI<0, 0b000, 0b1000, 0b0011, 0b010, REG_REQUIRED>;
+def VAAE1IS : TLBI<1, 0b000, 0b1000, 0b0011, 0b011, REG_REQUIRED>;
+def ALLE1IS : TLBI<0, 0b100, 0b1000, 0b0011, 0b100, REG_OPTIONAL>;
+def VALE1IS : TLBI<1, 0b000, 0b1000, 0b0011, 0b101, REG_REQUIRED>;
+def VALE2IS : TLBI<1, 0b100, 0b1000, 0b0011, 0b101, REG_REQUIRED>;
+def VALE3IS : TLBI<1, 0b110, 0b1000, 0b0011, 0b101, REG_REQUIRED>;
+def VMALLS12E1IS : TLBI<0, 0b100, 0b1000, 0b0011, 0b110, REG_OPTIONAL>;
+def VAALE1IS : TLBI<1, 0b000, 0b1000, 0b0011, 0b111, REG_REQUIRED>;
+def IPAS2E1 : TLBI<1, 0b100, 0b1000, 0b0100, 0b001, REG_REQUIRED>;
+def IPAS2LE1 : TLBI<1, 0b100, 0b1000, 0b0100, 0b101, REG_REQUIRED>;
+def VMALLE1 : TLBI<0, 0b000, 0b1000, 0b0111, 0b000, REG_NONE>;
+def ALLE2: TLBI<0, 0b100, 0b1000, 0b0111, 0b000, REG_NONE>;
+def ALLE3: TLBI<0, 0b110, 0b1000, 0b0111, 0b000, REG_NONE>;
+def VAE1 : TLBI<1, 0b000, 0b1000, 0b0111, 0b001, REG_REQUIRED>;
+def VAE2 : TLBI<1, 0b100, 0b1000, 0b0111, 0b001, REG_REQUIRED>;
+def VAE3 : TLBI<1, 0b110, 0b1000, 0b0111, 0b001, REG_REQUIRED>;
+def ASIDE1 : TLBI<0, 0b000, 0b1000, 0b0111, 0b010, REG_REQUIRED>;
+def VAAE1: TLBI<1, 0b000, 0b1000, 0b0111, 0b011, REG_REQUIRED>;
+def ALLE1: TLBI<0, 0b100, 0b1000, 0b0111, 0b100, REG_NONE>;
+def VALE1: TLBI<1, 0b000, 0b1000, 0b0111, 0b101, REG_REQUIRED>;
+def VALE2: TLBI<1, 0b100, 0b1000, 0b0111, 0b101, REG_REQUIRED>;
+def VALE3: TLBI<1, 0b110, 0b1000, 0b0111, 0b101, REG_REQUIRED>;
+def VMALLS12E1 : TLBI<0, 0b100, 0b1000, 0b0111, 0b110, REG_NONE>;
+def VAALE1 : TLBI<1, 0b000, 0b1000, 0b0111, 0b111, REG_REQUIRED>;
+
+defvar TLBINames = [
+ "IPAS2E1IS", "IPAS2LE1IS", "VMALLE1IS", "ALLE2IS", "ALLE3IS",
+ "VAE1IS", "VAE2IS", "VAE3IS", "ASIDE1IS", "VAAE1IS",
+ "ALLE1IS", "VALE1IS", "VALE2IS", "VALE3IS", "VMALLS12E1IS",
+ "VAALE1IS", "IPAS2E1", "IPAS2LE1", "VMALLE1", "ALLE2",
+ "ALLE3", "VAE1", "VAE2", "VAE3", "ASIDE1", "VAAE1",
+ "ALLE1", "VALE1", "VALE2", "VALE3", "VMALLS12E1", "VAALE1"
+];
+
+foreach I = TLBINames in {
+ defvar Info = !cast(I);
+ def : TLBIEntry {
+let Encoding{7} = 0;
+ }
+
+ def : TLBIEntry {
let Encoding{7} = 1;
let ExtraRequires = ["AArch64::FeatureXS"];
}
- if !eq(hasTLBIP, true) then {
-def : TLBIPEntry {
- let ExtraRequires = ["AArch64::FeatureD128"];
-}
-def : TLBIPEntry {
- let Encoding{7} = 1;
- let ExtraRequires = ["AArch64::FeatureD128"];
+
+ if !eq(Info.HasTLBIP, true) then {
+foreach nxs = [0, 1] in {
Lukacma wrote:
This foreach loop looks to complicated simple if check would be cleaner
https://github.com/llvm/llvm-project/pull/187400
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[llvm-branch-commits] [llvm] [AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (PR #187400)
@@ -903,128 +903,250 @@ multiclass TLBITableBase {
defm TLBI : TLBITableBase;
defm TLBIP : TLBITableBase;
-multiclass TLBI op1, bits<4> crn, bits<4>
crm,
- bits<3> op2, int reguse = REG_REQUIRED> {
- def : TLBIEntry;
- def : TLBIEntry {
+class TLBI op1, bits<4> crn,
+ bits<4> crm, bits<3> op2, int reguse = REG_REQUIRED> {
+ string Name = NAME;
+ bit HasTLBIP = hasTLBIP;
+ bits<3> Op1 = op1;
+ bits<4> CRn = crn;
+ bits<4> CRm = crm;
+ bits<3> Op2 = op2;
+ int RegUse = reguse;
+}
+
+// TLBI and TLBIP instructions encodings
+// hasTLBIP op1CRn CRm op2reguse
+def IPAS2E1IS: TLBI<1, 0b100, 0b1000, 0b, 0b001, REG_REQUIRED>;
+def IPAS2LE1IS : TLBI<1, 0b100, 0b1000, 0b, 0b101, REG_REQUIRED>;
+def VMALLE1IS: TLBI<0, 0b000, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
+def ALLE2IS : TLBI<0, 0b100, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
+def ALLE3IS : TLBI<0, 0b110, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
+def VAE1IS : TLBI<1, 0b000, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
+def VAE2IS : TLBI<1, 0b100, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
+def VAE3IS : TLBI<1, 0b110, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
+def ASIDE1IS : TLBI<0, 0b000, 0b1000, 0b0011, 0b010, REG_REQUIRED>;
+def VAAE1IS : TLBI<1, 0b000, 0b1000, 0b0011, 0b011, REG_REQUIRED>;
+def ALLE1IS : TLBI<0, 0b100, 0b1000, 0b0011, 0b100, REG_OPTIONAL>;
+def VALE1IS : TLBI<1, 0b000, 0b1000, 0b0011, 0b101, REG_REQUIRED>;
+def VALE2IS : TLBI<1, 0b100, 0b1000, 0b0011, 0b101, REG_REQUIRED>;
+def VALE3IS : TLBI<1, 0b110, 0b1000, 0b0011, 0b101, REG_REQUIRED>;
+def VMALLS12E1IS : TLBI<0, 0b100, 0b1000, 0b0011, 0b110, REG_OPTIONAL>;
+def VAALE1IS : TLBI<1, 0b000, 0b1000, 0b0011, 0b111, REG_REQUIRED>;
+def IPAS2E1 : TLBI<1, 0b100, 0b1000, 0b0100, 0b001, REG_REQUIRED>;
+def IPAS2LE1 : TLBI<1, 0b100, 0b1000, 0b0100, 0b101, REG_REQUIRED>;
+def VMALLE1 : TLBI<0, 0b000, 0b1000, 0b0111, 0b000, REG_NONE>;
+def ALLE2: TLBI<0, 0b100, 0b1000, 0b0111, 0b000, REG_NONE>;
+def ALLE3: TLBI<0, 0b110, 0b1000, 0b0111, 0b000, REG_NONE>;
+def VAE1 : TLBI<1, 0b000, 0b1000, 0b0111, 0b001, REG_REQUIRED>;
+def VAE2 : TLBI<1, 0b100, 0b1000, 0b0111, 0b001, REG_REQUIRED>;
+def VAE3 : TLBI<1, 0b110, 0b1000, 0b0111, 0b001, REG_REQUIRED>;
+def ASIDE1 : TLBI<0, 0b000, 0b1000, 0b0111, 0b010, REG_REQUIRED>;
+def VAAE1: TLBI<1, 0b000, 0b1000, 0b0111, 0b011, REG_REQUIRED>;
+def ALLE1: TLBI<0, 0b100, 0b1000, 0b0111, 0b100, REG_NONE>;
+def VALE1: TLBI<1, 0b000, 0b1000, 0b0111, 0b101, REG_REQUIRED>;
+def VALE2: TLBI<1, 0b100, 0b1000, 0b0111, 0b101, REG_REQUIRED>;
+def VALE3: TLBI<1, 0b110, 0b1000, 0b0111, 0b101, REG_REQUIRED>;
+def VMALLS12E1 : TLBI<0, 0b100, 0b1000, 0b0111, 0b110, REG_NONE>;
+def VAALE1 : TLBI<1, 0b000, 0b1000, 0b0111, 0b111, REG_REQUIRED>;
+
+defvar TLBINames = [
Lukacma wrote:
I wonder if it would be enough to just inline these lists, instead of tying
them to variable. With proper formatting it doesn't have to look horrible.
Maybe
https://github.com/llvm/llvm-project/pull/187400
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[llvm-branch-commits] [llvm] [AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (PR #187400)
@@ -903,128 +903,250 @@ multiclass TLBITableBase {
defm TLBI : TLBITableBase;
defm TLBIP : TLBITableBase;
-multiclass TLBI op1, bits<4> crn, bits<4>
crm,
- bits<3> op2, int reguse = REG_REQUIRED> {
- def : TLBIEntry;
- def : TLBIEntry {
+class TLBI op1, bits<4> crn,
Lukacma wrote:
This is unnecessary and leads to you having to duplicate register name twice.
Firstly, when defining the record, the 2nd time when creating the iteration. I
would implement it as just a nested list with comments on top to explain what
each field does.
https://github.com/llvm/llvm-project/pull/187400
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[llvm-branch-commits] [llvm] [AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (PR #187400)
@@ -903,128 +903,250 @@ multiclass TLBITableBase {
defm TLBI : TLBITableBase;
defm TLBIP : TLBITableBase;
-multiclass TLBI op1, bits<4> crn, bits<4>
crm,
- bits<3> op2, int reguse = REG_REQUIRED> {
- def : TLBIEntry;
- def : TLBIEntry {
+class TLBI op1, bits<4> crn,
+ bits<4> crm, bits<3> op2, int reguse = REG_REQUIRED> {
+ string Name = NAME;
+ bit HasTLBIP = hasTLBIP;
+ bits<3> Op1 = op1;
+ bits<4> CRn = crn;
+ bits<4> CRm = crm;
+ bits<3> Op2 = op2;
+ int RegUse = reguse;
+}
+
+// TLBI and TLBIP instructions encodings
+// hasTLBIP op1CRn CRm op2reguse
+def IPAS2E1IS: TLBI<1, 0b100, 0b1000, 0b, 0b001, REG_REQUIRED>;
+def IPAS2LE1IS : TLBI<1, 0b100, 0b1000, 0b, 0b101, REG_REQUIRED>;
+def VMALLE1IS: TLBI<0, 0b000, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
+def ALLE2IS : TLBI<0, 0b100, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
+def ALLE3IS : TLBI<0, 0b110, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
+def VAE1IS : TLBI<1, 0b000, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
+def VAE2IS : TLBI<1, 0b100, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
+def VAE3IS : TLBI<1, 0b110, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
+def ASIDE1IS : TLBI<0, 0b000, 0b1000, 0b0011, 0b010, REG_REQUIRED>;
+def VAAE1IS : TLBI<1, 0b000, 0b1000, 0b0011, 0b011, REG_REQUIRED>;
+def ALLE1IS : TLBI<0, 0b100, 0b1000, 0b0011, 0b100, REG_OPTIONAL>;
+def VALE1IS : TLBI<1, 0b000, 0b1000, 0b0011, 0b101, REG_REQUIRED>;
+def VALE2IS : TLBI<1, 0b100, 0b1000, 0b0011, 0b101, REG_REQUIRED>;
+def VALE3IS : TLBI<1, 0b110, 0b1000, 0b0011, 0b101, REG_REQUIRED>;
+def VMALLS12E1IS : TLBI<0, 0b100, 0b1000, 0b0011, 0b110, REG_OPTIONAL>;
+def VAALE1IS : TLBI<1, 0b000, 0b1000, 0b0011, 0b111, REG_REQUIRED>;
+def IPAS2E1 : TLBI<1, 0b100, 0b1000, 0b0100, 0b001, REG_REQUIRED>;
+def IPAS2LE1 : TLBI<1, 0b100, 0b1000, 0b0100, 0b101, REG_REQUIRED>;
+def VMALLE1 : TLBI<0, 0b000, 0b1000, 0b0111, 0b000, REG_NONE>;
+def ALLE2: TLBI<0, 0b100, 0b1000, 0b0111, 0b000, REG_NONE>;
+def ALLE3: TLBI<0, 0b110, 0b1000, 0b0111, 0b000, REG_NONE>;
+def VAE1 : TLBI<1, 0b000, 0b1000, 0b0111, 0b001, REG_REQUIRED>;
+def VAE2 : TLBI<1, 0b100, 0b1000, 0b0111, 0b001, REG_REQUIRED>;
+def VAE3 : TLBI<1, 0b110, 0b1000, 0b0111, 0b001, REG_REQUIRED>;
+def ASIDE1 : TLBI<0, 0b000, 0b1000, 0b0111, 0b010, REG_REQUIRED>;
+def VAAE1: TLBI<1, 0b000, 0b1000, 0b0111, 0b011, REG_REQUIRED>;
+def ALLE1: TLBI<0, 0b100, 0b1000, 0b0111, 0b100, REG_NONE>;
+def VALE1: TLBI<1, 0b000, 0b1000, 0b0111, 0b101, REG_REQUIRED>;
+def VALE2: TLBI<1, 0b100, 0b1000, 0b0111, 0b101, REG_REQUIRED>;
+def VALE3: TLBI<1, 0b110, 0b1000, 0b0111, 0b101, REG_REQUIRED>;
+def VMALLS12E1 : TLBI<0, 0b100, 0b1000, 0b0111, 0b110, REG_NONE>;
+def VAALE1 : TLBI<1, 0b000, 0b1000, 0b0111, 0b111, REG_REQUIRED>;
+
+defvar TLBINames = [
+ "IPAS2E1IS", "IPAS2LE1IS", "VMALLE1IS", "ALLE2IS", "ALLE3IS",
+ "VAE1IS", "VAE2IS", "VAE3IS", "ASIDE1IS", "VAAE1IS",
+ "ALLE1IS", "VALE1IS", "VALE2IS", "VALE3IS", "VMALLS12E1IS",
+ "VAALE1IS", "IPAS2E1", "IPAS2LE1", "VMALLE1", "ALLE2",
+ "ALLE3", "VAE1", "VAE2", "VAE3", "ASIDE1", "VAAE1",
+ "ALLE1", "VALE1", "VALE2", "VALE3", "VMALLS12E1", "VAALE1"
+];
+
+foreach I = TLBINames in {
+ defvar Info = !cast(I);
+ def : TLBIEntry {
+let Encoding{7} = 0;
+ }
+
+ def : TLBIEntry {
let Encoding{7} = 1;
let ExtraRequires = ["AArch64::FeatureXS"];
}
- if !eq(hasTLBIP, true) then {
-def : TLBIPEntry {
- let ExtraRequires = ["AArch64::FeatureD128"];
-}
-def : TLBIPEntry {
- let Encoding{7} = 1;
- let ExtraRequires = ["AArch64::FeatureD128"];
+
+ if !eq(Info.HasTLBIP, true) then {
+foreach nxs = [0, 1] in {
+ defvar VariantName = !if(nxs, !strconcat(I, "nXS"), I);
+ def : TLBIPEntry {
+let Encoding{7} = nxs;
+let Requires = ["AArch64::FeatureD128"];
+ }
}
}
}
-// hasTLBIP op1CRn CRm op2reguse
-defm : TLBI<"IPAS2E1IS",1, 0b100, 0b1000, 0b, 0b001, REG_REQUIRED>;
-defm : TLBI<"IPAS2LE1IS", 1, 0b100, 0b1000, 0b, 0b101, REG_REQUIRED>;
-defm : TLBI<"VMALLE1IS",0, 0b000, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
-defm : TLBI<"ALLE2IS", 0, 0b100, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
-defm : TLBI<"ALLE3IS", 0, 0b110, 0b1000, 0b0011, 0b000, REG_OPTIONAL>;
-defm : TLBI<"VAE1IS", 1, 0b000, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
-defm : TLBI<"VAE2IS", 1, 0b100, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
-defm : TLBI<"VAE3IS", 1, 0b110, 0b1000, 0b0011, 0b001, REG_REQUIRED>;
-defm : TLBI<"ASIDE1IS", 0, 0b000, 0b1000, 0b0011, 0b010, REG_REQUIRED>;
-defm : TLBI<"VAAE1IS", 1, 0b000, 0b1000, 0b0011, 0b011, REG_REQUIRED>;
-defm : TLBI<"ALLE1IS", 0, 0b100, 0b1000, 0b0011, 0b100, REG_OPTIONAL>;
-defm : TLBI<"VALE1IS",
[llvm-branch-commits] [llvm] [AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (PR #187400)
https://github.com/Lukacma edited https://github.com/llvm/llvm-project/pull/187400 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (PR #187400)
https://github.com/Lukacma commented: I have noticed multiple correctness issues with this implementation, so if you could please go through the tlbi and tlbip table again and double check the feature guards, if tlbip variant exists and if nxs variant exists, that would be great https://github.com/llvm/llvm-project/pull/187400 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (PR #187400)
github-actions[bot] wrote: # :penguin: Linux x64 Test Results * 171547 tests passed * 3057 tests skipped * 1 test failed ## Failed Tests (click on a test name to see its output) ### lldb-api lldb-api.functionalities/data-formatter/data-formatter-stl/generic/list/TestDataFormatterGenericList.py ``` Script: -- /usr/bin/python3 /home/gha/actions-runner/_work/llvm-project/llvm-project/lldb/test/API/dotest.py -u CXXFLAGS -u CFLAGS --env LLVM_LIBS_DIR=/home/gha/actions-runner/_work/llvm-project/llvm-project/build/./lib --env LLVM_INCLUDE_DIR=/home/gha/actions-runner/_work/llvm-project/llvm-project/build/include --env LLVM_TOOLS_DIR=/home/gha/actions-runner/_work/llvm-project/llvm-project/build/./bin --libcxx-include-dir /home/gha/actions-runner/_work/llvm-project/llvm-project/build/include/c++/v1 --libcxx-include-target-dir /home/gha/actions-runner/_work/llvm-project/llvm-project/build/include/x86_64-unknown-linux-gnu/c++/v1 --libcxx-library-dir /home/gha/actions-runner/_work/llvm-project/llvm-project/build/./lib/x86_64-unknown-linux-gnu --arch x86_64 --build-dir /home/gha/actions-runner/_work/llvm-project/llvm-project/build/lldb-test-build.noindex --lldb-module-cache-dir /home/gha/actions-runner/_work/llvm-project/llvm-project/build/lldb-test-build.noindex/module-cache-lldb/lldb-api --clang-module-cache-dir /home/gha/actions-runner/_work/llvm-project/llvm-project/build/lldb-test-build.noindex/module-cache-clang/lldb-api --executable /home/gha/actions-runner/_work/llvm-project/llvm-project/build/./bin/lldb --compiler /home/gha/actions-runner/_work/llvm-project/llvm-project/build/./bin/clang --dsymutil /home/gha/actions-runner/_work/llvm-project/llvm-project/build/./bin/dsymutil --make /usr/bin/gmake --llvm-tools-dir /home/gha/actions-runner/_work/llvm-project/llvm-project/build/./bin --lldb-obj-root /home/gha/actions-runner/_work/llvm-project/llvm-project/build/tools/lldb --lldb-libs-dir /home/gha/actions-runner/_work/llvm-project/llvm-project/build/./lib --cmake-build-type Release /home/gha/actions-runner/_work/llvm-project/llvm-project/lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/list -p TestDataFormatterGenericList.py -- Exit Code: 1 Command Output (stdout): -- lldb version 23.0.0git (https://github.com/llvm/llvm-project revision 063da4a104ca7ba2c14894d5173bd170f016d2c5) clang revision 063da4a104ca7ba2c14894d5173bd170f016d2c5 llvm revision 063da4a104ca7ba2c14894d5173bd170f016d2c5 Skipping the following test categories: msvcstl, dsym, pdb, gmodules, debugserver, objc -- Command Output (stderr): -- UNSUPPORTED: LLDB (/home/gha/actions-runner/_work/llvm-project/llvm-project/build/bin/clang-x86_64) :: test_ptr_and_ref_libcpp_dsym (TestDataFormatterGenericList.GenericListDataFormatterTestCase.test_ptr_and_ref_libcpp_dsym) (test case does not fall in any category of interest for this run) PASS: LLDB (/home/gha/actions-runner/_work/llvm-project/llvm-project/build/bin/clang-x86_64) :: test_ptr_and_ref_libcpp_dwarf (TestDataFormatterGenericList.GenericListDataFormatterTestCase.test_ptr_and_ref_libcpp_dwarf) PASS: LLDB (/home/gha/actions-runner/_work/llvm-project/llvm-project/build/bin/clang-x86_64) :: test_ptr_and_ref_libcpp_dwo (TestDataFormatterGenericList.GenericListDataFormatterTestCase.test_ptr_and_ref_libcpp_dwo) UNSUPPORTED: LLDB (/home/gha/actions-runner/_work/llvm-project/llvm-project/build/bin/clang-x86_64) :: test_ptr_and_ref_libcpp_pdb (TestDataFormatterGenericList.GenericListDataFormatterTestCase.test_ptr_and_ref_libcpp_pdb) (test case does not fall in any category of interest for this run) UNSUPPORTED: LLDB (/home/gha/actions-runner/_work/llvm-project/llvm-project/build/bin/clang-x86_64) :: test_ptr_and_ref_libstdcpp_dsym (TestDataFormatterGenericList.GenericListDataFormatterTestCase.test_ptr_and_ref_libstdcpp_dsym) (test case does not fall in any category of interest for this run) PASS: LLDB (/home/gha/actions-runner/_work/llvm-project/llvm-project/build/bin/clang-x86_64) :: test_ptr_and_ref_libstdcpp_dwarf (TestDataFormatterGenericList.GenericListDataFormatterTestCase.test_ptr_and_ref_libstdcpp_dwarf) PASS: LLDB (/home/gha/actions-runner/_work/llvm-project/llvm-project/build/bin/clang-x86_64) :: test_ptr_and_ref_libstdcpp_dwo (TestDataFormatterGenericList.GenericListDataFormatterTestCase.test_ptr_and_ref_libstdcpp_dwo) UNSUPPORTED: LLDB (/home/gha/actions-runner/_work/llvm-project/llvm-project/build/bin/clang-x86_64) :: test_ptr_and_ref_libstdcpp_pdb (TestDataFormatterGenericList.GenericListDataFormatterTestCase.test_ptr_and_ref_libstdcpp_pdb) (test case does not fall in any category of interest for this run) UNSUPPORTED: LLDB (/home/gha/actions-runner/_work/llvm-project/llvm-project/build/bin/clang-x86_64) :: test_ptr_and_ref_msvcstl_dsym (TestDataFormatterGenericList.GenericListDataFormatterTestCase.test_ptr_and_ref_msvcstl_dsym) (test case does not fall in any category of interest for
[llvm-branch-commits] [llvm] [AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (PR #187400)
https://github.com/jthackray updated
https://github.com/llvm/llvm-project/pull/187400
>From 7a74c1de4e939ad8097341da35f689cc4be77edf Mon Sep 17 00:00:00 2001
From: Jonathan Thackray
Date: Wed, 18 Mar 2026 20:54:50 +
Subject: [PATCH 1/3] [AArch64][llvm] Separate TLBI-only feature gating from
TLBIP aliases
Refactor the TLBI system operand definitions so that TLBI and TLBIP
records are emitted through separate helper multiclasses, whilst keeping
the table layout readable.
The feature-scoped wrappers now apply FeatureTLB_RMI, FeatureRME, and
FeatureTLBIW only to TLBI records (it was previously incorrectly also
applied to TLBIP instructions), while TLBIP aliases remain gated only
by FeatureD128, including their nXS forms.
Update testcases accordingly.
---
.../Target/AArch64/AArch64SystemOperands.td | 178 ++
llvm/test/MC/AArch64/armv9a-tlbip.s | 17 +-
2 files changed, 111 insertions(+), 84 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
index 257a4958e8305..d914b253c5358 100644
--- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
+++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
@@ -903,24 +903,54 @@ multiclass TLBITableBase {
defm TLBI : TLBITableBase;
defm TLBIP : TLBITableBase;
-multiclass TLBI op1, bits<4> crn, bits<4>
crm,
- bits<3> op2, int reguse = REG_REQUIRED> {
- def : TLBIEntry;
- def : TLBIEntry {
-let Encoding{7} = 1;
-let ExtraRequires = ["AArch64::FeatureXS"];
- }
- if !eq(hasTLBIP, true) then {
-def : TLBIPEntry {
- let ExtraRequires = ["AArch64::FeatureD128"];
+multiclass TLBI_Base op1, bits<4> crn, bits<4> crm,
+ bits<3> op2, int reguse = REG_REQUIRED,
+ list extra_requires = []> {
+ foreach nxs = [0, 1] in {
+defvar VariantName = !if(nxs, !strconcat(name, "nXS"), name);
+defvar VariantRequires = !if(nxs,
+ extra_requires # ["AArch64::FeatureXS"],
+ extra_requires);
+def : TLBIEntry {
+ let Encoding{7} = nxs;
+ let ExtraRequires = VariantRequires;
}
-def : TLBIPEntry {
- let Encoding{7} = 1;
- let ExtraRequires = ["AArch64::FeatureD128"];
+ }
+}
+
+multiclass TLBIP_Base op1, bits<4> crn, bits<4> crm,
+ bits<3> op2, int reguse = REG_REQUIRED,
+ list extra_requires = ["AArch64::FeatureD128"]> {
+ foreach nxs = [0, 1] in {
+// TLBIP instructions aren't gated by FeatureXS like TLBI ones
+defvar VariantName = !if(nxs, !strconcat(name, "nXS"), name);
+def : TLBIPEntry {
+ let Encoding{7} = nxs;
+ let ExtraRequires = extra_requires;
}
}
}
+multiclass TLBI op1, bits<4> crn,
+bits<4> crm, bits<3> op2, int reguse = REG_REQUIRED> {
+ defm : TLBI_Base;
+ if !eq(hasTLBIP, true) then {
+defm : TLBIP_Base;
+ }
+}
+
+multiclass TLBI_RMI op1, bits<4> crn,
+bits<4> crm, bits<3> op2, int reguse = REG_REQUIRED> {
+ let Requires = ["AArch64::FeatureTLB_RMI"] in {
+defm : TLBI_Base;
+ }
+ // TLBIP instructions aren't gated by FeatureTLB_RMI
+ if !eq(hasTLBIP, true) then {
+defm : TLBIP_Base;
+ }
+}
+
+// TLBI and TLBIP instructions encodings
// hasTLBIP op1CRn CRm op2reguse
defm : TLBI<"IPAS2E1IS",1, 0b100, 0b1000, 0b, 0b001, REG_REQUIRED>;
defm : TLBI<"IPAS2LE1IS", 1, 0b100, 0b1000, 0b, 0b101, REG_REQUIRED>;
@@ -955,76 +985,74 @@ defm : TLBI<"VALE3",1, 0b110, 0b1000, 0b0111,
0b101, REG_REQUIRED>;
defm : TLBI<"VMALLS12E1", 0, 0b100, 0b1000, 0b0111, 0b110, REG_NONE>;
defm : TLBI<"VAALE1", 1, 0b000, 0b1000, 0b0111, 0b111, REG_REQUIRED>;
-// Armv8.4-A Translation Lookaside Buffer Instructions (TLBI)
-let Requires = ["AArch64::FeatureTLB_RMI"] in {
+// Armv8.4-A Translation Lookaside Buffer Instructions (TLBI and TLBIP)
// Armv8.4-A Outer Sharable TLB Maintenance instructions:
-// hasTLBIP op1CRn CRm op2reguse
-defm : TLBI<"VMALLE1OS",0, 0b000, 0b1000, 0b0001, 0b000, REG_OPTIONAL>;
-defm : TLBI<"VAE1OS", 1, 0b000, 0b1000, 0b0001, 0b001, REG_REQUIRED>;
-defm : TLBI<"ASIDE1OS", 0, 0b000, 0b1000, 0b0001, 0b010, REG_REQUIRED>;
-defm : TLBI<"VAAE1OS", 1, 0b000, 0b1000, 0b0001, 0b011, REG_REQUIRED>;
-defm : TLBI<"VALE1OS", 1, 0b000, 0b1000, 0b0001, 0b101, REG_REQUIRED>;
-defm : TLBI<"VAALE1OS", 1, 0b000, 0b1000, 0b0001, 0b111, REG_REQUIRED>;
-defm : TLBI<"IPAS2E1OS",1, 0b100, 0b1000, 0b0100, 0b000, REG_REQUIRED>;
-defm : TLBI<"IPAS2LE1OS", 1, 0b100, 0b1000, 0b0100, 0b100, REG_REQUIRED>;
-defm : TLBI<"VAE2OS", 1, 0b100, 0b1000, 0b0001, 0b001, REG_REQUIRED>;
-defm : TLBI<"VALE2OS", 1, 0b100, 0b1000, 0b0001, 0b101, REG_REQUIRED>;
-defm : TLBI<"VMALLS12E1OS", 0, 0b100, 0b1000, 0b0001, 0b110, REG_OPTIONAL>;
-defm : TLBI<"VAE3OS", 1,
[llvm-branch-commits] [llvm] [AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (PR #187400)
https://github.com/jthackray updated
https://github.com/llvm/llvm-project/pull/187400
>From 7a74c1de4e939ad8097341da35f689cc4be77edf Mon Sep 17 00:00:00 2001
From: Jonathan Thackray
Date: Wed, 18 Mar 2026 20:54:50 +
Subject: [PATCH 1/3] [AArch64][llvm] Separate TLBI-only feature gating from
TLBIP aliases
Refactor the TLBI system operand definitions so that TLBI and TLBIP
records are emitted through separate helper multiclasses, whilst keeping
the table layout readable.
The feature-scoped wrappers now apply FeatureTLB_RMI, FeatureRME, and
FeatureTLBIW only to TLBI records (it was previously incorrectly also
applied to TLBIP instructions), while TLBIP aliases remain gated only
by FeatureD128, including their nXS forms.
Update testcases accordingly.
---
.../Target/AArch64/AArch64SystemOperands.td | 178 ++
llvm/test/MC/AArch64/armv9a-tlbip.s | 17 +-
2 files changed, 111 insertions(+), 84 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
index 257a4958e8305..d914b253c5358 100644
--- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
+++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
@@ -903,24 +903,54 @@ multiclass TLBITableBase {
defm TLBI : TLBITableBase;
defm TLBIP : TLBITableBase;
-multiclass TLBI op1, bits<4> crn, bits<4>
crm,
- bits<3> op2, int reguse = REG_REQUIRED> {
- def : TLBIEntry;
- def : TLBIEntry {
-let Encoding{7} = 1;
-let ExtraRequires = ["AArch64::FeatureXS"];
- }
- if !eq(hasTLBIP, true) then {
-def : TLBIPEntry {
- let ExtraRequires = ["AArch64::FeatureD128"];
+multiclass TLBI_Base op1, bits<4> crn, bits<4> crm,
+ bits<3> op2, int reguse = REG_REQUIRED,
+ list extra_requires = []> {
+ foreach nxs = [0, 1] in {
+defvar VariantName = !if(nxs, !strconcat(name, "nXS"), name);
+defvar VariantRequires = !if(nxs,
+ extra_requires # ["AArch64::FeatureXS"],
+ extra_requires);
+def : TLBIEntry {
+ let Encoding{7} = nxs;
+ let ExtraRequires = VariantRequires;
}
-def : TLBIPEntry {
- let Encoding{7} = 1;
- let ExtraRequires = ["AArch64::FeatureD128"];
+ }
+}
+
+multiclass TLBIP_Base op1, bits<4> crn, bits<4> crm,
+ bits<3> op2, int reguse = REG_REQUIRED,
+ list extra_requires = ["AArch64::FeatureD128"]> {
+ foreach nxs = [0, 1] in {
+// TLBIP instructions aren't gated by FeatureXS like TLBI ones
+defvar VariantName = !if(nxs, !strconcat(name, "nXS"), name);
+def : TLBIPEntry {
+ let Encoding{7} = nxs;
+ let ExtraRequires = extra_requires;
}
}
}
+multiclass TLBI op1, bits<4> crn,
+bits<4> crm, bits<3> op2, int reguse = REG_REQUIRED> {
+ defm : TLBI_Base;
+ if !eq(hasTLBIP, true) then {
+defm : TLBIP_Base;
+ }
+}
+
+multiclass TLBI_RMI op1, bits<4> crn,
+bits<4> crm, bits<3> op2, int reguse = REG_REQUIRED> {
+ let Requires = ["AArch64::FeatureTLB_RMI"] in {
+defm : TLBI_Base;
+ }
+ // TLBIP instructions aren't gated by FeatureTLB_RMI
+ if !eq(hasTLBIP, true) then {
+defm : TLBIP_Base;
+ }
+}
+
+// TLBI and TLBIP instructions encodings
// hasTLBIP op1CRn CRm op2reguse
defm : TLBI<"IPAS2E1IS",1, 0b100, 0b1000, 0b, 0b001, REG_REQUIRED>;
defm : TLBI<"IPAS2LE1IS", 1, 0b100, 0b1000, 0b, 0b101, REG_REQUIRED>;
@@ -955,76 +985,74 @@ defm : TLBI<"VALE3",1, 0b110, 0b1000, 0b0111,
0b101, REG_REQUIRED>;
defm : TLBI<"VMALLS12E1", 0, 0b100, 0b1000, 0b0111, 0b110, REG_NONE>;
defm : TLBI<"VAALE1", 1, 0b000, 0b1000, 0b0111, 0b111, REG_REQUIRED>;
-// Armv8.4-A Translation Lookaside Buffer Instructions (TLBI)
-let Requires = ["AArch64::FeatureTLB_RMI"] in {
+// Armv8.4-A Translation Lookaside Buffer Instructions (TLBI and TLBIP)
// Armv8.4-A Outer Sharable TLB Maintenance instructions:
-// hasTLBIP op1CRn CRm op2reguse
-defm : TLBI<"VMALLE1OS",0, 0b000, 0b1000, 0b0001, 0b000, REG_OPTIONAL>;
-defm : TLBI<"VAE1OS", 1, 0b000, 0b1000, 0b0001, 0b001, REG_REQUIRED>;
-defm : TLBI<"ASIDE1OS", 0, 0b000, 0b1000, 0b0001, 0b010, REG_REQUIRED>;
-defm : TLBI<"VAAE1OS", 1, 0b000, 0b1000, 0b0001, 0b011, REG_REQUIRED>;
-defm : TLBI<"VALE1OS", 1, 0b000, 0b1000, 0b0001, 0b101, REG_REQUIRED>;
-defm : TLBI<"VAALE1OS", 1, 0b000, 0b1000, 0b0001, 0b111, REG_REQUIRED>;
-defm : TLBI<"IPAS2E1OS",1, 0b100, 0b1000, 0b0100, 0b000, REG_REQUIRED>;
-defm : TLBI<"IPAS2LE1OS", 1, 0b100, 0b1000, 0b0100, 0b100, REG_REQUIRED>;
-defm : TLBI<"VAE2OS", 1, 0b100, 0b1000, 0b0001, 0b001, REG_REQUIRED>;
-defm : TLBI<"VALE2OS", 1, 0b100, 0b1000, 0b0001, 0b101, REG_REQUIRED>;
-defm : TLBI<"VMALLS12E1OS", 0, 0b100, 0b1000, 0b0001, 0b110, REG_OPTIONAL>;
-defm : TLBI<"VAE3OS", 1,
[llvm-branch-commits] [llvm] [AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (PR #187400)
https://github.com/jthackray updated
https://github.com/llvm/llvm-project/pull/187400
>From 141a98745e5eae25fb1e5748a3b25d1cb79418bb Mon Sep 17 00:00:00 2001
From: Jonathan Thackray
Date: Wed, 18 Mar 2026 20:54:50 +
Subject: [PATCH 1/2] [AArch64][llvm] Separate TLBI-only feature gating from
TLBIP aliases
Refactor the TLBI system operand definitions so that TLBI and TLBIP
records are emitted through separate helper multiclasses, whilst keeping
the table layout readable.
The feature-scoped wrappers now apply FeatureTLB_RMI, FeatureRME, and
FeatureTLBIW only to TLBI records (it was previously incorrectly also
applied to TLBIP instructions), while TLBIP aliases remain gated only
by FeatureD128, including their nXS forms.
Update testcases accordingly.
---
.../Target/AArch64/AArch64SystemOperands.td | 178 ++
llvm/test/MC/AArch64/armv9a-tlbip.s | 17 +-
2 files changed, 111 insertions(+), 84 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
index 257a4958e8305..d914b253c5358 100644
--- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
+++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
@@ -903,24 +903,54 @@ multiclass TLBITableBase {
defm TLBI : TLBITableBase;
defm TLBIP : TLBITableBase;
-multiclass TLBI op1, bits<4> crn, bits<4>
crm,
- bits<3> op2, int reguse = REG_REQUIRED> {
- def : TLBIEntry;
- def : TLBIEntry {
-let Encoding{7} = 1;
-let ExtraRequires = ["AArch64::FeatureXS"];
- }
- if !eq(hasTLBIP, true) then {
-def : TLBIPEntry {
- let ExtraRequires = ["AArch64::FeatureD128"];
+multiclass TLBI_Base op1, bits<4> crn, bits<4> crm,
+ bits<3> op2, int reguse = REG_REQUIRED,
+ list extra_requires = []> {
+ foreach nxs = [0, 1] in {
+defvar VariantName = !if(nxs, !strconcat(name, "nXS"), name);
+defvar VariantRequires = !if(nxs,
+ extra_requires # ["AArch64::FeatureXS"],
+ extra_requires);
+def : TLBIEntry {
+ let Encoding{7} = nxs;
+ let ExtraRequires = VariantRequires;
}
-def : TLBIPEntry {
- let Encoding{7} = 1;
- let ExtraRequires = ["AArch64::FeatureD128"];
+ }
+}
+
+multiclass TLBIP_Base op1, bits<4> crn, bits<4> crm,
+ bits<3> op2, int reguse = REG_REQUIRED,
+ list extra_requires = ["AArch64::FeatureD128"]> {
+ foreach nxs = [0, 1] in {
+// TLBIP instructions aren't gated by FeatureXS like TLBI ones
+defvar VariantName = !if(nxs, !strconcat(name, "nXS"), name);
+def : TLBIPEntry {
+ let Encoding{7} = nxs;
+ let ExtraRequires = extra_requires;
}
}
}
+multiclass TLBI op1, bits<4> crn,
+bits<4> crm, bits<3> op2, int reguse = REG_REQUIRED> {
+ defm : TLBI_Base;
+ if !eq(hasTLBIP, true) then {
+defm : TLBIP_Base;
+ }
+}
+
+multiclass TLBI_RMI op1, bits<4> crn,
+bits<4> crm, bits<3> op2, int reguse = REG_REQUIRED> {
+ let Requires = ["AArch64::FeatureTLB_RMI"] in {
+defm : TLBI_Base;
+ }
+ // TLBIP instructions aren't gated by FeatureTLB_RMI
+ if !eq(hasTLBIP, true) then {
+defm : TLBIP_Base;
+ }
+}
+
+// TLBI and TLBIP instructions encodings
// hasTLBIP op1CRn CRm op2reguse
defm : TLBI<"IPAS2E1IS",1, 0b100, 0b1000, 0b, 0b001, REG_REQUIRED>;
defm : TLBI<"IPAS2LE1IS", 1, 0b100, 0b1000, 0b, 0b101, REG_REQUIRED>;
@@ -955,76 +985,74 @@ defm : TLBI<"VALE3",1, 0b110, 0b1000, 0b0111,
0b101, REG_REQUIRED>;
defm : TLBI<"VMALLS12E1", 0, 0b100, 0b1000, 0b0111, 0b110, REG_NONE>;
defm : TLBI<"VAALE1", 1, 0b000, 0b1000, 0b0111, 0b111, REG_REQUIRED>;
-// Armv8.4-A Translation Lookaside Buffer Instructions (TLBI)
-let Requires = ["AArch64::FeatureTLB_RMI"] in {
+// Armv8.4-A Translation Lookaside Buffer Instructions (TLBI and TLBIP)
// Armv8.4-A Outer Sharable TLB Maintenance instructions:
-// hasTLBIP op1CRn CRm op2reguse
-defm : TLBI<"VMALLE1OS",0, 0b000, 0b1000, 0b0001, 0b000, REG_OPTIONAL>;
-defm : TLBI<"VAE1OS", 1, 0b000, 0b1000, 0b0001, 0b001, REG_REQUIRED>;
-defm : TLBI<"ASIDE1OS", 0, 0b000, 0b1000, 0b0001, 0b010, REG_REQUIRED>;
-defm : TLBI<"VAAE1OS", 1, 0b000, 0b1000, 0b0001, 0b011, REG_REQUIRED>;
-defm : TLBI<"VALE1OS", 1, 0b000, 0b1000, 0b0001, 0b101, REG_REQUIRED>;
-defm : TLBI<"VAALE1OS", 1, 0b000, 0b1000, 0b0001, 0b111, REG_REQUIRED>;
-defm : TLBI<"IPAS2E1OS",1, 0b100, 0b1000, 0b0100, 0b000, REG_REQUIRED>;
-defm : TLBI<"IPAS2LE1OS", 1, 0b100, 0b1000, 0b0100, 0b100, REG_REQUIRED>;
-defm : TLBI<"VAE2OS", 1, 0b100, 0b1000, 0b0001, 0b001, REG_REQUIRED>;
-defm : TLBI<"VALE2OS", 1, 0b100, 0b1000, 0b0001, 0b101, REG_REQUIRED>;
-defm : TLBI<"VMALLS12E1OS", 0, 0b100, 0b1000, 0b0001, 0b110, REG_OPTIONAL>;
-defm : TLBI<"VAE3OS", 1,
[llvm-branch-commits] [llvm] [AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (PR #187400)
https://github.com/jthackray updated
https://github.com/llvm/llvm-project/pull/187400
>From 141a98745e5eae25fb1e5748a3b25d1cb79418bb Mon Sep 17 00:00:00 2001
From: Jonathan Thackray
Date: Wed, 18 Mar 2026 20:54:50 +
Subject: [PATCH 1/2] [AArch64][llvm] Separate TLBI-only feature gating from
TLBIP aliases
Refactor the TLBI system operand definitions so that TLBI and TLBIP
records are emitted through separate helper multiclasses, whilst keeping
the table layout readable.
The feature-scoped wrappers now apply FeatureTLB_RMI, FeatureRME, and
FeatureTLBIW only to TLBI records (it was previously incorrectly also
applied to TLBIP instructions), while TLBIP aliases remain gated only
by FeatureD128, including their nXS forms.
Update testcases accordingly.
---
.../Target/AArch64/AArch64SystemOperands.td | 178 ++
llvm/test/MC/AArch64/armv9a-tlbip.s | 17 +-
2 files changed, 111 insertions(+), 84 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
index 257a4958e8305..d914b253c5358 100644
--- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
+++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
@@ -903,24 +903,54 @@ multiclass TLBITableBase {
defm TLBI : TLBITableBase;
defm TLBIP : TLBITableBase;
-multiclass TLBI op1, bits<4> crn, bits<4>
crm,
- bits<3> op2, int reguse = REG_REQUIRED> {
- def : TLBIEntry;
- def : TLBIEntry {
-let Encoding{7} = 1;
-let ExtraRequires = ["AArch64::FeatureXS"];
- }
- if !eq(hasTLBIP, true) then {
-def : TLBIPEntry {
- let ExtraRequires = ["AArch64::FeatureD128"];
+multiclass TLBI_Base op1, bits<4> crn, bits<4> crm,
+ bits<3> op2, int reguse = REG_REQUIRED,
+ list extra_requires = []> {
+ foreach nxs = [0, 1] in {
+defvar VariantName = !if(nxs, !strconcat(name, "nXS"), name);
+defvar VariantRequires = !if(nxs,
+ extra_requires # ["AArch64::FeatureXS"],
+ extra_requires);
+def : TLBIEntry {
+ let Encoding{7} = nxs;
+ let ExtraRequires = VariantRequires;
}
-def : TLBIPEntry {
- let Encoding{7} = 1;
- let ExtraRequires = ["AArch64::FeatureD128"];
+ }
+}
+
+multiclass TLBIP_Base op1, bits<4> crn, bits<4> crm,
+ bits<3> op2, int reguse = REG_REQUIRED,
+ list extra_requires = ["AArch64::FeatureD128"]> {
+ foreach nxs = [0, 1] in {
+// TLBIP instructions aren't gated by FeatureXS like TLBI ones
+defvar VariantName = !if(nxs, !strconcat(name, "nXS"), name);
+def : TLBIPEntry {
+ let Encoding{7} = nxs;
+ let ExtraRequires = extra_requires;
}
}
}
+multiclass TLBI op1, bits<4> crn,
+bits<4> crm, bits<3> op2, int reguse = REG_REQUIRED> {
+ defm : TLBI_Base;
+ if !eq(hasTLBIP, true) then {
+defm : TLBIP_Base;
+ }
+}
+
+multiclass TLBI_RMI op1, bits<4> crn,
+bits<4> crm, bits<3> op2, int reguse = REG_REQUIRED> {
+ let Requires = ["AArch64::FeatureTLB_RMI"] in {
+defm : TLBI_Base;
+ }
+ // TLBIP instructions aren't gated by FeatureTLB_RMI
+ if !eq(hasTLBIP, true) then {
+defm : TLBIP_Base;
+ }
+}
+
+// TLBI and TLBIP instructions encodings
// hasTLBIP op1CRn CRm op2reguse
defm : TLBI<"IPAS2E1IS",1, 0b100, 0b1000, 0b, 0b001, REG_REQUIRED>;
defm : TLBI<"IPAS2LE1IS", 1, 0b100, 0b1000, 0b, 0b101, REG_REQUIRED>;
@@ -955,76 +985,74 @@ defm : TLBI<"VALE3",1, 0b110, 0b1000, 0b0111,
0b101, REG_REQUIRED>;
defm : TLBI<"VMALLS12E1", 0, 0b100, 0b1000, 0b0111, 0b110, REG_NONE>;
defm : TLBI<"VAALE1", 1, 0b000, 0b1000, 0b0111, 0b111, REG_REQUIRED>;
-// Armv8.4-A Translation Lookaside Buffer Instructions (TLBI)
-let Requires = ["AArch64::FeatureTLB_RMI"] in {
+// Armv8.4-A Translation Lookaside Buffer Instructions (TLBI and TLBIP)
// Armv8.4-A Outer Sharable TLB Maintenance instructions:
-// hasTLBIP op1CRn CRm op2reguse
-defm : TLBI<"VMALLE1OS",0, 0b000, 0b1000, 0b0001, 0b000, REG_OPTIONAL>;
-defm : TLBI<"VAE1OS", 1, 0b000, 0b1000, 0b0001, 0b001, REG_REQUIRED>;
-defm : TLBI<"ASIDE1OS", 0, 0b000, 0b1000, 0b0001, 0b010, REG_REQUIRED>;
-defm : TLBI<"VAAE1OS", 1, 0b000, 0b1000, 0b0001, 0b011, REG_REQUIRED>;
-defm : TLBI<"VALE1OS", 1, 0b000, 0b1000, 0b0001, 0b101, REG_REQUIRED>;
-defm : TLBI<"VAALE1OS", 1, 0b000, 0b1000, 0b0001, 0b111, REG_REQUIRED>;
-defm : TLBI<"IPAS2E1OS",1, 0b100, 0b1000, 0b0100, 0b000, REG_REQUIRED>;
-defm : TLBI<"IPAS2LE1OS", 1, 0b100, 0b1000, 0b0100, 0b100, REG_REQUIRED>;
-defm : TLBI<"VAE2OS", 1, 0b100, 0b1000, 0b0001, 0b001, REG_REQUIRED>;
-defm : TLBI<"VALE2OS", 1, 0b100, 0b1000, 0b0001, 0b101, REG_REQUIRED>;
-defm : TLBI<"VMALLS12E1OS", 0, 0b100, 0b1000, 0b0001, 0b110, REG_OPTIONAL>;
-defm : TLBI<"VAE3OS", 1,
[llvm-branch-commits] [llvm] [AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (PR #187400)
https://github.com/jthackray edited https://github.com/llvm/llvm-project/pull/187400 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (PR #187400)
https://github.com/jthackray edited https://github.com/llvm/llvm-project/pull/187400 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (PR #187400)
https://github.com/jthackray edited https://github.com/llvm/llvm-project/pull/187400 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (PR #187400)
jthackray wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.com/github/pr/llvm/llvm-project/187400?utm_source=stack-comment-downstack-mergeability-warning"; > >on Graphite. > https://graphite.dev/docs/merge-pull-requests";>Learn more * **#187400** https://app.graphite.com/github/pr/llvm/llvm-project/187400?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> 👈 https://app.graphite.com/github/pr/llvm/llvm-project/187400?utm_source=stack-comment-view-in-graphite"; target="_blank">(View in Graphite) * **#186451** https://app.graphite.com/github/pr/llvm/llvm-project/186451?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * `main` This stack of pull requests is managed by https://graphite.dev?utm-source=stack-comment";>Graphite. Learn more about https://stacking.dev/?utm_source=stack-comment";>stacking. https://github.com/llvm/llvm-project/pull/187400 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (PR #187400)
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[llvm-branch-commits] [llvm] [AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (PR #187400)
https://github.com/jthackray created
https://github.com/llvm/llvm-project/pull/187400
Refactor the TLBI system operand definitions so that TLBI and TLBIP
records are emitted through separate helper multiclasses, whilst keeping
the table layout readable.
The feature-scoped wrappers now apply FeatureTLB_RMI, FeatureRME, and
FeatureTLBIW only to TLBI records (it was previously incorrectly also
applied to TLBIP instructions), while TLBIP aliases remain gated only
by FeatureD128, including their nXS forms.
Update testcases accordingly.
>From b7e347cc5eaf00e6e183af4c8684394aa6a2b55a Mon Sep 17 00:00:00 2001
From: Jonathan Thackray
Date: Wed, 18 Mar 2026 20:54:50 +
Subject: [PATCH] [AArch64][llvm] Separate TLBI-only feature gating from TLBIP
aliases
Refactor the TLBI system operand definitions so that TLBI and TLBIP
records are emitted through separate helper multiclasses, whilst keeping
the table layout readable.
The feature-scoped wrappers now apply FeatureTLB_RMI, FeatureRME, and
FeatureTLBIW only to TLBI records (it was previously incorrectly also
applied to TLBIP instructions), while TLBIP aliases remain gated only
by FeatureD128, including their nXS forms.
Update testcases accordingly.
---
.../Target/AArch64/AArch64SystemOperands.td | 198 +++---
llvm/test/MC/AArch64/armv9a-tlbip.s | 17 +-
2 files changed, 127 insertions(+), 88 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
index 257a4958e8305..6fb0519792fdf 100644
--- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
+++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
@@ -903,24 +903,70 @@ multiclass TLBITableBase {
defm TLBI : TLBITableBase;
defm TLBIP : TLBITableBase;
-multiclass TLBI op1, bits<4> crn, bits<4>
crm,
- bits<3> op2, int reguse = REG_REQUIRED> {
- def : TLBIEntry;
- def : TLBIEntry {
-let Encoding{7} = 1;
-let ExtraRequires = ["AArch64::FeatureXS"];
- }
- if !eq(hasTLBIP, true) then {
-def : TLBIPEntry {
- let ExtraRequires = ["AArch64::FeatureD128"];
+multiclass TLBI_Base op1, bits<4> crn, bits<4> crm,
+ bits<3> op2, int reguse = REG_REQUIRED,
+ list extra_requires = []> {
+ foreach nxs = [0, 1] in {
+defvar VariantName = !if(nxs, !strconcat(name, "nXS"), name);
+defvar VariantRequires = !if(nxs,
+ extra_requires # ["AArch64::FeatureXS"],
+ extra_requires);
+def : TLBIEntry {
+ let Encoding{7} = nxs;
+ let ExtraRequires = VariantRequires;
}
-def : TLBIPEntry {
- let Encoding{7} = 1;
- let ExtraRequires = ["AArch64::FeatureD128"];
+ }
+}
+
+multiclass TLBIP_Base op1, bits<4> crn, bits<4> crm,
+ bits<3> op2, int reguse = REG_REQUIRED,
+ list extra_requires = ["AArch64::FeatureD128"]> {
+ foreach nxs = [0, 1] in {
+// TLBIP instructions aren't gated by FeatureXS like TLBI ones
+defvar VariantName = !if(nxs, !strconcat(name, "nXS"), name);
+def : TLBIPEntry {
+ let Encoding{7} = nxs;
+ let ExtraRequires = extra_requires;
}
}
}
+multiclass TLBI op1, bits<4> crn,
+bits<4> crm, bits<3> op2, int reguse = REG_REQUIRED> {
+ defm "" : TLBI_Base;
+ if !eq(hasTLBIP, true) then {
+defm "" : TLBIP_Base;
+ }
+}
+
+multiclass TLBI_RMI op1, bits<4> crn,
+bits<4> crm, bits<3> op2, int reguse = REG_REQUIRED> {
+ let Requires = ["AArch64::FeatureTLB_RMI"] in {
+defm "" : TLBI_Base;
+ }
+ // TLBIP instructions aren't gated by FeatureTLB_RMI
+ if !eq(hasTLBIP, true) then {
+defm "" : TLBIP_Base;
+ }
+}
+
+multiclass TLBI_RME op1, bits<4> crn, bits<4> crm,
+bits<3> op2, int reguse = REG_REQUIRED> {
+ let Requires = ["AArch64::FeatureRME"] in {
+defm "" : TLBI_Base;
+ }
+ // No TLBIP instructions defined here
+}
+
+multiclass TLBI_TLBIW op1, bits<4> crn, bits<4> crm,
+ bits<3> op2, int reguse = REG_REQUIRED> {
+ let Requires = ["AArch64::FeatureTLBIW"] in {
+defm "" : TLBI_Base;
+ }
+ // No TLBIP instructions defined here
+}
+
+// TLBI and TLBIP instructions encodings
// hasTLBIP op1CRn CRm op2reguse
defm : TLBI<"IPAS2E1IS",1, 0b100, 0b1000, 0b, 0b001, REG_REQUIRED>;
defm : TLBI<"IPAS2LE1IS", 1, 0b100, 0b1000, 0b, 0b101, REG_REQUIRED>;
@@ -955,77 +1001,71 @@ defm : TLBI<"VALE3",1, 0b110, 0b1000, 0b0111,
0b101, REG_REQUIRED>;
defm : TLBI<"VMALLS12E1", 0, 0b100, 0b1000, 0b0111, 0b110, REG_NONE>;
defm : TLBI<"VAALE1", 1, 0b000, 0b1000, 0b0111, 0b111, REG_REQUIRED>;
-// Armv8.4-A Translation Lookaside Buffer Instructions (TLBI)
-let Requires = ["AArch64::FeatureTLB_RMI"] in {
+// Armv8.4-A Translation Lookaside Buffer Instructions (TLBI and TLBIP)
// Armv8.4-A Outer Sharable TLB Maintenance instructions:
