[llvm-branch-commits] [llvm] [RISCV] Support non-power-of-2 types when expanding memcmp (PR #114971)

2025-06-18 Thread Pengcheng Wang via llvm-branch-commits 

https://github.com/wangpc-pp updated 
https://github.com/llvm/llvm-project/pull/114971

>From 3fd27bd1405a8b2c068786a200d610b9cacb65ef Mon Sep 17 00:00:00 2001
From: Wang Pengcheng 
Date: Tue, 5 Nov 2024 20:38:44 +0800
Subject: [PATCH 1/5] Set max bytes

Created using spr 1.3.6-beta.1
---
 llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp 
b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index c65feb9755633..a1c5f76bae009 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -2508,7 +2508,10 @@ RISCVTTIImpl::enableMemCmpExpansion(bool OptSize, bool 
IsZeroCmp) const {
 Options.LoadSizes = {4, 2, 1};
   if (IsZeroCmp && ST->hasVInstructions()) {
 unsigned VLenB = ST->getRealMinVLen() / 8;
-for (unsigned Size = ST->getXLen() / 8 + 1;
+// The minimum size should be the maximum bytes between `VLen * LMUL_MF8`
+// and `XLen + 8`.
+unsigned MinSize = std::max(VLenB / 8, ST->getXLen() / 8 + 1);
+for (unsigned Size = MinSize;
  Size <= VLenB * ST->getMaxLMULForFixedLengthVectors(); Size++)
   Options.LoadSizes.insert(Options.LoadSizes.begin(), Size);
   }

>From 17115212f1d7af68f5374896d1ddadf464b2bc11 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng 
Date: Fri, 13 Jun 2025 18:24:15 +0800
Subject: [PATCH 2/5] Change to XLen + 1

Created using spr 1.3.6-beta.1
---
 .../Target/RISCV/RISCVTargetTransformInfo.cpp |   4 +-
 llvm/test/CodeGen/RISCV/memcmp-optsize.ll | 324 +++---
 llvm/test/CodeGen/RISCV/memcmp.ll | 324 +++---
 3 files changed, 570 insertions(+), 82 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp 
b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index 4b9ea30a92c99..3aa0fcbb723a1 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -2956,8 +2956,8 @@ RISCVTTIImpl::enableMemCmpExpansion(bool OptSize, bool 
IsZeroCmp) const {
   if (IsZeroCmp && ST->hasVInstructions()) {
 unsigned VLenB = ST->getRealMinVLen() / 8;
 // The minimum size should be the maximum bytes between `VLen * LMUL_MF8`
-// and `XLen * 2`.
-unsigned MinSize = std::max(VLenB / 8, ST->getXLen() * 2 / 8);
+// and `XLen + 1`.
+unsigned MinSize = std::max(VLenB / 8, ST->getXLen() / 8 + 1);
 for (unsigned Size = MinSize;
  Size <= VLenB * ST->getMaxLMULForFixedLengthVectors(); Size++)
   Options.LoadSizes.insert(Options.LoadSizes.begin(), Size);
diff --git a/llvm/test/CodeGen/RISCV/memcmp-optsize.ll 
b/llvm/test/CodeGen/RISCV/memcmp-optsize.ll
index d4d12a932d0ec..0d57e4201512e 100644
--- a/llvm/test/CodeGen/RISCV/memcmp-optsize.ll
+++ b/llvm/test/CodeGen/RISCV/memcmp-optsize.ll
@@ -517,17 +517,99 @@ define i32 @bcmp_size_5(ptr %s1, ptr %s2) nounwind 
optsize {
 ; CHECK-ALIGNED-RV64-V-NEXT:addi sp, sp, 16
 ; CHECK-ALIGNED-RV64-V-NEXT:ret
 ;
-; CHECK-UNALIGNED-LABEL: bcmp_size_5:
-; CHECK-UNALIGNED:   # %bb.0: # %entry
-; CHECK-UNALIGNED-NEXT:lw a2, 0(a0)
-; CHECK-UNALIGNED-NEXT:lbu a0, 4(a0)
-; CHECK-UNALIGNED-NEXT:lw a3, 0(a1)
-; CHECK-UNALIGNED-NEXT:lbu a1, 4(a1)
-; CHECK-UNALIGNED-NEXT:xor a2, a2, a3
-; CHECK-UNALIGNED-NEXT:xor a0, a0, a1
-; CHECK-UNALIGNED-NEXT:or a0, a2, a0
-; CHECK-UNALIGNED-NEXT:snez a0, a0
-; CHECK-UNALIGNED-NEXT:ret
+; CHECK-UNALIGNED-RV32-LABEL: bcmp_size_5:
+; CHECK-UNALIGNED-RV32:   # %bb.0: # %entry
+; CHECK-UNALIGNED-RV32-NEXT:lw a2, 0(a0)
+; CHECK-UNALIGNED-RV32-NEXT:lbu a0, 4(a0)
+; CHECK-UNALIGNED-RV32-NEXT:lw a3, 0(a1)
+; CHECK-UNALIGNED-RV32-NEXT:lbu a1, 4(a1)
+; CHECK-UNALIGNED-RV32-NEXT:xor a2, a2, a3
+; CHECK-UNALIGNED-RV32-NEXT:xor a0, a0, a1
+; CHECK-UNALIGNED-RV32-NEXT:or a0, a2, a0
+; CHECK-UNALIGNED-RV32-NEXT:snez a0, a0
+; CHECK-UNALIGNED-RV32-NEXT:ret
+;
+; CHECK-UNALIGNED-RV64-LABEL: bcmp_size_5:
+; CHECK-UNALIGNED-RV64:   # %bb.0: # %entry
+; CHECK-UNALIGNED-RV64-NEXT:lw a2, 0(a0)
+; CHECK-UNALIGNED-RV64-NEXT:lbu a0, 4(a0)
+; CHECK-UNALIGNED-RV64-NEXT:lw a3, 0(a1)
+; CHECK-UNALIGNED-RV64-NEXT:lbu a1, 4(a1)
+; CHECK-UNALIGNED-RV64-NEXT:xor a2, a2, a3
+; CHECK-UNALIGNED-RV64-NEXT:xor a0, a0, a1
+; CHECK-UNALIGNED-RV64-NEXT:or a0, a2, a0
+; CHECK-UNALIGNED-RV64-NEXT:snez a0, a0
+; CHECK-UNALIGNED-RV64-NEXT:ret
+;
+; CHECK-UNALIGNED-RV32-ZBB-LABEL: bcmp_size_5:
+; CHECK-UNALIGNED-RV32-ZBB:   # %bb.0: # %entry
+; CHECK-UNALIGNED-RV32-ZBB-NEXT:lw a2, 0(a0)
+; CHECK-UNALIGNED-RV32-ZBB-NEXT:lbu a0, 4(a0)
+; CHECK-UNALIGNED-RV32-ZBB-NEXT:lw a3, 0(a1)
+; CHECK-UNALIGNED-RV32-ZBB-NEXT:lbu a1, 4(a1)
+; CHECK-UNALIGNED-RV32-ZBB-NEXT:xor a2, a2, a3
+; CHECK-UNALIGNED-RV32-ZBB-NEXT:xor a0, a0, a1
+; CHECK-UNALIGNED-RV32-ZBB-NEXT:or a0, a2, a0

[llvm-branch-commits] [llvm] [RISCV] Support non-power-of-2 types when expanding memcmp (PR #114971)

2025-06-18 Thread Pengcheng Wang via llvm-branch-commits 

https://github.com/wangpc-pp updated 
https://github.com/llvm/llvm-project/pull/114971

>From 3fd27bd1405a8b2c068786a200d610b9cacb65ef Mon Sep 17 00:00:00 2001
From: Wang Pengcheng 
Date: Tue, 5 Nov 2024 20:38:44 +0800
Subject: [PATCH 1/5] Set max bytes

Created using spr 1.3.6-beta.1
---
 llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp 
b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index c65feb9755633..a1c5f76bae009 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -2508,7 +2508,10 @@ RISCVTTIImpl::enableMemCmpExpansion(bool OptSize, bool 
IsZeroCmp) const {
 Options.LoadSizes = {4, 2, 1};
   if (IsZeroCmp && ST->hasVInstructions()) {
 unsigned VLenB = ST->getRealMinVLen() / 8;
-for (unsigned Size = ST->getXLen() / 8 + 1;
+// The minimum size should be the maximum bytes between `VLen * LMUL_MF8`
+// and `XLen + 8`.
+unsigned MinSize = std::max(VLenB / 8, ST->getXLen() / 8 + 1);
+for (unsigned Size = MinSize;
  Size <= VLenB * ST->getMaxLMULForFixedLengthVectors(); Size++)
   Options.LoadSizes.insert(Options.LoadSizes.begin(), Size);
   }

>From 17115212f1d7af68f5374896d1ddadf464b2bc11 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng 
Date: Fri, 13 Jun 2025 18:24:15 +0800
Subject: [PATCH 2/5] Change to XLen + 1

Created using spr 1.3.6-beta.1
---
 .../Target/RISCV/RISCVTargetTransformInfo.cpp |   4 +-
 llvm/test/CodeGen/RISCV/memcmp-optsize.ll | 324 +++---
 llvm/test/CodeGen/RISCV/memcmp.ll | 324 +++---
 3 files changed, 570 insertions(+), 82 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp 
b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index 4b9ea30a92c99..3aa0fcbb723a1 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -2956,8 +2956,8 @@ RISCVTTIImpl::enableMemCmpExpansion(bool OptSize, bool 
IsZeroCmp) const {
   if (IsZeroCmp && ST->hasVInstructions()) {
 unsigned VLenB = ST->getRealMinVLen() / 8;
 // The minimum size should be the maximum bytes between `VLen * LMUL_MF8`
-// and `XLen * 2`.
-unsigned MinSize = std::max(VLenB / 8, ST->getXLen() * 2 / 8);
+// and `XLen + 1`.
+unsigned MinSize = std::max(VLenB / 8, ST->getXLen() / 8 + 1);
 for (unsigned Size = MinSize;
  Size <= VLenB * ST->getMaxLMULForFixedLengthVectors(); Size++)
   Options.LoadSizes.insert(Options.LoadSizes.begin(), Size);
diff --git a/llvm/test/CodeGen/RISCV/memcmp-optsize.ll 
b/llvm/test/CodeGen/RISCV/memcmp-optsize.ll
index d4d12a932d0ec..0d57e4201512e 100644
--- a/llvm/test/CodeGen/RISCV/memcmp-optsize.ll
+++ b/llvm/test/CodeGen/RISCV/memcmp-optsize.ll
@@ -517,17 +517,99 @@ define i32 @bcmp_size_5(ptr %s1, ptr %s2) nounwind 
optsize {
 ; CHECK-ALIGNED-RV64-V-NEXT:addi sp, sp, 16
 ; CHECK-ALIGNED-RV64-V-NEXT:ret
 ;
-; CHECK-UNALIGNED-LABEL: bcmp_size_5:
-; CHECK-UNALIGNED:   # %bb.0: # %entry
-; CHECK-UNALIGNED-NEXT:lw a2, 0(a0)
-; CHECK-UNALIGNED-NEXT:lbu a0, 4(a0)
-; CHECK-UNALIGNED-NEXT:lw a3, 0(a1)
-; CHECK-UNALIGNED-NEXT:lbu a1, 4(a1)
-; CHECK-UNALIGNED-NEXT:xor a2, a2, a3
-; CHECK-UNALIGNED-NEXT:xor a0, a0, a1
-; CHECK-UNALIGNED-NEXT:or a0, a2, a0
-; CHECK-UNALIGNED-NEXT:snez a0, a0
-; CHECK-UNALIGNED-NEXT:ret
+; CHECK-UNALIGNED-RV32-LABEL: bcmp_size_5:
+; CHECK-UNALIGNED-RV32:   # %bb.0: # %entry
+; CHECK-UNALIGNED-RV32-NEXT:lw a2, 0(a0)
+; CHECK-UNALIGNED-RV32-NEXT:lbu a0, 4(a0)
+; CHECK-UNALIGNED-RV32-NEXT:lw a3, 0(a1)
+; CHECK-UNALIGNED-RV32-NEXT:lbu a1, 4(a1)
+; CHECK-UNALIGNED-RV32-NEXT:xor a2, a2, a3
+; CHECK-UNALIGNED-RV32-NEXT:xor a0, a0, a1
+; CHECK-UNALIGNED-RV32-NEXT:or a0, a2, a0
+; CHECK-UNALIGNED-RV32-NEXT:snez a0, a0
+; CHECK-UNALIGNED-RV32-NEXT:ret
+;
+; CHECK-UNALIGNED-RV64-LABEL: bcmp_size_5:
+; CHECK-UNALIGNED-RV64:   # %bb.0: # %entry
+; CHECK-UNALIGNED-RV64-NEXT:lw a2, 0(a0)
+; CHECK-UNALIGNED-RV64-NEXT:lbu a0, 4(a0)
+; CHECK-UNALIGNED-RV64-NEXT:lw a3, 0(a1)
+; CHECK-UNALIGNED-RV64-NEXT:lbu a1, 4(a1)
+; CHECK-UNALIGNED-RV64-NEXT:xor a2, a2, a3
+; CHECK-UNALIGNED-RV64-NEXT:xor a0, a0, a1
+; CHECK-UNALIGNED-RV64-NEXT:or a0, a2, a0
+; CHECK-UNALIGNED-RV64-NEXT:snez a0, a0
+; CHECK-UNALIGNED-RV64-NEXT:ret
+;
+; CHECK-UNALIGNED-RV32-ZBB-LABEL: bcmp_size_5:
+; CHECK-UNALIGNED-RV32-ZBB:   # %bb.0: # %entry
+; CHECK-UNALIGNED-RV32-ZBB-NEXT:lw a2, 0(a0)
+; CHECK-UNALIGNED-RV32-ZBB-NEXT:lbu a0, 4(a0)
+; CHECK-UNALIGNED-RV32-ZBB-NEXT:lw a3, 0(a1)
+; CHECK-UNALIGNED-RV32-ZBB-NEXT:lbu a1, 4(a1)
+; CHECK-UNALIGNED-RV32-ZBB-NEXT:xor a2, a2, a3
+; CHECK-UNALIGNED-RV32-ZBB-NEXT:xor a0, a0, a1
+; CHECK-UNALIGNED-RV32-ZBB-NEXT:or a0, a2, a0

[llvm-branch-commits] [llvm] [RISCV] Support non-power-of-2 types when expanding memcmp (PR #114971)

2025-06-16 Thread Pengcheng Wang via llvm-branch-commits 

https://github.com/wangpc-pp updated 
https://github.com/llvm/llvm-project/pull/114971

>From 3fd27bd1405a8b2c068786a200d610b9cacb65ef Mon Sep 17 00:00:00 2001
From: Wang Pengcheng 
Date: Tue, 5 Nov 2024 20:38:44 +0800
Subject: [PATCH 1/4] Set max bytes

Created using spr 1.3.6-beta.1
---
 llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp 
b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index c65feb9755633..a1c5f76bae009 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -2508,7 +2508,10 @@ RISCVTTIImpl::enableMemCmpExpansion(bool OptSize, bool 
IsZeroCmp) const {
 Options.LoadSizes = {4, 2, 1};
   if (IsZeroCmp && ST->hasVInstructions()) {
 unsigned VLenB = ST->getRealMinVLen() / 8;
-for (unsigned Size = ST->getXLen() / 8 + 1;
+// The minimum size should be the maximum bytes between `VLen * LMUL_MF8`
+// and `XLen + 8`.
+unsigned MinSize = std::max(VLenB / 8, ST->getXLen() / 8 + 1);
+for (unsigned Size = MinSize;
  Size <= VLenB * ST->getMaxLMULForFixedLengthVectors(); Size++)
   Options.LoadSizes.insert(Options.LoadSizes.begin(), Size);
   }

>From 17115212f1d7af68f5374896d1ddadf464b2bc11 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng 
Date: Fri, 13 Jun 2025 18:24:15 +0800
Subject: [PATCH 2/4] Change to XLen + 1

Created using spr 1.3.6-beta.1
---
 .../Target/RISCV/RISCVTargetTransformInfo.cpp |   4 +-
 llvm/test/CodeGen/RISCV/memcmp-optsize.ll | 324 +++---
 llvm/test/CodeGen/RISCV/memcmp.ll | 324 +++---
 3 files changed, 570 insertions(+), 82 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp 
b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index 4b9ea30a92c99..3aa0fcbb723a1 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -2956,8 +2956,8 @@ RISCVTTIImpl::enableMemCmpExpansion(bool OptSize, bool 
IsZeroCmp) const {
   if (IsZeroCmp && ST->hasVInstructions()) {
 unsigned VLenB = ST->getRealMinVLen() / 8;
 // The minimum size should be the maximum bytes between `VLen * LMUL_MF8`
-// and `XLen * 2`.
-unsigned MinSize = std::max(VLenB / 8, ST->getXLen() * 2 / 8);
+// and `XLen + 1`.
+unsigned MinSize = std::max(VLenB / 8, ST->getXLen() / 8 + 1);
 for (unsigned Size = MinSize;
  Size <= VLenB * ST->getMaxLMULForFixedLengthVectors(); Size++)
   Options.LoadSizes.insert(Options.LoadSizes.begin(), Size);
diff --git a/llvm/test/CodeGen/RISCV/memcmp-optsize.ll 
b/llvm/test/CodeGen/RISCV/memcmp-optsize.ll
index d4d12a932d0ec..0d57e4201512e 100644
--- a/llvm/test/CodeGen/RISCV/memcmp-optsize.ll
+++ b/llvm/test/CodeGen/RISCV/memcmp-optsize.ll
@@ -517,17 +517,99 @@ define i32 @bcmp_size_5(ptr %s1, ptr %s2) nounwind 
optsize {
 ; CHECK-ALIGNED-RV64-V-NEXT:addi sp, sp, 16
 ; CHECK-ALIGNED-RV64-V-NEXT:ret
 ;
-; CHECK-UNALIGNED-LABEL: bcmp_size_5:
-; CHECK-UNALIGNED:   # %bb.0: # %entry
-; CHECK-UNALIGNED-NEXT:lw a2, 0(a0)
-; CHECK-UNALIGNED-NEXT:lbu a0, 4(a0)
-; CHECK-UNALIGNED-NEXT:lw a3, 0(a1)
-; CHECK-UNALIGNED-NEXT:lbu a1, 4(a1)
-; CHECK-UNALIGNED-NEXT:xor a2, a2, a3
-; CHECK-UNALIGNED-NEXT:xor a0, a0, a1
-; CHECK-UNALIGNED-NEXT:or a0, a2, a0
-; CHECK-UNALIGNED-NEXT:snez a0, a0
-; CHECK-UNALIGNED-NEXT:ret
+; CHECK-UNALIGNED-RV32-LABEL: bcmp_size_5:
+; CHECK-UNALIGNED-RV32:   # %bb.0: # %entry
+; CHECK-UNALIGNED-RV32-NEXT:lw a2, 0(a0)
+; CHECK-UNALIGNED-RV32-NEXT:lbu a0, 4(a0)
+; CHECK-UNALIGNED-RV32-NEXT:lw a3, 0(a1)
+; CHECK-UNALIGNED-RV32-NEXT:lbu a1, 4(a1)
+; CHECK-UNALIGNED-RV32-NEXT:xor a2, a2, a3
+; CHECK-UNALIGNED-RV32-NEXT:xor a0, a0, a1
+; CHECK-UNALIGNED-RV32-NEXT:or a0, a2, a0
+; CHECK-UNALIGNED-RV32-NEXT:snez a0, a0
+; CHECK-UNALIGNED-RV32-NEXT:ret
+;
+; CHECK-UNALIGNED-RV64-LABEL: bcmp_size_5:
+; CHECK-UNALIGNED-RV64:   # %bb.0: # %entry
+; CHECK-UNALIGNED-RV64-NEXT:lw a2, 0(a0)
+; CHECK-UNALIGNED-RV64-NEXT:lbu a0, 4(a0)
+; CHECK-UNALIGNED-RV64-NEXT:lw a3, 0(a1)
+; CHECK-UNALIGNED-RV64-NEXT:lbu a1, 4(a1)
+; CHECK-UNALIGNED-RV64-NEXT:xor a2, a2, a3
+; CHECK-UNALIGNED-RV64-NEXT:xor a0, a0, a1
+; CHECK-UNALIGNED-RV64-NEXT:or a0, a2, a0
+; CHECK-UNALIGNED-RV64-NEXT:snez a0, a0
+; CHECK-UNALIGNED-RV64-NEXT:ret
+;
+; CHECK-UNALIGNED-RV32-ZBB-LABEL: bcmp_size_5:
+; CHECK-UNALIGNED-RV32-ZBB:   # %bb.0: # %entry
+; CHECK-UNALIGNED-RV32-ZBB-NEXT:lw a2, 0(a0)
+; CHECK-UNALIGNED-RV32-ZBB-NEXT:lbu a0, 4(a0)
+; CHECK-UNALIGNED-RV32-ZBB-NEXT:lw a3, 0(a1)
+; CHECK-UNALIGNED-RV32-ZBB-NEXT:lbu a1, 4(a1)
+; CHECK-UNALIGNED-RV32-ZBB-NEXT:xor a2, a2, a3
+; CHECK-UNALIGNED-RV32-ZBB-NEXT:xor a0, a0, a1
+; CHECK-UNALIGNED-RV32-ZBB-NEXT:or a0, a2, a0

[llvm-branch-commits] [llvm] [RISCV] Support non-power-of-2 types when expanding memcmp (PR #114971)

2025-06-16 Thread Pengcheng Wang via llvm-branch-commits 

https://github.com/wangpc-pp updated 
https://github.com/llvm/llvm-project/pull/114971

>From 3fd27bd1405a8b2c068786a200d610b9cacb65ef Mon Sep 17 00:00:00 2001
From: Wang Pengcheng 
Date: Tue, 5 Nov 2024 20:38:44 +0800
Subject: [PATCH 1/3] Set max bytes

Created using spr 1.3.6-beta.1
---
 llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp 
b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index c65feb9755633..a1c5f76bae009 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -2508,7 +2508,10 @@ RISCVTTIImpl::enableMemCmpExpansion(bool OptSize, bool 
IsZeroCmp) const {
 Options.LoadSizes = {4, 2, 1};
   if (IsZeroCmp && ST->hasVInstructions()) {
 unsigned VLenB = ST->getRealMinVLen() / 8;
-for (unsigned Size = ST->getXLen() / 8 + 1;
+// The minimum size should be the maximum bytes between `VLen * LMUL_MF8`
+// and `XLen + 8`.
+unsigned MinSize = std::max(VLenB / 8, ST->getXLen() / 8 + 1);
+for (unsigned Size = MinSize;
  Size <= VLenB * ST->getMaxLMULForFixedLengthVectors(); Size++)
   Options.LoadSizes.insert(Options.LoadSizes.begin(), Size);
   }

>From 17115212f1d7af68f5374896d1ddadf464b2bc11 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng 
Date: Fri, 13 Jun 2025 18:24:15 +0800
Subject: [PATCH 2/3] Change to XLen + 1

Created using spr 1.3.6-beta.1
---
 .../Target/RISCV/RISCVTargetTransformInfo.cpp |   4 +-
 llvm/test/CodeGen/RISCV/memcmp-optsize.ll | 324 +++---
 llvm/test/CodeGen/RISCV/memcmp.ll | 324 +++---
 3 files changed, 570 insertions(+), 82 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp 
b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index 4b9ea30a92c99..3aa0fcbb723a1 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -2956,8 +2956,8 @@ RISCVTTIImpl::enableMemCmpExpansion(bool OptSize, bool 
IsZeroCmp) const {
   if (IsZeroCmp && ST->hasVInstructions()) {
 unsigned VLenB = ST->getRealMinVLen() / 8;
 // The minimum size should be the maximum bytes between `VLen * LMUL_MF8`
-// and `XLen * 2`.
-unsigned MinSize = std::max(VLenB / 8, ST->getXLen() * 2 / 8);
+// and `XLen + 1`.
+unsigned MinSize = std::max(VLenB / 8, ST->getXLen() / 8 + 1);
 for (unsigned Size = MinSize;
  Size <= VLenB * ST->getMaxLMULForFixedLengthVectors(); Size++)
   Options.LoadSizes.insert(Options.LoadSizes.begin(), Size);
diff --git a/llvm/test/CodeGen/RISCV/memcmp-optsize.ll 
b/llvm/test/CodeGen/RISCV/memcmp-optsize.ll
index d4d12a932d0ec..0d57e4201512e 100644
--- a/llvm/test/CodeGen/RISCV/memcmp-optsize.ll
+++ b/llvm/test/CodeGen/RISCV/memcmp-optsize.ll
@@ -517,17 +517,99 @@ define i32 @bcmp_size_5(ptr %s1, ptr %s2) nounwind 
optsize {
 ; CHECK-ALIGNED-RV64-V-NEXT:addi sp, sp, 16
 ; CHECK-ALIGNED-RV64-V-NEXT:ret
 ;
-; CHECK-UNALIGNED-LABEL: bcmp_size_5:
-; CHECK-UNALIGNED:   # %bb.0: # %entry
-; CHECK-UNALIGNED-NEXT:lw a2, 0(a0)
-; CHECK-UNALIGNED-NEXT:lbu a0, 4(a0)
-; CHECK-UNALIGNED-NEXT:lw a3, 0(a1)
-; CHECK-UNALIGNED-NEXT:lbu a1, 4(a1)
-; CHECK-UNALIGNED-NEXT:xor a2, a2, a3
-; CHECK-UNALIGNED-NEXT:xor a0, a0, a1
-; CHECK-UNALIGNED-NEXT:or a0, a2, a0
-; CHECK-UNALIGNED-NEXT:snez a0, a0
-; CHECK-UNALIGNED-NEXT:ret
+; CHECK-UNALIGNED-RV32-LABEL: bcmp_size_5:
+; CHECK-UNALIGNED-RV32:   # %bb.0: # %entry
+; CHECK-UNALIGNED-RV32-NEXT:lw a2, 0(a0)
+; CHECK-UNALIGNED-RV32-NEXT:lbu a0, 4(a0)
+; CHECK-UNALIGNED-RV32-NEXT:lw a3, 0(a1)
+; CHECK-UNALIGNED-RV32-NEXT:lbu a1, 4(a1)
+; CHECK-UNALIGNED-RV32-NEXT:xor a2, a2, a3
+; CHECK-UNALIGNED-RV32-NEXT:xor a0, a0, a1
+; CHECK-UNALIGNED-RV32-NEXT:or a0, a2, a0
+; CHECK-UNALIGNED-RV32-NEXT:snez a0, a0
+; CHECK-UNALIGNED-RV32-NEXT:ret
+;
+; CHECK-UNALIGNED-RV64-LABEL: bcmp_size_5:
+; CHECK-UNALIGNED-RV64:   # %bb.0: # %entry
+; CHECK-UNALIGNED-RV64-NEXT:lw a2, 0(a0)
+; CHECK-UNALIGNED-RV64-NEXT:lbu a0, 4(a0)
+; CHECK-UNALIGNED-RV64-NEXT:lw a3, 0(a1)
+; CHECK-UNALIGNED-RV64-NEXT:lbu a1, 4(a1)
+; CHECK-UNALIGNED-RV64-NEXT:xor a2, a2, a3
+; CHECK-UNALIGNED-RV64-NEXT:xor a0, a0, a1
+; CHECK-UNALIGNED-RV64-NEXT:or a0, a2, a0
+; CHECK-UNALIGNED-RV64-NEXT:snez a0, a0
+; CHECK-UNALIGNED-RV64-NEXT:ret
+;
+; CHECK-UNALIGNED-RV32-ZBB-LABEL: bcmp_size_5:
+; CHECK-UNALIGNED-RV32-ZBB:   # %bb.0: # %entry
+; CHECK-UNALIGNED-RV32-ZBB-NEXT:lw a2, 0(a0)
+; CHECK-UNALIGNED-RV32-ZBB-NEXT:lbu a0, 4(a0)
+; CHECK-UNALIGNED-RV32-ZBB-NEXT:lw a3, 0(a1)
+; CHECK-UNALIGNED-RV32-ZBB-NEXT:lbu a1, 4(a1)
+; CHECK-UNALIGNED-RV32-ZBB-NEXT:xor a2, a2, a3
+; CHECK-UNALIGNED-RV32-ZBB-NEXT:xor a0, a0, a1
+; CHECK-UNALIGNED-RV32-ZBB-NEXT:or a0, a2, a0

[llvm-branch-commits] [llvm] [RISCV] Support non-power-of-2 types when expanding memcmp (PR #114971)

2025-06-16 Thread Pengcheng Wang via llvm-branch-commits 

https://github.com/wangpc-pp updated 
https://github.com/llvm/llvm-project/pull/114971

>From 3fd27bd1405a8b2c068786a200d610b9cacb65ef Mon Sep 17 00:00:00 2001
From: Wang Pengcheng 
Date: Tue, 5 Nov 2024 20:38:44 +0800
Subject: [PATCH 1/3] Set max bytes

Created using spr 1.3.6-beta.1
---
 llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp 
b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index c65feb9755633..a1c5f76bae009 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -2508,7 +2508,10 @@ RISCVTTIImpl::enableMemCmpExpansion(bool OptSize, bool 
IsZeroCmp) const {
 Options.LoadSizes = {4, 2, 1};
   if (IsZeroCmp && ST->hasVInstructions()) {
 unsigned VLenB = ST->getRealMinVLen() / 8;
-for (unsigned Size = ST->getXLen() / 8 + 1;
+// The minimum size should be the maximum bytes between `VLen * LMUL_MF8`
+// and `XLen + 8`.
+unsigned MinSize = std::max(VLenB / 8, ST->getXLen() / 8 + 1);
+for (unsigned Size = MinSize;
  Size <= VLenB * ST->getMaxLMULForFixedLengthVectors(); Size++)
   Options.LoadSizes.insert(Options.LoadSizes.begin(), Size);
   }

>From 17115212f1d7af68f5374896d1ddadf464b2bc11 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng 
Date: Fri, 13 Jun 2025 18:24:15 +0800
Subject: [PATCH 2/3] Change to XLen + 1

Created using spr 1.3.6-beta.1
---
 .../Target/RISCV/RISCVTargetTransformInfo.cpp |   4 +-
 llvm/test/CodeGen/RISCV/memcmp-optsize.ll | 324 +++---
 llvm/test/CodeGen/RISCV/memcmp.ll | 324 +++---
 3 files changed, 570 insertions(+), 82 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp 
b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index 4b9ea30a92c99..3aa0fcbb723a1 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -2956,8 +2956,8 @@ RISCVTTIImpl::enableMemCmpExpansion(bool OptSize, bool 
IsZeroCmp) const {
   if (IsZeroCmp && ST->hasVInstructions()) {
 unsigned VLenB = ST->getRealMinVLen() / 8;
 // The minimum size should be the maximum bytes between `VLen * LMUL_MF8`
-// and `XLen * 2`.
-unsigned MinSize = std::max(VLenB / 8, ST->getXLen() * 2 / 8);
+// and `XLen + 1`.
+unsigned MinSize = std::max(VLenB / 8, ST->getXLen() / 8 + 1);
 for (unsigned Size = MinSize;
  Size <= VLenB * ST->getMaxLMULForFixedLengthVectors(); Size++)
   Options.LoadSizes.insert(Options.LoadSizes.begin(), Size);
diff --git a/llvm/test/CodeGen/RISCV/memcmp-optsize.ll 
b/llvm/test/CodeGen/RISCV/memcmp-optsize.ll
index d4d12a932d0ec..0d57e4201512e 100644
--- a/llvm/test/CodeGen/RISCV/memcmp-optsize.ll
+++ b/llvm/test/CodeGen/RISCV/memcmp-optsize.ll
@@ -517,17 +517,99 @@ define i32 @bcmp_size_5(ptr %s1, ptr %s2) nounwind 
optsize {
 ; CHECK-ALIGNED-RV64-V-NEXT:addi sp, sp, 16
 ; CHECK-ALIGNED-RV64-V-NEXT:ret
 ;
-; CHECK-UNALIGNED-LABEL: bcmp_size_5:
-; CHECK-UNALIGNED:   # %bb.0: # %entry
-; CHECK-UNALIGNED-NEXT:lw a2, 0(a0)
-; CHECK-UNALIGNED-NEXT:lbu a0, 4(a0)
-; CHECK-UNALIGNED-NEXT:lw a3, 0(a1)
-; CHECK-UNALIGNED-NEXT:lbu a1, 4(a1)
-; CHECK-UNALIGNED-NEXT:xor a2, a2, a3
-; CHECK-UNALIGNED-NEXT:xor a0, a0, a1
-; CHECK-UNALIGNED-NEXT:or a0, a2, a0
-; CHECK-UNALIGNED-NEXT:snez a0, a0
-; CHECK-UNALIGNED-NEXT:ret
+; CHECK-UNALIGNED-RV32-LABEL: bcmp_size_5:
+; CHECK-UNALIGNED-RV32:   # %bb.0: # %entry
+; CHECK-UNALIGNED-RV32-NEXT:lw a2, 0(a0)
+; CHECK-UNALIGNED-RV32-NEXT:lbu a0, 4(a0)
+; CHECK-UNALIGNED-RV32-NEXT:lw a3, 0(a1)
+; CHECK-UNALIGNED-RV32-NEXT:lbu a1, 4(a1)
+; CHECK-UNALIGNED-RV32-NEXT:xor a2, a2, a3
+; CHECK-UNALIGNED-RV32-NEXT:xor a0, a0, a1
+; CHECK-UNALIGNED-RV32-NEXT:or a0, a2, a0
+; CHECK-UNALIGNED-RV32-NEXT:snez a0, a0
+; CHECK-UNALIGNED-RV32-NEXT:ret
+;
+; CHECK-UNALIGNED-RV64-LABEL: bcmp_size_5:
+; CHECK-UNALIGNED-RV64:   # %bb.0: # %entry
+; CHECK-UNALIGNED-RV64-NEXT:lw a2, 0(a0)
+; CHECK-UNALIGNED-RV64-NEXT:lbu a0, 4(a0)
+; CHECK-UNALIGNED-RV64-NEXT:lw a3, 0(a1)
+; CHECK-UNALIGNED-RV64-NEXT:lbu a1, 4(a1)
+; CHECK-UNALIGNED-RV64-NEXT:xor a2, a2, a3
+; CHECK-UNALIGNED-RV64-NEXT:xor a0, a0, a1
+; CHECK-UNALIGNED-RV64-NEXT:or a0, a2, a0
+; CHECK-UNALIGNED-RV64-NEXT:snez a0, a0
+; CHECK-UNALIGNED-RV64-NEXT:ret
+;
+; CHECK-UNALIGNED-RV32-ZBB-LABEL: bcmp_size_5:
+; CHECK-UNALIGNED-RV32-ZBB:   # %bb.0: # %entry
+; CHECK-UNALIGNED-RV32-ZBB-NEXT:lw a2, 0(a0)
+; CHECK-UNALIGNED-RV32-ZBB-NEXT:lbu a0, 4(a0)
+; CHECK-UNALIGNED-RV32-ZBB-NEXT:lw a3, 0(a1)
+; CHECK-UNALIGNED-RV32-ZBB-NEXT:lbu a1, 4(a1)
+; CHECK-UNALIGNED-RV32-ZBB-NEXT:xor a2, a2, a3
+; CHECK-UNALIGNED-RV32-ZBB-NEXT:xor a0, a0, a1
+; CHECK-UNALIGNED-RV32-ZBB-NEXT:or a0, a2, a0

[llvm-branch-commits] [llvm] [RISCV] Support non-power-of-2 types when expanding memcmp (PR #114971)

2025-06-16 Thread Philip Reames via llvm-branch-commits 


@@ -16190,13 +16186,20 @@ combineVectorSizedSetCCEquality(EVT VT, SDValue X, 
SDValue Y, ISD::CondCode CC,
 return SDValue();
 
   unsigned VecSize = OpSize / 8;

preames wrote:

Where in the code above do we have a guarantee that OpSize is a multiple of 8?  

https://github.com/llvm/llvm-project/pull/114971
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[llvm-branch-commits] [llvm] [RISCV] Support non-power-of-2 types when expanding memcmp (PR #114971)

2025-06-16 Thread Craig Topper via llvm-branch-commits 


@@ -2954,20 +2954,12 @@ RISCVTTIImpl::enableMemCmpExpansion(bool OptSize, bool 
IsZeroCmp) const {
   }
 
   if (IsZeroCmp && ST->hasVInstructions()) {
-unsigned RealMinVLen = ST->getRealMinVLen();
-// Support Fractional LMULs if the lengths are larger than XLen.
-// TODO: Support non-power-of-2 types.
-for (unsigned FLMUL = 8; FLMUL >= 2; FLMUL /= 2) {
-  unsigned Len = RealMinVLen / FLMUL;
-  if (Len > ST->getXLen())
-Options.LoadSizes.insert(Options.LoadSizes.begin(), Len / 8);
-}
-for (unsigned LMUL = 1; LMUL <= ST->getMaxLMULForFixedLengthVectors();
- LMUL *= 2) {
-  unsigned Len = RealMinVLen * LMUL;
-  if (Len > ST->getXLen())
-Options.LoadSizes.insert(Options.LoadSizes.begin(), Len / 8);
-}
+unsigned VLenB = ST->getRealMinVLen() / 8;
+// The minimum size should be `XLen + 1`.

topperc wrote:

Comment doesn't match the code. Is it Xlen+1 or Xlen/8 + 1?

https://github.com/llvm/llvm-project/pull/114971
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[llvm-branch-commits] [llvm] [RISCV] Support non-power-of-2 types when expanding memcmp (PR #114971)

2025-06-16 Thread Luke Lau via llvm-branch-commits 

https://github.com/lukel97 approved this pull request.

LGTM

https://github.com/llvm/llvm-project/pull/114971
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[llvm-branch-commits] [llvm] [RISCV] Support non-power-of-2 types when expanding memcmp (PR #114971)

2025-06-15 Thread Pengcheng Wang via llvm-branch-commits 

https://github.com/wangpc-pp updated 
https://github.com/llvm/llvm-project/pull/114971

>From 3fd27bd1405a8b2c068786a200d610b9cacb65ef Mon Sep 17 00:00:00 2001
From: Wang Pengcheng 
Date: Tue, 5 Nov 2024 20:38:44 +0800
Subject: [PATCH 1/3] Set max bytes

Created using spr 1.3.6-beta.1
---
 llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp 
b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index c65feb9755633..a1c5f76bae009 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -2508,7 +2508,10 @@ RISCVTTIImpl::enableMemCmpExpansion(bool OptSize, bool 
IsZeroCmp) const {
 Options.LoadSizes = {4, 2, 1};
   if (IsZeroCmp && ST->hasVInstructions()) {
 unsigned VLenB = ST->getRealMinVLen() / 8;
-for (unsigned Size = ST->getXLen() / 8 + 1;
+// The minimum size should be the maximum bytes between `VLen * LMUL_MF8`
+// and `XLen + 8`.
+unsigned MinSize = std::max(VLenB / 8, ST->getXLen() / 8 + 1);
+for (unsigned Size = MinSize;
  Size <= VLenB * ST->getMaxLMULForFixedLengthVectors(); Size++)
   Options.LoadSizes.insert(Options.LoadSizes.begin(), Size);
   }

>From 17115212f1d7af68f5374896d1ddadf464b2bc11 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng 
Date: Fri, 13 Jun 2025 18:24:15 +0800
Subject: [PATCH 2/3] Change to XLen + 1

Created using spr 1.3.6-beta.1
---
 .../Target/RISCV/RISCVTargetTransformInfo.cpp |   4 +-
 llvm/test/CodeGen/RISCV/memcmp-optsize.ll | 324 +++---
 llvm/test/CodeGen/RISCV/memcmp.ll | 324 +++---
 3 files changed, 570 insertions(+), 82 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp 
b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index 4b9ea30a92c99..3aa0fcbb723a1 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -2956,8 +2956,8 @@ RISCVTTIImpl::enableMemCmpExpansion(bool OptSize, bool 
IsZeroCmp) const {
   if (IsZeroCmp && ST->hasVInstructions()) {
 unsigned VLenB = ST->getRealMinVLen() / 8;
 // The minimum size should be the maximum bytes between `VLen * LMUL_MF8`
-// and `XLen * 2`.
-unsigned MinSize = std::max(VLenB / 8, ST->getXLen() * 2 / 8);
+// and `XLen + 1`.
+unsigned MinSize = std::max(VLenB / 8, ST->getXLen() / 8 + 1);
 for (unsigned Size = MinSize;
  Size <= VLenB * ST->getMaxLMULForFixedLengthVectors(); Size++)
   Options.LoadSizes.insert(Options.LoadSizes.begin(), Size);
diff --git a/llvm/test/CodeGen/RISCV/memcmp-optsize.ll 
b/llvm/test/CodeGen/RISCV/memcmp-optsize.ll
index d4d12a932d0ec..0d57e4201512e 100644
--- a/llvm/test/CodeGen/RISCV/memcmp-optsize.ll
+++ b/llvm/test/CodeGen/RISCV/memcmp-optsize.ll
@@ -517,17 +517,99 @@ define i32 @bcmp_size_5(ptr %s1, ptr %s2) nounwind 
optsize {
 ; CHECK-ALIGNED-RV64-V-NEXT:addi sp, sp, 16
 ; CHECK-ALIGNED-RV64-V-NEXT:ret
 ;
-; CHECK-UNALIGNED-LABEL: bcmp_size_5:
-; CHECK-UNALIGNED:   # %bb.0: # %entry
-; CHECK-UNALIGNED-NEXT:lw a2, 0(a0)
-; CHECK-UNALIGNED-NEXT:lbu a0, 4(a0)
-; CHECK-UNALIGNED-NEXT:lw a3, 0(a1)
-; CHECK-UNALIGNED-NEXT:lbu a1, 4(a1)
-; CHECK-UNALIGNED-NEXT:xor a2, a2, a3
-; CHECK-UNALIGNED-NEXT:xor a0, a0, a1
-; CHECK-UNALIGNED-NEXT:or a0, a2, a0
-; CHECK-UNALIGNED-NEXT:snez a0, a0
-; CHECK-UNALIGNED-NEXT:ret
+; CHECK-UNALIGNED-RV32-LABEL: bcmp_size_5:
+; CHECK-UNALIGNED-RV32:   # %bb.0: # %entry
+; CHECK-UNALIGNED-RV32-NEXT:lw a2, 0(a0)
+; CHECK-UNALIGNED-RV32-NEXT:lbu a0, 4(a0)
+; CHECK-UNALIGNED-RV32-NEXT:lw a3, 0(a1)
+; CHECK-UNALIGNED-RV32-NEXT:lbu a1, 4(a1)
+; CHECK-UNALIGNED-RV32-NEXT:xor a2, a2, a3
+; CHECK-UNALIGNED-RV32-NEXT:xor a0, a0, a1
+; CHECK-UNALIGNED-RV32-NEXT:or a0, a2, a0
+; CHECK-UNALIGNED-RV32-NEXT:snez a0, a0
+; CHECK-UNALIGNED-RV32-NEXT:ret
+;
+; CHECK-UNALIGNED-RV64-LABEL: bcmp_size_5:
+; CHECK-UNALIGNED-RV64:   # %bb.0: # %entry
+; CHECK-UNALIGNED-RV64-NEXT:lw a2, 0(a0)
+; CHECK-UNALIGNED-RV64-NEXT:lbu a0, 4(a0)
+; CHECK-UNALIGNED-RV64-NEXT:lw a3, 0(a1)
+; CHECK-UNALIGNED-RV64-NEXT:lbu a1, 4(a1)
+; CHECK-UNALIGNED-RV64-NEXT:xor a2, a2, a3
+; CHECK-UNALIGNED-RV64-NEXT:xor a0, a0, a1
+; CHECK-UNALIGNED-RV64-NEXT:or a0, a2, a0
+; CHECK-UNALIGNED-RV64-NEXT:snez a0, a0
+; CHECK-UNALIGNED-RV64-NEXT:ret
+;
+; CHECK-UNALIGNED-RV32-ZBB-LABEL: bcmp_size_5:
+; CHECK-UNALIGNED-RV32-ZBB:   # %bb.0: # %entry
+; CHECK-UNALIGNED-RV32-ZBB-NEXT:lw a2, 0(a0)
+; CHECK-UNALIGNED-RV32-ZBB-NEXT:lbu a0, 4(a0)
+; CHECK-UNALIGNED-RV32-ZBB-NEXT:lw a3, 0(a1)
+; CHECK-UNALIGNED-RV32-ZBB-NEXT:lbu a1, 4(a1)
+; CHECK-UNALIGNED-RV32-ZBB-NEXT:xor a2, a2, a3
+; CHECK-UNALIGNED-RV32-ZBB-NEXT:xor a0, a0, a1
+; CHECK-UNALIGNED-RV32-ZBB-NEXT:or a0, a2, a0

[llvm-branch-commits] [llvm] [RISCV] Support non-power-of-2 types when expanding memcmp (PR #114971)

2025-06-13 Thread Luke Lau via llvm-branch-commits 


@@ -2954,20 +2954,13 @@ RISCVTTIImpl::enableMemCmpExpansion(bool OptSize, bool 
IsZeroCmp) const {
   }
 
   if (IsZeroCmp && ST->hasVInstructions()) {
-unsigned RealMinVLen = ST->getRealMinVLen();
-// Support Fractional LMULs if the lengths are larger than XLen.
-// TODO: Support non-power-of-2 types.
-for (unsigned FLMUL = 8; FLMUL >= 2; FLMUL /= 2) {
-  unsigned Len = RealMinVLen / FLMUL;
-  if (Len > ST->getXLen())
-Options.LoadSizes.insert(Options.LoadSizes.begin(), Len / 8);
-}
-for (unsigned LMUL = 1; LMUL <= ST->getMaxLMULForFixedLengthVectors();
- LMUL *= 2) {
-  unsigned Len = RealMinVLen * LMUL;
-  if (Len > ST->getXLen())
-Options.LoadSizes.insert(Options.LoadSizes.begin(), Len / 8);
-}
+unsigned VLenB = ST->getRealMinVLen() / 8;
+// The minimum size should be the maximum bytes between `VLen * LMUL_MF8`
+// and `XLen * 2`.
+unsigned MinSize = std::max(VLenB / 8, ST->getXLen() * 2 / 8);

lukel97 wrote:

If that's the case, do we even need the LMUL check? I.e. can we just do 

```
unsigned MinSize = ST->getXLen() + 1;
```

And presumably for sizes < MF8, lowering will use the correct container anyway?

https://github.com/llvm/llvm-project/pull/114971
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[llvm-branch-commits] [llvm] [RISCV] Support non-power-of-2 types when expanding memcmp (PR #114971)

2025-06-13 Thread Pengcheng Wang via llvm-branch-commits 


@@ -2954,20 +2954,13 @@ RISCVTTIImpl::enableMemCmpExpansion(bool OptSize, bool 
IsZeroCmp) const {
   }
 
   if (IsZeroCmp && ST->hasVInstructions()) {
-unsigned RealMinVLen = ST->getRealMinVLen();
-// Support Fractional LMULs if the lengths are larger than XLen.
-// TODO: Support non-power-of-2 types.
-for (unsigned FLMUL = 8; FLMUL >= 2; FLMUL /= 2) {
-  unsigned Len = RealMinVLen / FLMUL;
-  if (Len > ST->getXLen())
-Options.LoadSizes.insert(Options.LoadSizes.begin(), Len / 8);
-}
-for (unsigned LMUL = 1; LMUL <= ST->getMaxLMULForFixedLengthVectors();
- LMUL *= 2) {
-  unsigned Len = RealMinVLen * LMUL;
-  if (Len > ST->getXLen())
-Options.LoadSizes.insert(Options.LoadSizes.begin(), Len / 8);
-}
+unsigned VLenB = ST->getRealMinVLen() / 8;
+// The minimum size should be the maximum bytes between `VLen * LMUL_MF8`
+// and `XLen * 2`.
+unsigned MinSize = std::max(VLenB / 8, ST->getXLen() * 2 / 8);

wangpc-pp wrote:

Oh, the commit history shows the reason: 
https://github.com/llvm/llvm-project/pull/114971/commits/5dfa889b2cf4ec49f2e4da2c3ff8a08610258193.
 But this should have been fixed by using VP nodes. It should be good now. :-)


https://github.com/llvm/llvm-project/pull/114971
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[llvm-branch-commits] [llvm] [RISCV] Support non-power-of-2 types when expanding memcmp (PR #114971)

2025-06-13 Thread Pengcheng Wang via llvm-branch-commits 


@@ -2954,20 +2954,13 @@ RISCVTTIImpl::enableMemCmpExpansion(bool OptSize, bool 
IsZeroCmp) const {
   }
 
   if (IsZeroCmp && ST->hasVInstructions()) {
-unsigned RealMinVLen = ST->getRealMinVLen();
-// Support Fractional LMULs if the lengths are larger than XLen.
-// TODO: Support non-power-of-2 types.
-for (unsigned FLMUL = 8; FLMUL >= 2; FLMUL /= 2) {
-  unsigned Len = RealMinVLen / FLMUL;
-  if (Len > ST->getXLen())
-Options.LoadSizes.insert(Options.LoadSizes.begin(), Len / 8);
-}
-for (unsigned LMUL = 1; LMUL <= ST->getMaxLMULForFixedLengthVectors();
- LMUL *= 2) {
-  unsigned Len = RealMinVLen * LMUL;
-  if (Len > ST->getXLen())
-Options.LoadSizes.insert(Options.LoadSizes.begin(), Len / 8);
-}
+unsigned VLenB = ST->getRealMinVLen() / 8;
+// The minimum size should be the maximum bytes between `VLen * LMUL_MF8`
+// and `XLen * 2`.
+unsigned MinSize = std::max(VLenB / 8, ST->getXLen() * 2 / 8);

wangpc-pp wrote:

It is `XLen + 1` now. IIRC, I saw some suspect CodeGen for sizes in `(XLen, 
XLen * 2)` at that time. But it seems to be normal now.

https://github.com/llvm/llvm-project/pull/114971
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[llvm-branch-commits] [llvm] [RISCV] Support non-power-of-2 types when expanding memcmp (PR #114971)

2025-06-13 Thread Pengcheng Wang via llvm-branch-commits 

https://github.com/wangpc-pp updated 
https://github.com/llvm/llvm-project/pull/114971

>From 3fd27bd1405a8b2c068786a200d610b9cacb65ef Mon Sep 17 00:00:00 2001
From: Wang Pengcheng 
Date: Tue, 5 Nov 2024 20:38:44 +0800
Subject: [PATCH 1/2] Set max bytes

Created using spr 1.3.6-beta.1
---
 llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp 
b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index c65feb9755633..a1c5f76bae009 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -2508,7 +2508,10 @@ RISCVTTIImpl::enableMemCmpExpansion(bool OptSize, bool 
IsZeroCmp) const {
 Options.LoadSizes = {4, 2, 1};
   if (IsZeroCmp && ST->hasVInstructions()) {
 unsigned VLenB = ST->getRealMinVLen() / 8;
-for (unsigned Size = ST->getXLen() / 8 + 1;
+// The minimum size should be the maximum bytes between `VLen * LMUL_MF8`
+// and `XLen + 8`.
+unsigned MinSize = std::max(VLenB / 8, ST->getXLen() / 8 + 1);
+for (unsigned Size = MinSize;
  Size <= VLenB * ST->getMaxLMULForFixedLengthVectors(); Size++)
   Options.LoadSizes.insert(Options.LoadSizes.begin(), Size);
   }

>From 17115212f1d7af68f5374896d1ddadf464b2bc11 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng 
Date: Fri, 13 Jun 2025 18:24:15 +0800
Subject: [PATCH 2/2] Change to XLen + 1

Created using spr 1.3.6-beta.1
---
 .../Target/RISCV/RISCVTargetTransformInfo.cpp |   4 +-
 llvm/test/CodeGen/RISCV/memcmp-optsize.ll | 324 +++---
 llvm/test/CodeGen/RISCV/memcmp.ll | 324 +++---
 3 files changed, 570 insertions(+), 82 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp 
b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index 4b9ea30a92c99..3aa0fcbb723a1 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -2956,8 +2956,8 @@ RISCVTTIImpl::enableMemCmpExpansion(bool OptSize, bool 
IsZeroCmp) const {
   if (IsZeroCmp && ST->hasVInstructions()) {
 unsigned VLenB = ST->getRealMinVLen() / 8;
 // The minimum size should be the maximum bytes between `VLen * LMUL_MF8`
-// and `XLen * 2`.
-unsigned MinSize = std::max(VLenB / 8, ST->getXLen() * 2 / 8);
+// and `XLen + 1`.
+unsigned MinSize = std::max(VLenB / 8, ST->getXLen() / 8 + 1);
 for (unsigned Size = MinSize;
  Size <= VLenB * ST->getMaxLMULForFixedLengthVectors(); Size++)
   Options.LoadSizes.insert(Options.LoadSizes.begin(), Size);
diff --git a/llvm/test/CodeGen/RISCV/memcmp-optsize.ll 
b/llvm/test/CodeGen/RISCV/memcmp-optsize.ll
index d4d12a932d0ec..0d57e4201512e 100644
--- a/llvm/test/CodeGen/RISCV/memcmp-optsize.ll
+++ b/llvm/test/CodeGen/RISCV/memcmp-optsize.ll
@@ -517,17 +517,99 @@ define i32 @bcmp_size_5(ptr %s1, ptr %s2) nounwind 
optsize {
 ; CHECK-ALIGNED-RV64-V-NEXT:addi sp, sp, 16
 ; CHECK-ALIGNED-RV64-V-NEXT:ret
 ;
-; CHECK-UNALIGNED-LABEL: bcmp_size_5:
-; CHECK-UNALIGNED:   # %bb.0: # %entry
-; CHECK-UNALIGNED-NEXT:lw a2, 0(a0)
-; CHECK-UNALIGNED-NEXT:lbu a0, 4(a0)
-; CHECK-UNALIGNED-NEXT:lw a3, 0(a1)
-; CHECK-UNALIGNED-NEXT:lbu a1, 4(a1)
-; CHECK-UNALIGNED-NEXT:xor a2, a2, a3
-; CHECK-UNALIGNED-NEXT:xor a0, a0, a1
-; CHECK-UNALIGNED-NEXT:or a0, a2, a0
-; CHECK-UNALIGNED-NEXT:snez a0, a0
-; CHECK-UNALIGNED-NEXT:ret
+; CHECK-UNALIGNED-RV32-LABEL: bcmp_size_5:
+; CHECK-UNALIGNED-RV32:   # %bb.0: # %entry
+; CHECK-UNALIGNED-RV32-NEXT:lw a2, 0(a0)
+; CHECK-UNALIGNED-RV32-NEXT:lbu a0, 4(a0)
+; CHECK-UNALIGNED-RV32-NEXT:lw a3, 0(a1)
+; CHECK-UNALIGNED-RV32-NEXT:lbu a1, 4(a1)
+; CHECK-UNALIGNED-RV32-NEXT:xor a2, a2, a3
+; CHECK-UNALIGNED-RV32-NEXT:xor a0, a0, a1
+; CHECK-UNALIGNED-RV32-NEXT:or a0, a2, a0
+; CHECK-UNALIGNED-RV32-NEXT:snez a0, a0
+; CHECK-UNALIGNED-RV32-NEXT:ret
+;
+; CHECK-UNALIGNED-RV64-LABEL: bcmp_size_5:
+; CHECK-UNALIGNED-RV64:   # %bb.0: # %entry
+; CHECK-UNALIGNED-RV64-NEXT:lw a2, 0(a0)
+; CHECK-UNALIGNED-RV64-NEXT:lbu a0, 4(a0)
+; CHECK-UNALIGNED-RV64-NEXT:lw a3, 0(a1)
+; CHECK-UNALIGNED-RV64-NEXT:lbu a1, 4(a1)
+; CHECK-UNALIGNED-RV64-NEXT:xor a2, a2, a3
+; CHECK-UNALIGNED-RV64-NEXT:xor a0, a0, a1
+; CHECK-UNALIGNED-RV64-NEXT:or a0, a2, a0
+; CHECK-UNALIGNED-RV64-NEXT:snez a0, a0
+; CHECK-UNALIGNED-RV64-NEXT:ret
+;
+; CHECK-UNALIGNED-RV32-ZBB-LABEL: bcmp_size_5:
+; CHECK-UNALIGNED-RV32-ZBB:   # %bb.0: # %entry
+; CHECK-UNALIGNED-RV32-ZBB-NEXT:lw a2, 0(a0)
+; CHECK-UNALIGNED-RV32-ZBB-NEXT:lbu a0, 4(a0)
+; CHECK-UNALIGNED-RV32-ZBB-NEXT:lw a3, 0(a1)
+; CHECK-UNALIGNED-RV32-ZBB-NEXT:lbu a1, 4(a1)
+; CHECK-UNALIGNED-RV32-ZBB-NEXT:xor a2, a2, a3
+; CHECK-UNALIGNED-RV32-ZBB-NEXT:xor a0, a0, a1
+; CHECK-UNALIGNED-RV32-ZBB-NEXT:or a0, a2, a0

[llvm-branch-commits] [llvm] [RISCV] Support non-power-of-2 types when expanding memcmp (PR #114971)

2025-06-13 Thread Pengcheng Wang via llvm-branch-commits 


@@ -2954,20 +2954,13 @@ RISCVTTIImpl::enableMemCmpExpansion(bool OptSize, bool 
IsZeroCmp) const {
   }
 
   if (IsZeroCmp && ST->hasVInstructions()) {
-unsigned RealMinVLen = ST->getRealMinVLen();
-// Support Fractional LMULs if the lengths are larger than XLen.
-// TODO: Support non-power-of-2 types.
-for (unsigned FLMUL = 8; FLMUL >= 2; FLMUL /= 2) {
-  unsigned Len = RealMinVLen / FLMUL;
-  if (Len > ST->getXLen())
-Options.LoadSizes.insert(Options.LoadSizes.begin(), Len / 8);
-}
-for (unsigned LMUL = 1; LMUL <= ST->getMaxLMULForFixedLengthVectors();
- LMUL *= 2) {
-  unsigned Len = RealMinVLen * LMUL;
-  if (Len > ST->getXLen())
-Options.LoadSizes.insert(Options.LoadSizes.begin(), Len / 8);
-}
+unsigned VLenB = ST->getRealMinVLen() / 8;
+// The minimum size should be the maximum bytes between `VLen * LMUL_MF8`
+// and `XLen * 2`.
+unsigned MinSize = std::max(VLenB / 8, ST->getXLen() * 2 / 8);

wangpc-pp wrote:

I remember I limited it with a reason but I forget the reason since it is 8 
months ago. I will check.

https://github.com/llvm/llvm-project/pull/114971
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[llvm-branch-commits] [llvm] [RISCV] Support non-power-of-2 types when expanding memcmp (PR #114971)

2025-06-13 Thread Pengcheng Wang via llvm-branch-commits 


@@ -2954,20 +2954,13 @@ RISCVTTIImpl::enableMemCmpExpansion(bool OptSize, bool 
IsZeroCmp) const {
   }
 
   if (IsZeroCmp && ST->hasVInstructions()) {
-unsigned RealMinVLen = ST->getRealMinVLen();
-// Support Fractional LMULs if the lengths are larger than XLen.
-// TODO: Support non-power-of-2 types.
-for (unsigned FLMUL = 8; FLMUL >= 2; FLMUL /= 2) {
-  unsigned Len = RealMinVLen / FLMUL;
-  if (Len > ST->getXLen())
-Options.LoadSizes.insert(Options.LoadSizes.begin(), Len / 8);
-}
-for (unsigned LMUL = 1; LMUL <= ST->getMaxLMULForFixedLengthVectors();
- LMUL *= 2) {
-  unsigned Len = RealMinVLen * LMUL;
-  if (Len > ST->getXLen())
-Options.LoadSizes.insert(Options.LoadSizes.begin(), Len / 8);
-}
+unsigned VLenB = ST->getRealMinVLen() / 8;
+// The minimum size should be the maximum bytes between `VLen * LMUL_MF8`
+// and `XLen * 2`.
+unsigned MinSize = std::max(VLenB / 8, ST->getXLen() * 2 / 8);

wangpc-pp wrote:

IIUC, it is YES.

https://github.com/llvm/llvm-project/pull/114971
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[llvm-branch-commits] [llvm] [RISCV] Support non-power-of-2 types when expanding memcmp (PR #114971)

2025-06-13 Thread Luke Lau via llvm-branch-commits 


@@ -2954,20 +2954,13 @@ RISCVTTIImpl::enableMemCmpExpansion(bool OptSize, bool 
IsZeroCmp) const {
   }
 
   if (IsZeroCmp && ST->hasVInstructions()) {
-unsigned RealMinVLen = ST->getRealMinVLen();
-// Support Fractional LMULs if the lengths are larger than XLen.
-// TODO: Support non-power-of-2 types.
-for (unsigned FLMUL = 8; FLMUL >= 2; FLMUL /= 2) {
-  unsigned Len = RealMinVLen / FLMUL;
-  if (Len > ST->getXLen())
-Options.LoadSizes.insert(Options.LoadSizes.begin(), Len / 8);
-}
-for (unsigned LMUL = 1; LMUL <= ST->getMaxLMULForFixedLengthVectors();
- LMUL *= 2) {
-  unsigned Len = RealMinVLen * LMUL;
-  if (Len > ST->getXLen())
-Options.LoadSizes.insert(Options.LoadSizes.begin(), Len / 8);
-}
+unsigned VLenB = ST->getRealMinVLen() / 8;
+// The minimum size should be the maximum bytes between `VLen * LMUL_MF8`
+// and `XLen * 2`.
+unsigned MinSize = std::max(VLenB / 8, ST->getXLen() * 2 / 8);

lukel97 wrote:

Just checking, if MF8 isn't supported for the ELEN, e.g. MF8 on zve32x, 
`getContainerForFixedLengthVector` in RISCVISelLowering will still lower it 
into the next largest LMUL so this should be fine right?


https://github.com/llvm/llvm-project/pull/114971
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[llvm-branch-commits] [llvm] [RISCV] Support non-power-of-2 types when expanding memcmp (PR #114971)

2025-06-13 Thread Luke Lau via llvm-branch-commits 


@@ -2954,20 +2954,13 @@ RISCVTTIImpl::enableMemCmpExpansion(bool OptSize, bool 
IsZeroCmp) const {
   }
 
   if (IsZeroCmp && ST->hasVInstructions()) {
-unsigned RealMinVLen = ST->getRealMinVLen();
-// Support Fractional LMULs if the lengths are larger than XLen.
-// TODO: Support non-power-of-2 types.
-for (unsigned FLMUL = 8; FLMUL >= 2; FLMUL /= 2) {
-  unsigned Len = RealMinVLen / FLMUL;
-  if (Len > ST->getXLen())
-Options.LoadSizes.insert(Options.LoadSizes.begin(), Len / 8);
-}
-for (unsigned LMUL = 1; LMUL <= ST->getMaxLMULForFixedLengthVectors();
- LMUL *= 2) {
-  unsigned Len = RealMinVLen * LMUL;
-  if (Len > ST->getXLen())
-Options.LoadSizes.insert(Options.LoadSizes.begin(), Len / 8);
-}
+unsigned VLenB = ST->getRealMinVLen() / 8;
+// The minimum size should be the maximum bytes between `VLen * LMUL_MF8`
+// and `XLen * 2`.
+unsigned MinSize = std::max(VLenB / 8, ST->getXLen() * 2 / 8);

lukel97 wrote:

How come we need to limit the minimum size to XLen * 2? Can we not use vectors 
for the `bcmp_size_15` test case on RV64 too?

https://github.com/llvm/llvm-project/pull/114971
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[llvm-branch-commits] [llvm] [RISCV] Support non-power-of-2 types when expanding memcmp (PR #114971)

2025-06-13 Thread Pengcheng Wang via llvm-branch-commits 

wangpc-pp wrote:

Oh, I forgot that. Can you please test the performance impact on BPI-F3? 
@lukel97

https://github.com/llvm/llvm-project/pull/114971
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[llvm-branch-commits] [llvm] [RISCV] Support non-power-of-2 types when expanding memcmp (PR #114971)

2025-06-13 Thread Pengcheng Wang via llvm-branch-commits 

https://github.com/wangpc-pp updated 
https://github.com/llvm/llvm-project/pull/114971

>From 3fd27bd1405a8b2c068786a200d610b9cacb65ef Mon Sep 17 00:00:00 2001
From: Wang Pengcheng 
Date: Tue, 5 Nov 2024 20:38:44 +0800
Subject: [PATCH] Set max bytes

Created using spr 1.3.6-beta.1
---
 llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp 
b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index c65feb9755633..a1c5f76bae009 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -2508,7 +2508,10 @@ RISCVTTIImpl::enableMemCmpExpansion(bool OptSize, bool 
IsZeroCmp) const {
 Options.LoadSizes = {4, 2, 1};
   if (IsZeroCmp && ST->hasVInstructions()) {
 unsigned VLenB = ST->getRealMinVLen() / 8;
-for (unsigned Size = ST->getXLen() / 8 + 1;
+// The minimum size should be the maximum bytes between `VLen * LMUL_MF8`
+// and `XLen + 8`.
+unsigned MinSize = std::max(VLenB / 8, ST->getXLen() / 8 + 1);
+for (unsigned Size = MinSize;
  Size <= VLenB * ST->getMaxLMULForFixedLengthVectors(); Size++)
   Options.LoadSizes.insert(Options.LoadSizes.begin(), Size);
   }

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[llvm-branch-commits] [llvm] [RISCV] Support non-power-of-2 types when expanding memcmp (PR #114971)

2025-06-13 Thread Pengcheng Wang via llvm-branch-commits 

https://github.com/wangpc-pp updated 
https://github.com/llvm/llvm-project/pull/114971

>From 3fd27bd1405a8b2c068786a200d610b9cacb65ef Mon Sep 17 00:00:00 2001
From: Wang Pengcheng 
Date: Tue, 5 Nov 2024 20:38:44 +0800
Subject: [PATCH] Set max bytes

Created using spr 1.3.6-beta.1
---
 llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp 
b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index c65feb9755633..a1c5f76bae009 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -2508,7 +2508,10 @@ RISCVTTIImpl::enableMemCmpExpansion(bool OptSize, bool 
IsZeroCmp) const {
 Options.LoadSizes = {4, 2, 1};
   if (IsZeroCmp && ST->hasVInstructions()) {
 unsigned VLenB = ST->getRealMinVLen() / 8;
-for (unsigned Size = ST->getXLen() / 8 + 1;
+// The minimum size should be the maximum bytes between `VLen * LMUL_MF8`
+// and `XLen + 8`.
+unsigned MinSize = std::max(VLenB / 8, ST->getXLen() / 8 + 1);
+for (unsigned Size = MinSize;
  Size <= VLenB * ST->getMaxLMULForFixedLengthVectors(); Size++)
   Options.LoadSizes.insert(Options.LoadSizes.begin(), Size);
   }

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[llvm-branch-commits] [llvm] [RISCV] Support non-power-of-2 types when expanding memcmp (PR #114971)

2025-06-12 Thread Pengcheng Wang via llvm-branch-commits 


@@ -16190,13 +16186,20 @@ combineVectorSizedSetCCEquality(EVT VT, SDValue X, 
SDValue Y, ISD::CondCode CC,
 return SDValue();
 
   unsigned VecSize = OpSize / 8;
-  EVT VecVT = MVT::getVectorVT(MVT::i8, VecSize);
-  EVT CmpVT = MVT::getVectorVT(MVT::i1, VecSize);
+  EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i8, VecSize);
+  EVT CmpVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, VecSize);
 
   SDValue VecX = DAG.getBitcast(VecVT, X);
   SDValue VecY = DAG.getBitcast(VecVT, Y);
-  SDValue Cmp = DAG.getSetCC(DL, CmpVT, VecX, VecY, ISD::SETNE);
-  return DAG.getSetCC(DL, VT, DAG.getNode(ISD::VECREDUCE_OR, DL, XLenVT, Cmp),
+  SDValue Mask = DAG.getAllOnesConstant(DL, CmpVT);
+  SDValue VL = DAG.getConstant(VecSize, DL, XLenVT);
+
+  SDValue Cmp = DAG.getNode(ISD::VP_SETCC, DL, CmpVT, VecX, VecY,
+DAG.getCondCode(ISD::SETNE), Mask, VL);
+  return DAG.getSetCC(DL, VT,
+  DAG.getNode(ISD::VP_REDUCE_OR, DL, XLenVT,
+  DAG.getConstant(0, DL, XLenVT), Cmp, Mask,
+  VL),

wangpc-pp wrote:

I think so, because this PR was done several months later after that commit. 

https://github.com/llvm/llvm-project/pull/114971
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[llvm-branch-commits] [llvm] [RISCV] Support non-power-of-2 types when expanding memcmp (PR #114971)

2025-06-12 Thread Pengcheng Wang via llvm-branch-commits 

https://github.com/wangpc-pp updated 
https://github.com/llvm/llvm-project/pull/114971

>From 3fd27bd1405a8b2c068786a200d610b9cacb65ef Mon Sep 17 00:00:00 2001
From: Wang Pengcheng 
Date: Tue, 5 Nov 2024 20:38:44 +0800
Subject: [PATCH] Set max bytes

Created using spr 1.3.6-beta.1
---
 llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp 
b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index c65feb9755633..a1c5f76bae009 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -2508,7 +2508,10 @@ RISCVTTIImpl::enableMemCmpExpansion(bool OptSize, bool 
IsZeroCmp) const {
 Options.LoadSizes = {4, 2, 1};
   if (IsZeroCmp && ST->hasVInstructions()) {
 unsigned VLenB = ST->getRealMinVLen() / 8;
-for (unsigned Size = ST->getXLen() / 8 + 1;
+// The minimum size should be the maximum bytes between `VLen * LMUL_MF8`
+// and `XLen + 8`.
+unsigned MinSize = std::max(VLenB / 8, ST->getXLen() / 8 + 1);
+for (unsigned Size = MinSize;
  Size <= VLenB * ST->getMaxLMULForFixedLengthVectors(); Size++)
   Options.LoadSizes.insert(Options.LoadSizes.begin(), Size);
   }

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[llvm-branch-commits] [llvm] [RISCV] Support non-power-of-2 types when expanding memcmp (PR #114971)

2025-06-12 Thread Pengcheng Wang via llvm-branch-commits 

https://github.com/wangpc-pp updated 
https://github.com/llvm/llvm-project/pull/114971

>From 3fd27bd1405a8b2c068786a200d610b9cacb65ef Mon Sep 17 00:00:00 2001
From: Wang Pengcheng 
Date: Tue, 5 Nov 2024 20:38:44 +0800
Subject: [PATCH] Set max bytes

Created using spr 1.3.6-beta.1
---
 llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp 
b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index c65feb9755633..a1c5f76bae009 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -2508,7 +2508,10 @@ RISCVTTIImpl::enableMemCmpExpansion(bool OptSize, bool 
IsZeroCmp) const {
 Options.LoadSizes = {4, 2, 1};
   if (IsZeroCmp && ST->hasVInstructions()) {
 unsigned VLenB = ST->getRealMinVLen() / 8;
-for (unsigned Size = ST->getXLen() / 8 + 1;
+// The minimum size should be the maximum bytes between `VLen * LMUL_MF8`
+// and `XLen + 8`.
+unsigned MinSize = std::max(VLenB / 8, ST->getXLen() / 8 + 1);
+for (unsigned Size = MinSize;
  Size <= VLenB * ST->getMaxLMULForFixedLengthVectors(); Size++)
   Options.LoadSizes.insert(Options.LoadSizes.begin(), Size);
   }

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[llvm-branch-commits] [llvm] [RISCV] Support non-power-of-2 types when expanding memcmp (PR #114971)

2025-06-12 Thread Pengcheng Wang via llvm-branch-commits 

https://github.com/wangpc-pp updated 
https://github.com/llvm/llvm-project/pull/114971

>From 3fd27bd1405a8b2c068786a200d610b9cacb65ef Mon Sep 17 00:00:00 2001
From: Wang Pengcheng 
Date: Tue, 5 Nov 2024 20:38:44 +0800
Subject: [PATCH] Set max bytes

Created using spr 1.3.6-beta.1
---
 llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp 
b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index c65feb9755633..a1c5f76bae009 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -2508,7 +2508,10 @@ RISCVTTIImpl::enableMemCmpExpansion(bool OptSize, bool 
IsZeroCmp) const {
 Options.LoadSizes = {4, 2, 1};
   if (IsZeroCmp && ST->hasVInstructions()) {
 unsigned VLenB = ST->getRealMinVLen() / 8;
-for (unsigned Size = ST->getXLen() / 8 + 1;
+// The minimum size should be the maximum bytes between `VLen * LMUL_MF8`
+// and `XLen + 8`.
+unsigned MinSize = std::max(VLenB / 8, ST->getXLen() / 8 + 1);
+for (unsigned Size = MinSize;
  Size <= VLenB * ST->getMaxLMULForFixedLengthVectors(); Size++)
   Options.LoadSizes.insert(Options.LoadSizes.begin(), Size);
   }

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[llvm-branch-commits] [llvm] [RISCV] Support non-power-of-2 types when expanding memcmp (PR #114971)

2024-11-06 Thread Pengcheng Wang via llvm-branch-commits 


@@ -1069,21 +1069,14 @@ define i32 @bcmp_size_15(ptr %s1, ptr %s2) nounwind 
optsize {
 ;
 ; CHECK-UNALIGNED-RV32-V-LABEL: bcmp_size_15:
 ; CHECK-UNALIGNED-RV32-V:   # %bb.0: # %entry
-; CHECK-UNALIGNED-RV32-V-NEXT:lw a2, 0(a0)
-; CHECK-UNALIGNED-RV32-V-NEXT:lw a3, 4(a0)
-; CHECK-UNALIGNED-RV32-V-NEXT:lw a4, 7(a0)
-; CHECK-UNALIGNED-RV32-V-NEXT:lw a0, 11(a0)
-; CHECK-UNALIGNED-RV32-V-NEXT:lw a5, 0(a1)
-; CHECK-UNALIGNED-RV32-V-NEXT:lw a6, 4(a1)
-; CHECK-UNALIGNED-RV32-V-NEXT:lw a7, 7(a1)
-; CHECK-UNALIGNED-RV32-V-NEXT:lw a1, 11(a1)
-; CHECK-UNALIGNED-RV32-V-NEXT:xor a2, a2, a5
-; CHECK-UNALIGNED-RV32-V-NEXT:xor a3, a3, a6
-; CHECK-UNALIGNED-RV32-V-NEXT:xor a4, a4, a7
-; CHECK-UNALIGNED-RV32-V-NEXT:xor a0, a0, a1
-; CHECK-UNALIGNED-RV32-V-NEXT:or a0, a3, a0
-; CHECK-UNALIGNED-RV32-V-NEXT:or a2, a2, a4
-; CHECK-UNALIGNED-RV32-V-NEXT:or a0, a2, a0
+; CHECK-UNALIGNED-RV32-V-NEXT:vsetivli zero, 15, e8, m1, ta, ma
+; CHECK-UNALIGNED-RV32-V-NEXT:vle8.v v8, (a0)
+; CHECK-UNALIGNED-RV32-V-NEXT:vle8.v v9, (a1)
+; CHECK-UNALIGNED-RV32-V-NEXT:vsetivli zero, 16, e8, m1, ta, ma
+; CHECK-UNALIGNED-RV32-V-NEXT:vmset.m v0
+; CHECK-UNALIGNED-RV32-V-NEXT:vmsne.vv v8, v8, v9
+; CHECK-UNALIGNED-RV32-V-NEXT:vsetivli zero, 15, e8, m1, ta, ma
+; CHECK-UNALIGNED-RV32-V-NEXT:vcpop.m a0, v8, v0.t

wangpc-pp wrote:

Nope, it doesn't work. We should fix it in another place.

https://github.com/llvm/llvm-project/pull/114971
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[llvm-branch-commits] [llvm] [RISCV] Support non-power-of-2 types when expanding memcmp (PR #114971)

2024-11-06 Thread Pengcheng Wang via llvm-branch-commits 


@@ -1069,21 +1069,14 @@ define i32 @bcmp_size_15(ptr %s1, ptr %s2) nounwind 
optsize {
 ;
 ; CHECK-UNALIGNED-RV32-V-LABEL: bcmp_size_15:
 ; CHECK-UNALIGNED-RV32-V:   # %bb.0: # %entry
-; CHECK-UNALIGNED-RV32-V-NEXT:lw a2, 0(a0)
-; CHECK-UNALIGNED-RV32-V-NEXT:lw a3, 4(a0)
-; CHECK-UNALIGNED-RV32-V-NEXT:lw a4, 7(a0)
-; CHECK-UNALIGNED-RV32-V-NEXT:lw a0, 11(a0)
-; CHECK-UNALIGNED-RV32-V-NEXT:lw a5, 0(a1)
-; CHECK-UNALIGNED-RV32-V-NEXT:lw a6, 4(a1)
-; CHECK-UNALIGNED-RV32-V-NEXT:lw a7, 7(a1)
-; CHECK-UNALIGNED-RV32-V-NEXT:lw a1, 11(a1)
-; CHECK-UNALIGNED-RV32-V-NEXT:xor a2, a2, a5
-; CHECK-UNALIGNED-RV32-V-NEXT:xor a3, a3, a6
-; CHECK-UNALIGNED-RV32-V-NEXT:xor a4, a4, a7
-; CHECK-UNALIGNED-RV32-V-NEXT:xor a0, a0, a1
-; CHECK-UNALIGNED-RV32-V-NEXT:or a0, a3, a0
-; CHECK-UNALIGNED-RV32-V-NEXT:or a2, a2, a4
-; CHECK-UNALIGNED-RV32-V-NEXT:or a0, a2, a0
+; CHECK-UNALIGNED-RV32-V-NEXT:vsetivli zero, 15, e8, m1, ta, ma
+; CHECK-UNALIGNED-RV32-V-NEXT:vle8.v v8, (a0)
+; CHECK-UNALIGNED-RV32-V-NEXT:vle8.v v9, (a1)
+; CHECK-UNALIGNED-RV32-V-NEXT:vsetivli zero, 16, e8, m1, ta, ma
+; CHECK-UNALIGNED-RV32-V-NEXT:vmset.m v0
+; CHECK-UNALIGNED-RV32-V-NEXT:vmsne.vv v8, v8, v9
+; CHECK-UNALIGNED-RV32-V-NEXT:vsetivli zero, 15, e8, m1, ta, ma
+; CHECK-UNALIGNED-RV32-V-NEXT:vcpop.m a0, v8, v0.t

wangpc-pp wrote:

I think this is the lowering of `ISD::VECREDUCE_OR` nodes.
The `VL` parameter comes from `getDefaultVLOps` and its value is 16 because the 
vector type `v15i8` has been widened to `v16i8`.
We may use `VP_REDUCE_OR` here.

https://github.com/llvm/llvm-project/pull/114971
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[llvm-branch-commits] [llvm] [RISCV] Support non-power-of-2 types when expanding memcmp (PR #114971)

2024-11-06 Thread Pengcheng Wang via llvm-branch-commits 


@@ -1069,21 +1069,14 @@ define i32 @bcmp_size_15(ptr %s1, ptr %s2) nounwind 
optsize {
 ;
 ; CHECK-UNALIGNED-RV32-V-LABEL: bcmp_size_15:
 ; CHECK-UNALIGNED-RV32-V:   # %bb.0: # %entry
-; CHECK-UNALIGNED-RV32-V-NEXT:lw a2, 0(a0)
-; CHECK-UNALIGNED-RV32-V-NEXT:lw a3, 4(a0)
-; CHECK-UNALIGNED-RV32-V-NEXT:lw a4, 7(a0)
-; CHECK-UNALIGNED-RV32-V-NEXT:lw a0, 11(a0)
-; CHECK-UNALIGNED-RV32-V-NEXT:lw a5, 0(a1)
-; CHECK-UNALIGNED-RV32-V-NEXT:lw a6, 4(a1)
-; CHECK-UNALIGNED-RV32-V-NEXT:lw a7, 7(a1)
-; CHECK-UNALIGNED-RV32-V-NEXT:lw a1, 11(a1)
-; CHECK-UNALIGNED-RV32-V-NEXT:xor a2, a2, a5
-; CHECK-UNALIGNED-RV32-V-NEXT:xor a3, a3, a6
-; CHECK-UNALIGNED-RV32-V-NEXT:xor a4, a4, a7
-; CHECK-UNALIGNED-RV32-V-NEXT:xor a0, a0, a1
-; CHECK-UNALIGNED-RV32-V-NEXT:or a0, a3, a0
-; CHECK-UNALIGNED-RV32-V-NEXT:or a2, a2, a4
-; CHECK-UNALIGNED-RV32-V-NEXT:or a0, a2, a0
+; CHECK-UNALIGNED-RV32-V-NEXT:vsetivli zero, 15, e8, m1, ta, ma
+; CHECK-UNALIGNED-RV32-V-NEXT:vle8.v v8, (a0)
+; CHECK-UNALIGNED-RV32-V-NEXT:vle8.v v9, (a1)
+; CHECK-UNALIGNED-RV32-V-NEXT:vsetivli zero, 16, e8, m1, ta, ma
+; CHECK-UNALIGNED-RV32-V-NEXT:vmset.m v0
+; CHECK-UNALIGNED-RV32-V-NEXT:vmsne.vv v8, v8, v9
+; CHECK-UNALIGNED-RV32-V-NEXT:vsetivli zero, 15, e8, m1, ta, ma
+; CHECK-UNALIGNED-RV32-V-NEXT:vcpop.m a0, v8, v0.t

wangpc-pp wrote:

This should be fixed by using VP nodes and #115162.

https://github.com/llvm/llvm-project/pull/114971
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[llvm-branch-commits] [llvm] [RISCV] Support non-power-of-2 types when expanding memcmp (PR #114971)

2024-11-06 Thread Pengcheng Wang via llvm-branch-commits 

https://github.com/wangpc-pp updated 
https://github.com/llvm/llvm-project/pull/114971

>From 3fd27bd1405a8b2c068786a200d610b9cacb65ef Mon Sep 17 00:00:00 2001
From: Wang Pengcheng 
Date: Tue, 5 Nov 2024 20:38:44 +0800
Subject: [PATCH] Set max bytes

Created using spr 1.3.6-beta.1
---
 llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp 
b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index c65feb9755633c..a1c5f76bae0099 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -2508,7 +2508,10 @@ RISCVTTIImpl::enableMemCmpExpansion(bool OptSize, bool 
IsZeroCmp) const {
 Options.LoadSizes = {4, 2, 1};
   if (IsZeroCmp && ST->hasVInstructions()) {
 unsigned VLenB = ST->getRealMinVLen() / 8;
-for (unsigned Size = ST->getXLen() / 8 + 1;
+// The minimum size should be the maximum bytes between `VLen * LMUL_MF8`
+// and `XLen + 8`.
+unsigned MinSize = std::max(VLenB / 8, ST->getXLen() / 8 + 1);
+for (unsigned Size = MinSize;
  Size <= VLenB * ST->getMaxLMULForFixedLengthVectors(); Size++)
   Options.LoadSizes.insert(Options.LoadSizes.begin(), Size);
   }

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[llvm-branch-commits] [llvm] [RISCV] Support non-power-of-2 types when expanding memcmp (PR #114971)

2024-11-06 Thread Pengcheng Wang via llvm-branch-commits 

https://github.com/wangpc-pp updated 
https://github.com/llvm/llvm-project/pull/114971

>From 3fd27bd1405a8b2c068786a200d610b9cacb65ef Mon Sep 17 00:00:00 2001
From: Wang Pengcheng 
Date: Tue, 5 Nov 2024 20:38:44 +0800
Subject: [PATCH] Set max bytes

Created using spr 1.3.6-beta.1
---
 llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp 
b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index c65feb9755633c..a1c5f76bae0099 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -2508,7 +2508,10 @@ RISCVTTIImpl::enableMemCmpExpansion(bool OptSize, bool 
IsZeroCmp) const {
 Options.LoadSizes = {4, 2, 1};
   if (IsZeroCmp && ST->hasVInstructions()) {
 unsigned VLenB = ST->getRealMinVLen() / 8;
-for (unsigned Size = ST->getXLen() / 8 + 1;
+// The minimum size should be the maximum bytes between `VLen * LMUL_MF8`
+// and `XLen + 8`.
+unsigned MinSize = std::max(VLenB / 8, ST->getXLen() / 8 + 1);
+for (unsigned Size = MinSize;
  Size <= VLenB * ST->getMaxLMULForFixedLengthVectors(); Size++)
   Options.LoadSizes.insert(Options.LoadSizes.begin(), Size);
   }

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[llvm-branch-commits] [llvm] [RISCV] Support non-power-of-2 types when expanding memcmp (PR #114971)

2024-11-06 Thread Pengcheng Wang via llvm-branch-commits 

https://github.com/wangpc-pp updated 
https://github.com/llvm/llvm-project/pull/114971

>From 3fd27bd1405a8b2c068786a200d610b9cacb65ef Mon Sep 17 00:00:00 2001
From: Wang Pengcheng 
Date: Tue, 5 Nov 2024 20:38:44 +0800
Subject: [PATCH] Set max bytes

Created using spr 1.3.6-beta.1
---
 llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp 
b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index c65feb9755633c..a1c5f76bae0099 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -2508,7 +2508,10 @@ RISCVTTIImpl::enableMemCmpExpansion(bool OptSize, bool 
IsZeroCmp) const {
 Options.LoadSizes = {4, 2, 1};
   if (IsZeroCmp && ST->hasVInstructions()) {
 unsigned VLenB = ST->getRealMinVLen() / 8;
-for (unsigned Size = ST->getXLen() / 8 + 1;
+// The minimum size should be the maximum bytes between `VLen * LMUL_MF8`
+// and `XLen + 8`.
+unsigned MinSize = std::max(VLenB / 8, ST->getXLen() / 8 + 1);
+for (unsigned Size = MinSize;
  Size <= VLenB * ST->getMaxLMULForFixedLengthVectors(); Size++)
   Options.LoadSizes.insert(Options.LoadSizes.begin(), Size);
   }

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[llvm-branch-commits] [llvm] [RISCV] Support non-power-of-2 types when expanding memcmp (PR #114971)

2024-11-06 Thread Pengcheng Wang via llvm-branch-commits 

https://github.com/wangpc-pp updated 
https://github.com/llvm/llvm-project/pull/114971

>From 3fd27bd1405a8b2c068786a200d610b9cacb65ef Mon Sep 17 00:00:00 2001
From: Wang Pengcheng 
Date: Tue, 5 Nov 2024 20:38:44 +0800
Subject: [PATCH] Set max bytes

Created using spr 1.3.6-beta.1
---
 llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp 
b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index c65feb9755633c..a1c5f76bae0099 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -2508,7 +2508,10 @@ RISCVTTIImpl::enableMemCmpExpansion(bool OptSize, bool 
IsZeroCmp) const {
 Options.LoadSizes = {4, 2, 1};
   if (IsZeroCmp && ST->hasVInstructions()) {
 unsigned VLenB = ST->getRealMinVLen() / 8;
-for (unsigned Size = ST->getXLen() / 8 + 1;
+// The minimum size should be the maximum bytes between `VLen * LMUL_MF8`
+// and `XLen + 8`.
+unsigned MinSize = std::max(VLenB / 8, ST->getXLen() / 8 + 1);
+for (unsigned Size = MinSize;
  Size <= VLenB * ST->getMaxLMULForFixedLengthVectors(); Size++)
   Options.LoadSizes.insert(Options.LoadSizes.begin(), Size);
   }

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[llvm-branch-commits] [llvm] [RISCV] Support non-power-of-2 types when expanding memcmp (PR #114971)

2024-11-05 Thread Pengcheng Wang via llvm-branch-commits 

https://github.com/wangpc-pp updated 
https://github.com/llvm/llvm-project/pull/114971

>From 3fd27bd1405a8b2c068786a200d610b9cacb65ef Mon Sep 17 00:00:00 2001
From: Wang Pengcheng 
Date: Tue, 5 Nov 2024 20:38:44 +0800
Subject: [PATCH] Set max bytes

Created using spr 1.3.6-beta.1
---
 llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp 
b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index c65feb9755633c..a1c5f76bae0099 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -2508,7 +2508,10 @@ RISCVTTIImpl::enableMemCmpExpansion(bool OptSize, bool 
IsZeroCmp) const {
 Options.LoadSizes = {4, 2, 1};
   if (IsZeroCmp && ST->hasVInstructions()) {
 unsigned VLenB = ST->getRealMinVLen() / 8;
-for (unsigned Size = ST->getXLen() / 8 + 1;
+// The minimum size should be the maximum bytes between `VLen * LMUL_MF8`
+// and `XLen + 8`.
+unsigned MinSize = std::max(VLenB / 8, ST->getXLen() / 8 + 1);
+for (unsigned Size = MinSize;
  Size <= VLenB * ST->getMaxLMULForFixedLengthVectors(); Size++)
   Options.LoadSizes.insert(Options.LoadSizes.begin(), Size);
   }

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