[llvm-branch-commits] [llvm] AMDGPU: Move default wavesize hack for disassembler (PR #117422)

2024-11-23 Thread Matt Arsenault via llvm-branch-commits 

arsenm wrote:

### Merge activity

* **Nov 23, 12:16 PM EST**: A user started a stack merge that includes this 
pull request via 
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/117422).


https://github.com/llvm/llvm-project/pull/117422
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[llvm-branch-commits] [llvm] AMDGPU: Move default wavesize hack for disassembler (PR #117422)

2024-11-23 Thread Matt Arsenault via llvm-branch-commits 

https://github.com/arsenm updated 
https://github.com/llvm/llvm-project/pull/117422

>From 8c742b89a174e49f5ba6b48ca7812e9645dd Mon Sep 17 00:00:00 2001
From: Matt Arsenault 
Date: Fri, 22 Nov 2024 20:17:48 -0800
Subject: [PATCH] AMDGPU: Move default wavesize hack for disassembler

You cannot adjust the disassembler's subtarget. llvm-mc passes
the originally constructed MCSubtargetInfo around, rather than
querying the pointer in the disassembler instance.
---
 .../Disassembler/AMDGPUDisassembler.cpp   | 20 ++-
 .../MCTargetDesc/AMDGPUMCTargetDesc.cpp   | 17 +++-
 llvm/test/MC/AMDGPU/unknown-target-cpu.s  |  5 +++--
 3 files changed, 21 insertions(+), 21 deletions(-)

diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp 
b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
index f90121a86c846c..7817c5ff5acc0a 100644
--- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
+++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
@@ -45,26 +45,10 @@ using namespace llvm;
 
 using DecodeStatus = llvm::MCDisassembler::DecodeStatus;
 
-static const MCSubtargetInfo &addDefaultWaveSize(const MCSubtargetInfo &STI,
- MCContext &Ctx) {
-  if (!STI.hasFeature(AMDGPU::FeatureWavefrontSize64) &&
-  !STI.hasFeature(AMDGPU::FeatureWavefrontSize32)) {
-MCSubtargetInfo &STICopy = Ctx.getSubtargetCopy(STI);
-// If there is no default wave size it must be a generation before gfx10,
-// these have FeatureWavefrontSize64 in their definition already. For 
gfx10+
-// set wave32 as a default.
-STICopy.ToggleFeature(AMDGPU::FeatureWavefrontSize32);
-return STICopy;
-  }
-
-  return STI;
-}
-
 AMDGPUDisassembler::AMDGPUDisassembler(const MCSubtargetInfo &STI,
MCContext &Ctx, MCInstrInfo const *MCII)
-: MCDisassembler(addDefaultWaveSize(STI, Ctx), Ctx), MCII(MCII),
-  MRI(*Ctx.getRegisterInfo()), MAI(*Ctx.getAsmInfo()),
-  TargetMaxInstBytes(MAI.getMaxInstLength(&STI)),
+: MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()),
+  MAI(*Ctx.getAsmInfo()), TargetMaxInstBytes(MAI.getMaxInstLength(&STI)),
   CodeObjectVersion(AMDGPU::getDefaultAMDHSACodeObjectVersion()) {
   // ToDo: AMDGPUDisassembler supports only VI ISA.
   if (!STI.hasFeature(AMDGPU::FeatureGCN3Encoding) && !isGFX10Plus())
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp 
b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp
index 29be64625811f7..c692895d84c002 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp
@@ -77,7 +77,22 @@ static MCSubtargetInfo *
 createAMDGPUMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
   if (TT.getArch() == Triple::r600)
 return createR600MCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
-  return createAMDGPUMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
+
+  MCSubtargetInfo *STI =
+  createAMDGPUMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
+
+  // FIXME: We should error for the default target.
+  if (!STI->hasFeature(AMDGPU::FeatureWavefrontSize64) &&
+  !STI->hasFeature(AMDGPU::FeatureWavefrontSize32)) {
+// If there is no default wave size it must be a generation before gfx10,
+// these have FeatureWavefrontSize64 in their definition already. For 
gfx10+
+// set wave32 as a default.
+STI->ToggleFeature(AMDGPU::isGFX10Plus(*STI)
+   ? AMDGPU::FeatureWavefrontSize32
+   : AMDGPU::FeatureWavefrontSize64);
+  }
+
+  return STI;
 }
 
 static MCInstPrinter *createAMDGPUMCInstPrinter(const Triple &T,
diff --git a/llvm/test/MC/AMDGPU/unknown-target-cpu.s 
b/llvm/test/MC/AMDGPU/unknown-target-cpu.s
index b671770084a1fc..3d41e8eb5b2c45 100644
--- a/llvm/test/MC/AMDGPU/unknown-target-cpu.s
+++ b/llvm/test/MC/AMDGPU/unknown-target-cpu.s
@@ -1,4 +1,5 @@
-// RUN: llvm-mc -triple=amdgcn -show-encoding < %s | FileCheck %s
+// RUN: not llvm-mc -triple=amdgcn -show-encoding < %s | FileCheck %s
+// RUN: not llvm-mc -triple=amdgcn -show-encoding -filetype=null %s 2>&1 | 
FileCheck -check-prefix=ERR %s
 // RUN: llvm-mc -triple=amdgcn -mcpu=tahiti -show-encoding < %s | FileCheck %s
 
 // CHECK: v_cmp_lt_f32_e32 vcc, s2, v4; encoding: 
[0x02,0x08,0x02,0x7c]
@@ -7,7 +8,7 @@ v_cmp_lt_f32 vcc, s2, v4
 // CHECK: v_cndmask_b32_e32 v1, v2, v3, vcc   ; encoding: 
[0x02,0x07,0x02,0x00]
 v_cndmask_b32 v1, v2, v3, vcc
 
-// CHECK: v_mac_legacy_f32_e64 v1, v3, s5 ; encoding: 
[0x01,0x00,0x0c,0xd2,0x03,0x0b,0x00,0x00]
+// ERR: [[@LINE+1]]:1: error: instruction not supported on this GPU
 v_mac_legacy_f32 v1, v3, s5
 
 // CHECK: v_lshr_b32_e32 v0, v1, v2   ; encoding: 
[0x01,0x05,0x00,0x2a]

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[llvm-branch-commits] [llvm] AMDGPU: Move default wavesize hack for disassembler (PR #117422)

2024-11-23 Thread Joseph Huber via llvm-branch-commits 

https://github.com/jhuber6 approved this pull request.


https://github.com/llvm/llvm-project/pull/117422
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[llvm-branch-commits] [llvm] AMDGPU: Move default wavesize hack for disassembler (PR #117422)

2024-11-22 Thread via llvm-branch-commits 

llvmbot wrote:




@llvm/pr-subscribers-backend-amdgpu

Author: Matt Arsenault (arsenm)


Changes

You cannot adjust the disassembler's subtarget. llvm-mc passes
the originally constructed MCSubtargetInfo around, rather than
querying the pointer in the disassembler instance.

---
Full diff: https://github.com/llvm/llvm-project/pull/117422.diff


2 Files Affected:

- (modified) llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp (+2-18) 
- (modified) llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp (+16-1) 


``diff
diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp 
b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
index f90121a86c846c..7817c5ff5acc0a 100644
--- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
+++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
@@ -45,26 +45,10 @@ using namespace llvm;
 
 using DecodeStatus = llvm::MCDisassembler::DecodeStatus;
 
-static const MCSubtargetInfo &addDefaultWaveSize(const MCSubtargetInfo &STI,
- MCContext &Ctx) {
-  if (!STI.hasFeature(AMDGPU::FeatureWavefrontSize64) &&
-  !STI.hasFeature(AMDGPU::FeatureWavefrontSize32)) {
-MCSubtargetInfo &STICopy = Ctx.getSubtargetCopy(STI);
-// If there is no default wave size it must be a generation before gfx10,
-// these have FeatureWavefrontSize64 in their definition already. For 
gfx10+
-// set wave32 as a default.
-STICopy.ToggleFeature(AMDGPU::FeatureWavefrontSize32);
-return STICopy;
-  }
-
-  return STI;
-}
-
 AMDGPUDisassembler::AMDGPUDisassembler(const MCSubtargetInfo &STI,
MCContext &Ctx, MCInstrInfo const *MCII)
-: MCDisassembler(addDefaultWaveSize(STI, Ctx), Ctx), MCII(MCII),
-  MRI(*Ctx.getRegisterInfo()), MAI(*Ctx.getAsmInfo()),
-  TargetMaxInstBytes(MAI.getMaxInstLength(&STI)),
+: MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()),
+  MAI(*Ctx.getAsmInfo()), TargetMaxInstBytes(MAI.getMaxInstLength(&STI)),
   CodeObjectVersion(AMDGPU::getDefaultAMDHSACodeObjectVersion()) {
   // ToDo: AMDGPUDisassembler supports only VI ISA.
   if (!STI.hasFeature(AMDGPU::FeatureGCN3Encoding) && !isGFX10Plus())
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp 
b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp
index 29be64625811f7..c692895d84c002 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp
@@ -77,7 +77,22 @@ static MCSubtargetInfo *
 createAMDGPUMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
   if (TT.getArch() == Triple::r600)
 return createR600MCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
-  return createAMDGPUMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
+
+  MCSubtargetInfo *STI =
+  createAMDGPUMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
+
+  // FIXME: We should error for the default target.
+  if (!STI->hasFeature(AMDGPU::FeatureWavefrontSize64) &&
+  !STI->hasFeature(AMDGPU::FeatureWavefrontSize32)) {
+// If there is no default wave size it must be a generation before gfx10,
+// these have FeatureWavefrontSize64 in their definition already. For 
gfx10+
+// set wave32 as a default.
+STI->ToggleFeature(AMDGPU::isGFX10Plus(*STI)
+   ? AMDGPU::FeatureWavefrontSize32
+   : AMDGPU::FeatureWavefrontSize64);
+  }
+
+  return STI;
 }
 
 static MCInstPrinter *createAMDGPUMCInstPrinter(const Triple &T,

``




https://github.com/llvm/llvm-project/pull/117422
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[llvm-branch-commits] [llvm] AMDGPU: Move default wavesize hack for disassembler (PR #117422)

2024-11-22 Thread Matt Arsenault via llvm-branch-commits 

https://github.com/arsenm ready_for_review 
https://github.com/llvm/llvm-project/pull/117422
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[llvm-branch-commits] [llvm] AMDGPU: Move default wavesize hack for disassembler (PR #117422)

2024-11-22 Thread Matt Arsenault via llvm-branch-commits 

https://github.com/arsenm created 
https://github.com/llvm/llvm-project/pull/117422

You cannot adjust the disassembler's subtarget. llvm-mc passes
the originally constructed MCSubtargetInfo around, rather than
querying the pointer in the disassembler instance.

>From bccd64648635ab9cdab25bfe3c910edc7f1adff0 Mon Sep 17 00:00:00 2001
From: Matt Arsenault 
Date: Fri, 22 Nov 2024 20:17:48 -0800
Subject: [PATCH] AMDGPU: Move default wavesize hack for disassembler

You cannot adjust the disassembler's subtarget. llvm-mc passes
the originally constructed MCSubtargetInfo around, rather than
querying the pointer in the disassembler instance.
---
 .../Disassembler/AMDGPUDisassembler.cpp   | 20 ++-
 .../MCTargetDesc/AMDGPUMCTargetDesc.cpp   | 17 +++-
 2 files changed, 18 insertions(+), 19 deletions(-)

diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp 
b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
index f90121a86c846c..7817c5ff5acc0a 100644
--- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
+++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
@@ -45,26 +45,10 @@ using namespace llvm;
 
 using DecodeStatus = llvm::MCDisassembler::DecodeStatus;
 
-static const MCSubtargetInfo &addDefaultWaveSize(const MCSubtargetInfo &STI,
- MCContext &Ctx) {
-  if (!STI.hasFeature(AMDGPU::FeatureWavefrontSize64) &&
-  !STI.hasFeature(AMDGPU::FeatureWavefrontSize32)) {
-MCSubtargetInfo &STICopy = Ctx.getSubtargetCopy(STI);
-// If there is no default wave size it must be a generation before gfx10,
-// these have FeatureWavefrontSize64 in their definition already. For 
gfx10+
-// set wave32 as a default.
-STICopy.ToggleFeature(AMDGPU::FeatureWavefrontSize32);
-return STICopy;
-  }
-
-  return STI;
-}
-
 AMDGPUDisassembler::AMDGPUDisassembler(const MCSubtargetInfo &STI,
MCContext &Ctx, MCInstrInfo const *MCII)
-: MCDisassembler(addDefaultWaveSize(STI, Ctx), Ctx), MCII(MCII),
-  MRI(*Ctx.getRegisterInfo()), MAI(*Ctx.getAsmInfo()),
-  TargetMaxInstBytes(MAI.getMaxInstLength(&STI)),
+: MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()),
+  MAI(*Ctx.getAsmInfo()), TargetMaxInstBytes(MAI.getMaxInstLength(&STI)),
   CodeObjectVersion(AMDGPU::getDefaultAMDHSACodeObjectVersion()) {
   // ToDo: AMDGPUDisassembler supports only VI ISA.
   if (!STI.hasFeature(AMDGPU::FeatureGCN3Encoding) && !isGFX10Plus())
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp 
b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp
index 29be64625811f7..c692895d84c002 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp
@@ -77,7 +77,22 @@ static MCSubtargetInfo *
 createAMDGPUMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
   if (TT.getArch() == Triple::r600)
 return createR600MCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
-  return createAMDGPUMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
+
+  MCSubtargetInfo *STI =
+  createAMDGPUMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
+
+  // FIXME: We should error for the default target.
+  if (!STI->hasFeature(AMDGPU::FeatureWavefrontSize64) &&
+  !STI->hasFeature(AMDGPU::FeatureWavefrontSize32)) {
+// If there is no default wave size it must be a generation before gfx10,
+// these have FeatureWavefrontSize64 in their definition already. For 
gfx10+
+// set wave32 as a default.
+STI->ToggleFeature(AMDGPU::isGFX10Plus(*STI)
+   ? AMDGPU::FeatureWavefrontSize32
+   : AMDGPU::FeatureWavefrontSize64);
+  }
+
+  return STI;
 }
 
 static MCInstPrinter *createAMDGPUMCInstPrinter(const Triple &T,

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[llvm-branch-commits] [llvm] AMDGPU: Move default wavesize hack for disassembler (PR #117422)

2024-11-22 Thread Matt Arsenault via llvm-branch-commits 

arsenm wrote:

> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is 
> open. Once all requirements are satisfied, merge this PR as a stack  href="https://app.graphite.dev/github/pr/llvm/llvm-project/117422?utm_source=stack-comment-downstack-mergeability-warning";
>  >on Graphite.
> https://graphite.dev/docs/merge-pull-requests";>Learn more

* **#117422** https://app.graphite.dev/github/pr/llvm/llvm-project/117422?utm_source=stack-comment-icon";
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* `main`



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https://github.com/llvm/llvm-project/pull/117422
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