[llvm-branch-commits] [llvm] PeepholeOpt: Remove check for reg_sequence def of subregister (PR #124512)

2025-01-30 Thread Matt Arsenault via llvm-branch-commits 

arsenm wrote:

### Merge activity

* **Jan 30, 8:37 AM EST**: A user started a stack merge that includes this pull 
request via 
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/124512).


https://github.com/llvm/llvm-project/pull/124512
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[llvm-branch-commits] [llvm] PeepholeOpt: Remove check for reg_sequence def of subregister (PR #124512)

2025-01-29 Thread Matt Arsenault via llvm-branch-commits 

https://github.com/arsenm updated 
https://github.com/llvm/llvm-project/pull/124512

>From 8d6f4a951cb38399ca83a7e6d14fd7d10fb5da12 Mon Sep 17 00:00:00 2001
From: Matt Arsenault 
Date: Mon, 27 Jan 2025 13:57:08 +0700
Subject: [PATCH] PeepholeOpt: Remove check for reg_sequence def of subregister

The verifier does not allow reg_sequence to have subregister defs,
even if undef.
---
 llvm/lib/CodeGen/PeepholeOptimizer.cpp | 17 +
 1 file changed, 1 insertion(+), 16 deletions(-)

diff --git a/llvm/lib/CodeGen/PeepholeOptimizer.cpp 
b/llvm/lib/CodeGen/PeepholeOptimizer.cpp
index 2fc48209126acd..bf450e3af0deee 100644
--- a/llvm/lib/CodeGen/PeepholeOptimizer.cpp
+++ b/llvm/lib/CodeGen/PeepholeOptimizer.cpp
@@ -1956,22 +1956,7 @@ ValueTrackerResult 
ValueTracker::getNextSourceFromRegSequence() {
   assert((Def->isRegSequence() || Def->isRegSequenceLike()) &&
  "Invalid definition");
 
-  if (Def->getOperand(DefIdx).getSubReg())
-// If we are composing subregs, bail out.
-// The case we are checking is Def. = REG_SEQUENCE.
-// This should almost never happen as the SSA property is tracked at
-// the register level (as opposed to the subreg level).
-// I.e.,
-// Def.sub0 =
-// Def.sub1 =
-// is a valid SSA representation for Def.sub0 and Def.sub1, but not for
-// Def. Thus, it must not be generated.
-// However, some code could theoretically generates a single
-// Def.sub0 (i.e, not defining the other subregs) and we would
-// have this case.
-// If we can ascertain (or force) that this never happens, we could
-// turn that into an assertion.
-return ValueTrackerResult();
+  assert(!Def->getOperand(DefIdx).getSubReg() && "illegal subregister def");
 
   SmallVector RegSeqInputRegs;
   if (!TII->getRegSequenceInputs(*Def, DefIdx, RegSeqInputRegs))

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[llvm-branch-commits] [llvm] PeepholeOpt: Remove check for reg_sequence def of subregister (PR #124512)

2025-01-29 Thread Matt Arsenault via llvm-branch-commits 

https://github.com/arsenm updated 
https://github.com/llvm/llvm-project/pull/124512

>From 8d6f4a951cb38399ca83a7e6d14fd7d10fb5da12 Mon Sep 17 00:00:00 2001
From: Matt Arsenault 
Date: Mon, 27 Jan 2025 13:57:08 +0700
Subject: [PATCH] PeepholeOpt: Remove check for reg_sequence def of subregister

The verifier does not allow reg_sequence to have subregister defs,
even if undef.
---
 llvm/lib/CodeGen/PeepholeOptimizer.cpp | 17 +
 1 file changed, 1 insertion(+), 16 deletions(-)

diff --git a/llvm/lib/CodeGen/PeepholeOptimizer.cpp 
b/llvm/lib/CodeGen/PeepholeOptimizer.cpp
index 2fc48209126acd..bf450e3af0deee 100644
--- a/llvm/lib/CodeGen/PeepholeOptimizer.cpp
+++ b/llvm/lib/CodeGen/PeepholeOptimizer.cpp
@@ -1956,22 +1956,7 @@ ValueTrackerResult 
ValueTracker::getNextSourceFromRegSequence() {
   assert((Def->isRegSequence() || Def->isRegSequenceLike()) &&
  "Invalid definition");
 
-  if (Def->getOperand(DefIdx).getSubReg())
-// If we are composing subregs, bail out.
-// The case we are checking is Def. = REG_SEQUENCE.
-// This should almost never happen as the SSA property is tracked at
-// the register level (as opposed to the subreg level).
-// I.e.,
-// Def.sub0 =
-// Def.sub1 =
-// is a valid SSA representation for Def.sub0 and Def.sub1, but not for
-// Def. Thus, it must not be generated.
-// However, some code could theoretically generates a single
-// Def.sub0 (i.e, not defining the other subregs) and we would
-// have this case.
-// If we can ascertain (or force) that this never happens, we could
-// turn that into an assertion.
-return ValueTrackerResult();
+  assert(!Def->getOperand(DefIdx).getSubReg() && "illegal subregister def");
 
   SmallVector RegSeqInputRegs;
   if (!TII->getRegSequenceInputs(*Def, DefIdx, RegSeqInputRegs))

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[llvm-branch-commits] [llvm] PeepholeOpt: Remove check for reg_sequence def of subregister (PR #124512)

2025-01-27 Thread Shilei Tian via llvm-branch-commits 

https://github.com/shiltian edited 
https://github.com/llvm/llvm-project/pull/124512
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[llvm-branch-commits] [llvm] PeepholeOpt: Remove check for reg_sequence def of subregister (PR #124512)

2025-01-27 Thread Shilei Tian via llvm-branch-commits 

https://github.com/shiltian approved this pull request.


https://github.com/llvm/llvm-project/pull/124512
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[llvm-branch-commits] [llvm] PeepholeOpt: Remove check for reg_sequence def of subregister (PR #124512)

2025-01-26 Thread Matt Arsenault via llvm-branch-commits 

arsenm wrote:

> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is 
> open. Once all requirements are satisfied, merge this PR as a stack  href="https://app.graphite.dev/github/pr/llvm/llvm-project/124512?utm_source=stack-comment-downstack-mergeability-warning";
>  >on Graphite.
> https://graphite.dev/docs/merge-pull-requests";>Learn more

* **#124512** https://app.graphite.dev/github/pr/llvm/llvm-project/124512?utm_source=stack-comment-icon";
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* `main`




This stack of pull requests is managed by https://graphite.dev?utm-source=stack-comment";>Graphite. Learn 
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https://github.com/llvm/llvm-project/pull/124512
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[llvm-branch-commits] [llvm] PeepholeOpt: Remove check for reg_sequence def of subregister (PR #124512)

2025-01-26 Thread Matt Arsenault via llvm-branch-commits 

https://github.com/arsenm ready_for_review 
https://github.com/llvm/llvm-project/pull/124512
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[llvm-branch-commits] [llvm] PeepholeOpt: Remove check for reg_sequence def of subregister (PR #124512)

2025-01-26 Thread Matt Arsenault via llvm-branch-commits 

https://github.com/arsenm created 
https://github.com/llvm/llvm-project/pull/124512

The verifier does not allow reg_sequence to have subregister defs,
even if undef.

>From 436cde08aff59b2bf77c31e0e65fdaac31f0e520 Mon Sep 17 00:00:00 2001
From: Matt Arsenault 
Date: Mon, 27 Jan 2025 13:57:08 +0700
Subject: [PATCH] PeepholeOpt: Remove check for reg_sequence def of subregister

The verifier does not allow reg_sequence to have subregister defs,
even if undef.
---
 llvm/lib/CodeGen/PeepholeOptimizer.cpp | 17 +
 1 file changed, 1 insertion(+), 16 deletions(-)

diff --git a/llvm/lib/CodeGen/PeepholeOptimizer.cpp 
b/llvm/lib/CodeGen/PeepholeOptimizer.cpp
index 2fc48209126acd..bf450e3af0deee 100644
--- a/llvm/lib/CodeGen/PeepholeOptimizer.cpp
+++ b/llvm/lib/CodeGen/PeepholeOptimizer.cpp
@@ -1956,22 +1956,7 @@ ValueTrackerResult 
ValueTracker::getNextSourceFromRegSequence() {
   assert((Def->isRegSequence() || Def->isRegSequenceLike()) &&
  "Invalid definition");
 
-  if (Def->getOperand(DefIdx).getSubReg())
-// If we are composing subregs, bail out.
-// The case we are checking is Def. = REG_SEQUENCE.
-// This should almost never happen as the SSA property is tracked at
-// the register level (as opposed to the subreg level).
-// I.e.,
-// Def.sub0 =
-// Def.sub1 =
-// is a valid SSA representation for Def.sub0 and Def.sub1, but not for
-// Def. Thus, it must not be generated.
-// However, some code could theoretically generates a single
-// Def.sub0 (i.e, not defining the other subregs) and we would
-// have this case.
-// If we can ascertain (or force) that this never happens, we could
-// turn that into an assertion.
-return ValueTrackerResult();
+  assert(!Def->getOperand(DefIdx).getSubReg() && "illegal subregister def");
 
   SmallVector RegSeqInputRegs;
   if (!TII->getRegSequenceInputs(*Def, DefIdx, RegSeqInputRegs))

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