https://llvm.org/bugs/show_bug.cgi?id=30436
Bug ID: 30436 Summary: ARM64 assembler does not set shift bits on add instruction to calculate TLS address Product: new-bugs Version: trunk Hardware: PC OS: Linux Status: NEW Severity: normal Priority: P Component: new bugs Assignee: unassignedb...@nondot.org Reporter: lei.l...@windriver.com CC: llvm-bugs@lists.llvm.org Classification: Unclassified ARM64 assembler generates invalid code sequence to access TLS variables in local-exec TLS model. In particular, the add instruction generated to calculate the higher 12-bit value of TLS offset does not set its shift bit, so the immediate value is incorrectly added to the lower part of the register. E.g. .text .align 2 .global foo .type foo, %function foo: mrs x0, tpidr_el0 add x0, x0, #:tprel_hi12:ta add x0, x0, #:tprel_lo12_nc:ta Assembled with clang --target=arm64. 0000000000000000 <foo>: 0: d53bd040 mrs x0, tpidr_el0 4: 91000000 add x0, x0, #0x0 8: 91000000 add x0, x0, #0x0 Assembled with aarch64-linux-gnu-gcc. 0000000000000000 <foo>: 0: d53bd040 mrs x0, tpidr_el0 4: 91400000 add x0, x0, #0x0, lsl #12 8: 91000000 add x0, x0, #0x0 -- You are receiving this mail because: You are on the CC list for the bug.
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