Changes in directory llvm/lib/Analysis:
ScalarEvolution.cpp updated: 1.46 - 1.47
---
Log message:
Signed shr by a constant is not the same as sdiv by 2^k
---
Diffs of the changes: (+0 -9)
ScalarEvolution.cpp |9 -
1 files changed, 9 deletions(-)
Index:
Changes in directory llvm-test/SingleSource/UnitTests/Vector:
multiplies.c added (r1.1)
helpers.h updated: 1.4 - 1.5
---
Log message:
new testcase for multiplies
---
Diffs of the changes: (+50 -0)
helpers.h| 16
multiplies.c | 34 ++
Changes in directory llvm/test/Regression/CodeGen/PowerPC:
vec_spat.ll updated: 1.2 - 1.3
---
Log message:
new testcase
---
Diffs of the changes: (+17 -2)
vec_spat.ll | 19 +--
1 files changed, 17 insertions(+), 2 deletions(-)
Index:
Changes in directory llvm/include/llvm/Target:
TargetLowering.h updated: 1.66 - 1.67
---
Log message:
Move isShuffleLegal from TLI to Legalize.
---
Diffs of the changes: (+8 -17)
TargetLowering.h | 25 -
1 files changed, 8 insertions(+), 17 deletions(-)
Index:
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.351 - 1.352
---
Log message:
* Add supprot for SCALAR_TO_VECTOR operations where the input needs to be
promoted/expanded (e.g. SCALAR_TO_VECTOR from i8/i16 on PPC).
* Add support for targets to request that
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.128 - 1.129
PPCISelLowering.h updated: 1.38 - 1.39
PPCInstrAltivec.td updated: 1.32 - 1.33
---
Log message:
Ask legalize to promote all vector shuffles to be v16i8 instead of having to
handle all 4 PPC vector types.
Changes in directory llvm/test/Regression/CodeGen/Alpha:
2006-04-04-zextload.ll added (r1.1)
---
Log message:
New testcase
---
Diffs of the changes: (+36 -0)
2006-04-04-zextload.ll | 36
1 files changed, 36 insertions(+)
Index:
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.143 - 1.144
---
Log message:
Do not create ZEXTLOAD's unless we are before legalize or the operation is
legal.
---
Diffs of the changes: (+2 -1)
DAGCombiner.cpp |3 ++-
1 files changed, 2 insertions(+), 1
Changes in directory llvm/include/llvm/CodeGen:
MachineFrameInfo.h updated: 1.15 - 1.16
---
Log message:
Make sure to consider alignment of variable sized objects.
This, along with the previous dag combiner fix, fixes
CodeGen/Alpha/2006-04-04-zextload.ll
---
Diffs of the changes: (+1 -0)
Changes in directory llvm-www/pubs:
2006-04-04-CGO-GraphColoring.html added (r1.1)
2006-04-04-CGO-GraphColoring.pdf added (r1.1)
index.html updated: 1.35 - 1.36
---
Log message:
Add a new paper that uses LLVM.
---
Diffs of the changes: (+49 -0)
2006-04-04-CGO-GraphColoring.html | 47
Changes in directory llvm-test/SingleSource/UnitTests/Vector/SSE:
sse.expandfft.c updated: 1.1 - 1.2
---
Log message:
Eliminate timing printout. Dump more info for more meaningful comparison.
---
Diffs of the changes: (+10 -6)
sse.expandfft.c | 16 ++--
1 files changed, 10
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.58 - 1.59
---
Log message:
PSHUF* encoding bugs.
---
Diffs of the changes: (+6 -6)
X86InstrSSE.td | 12 ++--
1 files changed, 6 insertions(+), 6 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u
Changes in directory llvm-test/SingleSource/UnitTests/Vector/SSE:
sse.expandfft.c updated: 1.2 - 1.3
---
Log message:
Bump up the size of the test.
---
Diffs of the changes: (+3 -3)
sse.expandfft.c |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
Index:
Changes in directory llvm-test/SingleSource/UnitTests/Vector/SSE:
sse.stepfft.c updated: 1.1 - 1.2
---
Log message:
- Remove calls to clock() and timing printfs.
- Print out more data for comparisons.
- Bump up the test size.
---
Diffs of the changes: (+11 -7)
sse.stepfft.c | 18
Changes in directory llvm-test/SingleSource/UnitTests/Vector/Altivec:
alti.expandfft.c updated: 1.2 - 1.3
alti.stepfft.c updated: 1.2 - 1.3
---
Log message:
Remove calls to clock() and timing info printf's.
---
Diffs of the changes: (+0 -11)
alti.expandfft.c |5 -
alti.stepfft.c
Changes in directory llvm/include/llvm:
Type.h updated: 1.83 - 1.84
---
Log message:
How could this ever have worked?
---
Diffs of the changes: (+1 -1)
Type.h |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/include/llvm/Type.h
diff -u llvm/include/llvm/Type.h:1.83
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.59 - 1.60
X86RegisterInfo.cpp updated: 1.133 - 1.134
---
Log message:
Minor fixes + naming changes.
---
Diffs of the changes: (+157 -156)
X86InstrSSE.td | 309 ++--
Changes in directory llvm/include/llvm:
Intrinsics.td updated: 1.31 - 1.32
IntrinsicsX86.td updated: 1.8 - 1.9
---
Log message:
Added intrinsics to match __builtin_ia32_pslldqi128 and
__builtin_ia32_psrldqi128.
---
Diffs of the changes: (+11 -0)
Intrinsics.td|1 +
IntrinsicsX86.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.60 - 1.61
---
Log message:
Added pslldq and psrldq.
---
Diffs of the changes: (+18 -0)
X86InstrSSE.td | 18 ++
1 files changed, 18 insertions(+)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.129 - 1.130
---
Log message:
Fix some broken logic that would cause us to codegen
{2147483647,2147483647,2147483647,2147483647} as 'vspltisb v0, -1'.
---
Diffs of the changes: (+2 -2)
PPCISelLowering.cpp |4
Changes in directory llvm/include/llvm:
IntrinsicsPowerPC.td updated: 1.14 - 1.15
---
Log message:
add average intrinsics.
---
Diffs of the changes: (+8 -0)
IntrinsicsPowerPC.td |8
1 files changed, 8 insertions(+)
Index: llvm/include/llvm/IntrinsicsPowerPC.td
diff -u
Changes in directory llvm/lib/Target/PowerPC:
PPCInstrAltivec.td updated: 1.33 - 1.34
---
Log message:
add average intrinsics
---
Diffs of the changes: (+7 -0)
PPCInstrAltivec.td |7 +++
1 files changed, 7 insertions(+)
Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td
diff -u
Changes in directory llvm/include/llvm:
IntrinsicsPowerPC.td updated: 1.15 - 1.16
---
Log message:
Add FP - Int Conversions
---
Diffs of the changes: (+7 -1)
IntrinsicsPowerPC.td |8 +++-
1 files changed, 7 insertions(+), 1 deletion(-)
Index:
Changes in directory llvm/include/llvm:
IntrinsicsPowerPC.td updated: 1.16 - 1.17
---
Log message:
Add missing byte merges.
---
Diffs of the changes: (+6 -0)
IntrinsicsPowerPC.td |6 ++
1 files changed, 6 insertions(+)
Index: llvm/include/llvm/IntrinsicsPowerPC.td
diff -u
Changes in directory llvm/lib/Target/PowerPC:
PPCInstrAltivec.td updated: 1.35 - 1.36
---
Log message:
Add missing byte merges.
---
Diffs of the changes: (+2 -0)
PPCInstrAltivec.td |2 ++
1 files changed, 2 insertions(+)
Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td
diff -u
Changes in directory llvm/lib/Target/PowerPC:
README_ALTIVEC.txt updated: 1.12 - 1.13
---
Log message:
add a note
---
Diffs of the changes: (+4 -2)
README_ALTIVEC.txt |6 --
1 files changed, 4 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/PowerPC/README_ALTIVEC.txt
diff
Changes in directory llvm/include/llvm:
IntrinsicsPowerPC.td updated: 1.17 - 1.18
---
Log message:
Add m[tf]vscr intrinsics.
---
Diffs of the changes: (+7 -0)
IntrinsicsPowerPC.td |7 +++
1 files changed, 7 insertions(+)
Index: llvm/include/llvm/IntrinsicsPowerPC.td
diff -u
Changes in directory llvm/lib/Target/PowerPC:
PPCInstrAltivec.td updated: 1.36 - 1.37
PPCInstrFormats.td updated: 1.71 - 1.72
---
Log message:
Add m[tf]vscr instructions.
---
Diffs of the changes: (+34 -0)
PPCInstrAltivec.td |7 +++
PPCInstrFormats.td | 27
Changes in directory llvm/include/llvm:
IntrinsicsPowerPC.td updated: 1.18 - 1.19
---
Log message:
correct the type of two intrinsics, add int_ppc_altivec_vmladduhm
---
Diffs of the changes: (+7 -2)
IntrinsicsPowerPC.td |9 +++--
1 files changed, 7 insertions(+), 2 deletions(-)
Changes in directory llvm/lib/Target/PowerPC:
PPCInstrAltivec.td updated: 1.37 - 1.38
README_ALTIVEC.txt updated: 1.13 - 1.14
---
Log message:
add vmladduhm
---
Diffs of the changes: (+2 -2)
PPCInstrAltivec.td |2 ++
README_ALTIVEC.txt |2 --
2 files changed, 2 insertions(+), 2
Changes in directory llvm/lib/Target/PowerPC:
PPCInstrAltivec.td updated: 1.38 - 1.39
---
Log message:
add vsl
---
Diffs of the changes: (+2 -0)
PPCInstrAltivec.td |2 ++
1 files changed, 2 insertions(+)
Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td
diff -u
Changes in directory llvm/test/Regression/CodeGen/X86:
vec_shuffle.ll updated: 1.4 - 1.5
---
Log message:
Add a new shuffle test case that requires pshuflw / pshufhw pair.
---
Diffs of the changes: (+27 -2)
vec_shuffle.ll | 29 +++--
1 files changed, 27
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.153 - 1.154
---
Log message:
Handle v8i16 shuffle that must be broken into a pair of pshufhw / pshuflw.
---
Diffs of the changes: (+55 -2)
X86ISelLowering.cpp | 57
Changes in directory llvm/lib/Analysis/DataStructure:
Local.cpp updated: 1.143 - 1.144
---
Log message:
revert this, this is safe, if conservative. leave a note to that effect
---
Diffs of the changes: (+7 -9)
Local.cpp | 16 +++-
1 files changed, 7 insertions(+), 9
Changes in directory llvm/test/Regression/Analysis/DSGraph:
2004-02-13-memcpy.ll updated: 1.3 - 1.4
---
Log message:
make this test less exacting
---
Diffs of the changes: (+1 -1)
2004-02-13-memcpy.ll |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index:
Changes in directory llvm/test/Regression/CodeGen/X86:
vec_shuffle.ll updated: 1.5 - 1.6
---
Log message:
Separate out to 2 test cases
---
Diffs of the changes: (+1 -26)
vec_shuffle.ll | 27 +--
1 files changed, 1 insertion(+), 26 deletions(-)
Index:
Changes in directory llvm/win32/x86:
x86.vcproj updated: 1.23 - 1.24
---
Log message:
Fix more tablegen depedency issues in Visual Studio.
---
Diffs of the changes: (+2 -2)
x86.vcproj |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
Index: llvm/win32/x86/x86.vcproj
diff -u
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