[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.cpp

Changes in directory llvm/lib/Target/X86: X86InstrInfo.cpp updated: 1.86 - 1.87 --- Log message: BlockHasNoFallThrough() now returns true if block ends with a return instruction. --- Diffs of the changes: (+5 -0) X86InstrInfo.cpp |5 + 1 files changed, 5 insertions(+) Index:

[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

Changes in directory llvm/lib/Target/PowerPC: PPCInstrInfo.cpp updated: 1.38 - 1.39 --- Log message: BlockHasNoFallThrough() now returns true if block ends with a return instruction. --- Diffs of the changes: (+1 -0) PPCInstrInfo.cpp |1 + 1 files changed, 1 insertion(+) Index:

[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaInstrInfo.cpp

Changes in directory llvm/lib/Target/Alpha: AlphaInstrInfo.cpp updated: 1.18 - 1.19 --- Log message: BlockHasNoFallThrough() now returns true if block ends with a return instruction. --- Diffs of the changes: (+2 -0) AlphaInstrInfo.cpp |2 ++ 1 files changed, 2 insertions(+) Index:

[llvm-commits] CVS: llvm/lib/CodeGen/DwarfWriter.cpp

Changes in directory llvm/lib/CodeGen: DwarfWriter.cpp updated: 1.146 - 1.147 --- Log message: Only emit one entry in the exception action table for each action, even if it occurs for multiple landing pads. --- Diffs of the changes: (+116 -65) DwarfWriter.cpp | 181

[llvm-commits] CVS: llvm/lib/Target/ARM/ARMInstrInfo.cpp

Changes in directory llvm/lib/Target/ARM: ARMInstrInfo.cpp updated: 1.28 - 1.29 --- Log message: BlockHasNoFallThrough() now returns true if block ends with a return instruction; AnalyzeBranch() should ignore predicated instructionsd. --- Diffs of the changes: (+13 -2) ARMInstrInfo.cpp |

Re: [llvm-commits] CVS: llvm/lib/Target/ARM/ARMInstrInfo.cpp

On May 21, 2007, at 11:56 AM, Evan Cheng wrote: - isTerminatorInstr((--I)-getOpcode())) + !isPredicated(--I) isTerminatorInstr(I-getOpcode())) Wouldn't it be better to have isTerminatorInst return false on predicated things? ___

[llvm-commits] CVS: llvm/lib/Target/ARM/ARMInstrInfo.td

Changes in directory llvm/lib/Target/ARM: ARMInstrInfo.td updated: 1.104 - 1.105 --- Log message: Add some patterns for PIC PC-relative loads and stores. --- Diffs of the changes: (+41 -2) ARMInstrInfo.td | 43 +-- 1 files changed, 41

[llvm-commits] CVS: llvm/lib/CodeGen/IfConversion.cpp

Changes in directory llvm/lib/CodeGen: IfConversion.cpp updated: 1.10 - 1.11 --- Log message: If-convert early exit blocks (returns, etc.); bug fixes, etc. --- Diffs of the changes: (+226 -141) IfConversion.cpp | 367 +-- 1 files

[llvm-commits] CVS: llvm/lib/Target/ARM/ARMInstrInfo.td

Changes in directory llvm/lib/Target/ARM: ARMInstrInfo.td updated: 1.105 - 1.106 --- Log message: Use AXI3 not AXI2 for appropriate PIC PC-relative loads and stores. Cosmetic. --- Diffs of the changes: (+7 -5) ARMInstrInfo.td | 12 +++- 1 files changed, 7 insertions(+), 5

[llvm-commits] CVS: llvm/lib/Target/ARM/ARMInstrInfo.cpp

Changes in directory llvm/lib/Target/ARM: ARMInstrInfo.cpp updated: 1.29 - 1.30 --- Log message: Fix some -march=thumb regressions. tBR_JTr is not predicable. --- Diffs of the changes: (+3 -1) ARMInstrInfo.cpp |4 +++- 1 files changed, 3 insertions(+), 1 deletion(-) Index:

Re: [llvm-commits] CVS: llvm/lib/Target/ARM/ARMInstrInfo.cpp

No. IsTerminatorInstr() simply checks opcode flag, it's not target dependent. Evan On May 21, 2007, at 12:01 PM, Dale Johannesen wrote: On May 21, 2007, at 11:56 AM, Evan Cheng wrote: - isTerminatorInstr((--I)-getOpcode())) + !isPredicated(--I)

[llvm-commits] CVS: llvm/test/CodeGen/X86/2007-03-18-LiveIntervalAssert.ll

Changes in directory llvm/test/CodeGen/X86: 2007-03-18-LiveIntervalAssert.ll added (r1.1) --- Log message: Add test for PR1259: http://llvm.org/PR1259 . --- Diffs of the changes: (+7 -0) 2007-03-18-LiveIntervalAssert.ll |7 +++ 1 files changed, 7 insertions(+) Index:

[llvm-commits] CVS: llvm/include/llvm/Target/TargetInstrInfo.h

Changes in directory llvm/include/llvm/Target: TargetInstrInfo.h updated: 1.122 - 1.123 --- Log message: Consistency. --- Diffs of the changes: (+3 -3) TargetInstrInfo.h |6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) Index: llvm/include/llvm/Target/TargetInstrInfo.h diff

Re: [llvm-commits] CVS: llvm/lib/VMCore/AsmWriter.cpp

On May 19, 2007, at 12:25 AM, Reid Spencer wrote: Adjust how LLVM names are produced: 1. Always use % for local and @ for global. 2. Replace NameNeedsQuotes with QuoteNameIfNeeded so that any adjustments to the name can be done in one pass. 3. Implement generation of hex escapes so

[llvm-commits] CVS: llvm/lib/Target/X86/X86.td

Changes in directory llvm/lib/Target/X86: X86.td updated: 1.33 - 1.34 --- Log message: We only need to specify the most-implied feature for an architecture. --- Diffs of the changes: (+21 -33) X86.td | 54 +- 1 files changed, 21

[llvm-commits] [release_20] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp

Changes in directory llvm/lib/Transforms/Scalar: InstructionCombining.cpp updated: 1.762.2.1 - 1.762.2.2 --- Log message: Merge from mainline --- Diffs of the changes: (+8 -0) InstructionCombining.cpp |8 1 files changed, 8 insertions(+) Index: