Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.495 - 1.496
SelectionDAG.cpp updated: 1.405 - 1.406
SelectionDAGISel.cpp updated: 1.460 - 1.461
---
Log message:
Introduce new SelectionDAG node opcodes VEXTRACT_SUBVECTOR and
VCONCAT_VECTORS. Use these for
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.459 - 1.460
---
Log message:
When creating CopyFromReg nodes, always use legal types. And use the
correct types for the result vector, even though it is currently bitcasted
to a different type immediately.
On Jun 12, 2007, at 1:19 PM, Lauro Ramos Venancio wrote:
The attached patch unify the handle of shifts when the shift amount is
greater or equal the bit width.
Nowadays, LLVM evaluates shl(i32 X,32) to 0 in some places and to
undef in other places.
For compatibility purpose, this patch
Look for eh.filter and eh.selector intrinsics in the
successor to an empty (exception for a branch) landing pad.
The big FIXME comment explains more. Testcase included,
along with an XFAIL for a test which uses eh.selector in a
routine with no landing pads (not possible in llvm-gcc
generated
Changes in directory llvm/lib/Target/X86:
X86InstrInfo.cpp updated: 1.88 - 1.89
---
Log message:
Handle blocks with 2 unconditional branches in AnalyzeBranch.
---
Diffs of the changes: (+10 -0)
X86InstrInfo.cpp | 10 ++
1 files changed, 10 insertions(+)
Index:
Changes in directory llvm/lib/Target/ARM:
ARMInstrInfo.cpp updated: 1.35 - 1.36
---
Log message:
Handle blocks with 2 unconditional branches in AnalyzeBranch.
---
Diffs of the changes: (+10 -0)
ARMInstrInfo.cpp | 10 ++
1 files changed, 10 insertions(+)
Index:
Changes in directory llvm/lib/Target/PowerPC:
PPCInstrInfo.cpp updated: 1.40 - 1.41
---
Log message:
Handle blocks with 2 unconditional branches in AnalyzeBranch.
---
Diffs of the changes: (+10 -0)
PPCInstrInfo.cpp | 10 ++
1 files changed, 10 insertions(+)
Index:
Changes in directory llvm/lib/Target/Alpha:
AlphaInstrInfo.cpp updated: 1.20 - 1.21
---
Log message:
Handle blocks with 2 unconditional branches in AnalyzeBranch.
---
Diffs of the changes: (+10 -0)
AlphaInstrInfo.cpp | 10 ++
1 files changed, 10 insertions(+)
Index:
This is not enough to make a compiler handle shifts by greater than the
word size consistently; in both gcc and llvm-gcc, for example, the
result of
int y=32;
xy
depends on optimization level.
I know. On x86, the result of
int n = 32;
1n
is 1 with gcc -O0 and 0 with gcc -O3. But
On Jun 13, 2007, at 11:34 AM, Lauro Ramos Venancio wrote:
This is not enough to make a compiler handle shifts by greater
than the
word size consistently; in both gcc and llvm-gcc, for example, the
result of
int y=32;
xy
depends on optimization level.
I know. On x86, the
I don't think this is appropriate Lauro. The program needs to be
fixed, it's not just a codegen or optimizer issue, everything in the
compiler assumes that these shifts are undefined. Programs cannot
reliably expect a compiler to do the right thing here, and your patch
isn't a fix.
On Jun 13, 2007, at 12:06 PM, Lauro Ramos Venancio wrote:
I don't think this is appropriate Lauro. The program needs to be
fixed, it's not just a codegen or optimizer issue, everything in the
compiler assumes that these shifts are undefined. Programs cannot
reliably expect a compiler to do
On Jun 13, 2007, at 10:55 AM, Duncan Sands wrote:
Look for eh.filter and eh.selector intrinsics in the
successor to an empty (exception for a branch) landing pad.
The big FIXME comment explains more. Testcase included,
along with an XFAIL for a test which uses eh.selector in a
routine with
Changes in directory llvm/utils/TableGen:
RegisterInfoEmitter.cpp updated: 1.56 - 1.57
CodeGenTarget.cpp updated: 1.91 - 1.92
CodeGenRegisters.h updated: 1.11 - 1.12
---
Log message:
Add support to tablegen for specifying subregister classes on a per register
class basis.
---
Diffs of the
Changes in directory llvm/lib/Target:
Target.td updated: 1.102 - 1.103
---
Log message:
Add support to tablegen for specifying subregister classes on a per register
class basis.
---
Diffs of the changes: (+4 -0)
Target.td |4
1 files changed, 4 insertions(+)
Index:
Changes in directory llvm/include/llvm/Target:
MRegisterInfo.h updated: 1.110 - 1.111
---
Log message:
Add support to tablegen for specifying subregister classes on a per register
class basis.
---
Diffs of the changes: (+44 -0)
MRegisterInfo.h | 44
Changes in directory llvm-www/pubs:
2006-10-ICNPC-ScalingTaskGraphs.html added (r1.1)
2006-10-ICNPC-ScalingTaskGraphs.pdf added (r1.1)
index.html updated: 1.50 - 1.51
---
Log message:
add a new paper
---
Diffs of the changes: (+65 -0)
2006-10-ICNPC-ScalingTaskGraphs.html | 58
Changes in directory llvm-www/pubs:
2006-01-LabrecqueMSThesis.html added (r1.1)
2006-01-LabrecqueMSThesis.pdf added (r1.1)
index.html updated: 1.51 - 1.52
---
Log message:
add an llvm-using thesis
---
Diffs of the changes: (+62 -0)
2006-01-LabrecqueMSThesis.html | 55
Changes in directory llvm-www/pubs:
2006-09-SOC-Synthesis.html added (r1.1)
2006-09-SOC-Synthesis.pdf added (r1.1)
index.html updated: 1.52 - 1.53
---
Log message:
add another paper
---
Diffs of the changes: (+60 -0)
2006-09-SOC-Synthesis.html | 57
Changes in directory llvm-www/pubs:
2005-07-ZimmermanMSThesis.html added (r1.1)
2005-07-ZimmermanMSThesis.pdf added (r1.1)
index.html updated: 1.53 - 1.54
---
Log message:
another ms thesis
---
Diffs of the changes: (+39 -0)
2005-07-ZimmermanMSThesis.html | 33
Changes in directory llvm-www/pubs:
2006-10-CASES-IncreaseMem.html added (r1.1)
2006-10-CASES-IncreaseMem.pdf added (r1.1)
index.html updated: 1.54 - 1.55
---
Log message:
add another paper
---
Diffs of the changes: (+60 -0)
2006-10-CASES-IncreaseMem.html | 54
Chris Lattner wrote:
have only 4Ð10 KB of RAM and
ndash; ?
Nick
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Changes in directory llvm-www/pubs:
2006-10-CASES-IncreaseMem.html updated: 1.1 - 1.2
---
Log message:
fix a unicode character
---
Diffs of the changes: (+1 -1)
2006-10-CASES-IncreaseMem.html |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index:
Changes in directory llvm-www/pubs:
2005-09-PASTE-GreedySuiteMinimization.html added (r1.1)
2005-09-PASTE-GreedySuiteMinimization.pdf added (r1.1)
index.html updated: 1.55 - 1.56
---
Log message:
new paper
---
Diffs of the changes: (+59 -1)
2005-09-PASTE-GreedySuiteMinimization.html |
Hi Chris,
+ // Inform the MachineModuleInfo of the personality for this
landing pad.
+ ConstantExpr *CE = dyn_castConstantExpr(I.getOperand(2));
+ assert(CE CE-getOpcode() == Instruction::BitCast
Please just use cast instead of dyn_cast, which guarantees no null
return.
but then
On Jun 13, 2007, at 10:51 PM, Duncan Sands wrote:
Hi Chris,
+ // Inform the MachineModuleInfo of the personality for this
landing pad.
+ ConstantExpr *CE = dyn_castConstantExpr(I.getOperand(2));
+ assert(CE CE-getOpcode() == Instruction::BitCast
Please just use cast instead of
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