Author: evancheng
Date: Fri Dec 7 02:07:39 2007
New Revision: 44676
URL: http://llvm.org/viewvc/llvm-project?rev=44676view=rev
Log:
Much improved v8i16 shuffles. (Step 1).
Added:
llvm/trunk/test/CodeGen/X86/vec_shuffle-12.ll
Removed:
Hey Evan,
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Dec 7
02:07:39 2007
@@ -2754,10 +2754,33 @@
}
std::swap(V1, V2);
- Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, MaskVec[0],
MaskVec.size());
+ Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, MaskVec[0],
On Dec 7, 2007 4:42 PM, Evan Cheng [EMAIL PROTECTED] wrote:
Nicely done!
Thx! :-)
+// Map the def of a virtual register to the machine instruction.
+std::mapunsigned, const MachineInstr* VRegDefs;
Consider using IndexedMap.
Okay.
+bool CanHoistInst(MachineInstr I) const {
Author: lattner
Date: Sat Dec 8 00:59:59 2007
New Revision: 44700
URL: http://llvm.org/viewvc/llvm-project?rev=44700view=rev
Log:
implement __builtin_return_addr(0) on ppc.
Added:
llvm/trunk/test/CodeGen/PowerPC/retaddr.ll
Modified:
llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
Author: lattner
Date: Sat Dec 8 01:22:58 2007
New Revision: 44703
URL: http://llvm.org/viewvc/llvm-project?rev=44703view=rev
Log:
aesthetic changes, no functionality change. Evan, it's not clear
what 'Available' is, please add a comment near it and rename it
if appropriate.
Modified:
Author: lattner
Date: Sat Dec 8 01:04:58 2007
New Revision: 44701
URL: http://llvm.org/viewvc/llvm-project?rev=44701view=rev
Log:
Fix a significant code quality regression I introduced on PPC64 quite
a while ago. We now produce:
_foo:
mflr r0
std r0, 16(r1)
ld r2,
Author: lattner
Date: Sat Dec 8 00:39:11 2007
New Revision: 44699
URL: http://llvm.org/viewvc/llvm-project?rev=44699view=rev
Log:
refactor some code to avoid overloading the name 'usesLR' in
different places to mean different things. Document what the
one in PPCFunctionInfo means and when it
Author: lattner
Date: Fri Dec 7 23:00:57 2007
New Revision: 44698
URL: http://llvm.org/viewvc/llvm-project?rev=44698view=rev
Log:
Enable machine-licm for ppc beta.
Modified:
test-suite/trunk/Makefile.programs
Modified: test-suite/trunk/Makefile.programs
URL:
Author: void
Date: Fri Dec 7 19:47:01 2007
New Revision: 44696
URL: http://llvm.org/viewvc/llvm-project?rev=44696view=rev
Log:
Incorporated comments from Evan and Chris:
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20071203/056043.html
Author: evancheng
Date: Fri Dec 7 19:01:07 2007
New Revision: 44694
URL: http://llvm.org/viewvc/llvm-project?rev=44694view=rev
Log:
Doh
Modified:
llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp
Modified: llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp
URL:
On Dec 7, 2007, at 1:42 PM, Bill Wendling wrote:
Author: void
Date: Fri Dec 7 15:42:31 2007
New Revision: 44687
URL: http://llvm.org/viewvc/llvm-project?rev=44687view=rev
Log:
Initial commit of the machine code LICM pass. It successfully
hoists this:
_foo:
li r2, 0
LBB1_1:
Author: void
Date: Fri Dec 7 15:42:31 2007
New Revision: 44687
URL: http://llvm.org/viewvc/llvm-project?rev=44687view=rev
Log:
Initial commit of the machine code LICM pass. It successfully hoists this:
_foo:
li r2, 0
LBB1_1: ; bb
li r5, 0
stw r5, 0(r3)
addi r2,
Author: criswell
Date: Fri Dec 7 15:05:23 2007
New Revision: 44683
URL: http://llvm.org/viewvc/llvm-project?rev=44683view=rev
Log:
Removed deleteValue() and copyValue() from TDDataStructure; these methods
should be implemented by the base class.
Modified:
On Dec 7, 2007 5:01 PM, Chris Lattner [EMAIL PROTECTED] wrote:
+// Visit all of the instructions of the loop. We want to visit
the subloops
+// first, though, so that we can hoist their invariants first
into their
+// containing loop before we process that loop.
+
But when I set the alignment of the loop in main to 8, it got
slightly faster:
$ time ./t.new
real 0m15.090s
user 0m15.079s
sys 0m0.010s
So there's some type of alignment thing that's getting in the way, but
it's encouraging for an initial pass that moved 3 instructions total.
Author: evancheng
Date: Fri Dec 7 19:00:31 2007
New Revision: 44692
URL: http://llvm.org/viewvc/llvm-project?rev=44692view=rev
Log:
Fix a compilation warning.
Modified:
llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp
Modified: llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp
URL:
Author: evancheng
Date: Fri Dec 7 15:30:01 2007
New Revision: 44686
URL: http://llvm.org/viewvc/llvm-project?rev=44686view=rev
Log:
Add comment.
Modified:
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL:
Author: void
Date: Sat Dec 8 01:17:56 2007
New Revision: 44702
URL: http://llvm.org/viewvc/llvm-project?rev=44702view=rev
Log:
Renaming:
isTriviallyReMaterializable - hasNoSideEffects
isReallyTriviallyReMaterializable - isTriviallyReMaterializable
Modified:
Author: cfr
Date: Fri Dec 7 18:53:13 2007
New Revision: 44690
URL: http://llvm.org/viewvc/llvm-project?rev=44690view=rev
Log:
Adding MachineLoopInfo.h,.cpp and MachineLICP.cpp to VStudio build
Modified:
llvm/trunk/win32/CodeGen/CodeGen.vcproj
Modified:
Author: evancheng
Date: Fri Dec 7 19:00:21 2007
New Revision: 44691
URL: http://llvm.org/viewvc/llvm-project?rev=44691view=rev
Log:
Fix a compilation warning.
Modified:
llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp
Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp
URL:
On Dec 7, 2007 2:24 PM, Chris Lattner [EMAIL PROTECTED] wrote:
I know you're kidding, but have you benchmarked this on the G5? In
this specific case, foo is probably MUCH faster because the loop is
one dispatch group instead of two (I think). :)
It made this program slower:
$ cat t.c
On Dec 7, 2007, at 8:13 AM, Chris Lattner wrote:
Hey Evan,
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Dec 7
02:07:39 2007
@@ -2754,10 +2754,33 @@
}
std::swap(V1, V2);
- Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, MaskVec[0],
MaskVec.size());
+ Mask =
On Dec 7, 2007, at 1:42 PM, Bill Wendling wrote:
_foo:
li r2, 0
LBB1_1: ; bb
li r5, 0
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
to:
_foo:
li r2, 0
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