Author: evancheng
Date: Fri Jul 6 18:22:46 2007
New Revision: 37961
URL: http://llvm.org/viewvc/llvm-project?rev=37961&view=rev
Log:
Do away with ImmutablePredicateOperand.
Modified:
llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=37961&r1=37960&r2=37961&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Fri Jul 6 18:22:46 2007
@@ -288,7 +288,7 @@
// Conditional code operand for conditional branches and conditional moves.
// No AlwaysVal value.
-def ccop : ImmutablePredicateOperand<OtherVT, (ops i32imm, CCR), (ops)> {
+def ccop : PredicateOperand<OtherVT, (ops i32imm, CCR), (ops)> {
let PrintMethod = "printPredicateOperand";
}
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td?rev=37961&r1=37960&r2=37961&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td Fri Jul 6 18:22:46 2007
@@ -272,8 +272,8 @@
// PowerPC Predicate operand. 20 = (0<<5)|20 = always, CR0 is a dummy reg
// that doesn't matter.
-def pred : ImmutablePredicateOperand<OtherVT, (ops imm, CRRC),
- (ops (i32 20), CR0)> {
+def pred : PredicateOperand<OtherVT, (ops imm, CRRC),
+ (ops (i32 20), CR0)> {
let PrintMethod = "printPredicateOperand";
}
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