Hi Chris,
Assuming an expansion from i64 to 2x i32, the code above will work
for sextinreg amounts between 1 and 32. For greater amounts, the top
part should get a sextinreg, and the bottom part should or togther
the top and bottom shifted parts, similar to a expanded shift.
not sure
On Oct 21, 2007, at 10:34 AM, Duncan Sands wrote:
Hi Chris,
Assuming an expansion from i64 to 2x i32, the code above will work
for sextinreg amounts between 1 and 32. For greater amounts, the top
part should get a sextinreg, and the bottom part should or togther
the top and bottom shifted
Hi Chris,
+void DAGTypeLegalizer::
+ExpandResult_SIGN_EXTEND_INREG(SDNode *N, SDOperand Lo, SDOperand Hi) {
+ GetExpandedOp(N-getOperand(0), Lo, Hi);
+
+ // sext_inreg the low part if needed.
+ Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, Lo.getValueType(), Lo,
+
On Oct 19, 2007, at 1:31 AM, Duncan Sands wrote:
Hi Chris,
+void DAGTypeLegalizer::
+ExpandResult_SIGN_EXTEND_INREG(SDNode *N, SDOperand Lo,
SDOperand Hi) {
+ GetExpandedOp(N-getOperand(0), Lo, Hi);
+
+ // sext_inreg the low part if needed.
+ Lo =
Author: lattner
Date: Thu Oct 18 23:46:45 2007
New Revision: 43171
URL: http://llvm.org/viewvc/llvm-project?rev=43171view=rev
Log:
Implement a few new operations.
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAGTypes.cpp
Modified:
