> Index: lib/CodeGen/LiveIntervalAnalysis.cpp
> ===
> RCS file: /var/cvs/llvm/llvm/lib/CodeGen/LiveIntervalAnalysis.cpp,v
> retrieving revision 1.204
> diff -u -r1.204 LiveIntervalAnalysis.cpp
> --- lib/CodeGen/LiveIntervalAnalysis.cpp
The read_latency.patch is incomplete. I forgot to deal with spill live
intervals.
Lauro
2007/2/6, Lauro Ramos Venancio <[EMAIL PROTECTED]>:
READ_LATENCY patch for review.
Sample of use:
class RegConstraint {
string Constraints = C;
}
// AI_orr - Defines a (op r, r) pattern.
class AI_orr
: A
READ_LATENCY patch for review.
Sample of use:
class RegConstraint {
string Constraints = C;
}
// AI_orr - Defines a (op r, r) pattern.
class AI_orr
: AI<(ops GPR:$dst, GPR:$a, GPR:$b),
!strconcat(opc, " $dst, $a, $b"),
[(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>,
RegConstraint<"$a
On Jan 26, 2007, at 1:07 PM, Lauro Ramos Venancio wrote:
>> The facility does that have to be that general. There are 4 cycles
>> between every two instructions. See LiveIntervalAnalysis:
>>
>> struct InstrSlots {
>>enum {
>> LOAD = 0,
>> USE = 1,
>> DE
On Jan 26, 2007, at 1:08 PM, Lauro Ramos Venancio wrote:
> Hi Chris,
>
> In ARM v4/v5 specification, mul %r0, %r0, %r1 (r0 = r0*r1) is invalid,
> but mul %r0, %r1, %r0 is valid. With early-clobber constraint, ARM
> backend wouldn't emit the the mul %r0, %r1, %r0. We need a constraint
> only for t
Hi Chris,
In ARM v4/v5 specification, mul %r0, %r0, %r1 (r0 = r0*r1) is invalid,
but mul %r0, %r1, %r0 is valid. With early-clobber constraint, ARM
backend wouldn't emit the the mul %r0, %r1, %r0. We need a constraint
only for the first source register.
Lauro
2007/1/26, Chris Lattner <[EMAIL PR
> The facility does that have to be that general. There are 4 cycles
> between every two instructions. See LiveIntervalAnalysis:
>
> struct InstrSlots {
>enum {
> LOAD = 0,
> USE = 1,
> DEF = 2,
> STORE = 3,
> NUM = 4
>};
>
On Jan 26, 2007, at 6:09 AM, Lauro Ramos Venancio wrote:
> Hi Evan,
>
> Tanks for your review.
>
>> 1. I think rather than adding a constraint that says a source operand
>> must not be assigned the same register as another. It would be better
>> if you add a constraint that says a source operand
On Jan 26, 2007, at 6:09 AM, Lauro Ramos Venancio wrote:
>> 1. I think rather than adding a constraint that says a source operand
>> must not be assigned the same register as another. It would be better
>> if you add a constraint that says a source operand "can be killed at
>> issue cycle + n". The
Hi Evan,
Tanks for your review.
> 1. I think rather than adding a constraint that says a source operand
> must not be assigned the same register as another. It would be better
> if you add a constraint that says a source operand "can be killed at
> issue cycle + n". The live range analysis curren
Hi Lauro,
Thanks for taking a crack at this! Your work is much appreciated.
However, I have some comments. :-)
1. I think rather than adding a constraint that says a source operand
must not be assigned the same register as another. It would be better
if you add a constraint that says a sourc
This patch implements the instruction constraint DestReg!=SrcReg. It
is needed by ARM backend.
A sample of use of this constraint is following:
class RegConstraint {
string Constraints = C;
}
// AI_orr - Defines a (op r, r) pattern.
class AI_orr
: AI<(ops GPR:$dst, GPR:$a, GPR:$b),
!str
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