Changes in directory llvm/lib/Target/PowerPC:
PPCBranchSelector.cpp updated: 1.21 -> 1.22 PPCISelDAGToDAG.cpp updated: 1.168 -> 1.169 PPCISelLowering.cpp updated: 1.96 -> 1.97 PPCInstrInfo.td updated: 1.185 -> 1.186 README.txt updated: 1.73 -> 1.74 --- Log message: Remove BRTWOWAY* Make the PPC backend not dependent on BRTWOWAY_CC and make the branch selector smarter about the code it generates, fixing a case in the readme. --- Diffs of the changes: (+11 -80) PPCBranchSelector.cpp | 8 ++------ PPCISelDAGToDAG.cpp | 38 ++++---------------------------------- PPCISelLowering.cpp | 5 ++--- PPCInstrInfo.td | 3 +-- README.txt | 37 ++----------------------------------- 5 files changed, 11 insertions(+), 80 deletions(-) Index: llvm/lib/Target/PowerPC/PPCBranchSelector.cpp diff -u llvm/lib/Target/PowerPC/PPCBranchSelector.cpp:1.21 llvm/lib/Target/PowerPC/PPCBranchSelector.cpp:1.22 --- llvm/lib/Target/PowerPC/PPCBranchSelector.cpp:1.21 Wed Feb 8 13:33:26 2006 +++ llvm/lib/Target/PowerPC/PPCBranchSelector.cpp Thu Mar 16 19:40:33 2006 @@ -48,10 +48,10 @@ static unsigned getNumBytesForInstruction(MachineInstr *MI) { switch (MI->getOpcode()) { case PPC::COND_BRANCH: - // while this will be 4 most of the time, if we emit 12 it is just a + // while this will be 4 most of the time, if we emit 8 it is just a // minor pessimization that saves us from having to worry about // keeping the offsets up to date later when we emit long branch glue. - return 12; + return 8; case PPC::IMPLICIT_DEF_GPR: // no asm emitted case PPC::IMPLICIT_DEF_F4: // no asm emitted case PPC::IMPLICIT_DEF_F8: // no asm emitted @@ -102,7 +102,6 @@ // long branch: // bInverseCC $PC+8 // b .L_TARGET_MBB - // b .L_FALLTHROUGH_MBB for (MachineFunction::iterator MFI = Fn.begin(), E = Fn.end(); MFI != E; ++MFI) { MachineBasicBlock *MBB = MFI; @@ -123,8 +122,6 @@ // 3. fallthrough MBB MachineBasicBlock *trueMBB = MBBI->getOperand(2).getMachineBasicBlock(); - MachineBasicBlock *falseMBB = - MBBI->getOperand(3).getMachineBasicBlock(); int Displacement = OffsetMap[trueMBB] - ByteCount; unsigned Opcode = MBBI->getOperand(1).getImmedValue(); @@ -136,7 +133,6 @@ } else { BuildMI(*MBB, MBBJ, Inverted, 2).addReg(CRReg).addSImm(8); BuildMI(*MBB, MBBJ, PPC::B, 1).addMBB(trueMBB); - BuildMI(*MBB, MBBJ, PPC::B, 1).addMBB(falseMBB); } // Erase the psuedo COND_BRANCH instruction, and then back up the Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp diff -u llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.168 llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.169 --- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.168 Thu Mar 16 12:25:23 2006 +++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Thu Mar 16 19:40:33 2006 @@ -1105,44 +1105,14 @@ N2, N3, getI32Imm(BROpc)); return; } - case ISD::BR_CC: - case ISD::BRTWOWAY_CC: { + case ISD::BR_CC: { SDOperand Chain; Select(Chain, N->getOperand(0)); - MachineBasicBlock *Dest = - cast<BasicBlockSDNode>(N->getOperand(4))->getBasicBlock(); ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get(); SDOperand CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC); - - // If this is a two way branch, then grab the fallthrough basic block - // argument and build a PowerPC branch pseudo-op, suitable for long branch - // conversion if necessary by the branch selection pass. Otherwise, emit a - // standard conditional branch. - if (N->getOpcode() == ISD::BRTWOWAY_CC) { - SDOperand CondTrueBlock = N->getOperand(4); - SDOperand CondFalseBlock = N->getOperand(5); - unsigned Opc = getBCCForSetCC(CC); - SDOperand CB = - SDOperand(CurDAG->getTargetNode(PPC::COND_BRANCH, MVT::Other, - CondCode, getI32Imm(Opc), - CondTrueBlock, CondFalseBlock, - Chain), 0); - Result = CurDAG->SelectNodeTo(N, PPC::B, MVT::Other, CondFalseBlock, CB); - } else { - // Iterate to the next basic block - ilist<MachineBasicBlock>::iterator It = BB; - ++It; - - // If the fallthrough path is off the end of the function, which would be - // undefined behavior, set it to be the same as the current block because - // we have nothing better to set it to, and leaving it alone will cause - // the PowerPC Branch Selection pass to crash. - if (It == BB->getParent()->end()) It = Dest; - Result = CurDAG->SelectNodeTo(N, PPC::COND_BRANCH, MVT::Other, CondCode, - getI32Imm(getBCCForSetCC(CC)), - N->getOperand(4), CurDAG->getBasicBlock(It), - Chain); - } + Result = CurDAG->SelectNodeTo(N, PPC::COND_BRANCH, MVT::Other, + CondCode, getI32Imm(getBCCForSetCC(CC)), + N->getOperand(4), Chain); return; } } Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.96 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.97 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.96 Mon Mar 13 17:20:37 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Thu Mar 16 19:40:33 2006 @@ -94,9 +94,8 @@ // PowerPC wants to optimize integer setcc a bit setOperationAction(ISD::SETCC, MVT::i32, Custom); - // PowerPC does not have BRCOND* which requires SetCC - setOperationAction(ISD::BRCOND, MVT::Other, Expand); - setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand); + // PowerPC does not have BRCOND which requires SetCC + setOperationAction(ISD::BRCOND, MVT::Other, Expand); // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores. setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.185 llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.186 --- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.185 Thu Mar 16 16:35:59 2006 +++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Thu Mar 16 19:40:33 2006 @@ -245,8 +245,7 @@ let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, noResults = 1, PPC970_Unit = 7 in { - def COND_BRANCH : Pseudo<(ops CRRC:$crS, u16imm:$opc, - target:$true, target:$false), + def COND_BRANCH : Pseudo<(ops CRRC:$crS, u16imm:$opc, target:$true), "; COND_BRANCH", []>; def B : IForm<18, 0, 0, (ops target:$dst), "b $dst", BrB, Index: llvm/lib/Target/PowerPC/README.txt diff -u llvm/lib/Target/PowerPC/README.txt:1.73 llvm/lib/Target/PowerPC/README.txt:1.74 --- llvm/lib/Target/PowerPC/README.txt:1.73 Thu Mar 16 16:37:48 2006 +++ llvm/lib/Target/PowerPC/README.txt Thu Mar 16 19:40:33 2006 @@ -10,41 +10,8 @@ ===-------------------------------------------------------------------------=== -Should hint to the branch select pass that it doesn't need to print the second -unconditional branch, so we don't end up with things like: - b .LBBl42__2E_expand_function_8_674 ; loopentry.24 - b .LBBl42__2E_expand_function_8_42 ; NewDefault - b .LBBl42__2E_expand_function_8_42 ; NewDefault - -This occurs in SPASS. - -The power of diet coke came up with a solution to this today: - -We know the only two cases that can happen here are either: -a) we have a conditional branch followed by a fallthrough to the next BB -b) we have a conditional branch followed by an unconditional branch - -We also invented the BRTWOWAY node to model (b). - -Currently, these are modeled by the PPC_BRCOND node which is a 12-byte pseudo -that codegens to - bccinv false -true: - b truebb -false: - b falsebb - -However, realizing that for (a), we can bccinv directly to the fallthrough -block, and for (b) we will already have another unconditional branch after -the conditional branch (see SPASS case above), then we know that we don't need -BRTWOWAY at all, and can just codegen PPC_BRCOND as - -bccinv +8 -b truebb - -This will also allow us to selectively not run the ppc branch selector, by just -selecting PPC_BRCOND pseudo directly to the correct conditional branch -instruction for small functions. +Teach the .td file to pattern match PPC::BR_COND to appropriate bc variant, so +we don't have to always run the branch selector for small functions. ===-------------------------------------------------------------------------=== _______________________________________________ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits