Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.cpp updated: 1.10 -> 1.11 SparcV8InstrInfo.h updated: 1.6 -> 1.7 SparcV8RegisterInfo.cpp updated: 1.34 -> 1.35 SparcV8RegisterInfo.h updated: 1.7 -> 1.8 SparcV8TargetMachine.cpp updated: 1.38 -> 1.39 --- Log message: Two changes: 1. Treat FMOVD as a copy instruction, to help with coallescing in V9 mode 2. When in V9 mode, insert FMOVD instead of FpMOVD instructions, as we don't ever rewrite FpMOVD instructions into FMOVS instructions, thus we just end up with commented out copies! This should fix a bunch of failures in V9 mode on sparc. --- Diffs of the changes: (+24 -17) SparcV8InstrInfo.cpp | 23 ++++++++++++----------- SparcV8InstrInfo.h | 2 +- SparcV8RegisterInfo.cpp | 9 ++++++--- SparcV8RegisterInfo.h | 5 ++++- SparcV8TargetMachine.cpp | 2 +- 5 files changed, 24 insertions(+), 17 deletions(-) Index: llvm/lib/Target/SparcV8/SparcV8InstrInfo.cpp diff -u llvm/lib/Target/SparcV8/SparcV8InstrInfo.cpp:1.10 llvm/lib/Target/SparcV8/SparcV8InstrInfo.cpp:1.11 --- llvm/lib/Target/SparcV8/SparcV8InstrInfo.cpp:1.10 Fri Feb 3 00:44:54 2006 +++ llvm/lib/Target/SparcV8/SparcV8InstrInfo.cpp Sat Feb 4 00:58:46 2006 @@ -17,12 +17,13 @@ #include "SparcV8GenInstrInfo.inc" using namespace llvm; -SparcV8InstrInfo::SparcV8InstrInfo() - : TargetInstrInfo(SparcV8Insts, sizeof(SparcV8Insts)/sizeof(SparcV8Insts[0])){ +SparcV8InstrInfo::SparcV8InstrInfo(SparcV8Subtarget &ST) + : TargetInstrInfo(SparcV8Insts, sizeof(SparcV8Insts)/sizeof(SparcV8Insts[0])), + RI(ST) { } -static bool isZeroImmed (const MachineOperand &op) { - return (op.isImmediate() && op.getImmedValue() == 0); +static bool isZeroImm(const MachineOperand &op) { + return op.isImmediate() && op.getImmedValue() == 0; } /// Return true if the instruction is a register to register move and @@ -44,13 +45,13 @@ SrcReg = MI.getOperand(1).getReg(); return true; } - } else if (MI.getOpcode() == V8::ORri || MI.getOpcode() == V8::ADDri) { - if (isZeroImmed(MI.getOperand(2)) && MI.getOperand(1).isRegister()) { - DstReg = MI.getOperand(0).getReg(); - SrcReg = MI.getOperand(1).getReg(); - return true; - } - } else if (MI.getOpcode() == V8::FMOVS || MI.getOpcode() == V8::FpMOVD) { + } else if (MI.getOpcode() == V8::ORri || MI.getOpcode() == V8::ADDri && + isZeroImm(MI.getOperand(2)) && MI.getOperand(1).isRegister()) { + DstReg = MI.getOperand(0).getReg(); + SrcReg = MI.getOperand(1).getReg(); + return true; + } else if (MI.getOpcode() == V8::FMOVS || MI.getOpcode() == V8::FpMOVD || + MI.getOpcode() == V8::FMOVD) { SrcReg = MI.getOperand(1).getReg(); DstReg = MI.getOperand(0).getReg(); return true; Index: llvm/lib/Target/SparcV8/SparcV8InstrInfo.h diff -u llvm/lib/Target/SparcV8/SparcV8InstrInfo.h:1.6 llvm/lib/Target/SparcV8/SparcV8InstrInfo.h:1.7 --- llvm/lib/Target/SparcV8/SparcV8InstrInfo.h:1.6 Fri Feb 3 00:44:54 2006 +++ llvm/lib/Target/SparcV8/SparcV8InstrInfo.h Sat Feb 4 00:58:46 2006 @@ -34,7 +34,7 @@ class SparcV8InstrInfo : public TargetInstrInfo { const SparcV8RegisterInfo RI; public: - SparcV8InstrInfo(); + SparcV8InstrInfo(SparcV8Subtarget &ST); /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As /// such, whenever a client has an instance of instruction info, it should Index: llvm/lib/Target/SparcV8/SparcV8RegisterInfo.cpp diff -u llvm/lib/Target/SparcV8/SparcV8RegisterInfo.cpp:1.34 llvm/lib/Target/SparcV8/SparcV8RegisterInfo.cpp:1.35 --- llvm/lib/Target/SparcV8/SparcV8RegisterInfo.cpp:1.34 Fri Feb 3 01:06:25 2006 +++ llvm/lib/Target/SparcV8/SparcV8RegisterInfo.cpp Sat Feb 4 00:58:46 2006 @@ -13,6 +13,7 @@ #include "SparcV8.h" #include "SparcV8RegisterInfo.h" +#include "SparcV8Subtarget.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFrameInfo.h" @@ -21,9 +22,10 @@ #include <iostream> using namespace llvm; -SparcV8RegisterInfo::SparcV8RegisterInfo() +SparcV8RegisterInfo::SparcV8RegisterInfo(SparcV8Subtarget &st) : SparcV8GenRegisterInfo(V8::ADJCALLSTACKDOWN, - V8::ADJCALLSTACKUP) {} + V8::ADJCALLSTACKUP), Subtarget(st) { +} void SparcV8RegisterInfo:: storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, @@ -63,7 +65,8 @@ else if (RC == V8::FPRegsRegisterClass) BuildMI(MBB, I, V8::FMOVS, 1, DestReg).addReg(SrcReg); else if (RC == V8::DFPRegsRegisterClass) - BuildMI(MBB, I, V8::FpMOVD, 1, DestReg).addReg(SrcReg); + BuildMI(MBB, I, Subtarget.isV9() ? V8::FMOVD : V8::FpMOVD, + 1, DestReg).addReg(SrcReg); else assert (0 && "Can't copy this register"); } Index: llvm/lib/Target/SparcV8/SparcV8RegisterInfo.h diff -u llvm/lib/Target/SparcV8/SparcV8RegisterInfo.h:1.7 llvm/lib/Target/SparcV8/SparcV8RegisterInfo.h:1.8 --- llvm/lib/Target/SparcV8/SparcV8RegisterInfo.h:1.7 Fri Feb 3 01:06:25 2006 +++ llvm/lib/Target/SparcV8/SparcV8RegisterInfo.h Sat Feb 4 00:58:46 2006 @@ -19,10 +19,13 @@ namespace llvm { +class SparcV8Subtarget; class Type; struct SparcV8RegisterInfo : public SparcV8GenRegisterInfo { - SparcV8RegisterInfo(); + SparcV8Subtarget &Subtarget; + + SparcV8RegisterInfo(SparcV8Subtarget &st); /// Code Generation virtual methods... void storeRegToStackSlot(MachineBasicBlock &MBB, Index: llvm/lib/Target/SparcV8/SparcV8TargetMachine.cpp diff -u llvm/lib/Target/SparcV8/SparcV8TargetMachine.cpp:1.38 llvm/lib/Target/SparcV8/SparcV8TargetMachine.cpp:1.39 --- llvm/lib/Target/SparcV8/SparcV8TargetMachine.cpp:1.38 Thu Jan 26 00:51:21 2006 +++ llvm/lib/Target/SparcV8/SparcV8TargetMachine.cpp Sat Feb 4 00:58:46 2006 @@ -35,7 +35,7 @@ IntrinsicLowering *IL, const std::string &FS) : TargetMachine("SparcV8", IL, false, 4, 4), - Subtarget(M, FS), + Subtarget(M, FS), InstrInfo(Subtarget), FrameInfo(TargetFrameInfo::StackGrowsDown, 8, 0) { } _______________________________________________ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits