[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp

Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.47 - 1.48 --- Log message: If a call return type is i1, insert a truncate from X86::AL to i1. --- Diffs of the changes: (+4 -0) X86ISelLowering.cpp |4 1 files changed, 4 insertions(+) Index:

[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp

Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.48 - 1.49 --- Log message: SRA shift amount must be in i8 --- Diffs of the changes: (+1 -1) X86ISelLowering.cpp |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index:

[llvm-commits] CVS: llvm/lib/CodeGen/DwarfWriter.cpp

Changes in directory llvm/lib/CodeGen: DwarfWriter.cpp updated: 1.7 - 1.8 --- Log message: Added minimum Dwarf aranges. Cleaned up some section headers. Line number support now works in gdb. --- Diffs of the changes: (+47 -7) DwarfWriter.cpp | 54

[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

Changes in directory llvm/lib/Target/PowerPC: PPCAsmPrinter.cpp updated: 1.138 - 1.139 --- Log message: Added minimum Dwarf aranges. Cleaned up some section headers. Line number support now works in gdb. --- Diffs of the changes: (+12 -12) PPCAsmPrinter.cpp | 24

[llvm-commits] CVS: llvm/include/llvm/CodeGen/DwarfWriter.h

Changes in directory llvm/include/llvm/CodeGen: DwarfWriter.h updated: 1.10 - 1.11 --- Log message: Added minimum Dwarf aranges. Cleaned up some section headers. Line number support now works in gdb. --- Diffs of the changes: (+6 -6) DwarfWriter.h | 12 ++-- 1 files changed, 6

[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Changes in directory llvm/lib/CodeGen/SelectionDAG: DAGCombiner.cpp updated: 1.83 - 1.84 --- Log message: Fix a backwards conditional that caused an inf loop in some cases. This fixes: test/Regression/CodeGen/Generic/2005-01-18-SetUO-InfLoop.ll --- Diffs of the changes: (+1 -1)

[llvm-commits] CVS: llvm/test/Regression/CodeGen/PowerPC/2006-01-18-InvalidBranchOpcodeAssert.ll

Changes in directory llvm/test/Regression/CodeGen/PowerPC: 2006-01-18-InvalidBranchOpcodeAssert.ll added (r1.1) --- Log message: new testcase --- Diffs of the changes: (+16 -0) 2006-01-18-InvalidBranchOpcodeAssert.ll | 16 1 files changed, 16 insertions(+) Index:

[llvm-commits] CVS: llvm/test/Regression/CodeGen/Generic/2005-01-18-SetUO-InfLoop.ll

Changes in directory llvm/test/Regression/CodeGen/Generic: 2005-01-18-SetUO-InfLoop.ll added (r1.1) --- Log message: this testcase sent the dag combiner spinning into an infinite loop --- Diffs of the changes: (+19 -0) 2005-01-18-SetUO-InfLoop.ll | 19 +++ 1 files

[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrInfo.h

Changes in directory llvm/lib/Target/PowerPC: PPCInstrInfo.h updated: 1.8 - 1.9 --- Log message: fix out of date comment --- Diffs of the changes: (+1 -1) PPCInstrInfo.h |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/PowerPC/PPCInstrInfo.h diff -u

[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp

Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.67 - 1.68 --- Log message: Don't assert on 'select_cc SETUO' --- Diffs of the changes: (+2 -2) PPCISelLowering.cpp |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index:

[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrInfo.h

Changes in directory llvm/lib/Target/PowerPC: PPCInstrInfo.h updated: 1.7 - 1.8 --- Log message: Fix Regression/CodeGen/PowerPC/2006-01-18-InvalidBranchOpcodeAssert.ll --- Diffs of the changes: (+2 -0) PPCInstrInfo.h |2 ++ 1 files changed, 2 insertions(+) Index:

[llvm-commits] CVS: llvm/lib/Transforms/Utils/CloneModule.cpp

Changes in directory llvm/lib/Transforms/Utils: CloneModule.cpp updated: 1.14 - 1.15 --- Log message: Make sure that cloning a module clones its target triple and dependent library list as well. This should help bugpoint. --- Diffs of the changes: (+7 -3) CloneModule.cpp | 10

[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

Changes in directory llvm/lib/CodeGen/SelectionDAG: SelectionDAGISel.cpp updated: 1.127 - 1.128 --- Log message: Temporary work around for a libcall insertion bug: If a target doesn't support FSIN/FCOS nodes, do not lower sin/cos to them. --- Diffs of the changes: (+6 -2)

[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Changes in directory llvm/lib/CodeGen/SelectionDAG: DAGCombiner.cpp updated: 1.84 - 1.85 --- Log message: Get rid of code in the DAGCombiner that is duplicated in SelectionDAG.cpp Now all constant folding in the code generator is in one place. --- Diffs of the changes: (+80 -74)

[llvm-commits] CVS: llvm/test/Regression/CodeGen/Alpha/2006-01-18-MissedGlobal.ll

Changes in directory llvm/test/Regression/CodeGen/Alpha: 2006-01-18-MissedGlobal.ll added (r1.1) --- Log message: a reduced test case, the GlobalAddress is never legalized --- Diffs of the changes: (+30 -0) 2006-01-18-MissedGlobal.ll | 30 ++ 1 files changed,

[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

Changes in directory llvm/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp updated: 1.269 - 1.270 --- Log message: was ignoring the legalized chain in this case, fixed SPASS on alpha --- Diffs of the changes: (+1 -1) LegalizeDAG.cpp |2 +- 1 files changed, 1 insertion(+), 1 deletion(-)

[llvm-commits] CVS: llvm/lib/Transforms/IPO/Internalize.cpp

Changes in directory llvm/lib/Transforms/IPO: Internalize.cpp updated: 1.28 - 1.29 --- Log message: Don't internalize llvm.global[cd]tor unless there are uses of it. This unbreaks front-ends that don't use __main (like the new CFE). --- Diffs of the changes: (+9 -3) Internalize.cpp |

[llvm-commits] CVS: llvm/lib/Transforms/IPO/Internalize.cpp

Changes in directory llvm/lib/Transforms/IPO: Internalize.cpp updated: 1.29 - 1.30 --- Log message: If not internalizing, don't mark llvm.global[cd]tors const, as a fix for a hypothetical future boog. --- Diffs of the changes: (+5 -2) Internalize.cpp |7 +-- 1 files changed, 5

[llvm-commits] CVS: llvm/test/Feature/intrinsics.ll

Changes in directory llvm/test/Feature: intrinsics.ll updated: 1.10 - 1.11 --- Log message: Expand test to cover the non-overloaded variants of the arithmetic and floating point intrinsics. --- Diffs of the changes: (+45 -1) intrinsics.ll | 46

[llvm-commits] CVS: llvm/lib/VMCore/Verifier.cpp

Changes in directory llvm/lib/VMCore: Verifier.cpp updated: 1.144 - 1.145 --- Log message: Don't accept the ctpop, cttz, or ctlz intrinsics with signed arguments. The interface requires unsigned arguments. --- Diffs of the changes: (+16 -36) Verifier.cpp | 52

[llvm-commits] CVS: llvm/lib/Bytecode/Reader/Reader.cpp

Changes in directory llvm/lib/Bytecode/Reader: Reader.cpp updated: 1.178 - 1.179 --- Log message: Make sure intrinsic auto-upgrade is invoked correctly. --- Diffs of the changes: (+5 -0) Reader.cpp |5 + 1 files changed, 5 insertions(+) Index: llvm/lib/Bytecode/Reader/Reader.cpp

[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp X86ISelLowering.cpp

Changes in directory llvm/lib/Target/X86: X86ISelDAGToDAG.cpp updated: 1.33 - 1.34 X86ISelLowering.cpp updated: 1.49 - 1.50 --- Log message: A obvious typo --- Diffs of the changes: (+3 -1) X86ISelDAGToDAG.cpp |2 ++ X86ISelLowering.cpp |2 +- 2 files changed, 3 insertions(+), 1

[llvm-commits] CVS: llvm/utils/TableGen/DAGISelEmitter.cpp

Changes in directory llvm/utils/TableGen: DAGISelEmitter.cpp updated: 1.135 - 1.136 --- Log message: Prevent unnecessary CopyToReg when the same HW register appears in two spots in the pattern. --- Diffs of the changes: (+9 -0) DAGISelEmitter.cpp |9 + 1 files changed, 9

[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.td

Changes in directory llvm/lib/Target/X86: X86InstrInfo.td updated: 1.211 - 1.212 --- Log message: Two peepholes: (or (x c) | (y (32 - c))) == (shrd x, y, c) (or (x c) | (y (32 - c))) == (shld x, y, c) --- Diffs of the changes: (+10 -0) X86InstrInfo.td | 10 ++ 1 files

[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp

Changes in directory llvm/lib/Target/X86: X86ISelDAGToDAG.cpp updated: 1.34 - 1.35 --- Log message: Didn't mean to check that in. --- Diffs of the changes: (+0 -2) X86ISelDAGToDAG.cpp |2 -- 1 files changed, 2 deletions(-) Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp diff -u

[llvm-commits] CVS: llvm/lib/Target/PowerPC/README.txt

Changes in directory llvm/lib/Target/PowerPC: README.txt updated: 1.45 - 1.46 --- Log message: add a note --- Diffs of the changes: (+4 -0) README.txt |4 1 files changed, 4 insertions(+) Index: llvm/lib/Target/PowerPC/README.txt diff -u llvm/lib/Target/PowerPC/README.txt:1.45

[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

Changes in directory llvm/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp updated: 1.270 - 1.271 --- Log message: Another typo --- Diffs of the changes: (+1 -1) LegalizeDAG.cpp |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp diff

[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.td

Changes in directory llvm/lib/Target/X86: X86InstrInfo.td updated: 1.212 - 1.213 --- Log message: adc and sbb need an incoming flag to ensure it reads the carry flag from add / sub. --- Diffs of the changes: (+3 -2) X86InstrInfo.td |5 +++-- 1 files changed, 3 insertions(+), 2

[llvm-commits] CVS: llvm/include/llvm/Assembly/AutoUpgrade.h

Changes in directory llvm/include/llvm/Assembly: AutoUpgrade.h updated: 1.2 - 1.3 --- Log message: 1. Documentation upgrade. 2. Have UpgradeInstrinicCall return an Instruction* instead of a CallInst* and return the needed CastInst* if the result of the upgraded call needs to be casted

[llvm-commits] CVS: llvm/lib/Bytecode/Reader/Reader.cpp

Changes in directory llvm/lib/Bytecode/Reader: Reader.cpp updated: 1.179 - 1.180 --- Log message: 1. Identify bytecode modules that have upgraded intrinsics by setting a boolean flag if we read a function prototype that needs upgrading. 2. Don't upgrade the CallInst instruction until after

[llvm-commits] CVS: llvm/lib/Bytecode/Reader/Reader.h

Changes in directory llvm/lib/Bytecode/Reader: Reader.h updated: 1.25 - 1.26 --- Log message: Add a flag to identify bytecode files that have intrinsic functions that need to be upgraded. --- Diffs of the changes: (+7 -0) Reader.h |7 +++ 1 files changed, 7 insertions(+) Index:

[llvm-commits] CVS: llvm/lib/VMCore/AutoUpgrade.cpp

Changes in directory llvm/lib/VMCore: AutoUpgrade.cpp updated: 1.3 - 1.4 --- Log message: Don't forget about casting the result of an upgraded call to an intrinsic in the case where it needs to cast back to a signed type. --- Diffs of the changes: (+4 -1) AutoUpgrade.cpp |5 - 1

[llvm-commits] CVS: llvm/test/Regression/Bytecode/old-intrinsics.ll

Changes in directory llvm/test/Regression/Bytecode: old-intrinsics.ll updated: 1.1 - 1.2 --- Log message: This test passes now. --- Diffs of the changes: (+0 -1) old-intrinsics.ll |1 - 1 files changed, 1 deletion(-) Index: llvm/test/Regression/Bytecode/old-intrinsics.ll diff -u

[llvm-commits] CVS: llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp

Changes in directory llvm/lib/Target/SparcV8: SparcV8ISelDAGToDAG.cpp updated: 1.55 - 1.56 --- Log message: implement support for f32 arguments past the first 6 words --- Diffs of the changes: (+5 -0) SparcV8ISelDAGToDAG.cpp |5 + 1 files changed, 5 insertions(+) Index: