Changes in directory llvm/test/Regression/Transforms/InstCombine:
2006-04-01-InfLoop.ll added (r1.1)
---
Log message:
New testcase that caused instcombine to infinitely loop (with my recent
patch), distilled from Applications/JM/ldecod
---
Diffs of the changes: (+441 -0)
Changes in directory llvm/lib/Transforms/Scalar:
InstructionCombining.cpp updated: 1.457 - 1.458
---
Log message:
Fix InstCombine/2006-04-01-InfLoop.ll
---
Diffs of the changes: (+2 -1)
InstructionCombining.cpp |3 ++-
1 files changed, 2 insertions(+), 1 deletion(-)
Index:
Changes in directory llvm/lib/Transforms/Utils:
ValueMapper.cpp updated: 1.22 - 1.23
---
Log message:
add valuemapper support for inline asm
---
Diffs of the changes: (+1 -1)
ValueMapper.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index:
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.124 - 1.125
---
Log message:
Custom lower all BUILD_VECTOR's so that we can compile vec_splat_u8(8) into
vspltisb v0, 8 instead of a constant pool load.
---
Diffs of the changes: (+2 -0)
PPCISelLowering.cpp |
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAG.cpp updated: 1.293 - 1.294
---
Log message:
Add some missing node names
---
Diffs of the changes: (+9 -0)
SelectionDAG.cpp |9 +
1 files changed, 9 insertions(+)
Index:
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAG.cpp updated: 1.294 - 1.295
---
Log message:
These entries already exist
---
Diffs of the changes: (+0 -4)
SelectionDAG.cpp |4
1 files changed, 4 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.136 - 1.137
---
Log message:
Implement constant folding of bit_convert of arbitrary constant vbuild_vector
nodes.
---
Diffs of the changes: (+139 -2)
DAGCombiner.cpp | 141
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.137 - 1.138
---
Log message:
Constant fold all of the vector binops. This allows us to compile this:
vector unsigned char mergeLowHigh = (vector unsigned char)
( 8, 9, 10, 11, 16, 17, 18, 19, 12, 13, 14, 15, 20,
Changes in directory llvm/utils/TableGen:
IntrinsicEmitter.cpp updated: 1.19 - 1.20
---
Log message:
Adjust the Intrinsics.gen interface a little bit
---
Diffs of the changes: (+2 -2)
IntrinsicEmitter.cpp |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
Index:
Changes in directory llvm/lib/Transforms/Utils:
Local.cpp updated: 1.53 - 1.54
---
Log message:
Adjust to change in Intrinsics.gen interface.
---
Diffs of the changes: (+1 -0)
Local.cpp |1 +
1 files changed, 1 insertion(+)
Index: llvm/lib/Transforms/Utils/Local.cpp
diff -u
Changes in directory llvm/lib/Target/PowerPC:
README_ALTIVEC.txt updated: 1.9 - 1.10
---
Log message:
add a note
---
Diffs of the changes: (+11 -0)
README_ALTIVEC.txt | 11 +++
1 files changed, 11 insertions(+)
Index: llvm/lib/Target/PowerPC/README_ALTIVEC.txt
diff -u
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.350 - 1.351
---
Log message:
Implement promotion for EXTRACT_VECTOR_ELT, allowing v16i8 multiplies to work
with PowerPC.
---
Diffs of the changes: (+27 -16)
LegalizeDAG.cpp | 43
Changes in directory llvm/win32/VMCore:
VMCore.vcproj updated: 1.19 - 1.20
---
Log message:
Fix tablegen related dependencies in Visual Studio.
---
Diffs of the changes: (+8 -8)
VMCore.vcproj | 16
1 files changed, 8 insertions(+), 8 deletions(-)
Index:
Changes in directory llvm/lib/Transforms/Scalar:
InstructionCombining.cpp updated: 1.458 - 1.459
---
Log message:
Turn altivec lvx/stvx intrinsics into loads and stores. This allows the
elimination of one load from this:
int AreSecondAndThirdElementsBothNegative( vector float *in ) {
#define
Changes in directory llvm/lib/Transforms/Scalar:
InstructionCombining.cpp updated: 1.459 - 1.460
---
Log message:
Allow transforming this:
%tmp = cast 4 x uint* %testData to 4 x int* ; 4 x int*
[#uses=1]
%tmp = load 4 x int* %tmp ; 4 x int [#uses=1]
to
Changes in directory llvm/lib/VMCore:
Type.cpp updated: 1.137 - 1.138
---
Log message:
vector casts never reinterpret bits
---
Diffs of the changes: (+5 -0)
Type.cpp |5 +
1 files changed, 5 insertions(+)
Index: llvm/lib/VMCore/Type.cpp
diff -u llvm/lib/VMCore/Type.cpp:1.137
Changes in directory llvm/lib/Transforms/Scalar:
InstructionCombining.cpp updated: 1.460 - 1.461
---
Log message:
vector casts of casts are eliminable. Transform this:
%tmp = cast 4 x uint %tmp to 4 x int; 4 x int
[#uses=1]
%tmp = cast 4 x int %tmp to 4 x
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.138 - 1.139
---
Log message:
Add a little dag combine to compile this:
int %AreSecondAndThirdElementsBothNegative(4 x float* %in) {
entry:
%tmp1 = load 4 x float* %in ; 4 x float [#uses=1]
Changes in directory llvm/lib/Target:
TargetLowering.cpp updated: 1.52 - 1.53
---
Log message:
relax assertion
---
Diffs of the changes: (+4 -1)
TargetLowering.cpp |5 -
1 files changed, 4 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/TargetLowering.cpp
diff -u
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.125 - 1.126
PPCISelLowering.h updated: 1.37 - 1.38
---
Log message:
Inform the dag combiner that the predicate compares only return a low bit.
---
Diffs of the changes: (+39 -1)
PPCISelLowering.cpp | 35
Changes in directory llvm/lib/Target/PowerPC:
README.txt updated: 1.83 - 1.84
---
Log message:
add a note
---
Diffs of the changes: (+9 -0)
README.txt |9 +
1 files changed, 9 insertions(+)
Index: llvm/lib/Target/PowerPC/README.txt
diff -u
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