[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp

Changes in directory llvm/lib/CodeGen/SelectionDAG: ScheduleDAGList.cpp updated: 1.56 - 1.57 --- Log message: Templatify RegReductionPriorityQueue --- Diffs of the changes: (+12 -7) ScheduleDAGList.cpp | 19 --- 1 files changed, 12 insertions(+), 7 deletions(-) Index:

[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp

Changes in directory llvm/lib/Target/PowerPC: PPCRegisterInfo.cpp updated: 1.65 - 1.66 --- Log message: Fix the PowerPC JIT-only failure on UnitTests/Vector/sumarray-dbl, which is really a bad codegen bug that LLC happens to get lucky with. I must chat with Nate for the proper fix. --- Diffs

[llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp

Changes in directory llvm/lib/Transforms/Scalar: InstructionCombining.cpp updated: 1.477 - 1.478 --- Log message: Two changes: 1. Implement InstCombine/deadcode.ll by not adding instructions in unreachable blocks (due to constants in conditional branches/switches) to the worklist. This

[llvm-commits] CVS: llvm/test/Regression/CodeGen/X86/2006-05-08-InstrSched.ll

Changes in directory llvm/test/Regression/CodeGen/X86: 2006-05-08-InstrSched.ll updated: 1.1 - 1.2 --- Log message: Update test case --- Diffs of the changes: (+1 -0) 2006-05-08-InstrSched.ll |1 + 1 files changed, 1 insertion(+) Index:

[llvm-commits] CVS: llvm/Makefile.rules

Changes in directory llvm: Makefile.rules updated: 1.365 - 1.366 --- Log message: Fix some problems linking stuff in libTarget. --- Diffs of the changes: (+1 -1) Makefile.rules |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/Makefile.rules diff -u