[llvm-commits] CVS: llvm/lib/Target/ARM/ARMTargetAsmInfo.cpp

Changes in directory llvm/lib/Target/ARM: ARMTargetAsmInfo.cpp updated: 1.2 - 1.3 --- Log message: Define StaticCtorsSection and StaticDtorsSection for ARM. --- Diffs of the changes: (+2 -0) ARMTargetAsmInfo.cpp |2 ++ 1 files changed, 2 insertions(+) Index:

[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp

Changes in directory llvm/lib/Target/ARM: ARMISelDAGToDAG.cpp updated: 1.96 - 1.97 --- Log message: Expand SELECT (f32/f64) and FCOPYSIGN (f32/f64). --- Diffs of the changes: (+5 -0) ARMISelDAGToDAG.cpp |5 + 1 files changed, 5 insertions(+) Index:

[llvm-commits] CVS: llvm/test/Regression/CodeGen/ARM/fcopysign.ll

Changes in directory llvm/test/Regression/CodeGen/ARM: fcopysign.ll added (r1.1) --- Log message: Add test for FCOPYSIGN. --- Diffs of the changes: (+21 -0) fcopysign.ll | 21 + 1 files changed, 21 insertions(+) Index: llvm/test/Regression/CodeGen/ARM/fcopysign.ll

[llvm-commits] CVS: llvm/test/Regression/CodeGen/ARM/extloadi1.ll

Changes in directory llvm/test/Regression/CodeGen/ARM: extloadi1.ll added (r1.1) --- Log message: Add extload(i1) test. --- Diffs of the changes: (+22 -0) extloadi1.ll | 22 ++ 1 files changed, 22 insertions(+) Index: llvm/test/Regression/CodeGen/ARM/extloadi1.ll

[llvm-commits] CVS: llvm/test/Regression/CodeGen/ARM/ctors_dtors.ll

Changes in directory llvm/test/Regression/CodeGen/ARM: ctors_dtors.ll added (r1.1) --- Log message: Add test for constructor and destructor sections. --- Diffs of the changes: (+16 -0) ctors_dtors.ll | 16 1 files changed, 16 insertions(+) Index:

Re: [llvm-commits] [LLVMdev] combined arm patch

The following patch updates Rafael's patch to apply it on svn revision 247. Lauro 2006/12/6, Rafael Espíndola [EMAIL PROTECTED]: Could you please try to remove the empty gcc/unwind.h and try again? I am currently compiling on a powerbook. I will report as soon as it finishes. The build

[llvm-commits] CVS: llvm/test/Regression/CodeGen/ARM/constants.ll fp.ll fpmem.ll

Changes in directory llvm/test/Regression/CodeGen/ARM: constants.ll updated: 1.8 - 1.9 fp.ll updated: 1.11 - 1.12 fpmem.ll updated: 1.3 - 1.4 --- Log message: Build constants using instructions mov/orr or mvn/eor. --- Diffs of the changes: (+10 -3) constants.ll |3 ++- fp.ll|

[llvm-commits] CVS: llvm/lib/Target/ARM/ARMCommon.cpp ARMCommon.h ARMISelDAGToDAG.cpp ARMRegisterInfo.cpp

Changes in directory llvm/lib/Target/ARM: ARMCommon.cpp added (r1.1) ARMCommon.h added (r1.1) ARMISelDAGToDAG.cpp updated: 1.97 - 1.98 ARMRegisterInfo.cpp updated: 1.31 - 1.32 --- Log message: Build constants using instructions mov/orr or mvn/eor. --- Diffs of the changes: (+186 -89)

[llvm-commits] CVS: llvm/lib/Target/ARM/ARMRegisterInfo.cpp

Changes in directory llvm/lib/Target/ARM: ARMRegisterInfo.cpp updated: 1.32 - 1.33 --- Log message: Don't add or sub zero to sp. --- Diffs of the changes: (+10 -6) ARMRegisterInfo.cpp | 16 ++-- 1 files changed, 10 insertions(+), 6 deletions(-) Index:

[llvm-commits] CVS: llvm/test/Regression/CodeGen/ARM/spaddsub.ll

Changes in directory llvm/test/Regression/CodeGen/ARM: spaddsub.ll added (r1.1) --- Log message: Don't add or sub zero to sp. --- Diffs of the changes: (+10 -0) spaddsub.ll | 10 ++ 1 files changed, 10 insertions(+) Index: llvm/test/Regression/CodeGen/ARM/spaddsub.ll diff -c

[llvm-commits] CVS: llvm/lib/Target/ARM/ARMAsmPrinter.cpp

Changes in directory llvm/lib/Target/ARM: ARMAsmPrinter.cpp updated: 1.43 - 1.44 --- Log message: Fix section definition. --- Diffs of the changes: (+2 -2) ARMAsmPrinter.cpp |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/lib/Target/ARM/ARMAsmPrinter.cpp diff

[llvm-commits] CVS: llvm/lib/Target/ARM/ARMAsmPrinter.cpp

Changes in directory llvm/lib/Target/ARM: ARMAsmPrinter.cpp updated: 1.47 - 1.48 --- Log message: Fix elf object definition. --- Diffs of the changes: (+1 -1) ARMAsmPrinter.cpp |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/ARM/ARMAsmPrinter.cpp diff

[llvm-commits] [patch] Intruction Constraint DestReg!=SrcReg (for review)

This patch implements the instruction constraint DestReg!=SrcReg. It is needed by ARM backend. A sample of use of this constraint is following: class RegConstraintstring C { string Constraints = C; } // AI_orr - Defines a (op r, r) pattern. class AI_orrstring opc, SDNode opnode : AI(ops

[llvm-commits] CVS: llvm/test/CodeGen/ARM/fcopysign.ll

Changes in directory llvm/test/CodeGen/ARM: fcopysign.ll updated: 1.4 - 1.5 --- Log message: fix fcopysign test --- Diffs of the changes: (+4 -4) fcopysign.ll |8 1 files changed, 4 insertions(+), 4 deletions(-) Index: llvm/test/CodeGen/ARM/fcopysign.ll diff -u

Re: [llvm-commits] [patch] Intruction Constraint DestReg!=SrcReg (for review)

Hi Evan, Tanks for your review. 1. I think rather than adding a constraint that says a source operand must not be assigned the same register as another. It would be better if you add a constraint that says a source operand can be killed at issue cycle + n. The live range analysis current

[llvm-commits] CVS: llvm/lib/Target/ARM/ARMAsmPrinter.cpp

Changes in directory llvm/lib/Target/ARM: ARMAsmPrinter.cpp updated: 1.48 - 1.49 --- Log message: If the constant pool value is a extern weak symbol, emit the weak reference. --- Diffs of the changes: (+7 -1) ARMAsmPrinter.cpp |8 +++- 1 files changed, 7 insertions(+), 1

Re: [llvm-commits] [patch] Intruction Constraint DestReg!=SrcReg (for review)

The facility does that have to be that general. There are 4 cycles between every two instructions. See LiveIntervalAnalysis: struct InstrSlots { enum { LOAD = 0, USE = 1, DEF = 2, STORE = 3, NUM = 4 }; }; We

[llvm-commits] [patch] Intruction Constraint DestReg!=SrcReg (for review)

PROTECTED]: On Jan 26, 2007, at 6:09 AM, Lauro Ramos Venancio wrote: 1. I think rather than adding a constraint that says a source operand must not be assigned the same register as another. It would be better if you add a constraint that says a source operand can be killed at issue cycle + n

[llvm-commits] CVS: llvm/lib/Target/ARM/ARMTargetAsmInfo.cpp

Changes in directory llvm/lib/Target/ARM: ARMTargetAsmInfo.cpp updated: 1.7 - 1.8 --- Log message: Fix Data16bitsDirective for ELF. --- Diffs of the changes: (+0 -1) ARMTargetAsmInfo.cpp |1 - 1 files changed, 1 deletion(-) Index: llvm/lib/Target/ARM/ARMTargetAsmInfo.cpp diff -u

[llvm-commits] CVS: llvm/lib/Target/ARM/ARMTargetAsmInfo.cpp

Changes in directory llvm/lib/Target/ARM: ARMTargetAsmInfo.cpp updated: 1.8 - 1.9 --- Log message: Some asm directives fixes for ELF. Now we can compile llvm-gcc on arm-linux-gnueabi! --- Diffs of the changes: (+7 -8) ARMTargetAsmInfo.cpp | 15 +++ 1 files changed, 7

[llvm-commits] CVS: llvm/test/CodeGen/ARM/hello.ll insn-sched1.ll ldm.ll

Changes in directory llvm/test/CodeGen/ARM: hello.ll updated: 1.3 - 1.4 insn-sched1.ll updated: 1.2 - 1.3 ldm.ll updated: 1.3 - 1.4 --- Log message: ARM fix: Miscompilation when frame pointer can't be eliminated. Uninitialized frame pointer register is used. --- Diffs of the changes: (+3

[llvm-commits] CVS: llvm/lib/Target/ARM/ARMRegisterInfo.cpp

Changes in directory llvm/lib/Target/ARM: ARMRegisterInfo.cpp updated: 1.47 - 1.48 --- Log message: ARM fix: Miscompilation when frame pointer can't be eliminated. Uninitialized frame pointer register is used. --- Diffs of the changes: (+9 -10) ARMRegisterInfo.cpp | 19

[llvm-commits] llvm-gcc patch: fix PR1150

Fix PR1150. http://llvm.org/bugs/show_bug.cgi?id=1150 Lauro Index: Makefile.in === --- Makefile.in (revision 262) +++ Makefile.in (working copy) @@ -179,7 +179,9 @@ STAGE_HOST_EXPORTS = \ $(HOST_EXPORTS) \

Re: [llvm-commits] CVS: llvm/lib/Target/ARM/ARMConstantIslandPass.cpp

Hi Evan, Does this patch is correct? According to ARM manual, AddrMode2 and AddrMode3 don't have scale (scale=1). I think MaxOffs should be ((1 Bits) - 1) * Scale. Lauro @@ -304,34 +307,42 @@ continue; assert(0 Unknown addressing mode for CP reference!);

[llvm-commits] CVS: llvm/lib/Target/ARM/ARMAsmPrinter.cpp

Changes in directory llvm/lib/Target/ARM: ARMAsmPrinter.cpp updated: 1.56 - 1.57 --- Log message: Fix .thumb_func directive on linux. --- Diffs of the changes: (+4 -1) ARMAsmPrinter.cpp |5 - 1 files changed, 4 insertions(+), 1 deletion(-) Index:

[llvm-commits] CVS: llvm/lib/Target/ARM/ARMTargetAsmInfo.cpp

Changes in directory llvm/lib/Target/ARM: ARMTargetAsmInfo.cpp updated: 1.10 - 1.11 --- Log message: Define PrivateGlobalPrefix for ARM Linux. (Fix CodeGen/ARM/large_stack.ll) --- Diffs of the changes: (+1 -0) ARMTargetAsmInfo.cpp |1 + 1 files changed, 1 insertion(+) Index:

[llvm-commits] CVS: llvm/lib/Target/ARM/ARMRegisterInfo.cpp

Changes in directory llvm/lib/Target/ARM: ARMRegisterInfo.cpp updated: 1.55 - 1.56 --- Log message: bugfix: SP isn't resetted when function has FP and there is no spills. --- Diffs of the changes: (+3 -2) ARMRegisterInfo.cpp |5 +++-- 1 files changed, 3 insertions(+), 2 deletions(-)

[llvm-commits] CVS: llvm/test/CodeGen/ARM/alloca.ll

Changes in directory llvm/test/CodeGen/ARM: alloca.ll updated: 1.4 - 1.5 --- Log message: Improves alloca test. Verifies SP restoration. --- Diffs of the changes: (+4 -1) alloca.ll |5 - 1 files changed, 4 insertions(+), 1 deletion(-) Index: llvm/test/CodeGen/ARM/alloca.ll diff

[llvm-commits] CVS: llvm/test/CodeGen/ARM/unord.ll

Changes in directory llvm/test/CodeGen/ARM: unord.ll updated: 1.1 - 1.2 --- Log message: Fix unord test. --- Diffs of the changes: (+2 -2) unord.ll |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/test/CodeGen/ARM/unord.ll diff -u

[llvm-commits] CVS: llvm/include/llvm/ADT/UniqueVector.h

Changes in directory llvm/include/llvm/ADT: UniqueVector.h updated: 1.8 - 1.9 --- Log message: Fix build error. UniqueVector.h:66: error: ‘assert’ was not declared in this scope --- Diffs of the changes: (+1 -0) UniqueVector.h |1 + 1 files changed, 1 insertion(+) Index:

Re: [llvm-commits] [patch] Intruction Constraint DestReg!=SrcReg (for review)

:$b))], RegConstraint$a lat 2; Lauro 2007/1/26, Evan Cheng [EMAIL PROTECTED]: On Jan 26, 2007, at 1:07 PM, Lauro Ramos Venancio wrote: The facility does that have to be that general. There are 4 cycles between every two instructions. See LiveIntervalAnalysis: struct InstrSlots

Re: [llvm-commits] [patch] Intruction Constraint DestReg!=SrcReg (for review)

The read_latency.patch is incomplete. I forgot to deal with spill live intervals. Lauro 2007/2/6, Lauro Ramos Venancio [EMAIL PROTECTED]: READ_LATENCY patch for review. Sample of use: class RegConstraintstring C { string Constraints = C; } // AI_orr - Defines a (op r, r) pattern. class

[llvm-commits] CVS: llvm/include/llvm/ADT/APInt.h

Changes in directory llvm/include/llvm/ADT: APInt.h updated: 1.3 - 1.4 --- Log message: Fix build error. include/llvm/ADT/APInt.h:326: error: ‘assert’ was not declared in this scope --- Diffs of the changes: (+1 -0) APInt.h |1 + 1 files changed, 1 insertion(+) Index:

[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

Changes in directory llvm/lib/CodeGen/SelectionDAG: SelectionDAGISel.cpp updated: 1.361 - 1.362 --- Log message: Add original alignment to function arguments flags. --- Diffs of the changes: (+30 -10) SelectionDAGISel.cpp | 40 ++-- 1 files changed,

[llvm-commits] CVS: llvm/test/CodeGen/ARM/arguments.ll

Changes in directory llvm/test/CodeGen/ARM: arguments.ll added (r1.1) --- Log message: According to ARM EABI, 8-bytes function arguments must be 8-bytes aligned. --- Diffs of the changes: (+10 -0) arguments.ll | 10 ++ 1 files changed, 10 insertions(+) Index:

[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp ARMTargetMachine.cpp

Changes in directory llvm/lib/Target/ARM: ARMISelLowering.cpp updated: 1.13 - 1.14 ARMTargetMachine.cpp updated: 1.20 - 1.21 --- Log message: According to ARM EABI, 8-bytes function arguments must be 8-bytes aligned. --- Diffs of the changes: (+53 -30) ARMISelLowering.cpp | 79

Re: [llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp ARMTargetMachine.cpp

there are 5 ARM abi's: ARM_ABI_APCS, ARM_ABI_ATPCS, ARM_ABI_AAPCS, ARM_ABI_IWMMXT, ARM_ABI_AAPCS_LINUX The default is ARM_ABI_APCS, I suppose ARM EABI is ARM_ABI_AAPCS_LINUX? Thanks, Evan On Feb 13, 2007, at 6:07 AM, Lauro Ramos Venancio wrote: Changes

[llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAGNodes.h

Changes in directory llvm/include/llvm/CodeGen: SelectionDAGNodes.h updated: 1.175 - 1.176 --- Log message: Add comment about original function argument alignment. --- Diffs of the changes: (+2 -0) SelectionDAGNodes.h |2 ++ 1 files changed, 2 insertions(+) Index:

[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

Changes in directory llvm/lib/CodeGen/SelectionDAG: SelectionDAGISel.cpp updated: 1.362 - 1.363 --- Log message: Add a space between // and the comment. --- Diffs of the changes: (+9 -9) SelectionDAGISel.cpp | 18 +- 1 files changed, 9 insertions(+), 9 deletions(-)

Re: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

Some comments: 1. Why 27 - 31 instead of 3 - 6? I preferred to separate multi-bit values from boolean values. Please add comment to SelectionDAGNodes.h (see CALL). Added. 2. Purely a stylistic nitpick. Please add a space between // and the actual comment. Added.

[llvm-commits] CVS: llvm/test/CodeGen/ARM/arguments.ll

Changes in directory llvm/test/CodeGen/ARM: arguments.ll updated: 1.1 - 1.2 --- Log message: Add ABI information to ARM subtarget. --- Diffs of the changes: (+1 -1) arguments.ll |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/CodeGen/ARM/arguments.ll diff -u

[llvm-commits] CVS: llvm/lib/Target/ARM/ARMSubtarget.cpp ARMSubtarget.h ARMTargetMachine.cpp

Changes in directory llvm/lib/Target/ARM: ARMSubtarget.cpp updated: 1.2 - 1.3 ARMSubtarget.h updated: 1.2 - 1.3 ARMTargetMachine.cpp updated: 1.21 - 1.22 --- Log message: Add ABI information to ARM subtarget. --- Diffs of the changes: (+24 -8) ARMSubtarget.cpp | 14 ++

Re: [llvm-commits] CVS: llvm/lib/Target/ARM/ARMSubtarget.cpp ARMSubtarget.h ARMTargetMachine.cpp

Hi Lauro, I am not sure if this is correct. Mac OS X sets i64 alignment to 8, but I am not sure if other OS which also uses APCS ABI has the same alignment requirement. In the code, i64 darwin alignment was always 4 bytes. I think it's possible for ARM / Linux to use APCS ABI as well? Is

[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp

Changes in directory llvm/lib/Target/ARM: ARMISelLowering.cpp updated: 1.16 - 1.17 --- Log message: Fix stack alignment in functions with varargs. --- Diffs of the changes: (+5 -2) ARMISelLowering.cpp |7 +-- 1 files changed, 5 insertions(+), 2 deletions(-) Index:

[llvm-commits] CVS: llvm/test/CodeGen/ARM/vargs_align.ll

Changes in directory llvm/test/CodeGen/ARM: vargs_align.ll added (r1.1) --- Log message: Fix stack alignment in functions with varargs. --- Diffs of the changes: (+20 -0) vargs_align.ll | 20 1 files changed, 20 insertions(+) Index:

[llvm-commits] CVS: llvm/test/CodeGen/ARM/vargs_align.ll

Changes in directory llvm/test/CodeGen/ARM: vargs_align.ll updated: 1.1 - 1.2 --- Log message: bugfix: SP wasn't updated for varargs when frame pointer was eliminated. --- Diffs of the changes: (+2 -2) vargs_align.ll |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index:

[llvm-commits] CVS: llvm/lib/Target/ARM/ARMRegisterInfo.cpp

Changes in directory llvm/lib/Target/ARM: ARMRegisterInfo.cpp updated: 1.71 - 1.72 --- Log message: bugfix: SP wasn't updated for varargs when frame pointer was eliminated. --- Diffs of the changes: (+65 -65) ARMRegisterInfo.cpp | 130 ++--

[llvm-commits] [llvm-gcc patch] workaround to fix function arguments aligment on arm-linux-gnueabi

This patch fixes SingleSource/UnitTests/2003-05-07-VarArgs.c test on arm-linux-gnueabi. Lauro Index: gcc/llvm-abi.h === --- gcc/llvm-abi.h (revision 285) +++ gcc/llvm-abi.h (working copy) @@ -32,6 +32,7 @@ #include llvm-internal.h

[llvm-commits] CVS: llvm/lib/Target/ARM/ARMTargetAsmInfo.cpp

Changes in directory llvm/lib/Target/ARM: ARMTargetAsmInfo.cpp updated: 1.11 - 1.12 --- Log message: Use init_array/fini_array sections for static contructors/destructors when the ABI is AAPCS. Fix SingleSource/Regression/C/ConstructorDestructorAttributes test on arm-linux-gnueabi. ---

[llvm-commits] CVS: llvm/test/CodeGen/ARM/ctors_dtors.ll

Changes in directory llvm/test/CodeGen/ARM: ctors_dtors.ll updated: 1.2 - 1.3 --- Log message: Use init_array/fini_array sections for static contructors/destructors when the ABI is AAPCS. Fix SingleSource/Regression/C/ConstructorDestructorAttributes test on arm-linux-gnueabi. --- Diffs of

[llvm-commits] CVS: llvm-test/SingleSource/Regression/C/casts.c

Changes in directory llvm-test/SingleSource/Regression/C: casts.c updated: 1.5 - 1.6 --- Log message: Fix test bug: int64_t isn't the same thing that long --- Diffs of the changes: (+2 -2) casts.c |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index:

[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp

Changes in directory llvm/lib/Target/ARM: ARMISelLowering.cpp updated: 1.23 - 1.24 --- Log message: Only ARMv6 has BSWAP. Fix MultiSource/Applications/aha test. --- Diffs of the changes: (+4 -0) ARMISelLowering.cpp |4 1 files changed, 4 insertions(+) Index:

[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp

Changes in directory llvm/lib/CodeGen/SelectionDAG: ScheduleDAG.cpp updated: 1.122 - 1.123 --- Log message: CopyToReg source operand can be a physical register. --- Diffs of the changes: (+19 -3) ScheduleDAG.cpp | 22 +++--- 1 files changed, 19 insertions(+), 3

[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp ARMInstrInfo.td ARMInstrThumb.td

Changes in directory llvm/lib/Target/ARM: ARMISelLowering.cpp updated: 1.26 - 1.27 ARMInstrInfo.td updated: 1.92 - 1.93 ARMInstrThumb.td updated: 1.17 - 1.18 --- Log message: bugfix: When the source register of CALL_NOLINK was LR, the following code was emitted: mov lr, pc bx lr So,

[llvm-commits] CVS: llvm/test/CodeGen/ARM/call_nolink.ll

Changes in directory llvm/test/CodeGen/ARM: call_nolink.ll added (r1.1) --- Log message: bugfix: When the source register of CALL_NOLINK was LR, the following code was emitted: mov lr, pc bx lr So, the function was not called. --- Diffs of the changes: (+53 -0) call_nolink.ll |

[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp

Changes in directory llvm/lib/CodeGen/SelectionDAG: ScheduleDAG.cpp updated: 1.123 - 1.124 --- Log message: Code clean up. --- Diffs of the changes: (+20 -23) ScheduleDAG.cpp | 43 --- 1 files changed, 20 insertions(+), 23 deletions(-) Index:

Re: [llvm-commits] [125160] Better support for variable size struct fields.

Something in this patch broke the llvm-gcc compilation on arm-linux: /home/laurov/llvm/llvm-gcc/build/gcc/xgcc -B/home/laurov/llvm/llvm-gcc/build/gcc/ -B/usr/local/arm-linux-gnueabi/bin/ -B/usr/local/arm-linux-gnueabi/lib/ -isystem /usr/local/arm-linux-gnueabi/include -isystem

Re: [llvm-commits] [LLVMdev] combined arm patch

The attached patch is the backport of ARM EABI. It is needed to compile llvm-gcc on arm-linux-gnueabi. Patched by Rafael. Important: This patch removes gcc/unwind.h file, so it must be applied using patch -E -p0. Lauro 2007/1/11, Lauro Ramos Venancio [EMAIL PROTECTED]: The following patch

[llvm-commits] CVS: llvm-test/MultiSource/Applications/JM/ldecod/cabac.c global.h loopFilter.c macroblock.c mbuffer.h vlc.c vlc.h

Changes in directory llvm-test/MultiSource/Applications/JM/ldecod: cabac.c updated: 1.4 - 1.5 global.h updated: 1.6 - 1.7 loopFilter.c updated: 1.4 - 1.5 macroblock.c updated: 1.4 - 1.5 mbuffer.h updated: 1.4 - 1.5 vlc.c updated: 1.4 - 1.5 vlc.h updated: 1.4 - 1.5 --- Log message: The C

[llvm-commits] CVS: llvm-test/MultiSource/Applications/JM/lencod/cabac.c global.h loopFilter.c mbuffer.h md_high.c md_highfast.c md_highloss.c md_low.c me_epzs.c me_epzs.h me_fullfast.c me_umhex.c me_

Changes in directory llvm-test/MultiSource/Applications/JM/lencod: cabac.c updated: 1.4 - 1.5 global.h updated: 1.4 - 1.5 loopFilter.c updated: 1.4 - 1.5 mbuffer.h updated: 1.4 - 1.5 md_high.c updated: 1.2 - 1.3 md_highfast.c updated: 1.2 - 1.3 md_highloss.c updated: 1.2 - 1.3 md_low.c updated:

[llvm-commits] CVS: llvm-test/MultiSource/Applications/minisat/Main.cpp

Changes in directory llvm-test/MultiSource/Applications/minisat: Main.cpp updated: 1.2 - 1.3 --- Log message: Fix compilation on arm-linux. --- Diffs of the changes: (+1 -1) Main.cpp |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index:

[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp

Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.263 - 1.264 --- Log message: The C standards do say that char may either be a signed char or unsigned char and it is up to the compilers implementation or the platform which is followed.

[llvm-commits] CVS: llvm/test/CodeGen/ARM/tst_teq.ll

Changes in directory llvm/test/CodeGen/ARM: tst_teq.ll added (r1.1) --- Log message: - Divides the comparisons in two types: comparisons that only use N and Z flags (ARMISD::CMPNZ) and comparisons that use all flags (ARMISD::CMP). - Defines the instructions: TST, TEQ (ARM) and TST (Thumb).

[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp ARMISelLowering.h ARMInstrInfo.td ARMInstrThumb.td

Changes in directory llvm/lib/Target/ARM: ARMISelLowering.cpp updated: 1.34 - 1.35 ARMISelLowering.h updated: 1.10 - 1.11 ARMInstrInfo.td updated: 1.94 - 1.95 ARMInstrThumb.td updated: 1.20 - 1.21 --- Log message: - Divides the comparisons in two types: comparisons that only use N and Z flags

Re: [llvm-commits] eh_arm.cc

The file eh_arm.cc wasn't committed. It is in the patch. I can't test and see if other files are missing because the patch doesn't reach the public svn yet. Lauro 2007/4/3, Devang Patel [EMAIL PROTECTED]: On Apr 2, 2007, at 11:34 PM, Bill Wendling wrote: I'm getting this error during

Re: [llvm-commits] eh_arm.cc

Ramos Venancio [EMAIL PROTECTED]: The file eh_arm.cc wasn't committed. It is in the patch. I can't test and see if other files are missing because the patch doesn't reach the public svn yet. Lauro 2007/4/3, Devang Patel [EMAIL PROTECTED]: On Apr 2, 2007, at 11:34 PM, Bill Wendling wrote

Re: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCCallingConv.td PPCFrameInfo.h PPCISelLowering.cpp PPCInstr64Bit.td PPCRegisterInfo.cpp PPCSubtarget.h

@@ -46,9 +46,9 @@ if (isMacho) return LP64 ? 40 : 20; -// For ELF ABI: +// For ELF 32 ABI: // Save it right before the link register -return LP64 ? -8 : -4; +return -4; } This function is unsigned and it is returning a negative value. Lauro

[llvm-commits] [patch llvm-gcc] change the function arguments lowering

This patch makes llvm-gcc use arrays to lower function arguments. For example a 30 bytes parameter is lowered to { [3 x i64], i32, i16} instead of { i64, i64, i64, i32, i16}. This reduces the size of ll file generated from lencod/rdopt.c from 17M to 1.2M. Lauro Index: gcc/llvm-abi.h

[llvm-commits] CVS: llvm/include/llvm/ADT/BitVector.h

Changes in directory llvm/include/llvm/ADT: BitVector.h updated: 1.19 - 1.20 --- Log message: Fix release build. --- Diffs of the changes: (+1 -0) BitVector.h |1 + 1 files changed, 1 insertion(+) Index: llvm/include/llvm/ADT/BitVector.h diff -u

[llvm-commits] CVS: llvm-test/SingleSource/UnitTests/tls.c Makefile

Changes in directory llvm-test/SingleSource/UnitTests: tls.c added (r1.1) Makefile updated: 1.14 - 1.15 --- Log message: Add a TLS test. --- Diffs of the changes: (+21 -0) Makefile |1 + tls.c| 20 2 files changed, 21 insertions(+) Index:

[llvm-commits] CVS: llvm/lib/Bytecode/Reader/Analyzer.cpp Reader.cpp

Changes in directory llvm/lib/Bytecode/Reader: Analyzer.cpp updated: 1.39 - 1.40 Reader.cpp updated: 1.247 - 1.248 --- Log message: Implement the thread_local keyword. --- Diffs of the changes: (+8 -5) Analyzer.cpp |4 +++- Reader.cpp |9 + 2 files changed, 8

[llvm-commits] CVS: llvm/lib/Transforms/IPO/GlobalOpt.cpp

Changes in directory llvm/lib/Transforms/IPO: GlobalOpt.cpp updated: 1.100 - 1.101 --- Log message: Implement the thread_local keyword. --- Diffs of the changes: (+19 -7) GlobalOpt.cpp | 26 +++--- 1 files changed, 19 insertions(+), 7 deletions(-) Index:

[llvm-commits] CVS: llvm/lib/VMCore/AsmWriter.cpp Globals.cpp

Changes in directory llvm/lib/VMCore: AsmWriter.cpp updated: 1.268 - 1.269 Globals.cpp updated: 1.18 - 1.19 --- Log message: Implement the thread_local keyword. --- Diffs of the changes: (+8 -7) AsmWriter.cpp |3 ++- Globals.cpp | 12 ++-- 2 files changed, 8 insertions(+),

[llvm-commits] CVS: llvm/lib/Linker/LinkModules.cpp

Changes in directory llvm/lib/Linker: LinkModules.cpp updated: 1.138 - 1.139 --- Log message: Implement the thread_local keyword. --- Diffs of the changes: (+4 -3) LinkModules.cpp |7 --- 1 files changed, 4 insertions(+), 3 deletions(-) Index: llvm/lib/Linker/LinkModules.cpp

[llvm-commits] CVS: llvm/include/llvm/Bytecode/BytecodeHandler.h

Changes in directory llvm/include/llvm/Bytecode: BytecodeHandler.h updated: 1.17 - 1.18 --- Log message: Implement the thread_local keyword. --- Diffs of the changes: (+2 -1) BytecodeHandler.h |3 ++- 1 files changed, 2 insertions(+), 1 deletion(-) Index:

[llvm-commits] CVS: llvm/include/llvm/GlobalVariable.h

Changes in directory llvm/include/llvm: GlobalVariable.h updated: 1.39 - 1.40 --- Log message: Implement the thread_local keyword. --- Diffs of the changes: (+7 -2) GlobalVariable.h |9 +++-- 1 files changed, 7 insertions(+), 2 deletions(-) Index:

[llvm-commits] CVS: llvm/lib/Transforms/Utils/CloneModule.cpp

Changes in directory llvm/lib/Transforms/Utils: CloneModule.cpp updated: 1.23 - 1.24 --- Log message: Implement the thread_local keyword. --- Diffs of the changes: (+2 -0) CloneModule.cpp |2 ++ 1 files changed, 2 insertions(+) Index: llvm/lib/Transforms/Utils/CloneModule.cpp diff

[llvm-commits] CVS: llvm/docs/BytecodeFormat.html

Changes in directory llvm/docs: BytecodeFormat.html updated: 1.67 - 1.68 --- Log message: update documentation --- Diffs of the changes: (+6 -2) BytecodeFormat.html |8 ++-- 1 files changed, 6 insertions(+), 2 deletions(-) Index: llvm/docs/BytecodeFormat.html diff -u

[llvm-commits] CVS: llvm/docs/LangRef.html

Changes in directory llvm/docs: LangRef.html updated: 1.233 - 1.234 --- Log message: update documentation --- Diffs of the changes: (+5 -3) LangRef.html |8 +--- 1 files changed, 5 insertions(+), 3 deletions(-) Index: llvm/docs/LangRef.html diff -u llvm/docs/LangRef.html:1.233

Re: [llvm-commits] CVS: llvm/test/lib/llvm.exp

I will investigate tomorrow, but I think the CodeGen/ARM/long.ll test is failing because its header has more than 1024 bytes. Lauro 2007/4/15, Chris Lattner [EMAIL PROTECTED]: On Apr 15, 2007, at 11:37 AM, Reid Spencer wrote: If this is such a big deal, why not run command line 'grep

[llvm-commits] CVS: llvm-test/SingleSource/UnitTests/Makefile tls.c

Changes in directory llvm-test/SingleSource/UnitTests: Makefile updated: 1.15 - 1.16 tls.c (r1.1) removed --- Log message: Move TLS test to Threads directory. --- Diffs of the changes: (+1 -2) Makefile |3 +-- 1 files changed, 1 insertion(+), 2 deletions(-) Index:

[llvm-commits] CVS: llvm-test/SingleSource/UnitTests/Threads/Makefile tls.c

Changes in directory llvm-test/SingleSource/UnitTests/Threads: Makefile added (r1.1) tls.c added (r1.1) --- Log message: Move TLS test to Threads directory. --- Diffs of the changes: (+27 -0) Makefile |7 +++ tls.c| 20 2 files changed, 27 insertions(+)

[llvm-commits] CVS: llvm/test/CodeGen/ARM/align.ll

Changes in directory llvm/test/CodeGen/ARM: align.ll updated: 1.4 - 1.5 --- Log message: Fix align test. --- Diffs of the changes: (+2 -3) align.ll |5 ++--- 1 files changed, 2 insertions(+), 3 deletions(-) Index: llvm/test/CodeGen/ARM/align.ll diff -u

[llvm-commits] CVS: llvm/test/CodeGen/ARM/hello.ll

Changes in directory llvm/test/CodeGen/ARM: hello.ll updated: 1.6 - 1.7 --- Log message: Fix hello.ll test. --- Diffs of the changes: (+3 -3) hello.ll |6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) Index: llvm/test/CodeGen/ARM/hello.ll diff -u

[llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAG.h SelectionDAGNodes.h

Changes in directory llvm/include/llvm/CodeGen: SelectionDAG.h updated: 1.146 - 1.147 SelectionDAGNodes.h updated: 1.184 - 1.185 --- Log message: Implement general dynamic, initial exec and local exec TLS models for X86 32 bits. --- Diffs of the changes: (+16 -4) SelectionDAG.h |

[llvm-commits] CVS: llvm/include/llvm/Target/TargetAsmInfo.h

Changes in directory llvm/include/llvm/Target: TargetAsmInfo.h updated: 1.28 - 1.29 --- Log message: Implement general dynamic, initial exec and local exec TLS models for X86 32 bits. --- Diffs of the changes: (+15 -1) TargetAsmInfo.h | 16 +++- 1 files changed, 15

[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp SelectionDAG.cpp

Changes in directory llvm/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp updated: 1.486 - 1.487 SelectionDAG.cpp updated: 1.397 - 1.398 --- Log message: Implement general dynamic, initial exec and local exec TLS models for X86 32 bits. --- Diffs of the changes: (+22 -2) LegalizeDAG.cpp |2

[llvm-commits] CVS: llvm/lib/Target/TargetAsmInfo.cpp TargetSelectionDAG.td

Changes in directory llvm/lib/Target: TargetAsmInfo.cpp updated: 1.21 - 1.22 TargetSelectionDAG.td updated: 1.78 - 1.79 --- Log message: Implement general dynamic, initial exec and local exec TLS models for X86 32 bits. --- Diffs of the changes: (+6 -0) TargetAsmInfo.cpp |2 ++

[llvm-commits] CVS: llvm/utils/TableGen/DAGISelEmitter.cpp

Changes in directory llvm/utils/TableGen: DAGISelEmitter.cpp updated: 1.292 - 1.293 --- Log message: Implement general dynamic, initial exec and local exec TLS models for X86 32 bits. --- Diffs of the changes: (+5 -2) DAGISelEmitter.cpp |7 +-- 1 files changed, 5 insertions(+), 2

[llvm-commits] CVS: llvm/lib/Target/ARM/ARMRegisterInfo.cpp

Changes in directory llvm/lib/Target/ARM: ARMRegisterInfo.cpp updated: 1.86 - 1.87 --- Log message: Fix a bug in getFrameRegister. Reported by Raul Herbster. --- Diffs of the changes: (+4 -1) ARMRegisterInfo.cpp |5 - 1 files changed, 4 insertions(+), 1 deletion(-) Index:

[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

Changes in directory llvm/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp updated: 1.487 - 1.488 --- Log message: Allow the lowering of ISD::GLOBAL_OFFSET_TABLE. --- Diffs of the changes: (+1 -1) LegalizeDAG.cpp |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index:

Re: [llvm-commits] CVS: llvm/lib/Target/X86/X86ATTAsmPrinter.cpp X86AsmPrinter.cpp X86ISelLowering.cpp X86ISelLowering.h X86InstrInfo.td

Thanks Lauro, very nice! Should the TLS bug be closed now? Now I will implement PIC and TLS for arm-linux, then I will close the PR941 and open a bug report for each target that doesn't implement TLS. Lauro ___ llvm-commits mailing list

[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Changes in directory llvm/lib/CodeGen/SelectionDAG: SelectionDAG.cpp updated: 1.400 - 1.401 --- Log message: X86 TLS: Implement review feedback. --- Diffs of the changes: (+11 -1) SelectionDAG.cpp | 12 +++- 1 files changed, 11 insertions(+), 1 deletion(-) Index:

[llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAGNodes.h

Changes in directory llvm/include/llvm/CodeGen: SelectionDAGNodes.h updated: 1.187 - 1.188 --- Log message: X86 TLS: Implement review feedback. --- Diffs of the changes: (+1 -11) SelectionDAGNodes.h | 12 +--- 1 files changed, 1 insertion(+), 11 deletions(-) Index:

[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp

Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.394 - 1.395 --- Log message: X86 TLS: Implement review feedback. --- Diffs of the changes: (+3 -2) X86ISelLowering.cpp |5 +++-- 1 files changed, 3 insertions(+), 2 deletions(-) Index:

[llvm-commits] CVS: llvm/test/CodeGen/ARM/call.ll load-global.ll

Changes in directory llvm/test/CodeGen/ARM: call.ll updated: 1.7 - 1.8 load-global.ll updated: 1.2 - 1.3 --- Log message: Implement PIC for arm-linux. --- Diffs of the changes: (+5 -1) call.ll|2 ++ load-global.ll |4 +++- 2 files changed, 5 insertions(+), 1 deletion(-)

[llvm-commits] CVS: llvm/lib/Target/ARM/ARMAsmPrinter.cpp ARMConstantPoolValue.cpp ARMConstantPoolValue.h ARMISelLowering.cpp ARMISelLowering.h

Changes in directory llvm/lib/Target/ARM: ARMAsmPrinter.cpp updated: 1.64 - 1.65 ARMConstantPoolValue.cpp updated: 1.2 - 1.3 ARMConstantPoolValue.h updated: 1.2 - 1.3 ARMISelLowering.cpp updated: 1.44 - 1.45 ARMISelLowering.h updated: 1.13 - 1.14 --- Log message: Implement PIC for arm-linux.

[llvm-commits] CVS: llvm/lib/Target/X86/X86ATTAsmPrinter.cpp X86ISelLowering.cpp X86InstrInfo.td

Changes in directory llvm/lib/Target/X86: X86ATTAsmPrinter.cpp updated: 1.101 - 1.102 X86ISelLowering.cpp updated: 1.395 - 1.396 X86InstrInfo.td updated: 1.303 - 1.304 --- Log message: X86 TLS: fix and optimize the implementation of initial exec model. --- Diffs of the changes: (+11 -2)

[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.td

Changes in directory llvm/lib/Target/X86: X86InstrInfo.td updated: 1.304 - 1.305 --- Log message: X86 TLS: optimize the implementation of local exec model. --- Diffs of the changes: (+10 -3) X86InstrInfo.td | 13 ++--- 1 files changed, 10 insertions(+), 3 deletions(-) Index:

[llvm-commits] CVS: llvm/test/CodeGen/X86/tls1.ll tls2.ll

Changes in directory llvm/test/CodeGen/X86: tls1.ll added (r1.1) tls2.ll added (r1.1) --- Log message: Add TLS tests. --- Diffs of the changes: (+38 -0) tls1.ll | 19 +++ tls2.ll | 19 +++ 2 files changed, 38 insertions(+) Index:

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