[llvm-commits] CVS: llvm/lib/Target/PowerPC/README.txt

Changes in directory llvm/lib/Target/PowerPC: README.txt updated: 1.35 - 1.36 --- Log message: New case to handle someday --- Diffs of the changes: (+17 -0) README.txt | 17 + 1 files changed, 17 insertions(+) Index: llvm/lib/Target/PowerPC/README.txt diff -u

[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Changes in directory llvm/lib/CodeGen/SelectionDAG: DAGCombiner.cpp updated: 1.59 - 1.60 --- Log message: Fix a crash that Andrew noticed, and add a pair of braces to unfconfuse XCode's indenting. --- Diffs of the changes: (+5 -5) DAGCombiner.cpp | 10 +- 1 files changed, 5

[llvm-commits] CVS: llvm/lib/Transforms/IPO/GlobalOpt.cpp

Changes in directory llvm/lib/Transforms/IPO: GlobalOpt.cpp updated: 1.59 - 1.60 --- Log message: Add support alignment of allocation instructions. Add support for specifying alignment and size of setjmp jmpbufs. No targets currently do anything with this information, nor is it presrved in

[llvm-commits] CVS: llvm/include/llvm/Instructions.h

Changes in directory llvm/include/llvm: Instructions.h updated: 1.27 - 1.28 --- Log message: Add support alignment of allocation instructions. Add support for specifying alignment and size of setjmp jmpbufs. No targets currently do anything with this information, nor is it presrved in the

[llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineFrameInfo.h

Changes in directory llvm/include/llvm/CodeGen: MachineFrameInfo.h updated: 1.12 - 1.13 --- Log message: Add the necessary support to the ISel to allow targets to codegen the new alignment information appropriately. Includes code for PowerPC to support fixed-size allocas with alignment larger

[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp

Changes in directory llvm/lib/Target/PowerPC: PPCRegisterInfo.cpp updated: 1.36 - 1.37 --- Log message: Add the necessary support to the ISel to allow targets to codegen the new alignment information appropriately. Includes code for PowerPC to support fixed-size allocas with alignment larger

[llvm-commits] CVS: llvm/lib/CodeGen/PrologEpilogInserter.cpp

Changes in directory llvm/lib/CodeGen: PrologEpilogInserter.cpp updated: 1.49 - 1.50 --- Log message: Add the necessary support to the ISel to allow targets to codegen the new alignment information appropriately. Includes code for PowerPC to support fixed-size allocas with alignment larger

[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

Changes in directory llvm/lib/CodeGen/SelectionDAG: SelectionDAGISel.cpp updated: 1.92 - 1.93 --- Log message: Add the necessary support to the ISel to allow targets to codegen the new alignment information appropriately. Includes code for PowerPC to support fixed-size allocas with alignment

[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp PPCCodeEmitter.cpp PPCISelDAGToDAG.cpp PPCISelPattern.cpp PPCInstrInfo.td

Changes in directory llvm/lib/Target/PowerPC: PPCAsmPrinter.cpp updated: 1.109 - 1.110 PPCCodeEmitter.cpp updated: 1.40 - 1.41 PPCISelDAGToDAG.cpp updated: 1.125 - 1.126 PPCISelPattern.cpp updated: 1.191 - 1.192 PPCInstrInfo.td updated: 1.138 - 1.139 --- Log message: Patch to clean up function

[llvm-commits] CVS: llvm/include/llvm/Target/TargetLowering.h

Changes in directory llvm/include/llvm/Target: TargetLowering.h updated: 1.27 - 1.28 --- Log message: Teach the type lowering code about turning packed types into vector types. Next step: generating vector dag nodes, and legalizing them into scalar code. --- Diffs of the changes: (+1 -0)

[llvm-commits] CVS: llvm/lib/Target/Target.td

Changes in directory llvm/lib/Target: Target.td updated: 1.56 - 1.57 --- Log message: Also add the new vector value type here, for completeness. --- Diffs of the changes: (+1 -0) Target.td |1 + 1 files changed, 1 insertion(+) Index: llvm/lib/Target/Target.td diff -u

[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

Changes in directory llvm/lib/CodeGen/SelectionDAG: SelectionDAGISel.cpp updated: 1.100 - 1.101 --- Log message: Split out the shift code from visitBinary. --- Diffs of the changes: (+14 -7) SelectionDAGISel.cpp | 21 ++--- 1 files changed, 14 insertions(+), 7

[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp SelectionDAG.cpp SelectionDAGISel.cpp

Changes in directory llvm/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp updated: 1.209 - 1.210 SelectionDAG.cpp updated: 1.212 - 1.213 SelectionDAGISel.cpp updated: 1.101 - 1.102 --- Log message: Teach LLVM how to scalarize packed types. Currently, this only works on packed types with an element

[llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp

Changes in directory llvm/lib/Target: TargetLowering.cpp updated: 1.13 - 1.14 --- Log message: Rather than attempting to legalize 1 x float, make sure the SD ISel never generates it. Make MVT::Vector expand-only, and remove the code in Legalize that attempts to legalize it. The plan for

[llvm-commits] CVS: llvm/include/llvm/CodeGen/ValueTypes.h

Changes in directory llvm/include/llvm/CodeGen: ValueTypes.h updated: 1.13 - 1.14 --- Log message: Add the majority of the vector machien value types we expect to support, and make a few changes to the legalization machinery to support more than 16 types. --- Diffs of the changes: (+21 -3)

[llvm-commits] CVS: llvm/lib/Target/Target.td TargetLowering.cpp

Changes in directory llvm/lib/Target: Target.td updated: 1.61 - 1.62 TargetLowering.cpp updated: 1.14 - 1.15 --- Log message: Add the majority of the vector machien value types we expect to support, and make a few changes to the legalization machinery to support more than 16 types. --- Diffs

[llvm-commits] CVS: llvm/include/llvm/Target/TargetLowering.h

Changes in directory llvm/include/llvm/Target: TargetLowering.h updated: 1.28 - 1.29 --- Log message: Add the majority of the vector machien value types we expect to support, and make a few changes to the legalization machinery to support more than 16 types. --- Diffs of the changes: (+2

[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

Changes in directory llvm/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp updated: 1.215 - 1.216 --- Log message: Add the majority of the vector machien value types we expect to support, and make a few changes to the legalization machinery to support more than 16 types. --- Diffs of the changes:

[llvm-commits] CVS: llvm/lib/CodeGen/ValueTypes.cpp

Changes in directory llvm/lib/CodeGen: ValueTypes.cpp updated: 1.5 - 1.6 --- Log message: Add the majority of the vector machien value types we expect to support, and make a few changes to the legalization machinery to support more than 16 types. --- Diffs of the changes: (+6 -0)

[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrFormats.td PPCInstrInfo.td

Changes in directory llvm/lib/Target/PowerPC: PPCInstrFormats.td updated: 1.57 - 1.58 PPCInstrInfo.td updated: 1.145 - 1.146 --- Log message: Add the remainder of the AltiVec 4 x float instructions. Further enhancements will be necessary to teach the code generator that since there is no

[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp

Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.46 - 1.47 --- Log message: Hook up one type, v4f32, to the VR RegisterClass for now. --- Diffs of the changes: (+6 -0) PPCISelLowering.cpp |6 ++ 1 files changed, 6 insertions(+) Index:

[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrFormats.td PPCInstrInfo.td

Changes in directory llvm/lib/Target/PowerPC: PPCInstrFormats.td updated: 1.58 - 1.59 PPCInstrInfo.td updated: 1.146 - 1.147 --- Log message: Represent the encoding of the SPR instructions as they actually are, so that we can use the correct SPR numbers in the InstrInfo.td file. This is

[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

Changes in directory llvm/lib/Target/PowerPC: PPCISelDAGToDAG.cpp updated: 1.130 - 1.131 --- Log message: First chunk of actually generating vector code for packed types. These changes allow us to generate the following code: _foo: li r2, 0 lvx v0, r2, r3 vaddfp v0,

[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

Changes in directory llvm/lib/CodeGen/SelectionDAG: SelectionDAGISel.cpp updated: 1.107 - 1.108 --- Log message: First chunk of actually generating vector code for packed types. These changes allow us to generate the following code: _foo: li r2, 0 lvx v0, r2, r3

[llvm-commits] CVS: llvm/include/llvm/CodeGen/ValueTypes.h

Changes in directory llvm/include/llvm/CodeGen: ValueTypes.h updated: 1.14 - 1.15 --- Log message: First chunk of actually generating vector code for packed types. These changes allow us to generate the following code: _foo: li r2, 0 lvx v0, r2, r3 vaddfp v0, v0, v0

[llvm-commits] CVS: llvm/utils/TableGen/Record.cpp

Changes in directory llvm/utils/TableGen: Record.cpp updated: 1.47 - 1.48 --- Log message: Fix some copy and paste typos. --- Diffs of the changes: (+2 -2) Record.cpp |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/utils/TableGen/Record.cpp diff -u

[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

Changes in directory llvm/lib/Target/PowerPC: PPCAsmPrinter.cpp updated: 1.121 - 1.122 --- Log message: No longer track value types for asm printer operands, and remove them as an argument to every operand printing function. Requires some slight tweaks to x86, the only user. --- Diffs of

[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp

Changes in directory llvm/lib/Target/Alpha: AlphaAsmPrinter.cpp updated: 1.26 - 1.27 --- Log message: No longer track value types for asm printer operands, and remove them as an argument to every operand printing function. Requires some slight tweaks to x86, the only user. --- Diffs of the

[llvm-commits] CVS: llvm/utils/TableGen/AsmWriterEmitter.cpp

Changes in directory llvm/utils/TableGen: AsmWriterEmitter.cpp updated: 1.22 - 1.23 --- Log message: No longer track value types for asm printer operands, and remove them as an argument to every operand printing function. Requires some slight tweaks to x86, the only user. --- Diffs of the

[llvm-commits] CVS: llvm/lib/Target/X86/X86ATTAsmPrinter.cpp X86ATTAsmPrinter.h X86InstrInfo.td X86IntelAsmPrinter.cpp X86IntelAsmPrinter.h

Changes in directory llvm/lib/Target/X86: X86ATTAsmPrinter.cpp updated: 1.16 - 1.17 X86ATTAsmPrinter.h updated: 1.2 - 1.3 X86InstrInfo.td updated: 1.143 - 1.144 X86IntelAsmPrinter.cpp updated: 1.12 - 1.13 X86IntelAsmPrinter.h updated: 1.2 - 1.3 --- Log message: No longer track value types for

[llvm-commits] CVS: llvm/utils/TableGen/CodeGenInstruction.h

Changes in directory llvm/utils/TableGen: CodeGenInstruction.h updated: 1.13 - 1.14 --- Log message: fit into 80 columns --- Diffs of the changes: (+2 -2) CodeGenInstruction.h |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/utils/TableGen/CodeGenInstruction.h

[llvm-commits] CVS: llvm/utils/TableGen/CodeGenTarget.h DAGISelEmitter.cpp DAGISelEmitter.h

Changes in directory llvm/utils/TableGen: CodeGenTarget.h updated: 1.19 - 1.20 DAGISelEmitter.cpp updated: 1.78 - 1.79 DAGISelEmitter.h updated: 1.36 - 1.37 --- Log message: Stop checking the ValueType of the CodeGenInstruction. Instead, use the ValueType from the RegisterClass or Operands.

[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.td

Changes in directory llvm/lib/Target/PowerPC: PPCRegisterInfo.td updated: 1.24 - 1.25 --- Log message: Cosmetic change, better reflects actual values --- Diffs of the changes: (+5 -6) PPCRegisterInfo.td | 11 +-- 1 files changed, 5 insertions(+), 6 deletions(-) Index:

[llvm-commits] CVS: llvm/lib/Target/Target.td

Changes in directory llvm/lib/Target: Target.td updated: 1.62 - 1.63 --- Log message: Support multiple ValueTypes per RegisterClass, needed for upcoming vector work. This change has no effect on generated code. --- Diffs of the changes: (+6 -3) Target.td |9 ++--- 1 files

[llvm-commits] CVS: llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td

Changes in directory llvm/lib/Target/SparcV8: SparcV8RegisterInfo.td updated: 1.22 - 1.23 --- Log message: Support multiple ValueTypes per RegisterClass, needed for upcoming vector work. This change has no effect on generated code. --- Diffs of the changes: (+3 -3) SparcV8RegisterInfo.td

[llvm-commits] CVS: llvm/lib/Target/IA64/IA64RegisterInfo.td

Changes in directory llvm/lib/Target/IA64: IA64RegisterInfo.td updated: 1.10 - 1.11 --- Log message: Support multiple ValueTypes per RegisterClass, needed for upcoming vector work. This change has no effect on generated code. --- Diffs of the changes: (+3 -3) IA64RegisterInfo.td |6

[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.td

Changes in directory llvm/lib/Target/X86: X86RegisterInfo.td updated: 1.22 - 1.23 --- Log message: Support multiple ValueTypes per RegisterClass, needed for upcoming vector work. This change has no effect on generated code. --- Diffs of the changes: (+8 -7) X86RegisterInfo.td | 15

[llvm-commits] CVS: llvm/lib/Target/SparcV9/SparcV9RegisterInfo.cpp SparcV9RegisterInfo.td

Changes in directory llvm/lib/Target/SparcV9: SparcV9RegisterInfo.cpp updated: 1.9 - 1.10 SparcV9RegisterInfo.td updated: 1.5 - 1.6 --- Log message: Support multiple ValueTypes per RegisterClass, needed for upcoming vector work. This change has no effect on generated code. --- Diffs of the

[llvm-commits] CVS: llvm/utils/TableGen/CodeGenRegisters.h CodeGenTarget.cpp DAGISelEmitter.cpp RegisterInfoEmitter.cpp

Changes in directory llvm/utils/TableGen: CodeGenRegisters.h updated: 1.8 - 1.9 CodeGenTarget.cpp updated: 1.45 - 1.46 DAGISelEmitter.cpp updated: 1.80 - 1.81 RegisterInfoEmitter.cpp updated: 1.37 - 1.38 --- Log message: Support multiple ValueTypes per RegisterClass, needed for upcoming vector

[llvm-commits] CVS: llvm/lib/Target/Skeleton/SkeletonRegisterInfo.td

Changes in directory llvm/lib/Target/Skeleton: SkeletonRegisterInfo.td updated: 1.5 - 1.6 --- Log message: Support multiple ValueTypes per RegisterClass, needed for upcoming vector work. This change has no effect on generated code. --- Diffs of the changes: (+2 -2)

[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaRegisterInfo.td

Changes in directory llvm/lib/Target/Alpha: AlphaRegisterInfo.td updated: 1.14 - 1.15 --- Log message: Support multiple ValueTypes per RegisterClass, needed for upcoming vector work. This change has no effect on generated code. --- Diffs of the changes: (+3 -3) AlphaRegisterInfo.td |

[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp SelectionDAG.cpp SelectionDAGISel.cpp

Changes in directory llvm/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp updated: 1.222 - 1.223 SelectionDAG.cpp updated: 1.222 - 1.223 SelectionDAGISel.cpp updated: 1.110 - 1.111 --- Log message: Teach the SelectionDAG ISel how to turn ConstantPacked values into constant nodes with vector types.

[llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAGNodes.h

Changes in directory llvm/include/llvm/CodeGen: SelectionDAGNodes.h updated: 1.80 - 1.81 --- Log message: Teach the SelectionDAG ISel how to turn ConstantPacked values into constant nodes with vector types. Also teach the asm printer how to print ConstantPacked constant pool entries. This

[llvm-commits] CVS: llvm/lib/CodeGen/AsmPrinter.cpp

Changes in directory llvm/lib/CodeGen: AsmPrinter.cpp updated: 1.29 - 1.30 --- Log message: Teach the SelectionDAG ISel how to turn ConstantPacked values into constant nodes with vector types. Also teach the asm printer how to print ConstantPacked constant pool entries. This allows us to

[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrFormats.td PPCInstrInfo.td

Changes in directory llvm/lib/Target/PowerPC: PPCInstrFormats.td updated: 1.60 - 1.61 PPCInstrInfo.td updated: 1.152 - 1.153 --- Log message: Add support patterns to many load and store instructions which will hopefully use patterns in the near future. --- Diffs of the changes: (+133 -76)

[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp PPCISelLowering.cpp PPCInstrInfo.td

Changes in directory llvm/lib/Target/PowerPC: PPCISelDAGToDAG.cpp updated: 1.139 - 1.140 PPCISelLowering.cpp updated: 1.49 - 1.50 PPCInstrInfo.td updated: 1.153 - 1.154 --- Log message: Add support for TargetConstantPool nodes to the dag isel emitter, and use them in the PPC backend, to

[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

Changes in directory llvm/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp updated: 1.225 - 1.226 --- Log message: Add support for TargetConstantPool nodes to the dag isel emitter, and use them in the PPC backend, to simplify some logic out of Select and SelectAddr. --- Diffs of the changes: (+3

[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td

Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.16 - 1.17 --- Log message: Add support for TargetConstantPool nodes to the dag isel emitter, and use them in the PPC backend, to simplify some logic out of Select and SelectAddr. --- Diffs of the changes: (+2 -0)

[llvm-commits] CVS: llvm/utils/TableGen/DAGISelEmitter.cpp

Changes in directory llvm/utils/TableGen: DAGISelEmitter.cpp updated: 1.93 - 1.94 --- Log message: Add support for TargetConstantPool nodes to the dag isel emitter, and use them in the PPC backend, to simplify some logic out of Select and SelectAddr. --- Diffs of the changes: (+2 -0)

[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td

Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.20 - 1.21 --- Log message: Prepare support for AltiVec multiply, divide, and sqrt. --- Diffs of the changes: (+3 -0) TargetSelectionDAG.td |3 +++ 1 files changed, 3 insertions(+) Index:

[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp PPCInstrInfo.td

Changes in directory llvm/lib/Target/PowerPC: PPCISelDAGToDAG.cpp updated: 1.140 - 1.141 PPCInstrInfo.td updated: 1.158 - 1.159 --- Log message: Use the new predicate support that Evan Cheng added to remove some code from the DAGToDAG cpp file. This adds pattern support for vector and scalar

[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

Changes in directory llvm/lib/Target/PowerPC: PPCISelDAGToDAG.cpp updated: 1.141 - 1.142 --- Log message: Remove a now unused statistic. --- Diffs of the changes: (+0 -1) PPCISelDAGToDAG.cpp |1 - 1 files changed, 1 deletion(-) Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp diff

[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp PPCISelDAGToDAG.cpp PPCISelLowering.cpp PPCInstrInfo.td

Changes in directory llvm/lib/Target/PowerPC: PPCAsmPrinter.cpp updated: 1.129 - 1.130 PPCISelDAGToDAG.cpp updated: 1.143 - 1.144 PPCISelLowering.cpp updated: 1.50 - 1.51 PPCInstrInfo.td updated: 1.161 - 1.162 --- Log message: Convert load/store over to being pattern matched --- Diffs of the

[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp PPCISelDAGToDAG.cpp

Changes in directory llvm/lib/Target/PowerPC: PPCAsmPrinter.cpp updated: 1.130 - 1.131 PPCISelDAGToDAG.cpp updated: 1.144 - 1.145 --- Log message: Fix a couple of the FIXMEs, thanks to suggestion from Chris. This allows us to load and store vectors directly at a pointer (offset of zero) by

[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp PPCISelLowering.cpp PPCISelLowering.h PPCInstrFormats.td PPCInstrInfo.td PPCRegisterInfo.td

Changes in directory llvm/lib/Target/PowerPC: PPCISelDAGToDAG.cpp updated: 1.145 - 1.146 PPCISelLowering.cpp updated: 1.51 - 1.52 PPCISelLowering.h updated: 1.12 - 1.13 PPCInstrFormats.td updated: 1.62 - 1.63 PPCInstrInfo.td updated: 1.162 - 1.163 PPCRegisterInfo.td updated: 1.27 - 1.28 --- Log

[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp PPCISelDAGToDAG.cpp PPCISelLowering.cpp README.txt

Changes in directory llvm/lib/Target/PowerPC: PPCAsmPrinter.cpp updated: 1.132 - 1.133 PPCISelDAGToDAG.cpp updated: 1.146 - 1.147 PPCISelLowering.cpp updated: 1.54 - 1.55 README.txt updated: 1.41 - 1.42 --- Log message: Fix one of the things in the todo file, and get a bit closer to folding

[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp

Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.55 - 1.56 --- Log message: Remove a fixme --- Diffs of the changes: (+0 -2) PPCISelLowering.cpp |2 -- 1 files changed, 2 deletions(-) Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u

[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrInfo.td

Changes in directory llvm/lib/Target/PowerPC: PPCInstrInfo.td updated: 1.166 - 1.167 --- Log message: Add support for generating v4i32 altivec code --- Diffs of the changes: (+10 -2) PPCInstrInfo.td | 12 ++-- 1 files changed, 10 insertions(+), 2 deletions(-) Index:

[llvm-commits] CVS: llvm/utils/TableGen/CodeGenRegisters.h DAGISelEmitter.cpp DAGISelEmitter.h

Changes in directory llvm/utils/TableGen: CodeGenRegisters.h updated: 1.10 - 1.11 DAGISelEmitter.cpp updated: 1.117 - 1.118 DAGISelEmitter.h updated: 1.48 - 1.49 --- Log message: Add support for generating v4i32 altivec code --- Diffs of the changes: (+180 -97) CodeGenRegisters.h |2

[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrInfo.td

Changes in directory llvm/lib/Target/PowerPC: PPCInstrInfo.td updated: 1.171 - 1.172 --- Log message: Remove a comment that no longer applies. --- Diffs of the changes: (+0 -1) PPCInstrInfo.td |1 - 1 files changed, 1 deletion(-) Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td diff

[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td

Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.42 - 1.43 --- Log message: Add bswap, rotl, and rotr nodes Add dag combiner code to recognize rotl, rotr Add ppc code to match rotl Targets should add rotl/rotr patterns if they have them --- Diffs of the changes: (+2

[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp PPCInstrInfo.td

Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.62 - 1.63 PPCInstrInfo.td updated: 1.172 - 1.173 --- Log message: Add bswap, rotl, and rotr nodes Add dag combiner code to recognize rotl, rotr Add ppc code to match rotl Targets should add rotl/rotr patterns if they

[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp LegalizeDAG.cpp SelectionDAG.cpp

Changes in directory llvm/lib/CodeGen/SelectionDAG: DAGCombiner.cpp updated: 1.79 - 1.80 LegalizeDAG.cpp updated: 1.258 - 1.259 SelectionDAG.cpp updated: 1.235 - 1.236 --- Log message: Add bswap, rotl, and rotr nodes Add dag combiner code to recognize rotl, rotr Add ppc code to match rotl

[llvm-commits] CVS: llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp

Changes in directory llvm/lib/Target/SparcV8: SparcV8ISelDAGToDAG.cpp updated: 1.44 - 1.45 --- Log message: Add bswap, rotl, and rotr nodes Add dag combiner code to recognize rotl, rotr Add ppc code to match rotl Targets should add rotl/rotr patterns if they have them --- Diffs of the

[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelLowering.cpp

Changes in directory llvm/lib/Target/Alpha: AlphaISelLowering.cpp updated: 1.18 - 1.19 --- Log message: Add bswap, rotl, and rotr nodes Add dag combiner code to recognize rotl, rotr Add ppc code to match rotl Targets should add rotl/rotr patterns if they have them --- Diffs of the changes:

[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp

Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.28 - 1.29 --- Log message: Add bswap, rotl, and rotr nodes Add dag combiner code to recognize rotl, rotr Add ppc code to match rotl Targets should add rotl/rotr patterns if they have them --- Diffs of the changes: (+7

[llvm-commits] CVS: llvm/test/Regression/CodeGen/PowerPC/rotl.ll

Changes in directory llvm/test/Regression/CodeGen/PowerPC: rotl.ll added (r1.1) --- Log message: Add testcase for rotate by register and rotate by immediate --- Diffs of the changes: (+51 -0) rotl.ll | 51 +++ 1 files changed, 51

[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelPattern.cpp

Changes in directory llvm/lib/Target/IA64: IA64ISelPattern.cpp updated: 1.73 - 1.74 --- Log message: Missed a spot. --- Diffs of the changes: (+2 -0) IA64ISelPattern.cpp |2 ++ 1 files changed, 2 insertions(+) Index: llvm/lib/Target/IA64/IA64ISelPattern.cpp diff -u

[llvm-commits] CVS: llvm/docs/LangRef.html

Changes in directory llvm/docs: LangRef.html updated: 1.123 - 1.124 --- Log message: Add documentation for the upcoming bswap intrinsics! --- Diffs of the changes: (+91 -1) LangRef.html | 92 ++- 1 files changed, 91 insertions(+),

[llvm-commits] CVS: llvm/docs/LangRef.html

Changes in directory llvm/docs: LangRef.html updated: 1.125 - 1.126 --- Log message: Make the bswap documentation more to sabre's liking! --- Diffs of the changes: (+40 -94) LangRef.html | 134 +-- 1 files changed, 40 insertions(+),

[llvm-commits] CVS: llvm/lib/VMCore/Function.cpp Verifier.cpp

Changes in directory llvm/lib/VMCore: Function.cpp updated: 1.97 - 1.98 Verifier.cpp updated: 1.139 - 1.140 --- Log message: Add bswap intrinsics as documented in the Language Reference --- Diffs of the changes: (+35 -0) Function.cpp |5 + Verifier.cpp | 30

[llvm-commits] CVS: llvm/lib/Transforms/Utils/Local.cpp

Changes in directory llvm/lib/Transforms/Utils: Local.cpp updated: 1.48 - 1.49 --- Log message: Add bswap intrinsics as documented in the Language Reference --- Diffs of the changes: (+3 -0) Local.cpp |3 +++ 1 files changed, 3 insertions(+) Index:

[llvm-commits] CVS: llvm/test/Regression/Transforms/ConstProp/bswap.ll

Changes in directory llvm/test/Regression/Transforms/ConstProp: bswap.ll added (r1.1) --- Log message: Add bswap intrinsics as documented in the Language Reference --- Diffs of the changes: (+22 -0) bswap.ll | 22 ++ 1 files changed, 22 insertions(+) Index:

[llvm-commits] CVS: llvm/lib/Analysis/BasicAliasAnalysis.cpp ConstantFolding.cpp

Changes in directory llvm/lib/Analysis: BasicAliasAnalysis.cpp updated: 1.75 - 1.76 ConstantFolding.cpp updated: 1.1 - 1.2 --- Log message: Add bswap intrinsics as documented in the Language Reference --- Diffs of the changes: (+17 -1) BasicAliasAnalysis.cpp |3 ++-

[llvm-commits] CVS: llvm/lib/Target/PowerPC/README.txt

Changes in directory llvm/lib/Target/PowerPC: README.txt updated: 1.42 - 1.43 --- Log message: Remove some redundant stuff out of the readme. --- Diffs of the changes: (+0 -18) README.txt | 18 -- 1 files changed, 18 deletions(-) Index:

[llvm-commits] CVS: llvm/include/llvm/Support/MathExtras.h

Changes in directory llvm/include/llvm/Support: MathExtras.h updated: 1.27 - 1.28 --- Log message: Add bswap intrinsics as documented in the Language Reference --- Diffs of the changes: (+26 -0) MathExtras.h | 26 ++ 1 files changed, 26 insertions(+) Index:

[llvm-commits] CVS: llvm/docs/ExtendingLLVM.html

Changes in directory llvm/docs: ExtendingLLVM.html updated: 1.19 - 1.20 --- Log message: Fix the instructions for adding an intrinsic. --- Diffs of the changes: (+8 -4) ExtendingLLVM.html | 12 1 files changed, 8 insertions(+), 4 deletions(-) Index:

[llvm-commits] CVS: llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp

Changes in directory llvm/lib/Target/SparcV8: SparcV8ISelDAGToDAG.cpp updated: 1.49 - 1.50 --- Log message: bswap implementation --- Diffs of the changes: (+1 -0) SparcV8ISelDAGToDAG.cpp |1 + 1 files changed, 1 insertion(+) Index: llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp

[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td

Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.43 - 1.44 --- Log message: bswap implementation --- Diffs of the changes: (+1 -0) TargetSelectionDAG.td |1 + 1 files changed, 1 insertion(+) Index: llvm/lib/Target/TargetSelectionDAG.td diff -u

[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86InstrInfo.td

Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.40 - 1.41 X86InstrInfo.td updated: 1.204 - 1.205 --- Log message: bswap implementation --- Diffs of the changes: (+5 -1) X86ISelLowering.cpp |2 ++ X86InstrInfo.td |4 +++- 2 files changed, 5

[llvm-commits] CVS: llvm/test/Regression/CodeGen/X86/bswap.ll

Changes in directory llvm/test/Regression/CodeGen/X86: bswap.ll added (r1.1) --- Log message: bswap implementation --- Diffs of the changes: (+23 -0) bswap.ll | 23 +++ 1 files changed, 23 insertions(+) Index: llvm/test/Regression/CodeGen/X86/bswap.ll diff -c

[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp

Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.65 - 1.66 --- Log message: bswap implementation --- Diffs of the changes: (+2 -1) PPCISelLowering.cpp |3 ++- 1 files changed, 2 insertions(+), 1 deletion(-) Index:

[llvm-commits] CVS: llvm/lib/CodeGen/IntrinsicLowering.cpp

Changes in directory llvm/lib/CodeGen: IntrinsicLowering.cpp updated: 1.37 - 1.38 --- Log message: Add BSWAP stuff to intrinsic lowering for CBE friends. --- Diffs of the changes: (+106 -2) IntrinsicLowering.cpp | 108 +- 1 files changed,

[llvm-commits] CVS: llvm/docs/ExtendingLLVM.html

Changes in directory llvm/docs: ExtendingLLVM.html updated: 1.20 - 1.21 --- Log message: Fix up 'adding an intrinsic' section a bit, first draft of 'adding a new sdnode' section. --- Diffs of the changes: (+116 -41) ExtendingLLVM.html | 157

[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Changes in directory llvm/lib/CodeGen/SelectionDAG: SelectionDAG.cpp updated: 1.239 - 1.240 --- Log message: Constant fold ctpop/ctlz/cttz, and a couple other small cleanups --- Diffs of the changes: (+58 -2) SelectionDAG.cpp | 60 +--

[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

Changes in directory llvm/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp updated: 1.266 - 1.267 --- Log message: Expand case for 64b Legalize, even though no one should end up using this (itanium supports bswap natively, alpha should custom lower it using the VAX floating point swapload, ha ha).

[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Changes in directory llvm/lib/CodeGen/SelectionDAG: DAGCombiner.cpp updated: 1.84 - 1.85 --- Log message: Get rid of code in the DAGCombiner that is duplicated in SelectionDAG.cpp Now all constant folding in the code generator is in one place. --- Diffs of the changes: (+80 -74)

[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp PPCISelLowering.h

Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.69 - 1.70 PPCISelLowering.h updated: 1.14 - 1.15 --- Log message: First part of bug 680: http://llvm.cs.uiuc.edu/PR680 : Remove TLI.LowerVA* and replace it with SDNodes that are lowered the same way as everything

[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelLowering.cpp AlphaISelLowering.h

Changes in directory llvm/lib/Target/Alpha: AlphaISelLowering.cpp updated: 1.28 - 1.29 AlphaISelLowering.h updated: 1.11 - 1.12 --- Log message: First part of bug 680: http://llvm.cs.uiuc.edu/PR680 : Remove TLI.LowerVA* and replace it with SDNodes that are lowered the same way as everything

[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86ISelLowering.h

Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.56 - 1.57 X86ISelLowering.h updated: 1.15 - 1.16 --- Log message: First part of bug 680: http://llvm.cs.uiuc.edu/PR680 : Remove TLI.LowerVA* and replace it with SDNodes that are lowered the same way as everything else.

[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp SelectionDAG.cpp SelectionDAGISel.cpp

Changes in directory llvm/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp updated: 1.276 - 1.277 SelectionDAG.cpp updated: 1.243 - 1.244 SelectionDAGISel.cpp updated: 1.136 - 1.137 --- Log message: First part of bug 680: http://llvm.cs.uiuc.edu/PR680 : Remove TLI.LowerVA* and replace it with SDNodes

[llvm-commits] CVS: llvm/include/llvm/Target/TargetLowering.h

Changes in directory llvm/include/llvm/Target: TargetLowering.h updated: 1.35 - 1.36 --- Log message: First part of bug 680: http://llvm.cs.uiuc.edu/PR680 : Remove TLI.LowerVA* and replace it with SDNodes that are lowered the same way as everything else. --- Diffs of the changes: (+0 -25)

[llvm-commits] CVS: llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp

Changes in directory llvm/lib/Target/SparcV8: SparcV8ISelDAGToDAG.cpp updated: 1.57 - 1.58 --- Log message: First part of bug 680: http://llvm.cs.uiuc.edu/PR680 : Remove TLI.LowerVA* and replace it with SDNodes that are lowered the same way as everything else. --- Diffs of the changes: (+18

[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelLowering.cpp IA64ISelLowering.h

Changes in directory llvm/lib/Target/IA64: IA64ISelLowering.cpp updated: 1.26 - 1.27 IA64ISelLowering.h updated: 1.5 - 1.6 --- Log message: First part of bug 680: http://llvm.cs.uiuc.edu/PR680 : Remove TLI.LowerVA* and replace it with SDNodes that are lowered the same way as everything else.

[llvm-commits] CVS: llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp

Changes in directory llvm/lib/Target/SparcV8: SparcV8ISelDAGToDAG.cpp updated: 1.60 - 1.61 --- Log message: Remove TLI.LowerReturnTo, and just let targets custom lower ISD::RET for the same functionality. This addresses another piece of bug 680: http://llvm.cs.uiuc.edu/PR680 . Next, on to

[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86ISelLowering.h

Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.59 - 1.60 X86ISelLowering.h updated: 1.17 - 1.18 --- Log message: Remove TLI.LowerReturnTo, and just let targets custom lower ISD::RET for the same functionality. This addresses another piece of bug 680:

[llvm-commits] CVS: llvm/include/llvm/Target/TargetLowering.h

Changes in directory llvm/include/llvm/Target: TargetLowering.h updated: 1.37 - 1.38 --- Log message: Remove TLI.LowerReturnTo, and just let targets custom lower ISD::RET for the same functionality. This addresses another piece of bug 680: http://llvm.cs.uiuc.edu/PR680 . Next, on to fixing

[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelLowering.cpp IA64ISelLowering.h

Changes in directory llvm/lib/Target/IA64: IA64ISelLowering.cpp updated: 1.28 - 1.29 IA64ISelLowering.h updated: 1.6 - 1.7 --- Log message: Remove TLI.LowerReturnTo, and just let targets custom lower ISD::RET for the same functionality. This addresses another piece of bug 680:

[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

Changes in directory llvm/lib/CodeGen/SelectionDAG: SelectionDAGISel.cpp updated: 1.138 - 1.139 --- Log message: Remove TLI.LowerReturnTo, and just let targets custom lower ISD::RET for the same functionality. This addresses another piece of bug 680: http://llvm.cs.uiuc.edu/PR680 . Next, on

[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp PPCISelLowering.h

Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.71 - 1.72 PPCISelLowering.h updated: 1.15 - 1.16 --- Log message: Remove TLI.LowerReturnTo, and just let targets custom lower ISD::RET for the same functionality. This addresses another piece of bug 680:

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