Author: djg Date: Mon Nov 5 17:16:33 2007 New Revision: 43743 URL: http://llvm.org/viewvc/llvm-project?rev=43743&view=rev Log: Fix an abort in instcombine when folding creates a vector rem instruction.
Added: llvm/trunk/test/Transforms/InstCombine/vector-srem.ll Modified: llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp Modified: llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp?rev=43743&r1=43742&r2=43743&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp Mon Nov 5 17:16:33 2007 @@ -2622,6 +2622,7 @@ if (I.getType()->isInteger()) { APInt Mask(APInt::getSignBit(I.getType()->getPrimitiveSizeInBits())); if (MaskedValueIsZero(Op1, Mask) && MaskedValueIsZero(Op0, Mask)) { + // X sdiv Y -> X udiv Y, iff X and Y don't have sign bit set return BinaryOperator::createUDiv(Op0, Op1, I.getName()); } } @@ -2811,6 +2812,7 @@ Instruction *InstCombiner::visitSRem(BinaryOperator &I) { Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); + // Handle the integer rem common cases if (Instruction *common = commonIRemTransforms(I)) return common; @@ -2823,12 +2825,14 @@ return &I; } - // If the top bits of both operands are zero (i.e. we can prove they are + // If the sign bits of both operands are zero (i.e. we can prove they are // unsigned inputs), turn this into a urem. - APInt Mask(APInt::getSignBit(I.getType()->getPrimitiveSizeInBits())); - if (MaskedValueIsZero(Op1, Mask) && MaskedValueIsZero(Op0, Mask)) { - // X srem Y -> X urem Y, iff X and Y don't have sign bit set - return BinaryOperator::createURem(Op0, Op1, I.getName()); + if (I.getType()->isInteger()) { + APInt Mask(APInt::getSignBit(I.getType()->getPrimitiveSizeInBits())); + if (MaskedValueIsZero(Op1, Mask) && MaskedValueIsZero(Op0, Mask)) { + // X srem Y -> X urem Y, iff X and Y don't have sign bit set + return BinaryOperator::createURem(Op0, Op1, I.getName()); + } } return 0; Added: llvm/trunk/test/Transforms/InstCombine/vector-srem.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/vector-srem.ll?rev=43743&view=auto ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/vector-srem.ll (added) +++ llvm/trunk/test/Transforms/InstCombine/vector-srem.ll Mon Nov 5 17:16:33 2007 @@ -0,0 +1,9 @@ +; RUN: llvm-as < %s | opt -instcombine | llvm-dis | grep {srem <4 x i32>} + +define <4 x i32> @foo(<4 x i32> %t, <4 x i32> %u) +{ + %k = sdiv <4 x i32> %t, %u + %l = mul <4 x i32> %k, %u + %m = sub <4 x i32> %t, %l + ret <4 x i32> %m +} _______________________________________________ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits