Author: djg Date: Wed Feb 13 16:28:48 2008 New Revision: 47096 URL: http://llvm.org/viewvc/llvm-project?rev=47096&view=rev Log: Simplify some logic in ComputeMaskedBits. And change ComputeMaskedBits to pass the mask APInt by value, not by reference.
Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h llvm/trunk/include/llvm/Target/TargetLowering.h llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp llvm/trunk/lib/Target/ARM/ARMISelLowering.h llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp llvm/trunk/lib/Target/CellSPU/SPUISelLowering.h llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.h Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=47096&r1=47095&r2=47096&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Wed Feb 13 16:28:48 2008 @@ -556,7 +556,7 @@ /// bitsets. This code only analyzes bits in Mask, in order to short-circuit /// processing. Targets can implement the computeMaskedBitsForTargetNode /// method in the TargetLowering class to allow target nodes to be understood. - void ComputeMaskedBits(SDOperand Op, APInt Mask, APInt &KnownZero, + void ComputeMaskedBits(SDOperand Op, const APInt &Mask, APInt &KnownZero, APInt &KnownOne, unsigned Depth = 0) const; /// ComputeMaskedBits - This is a wrapper around the APInt-using Modified: llvm/trunk/include/llvm/Target/TargetLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=47096&r1=47095&r2=47096&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetLowering.h (original) +++ llvm/trunk/include/llvm/Target/TargetLowering.h Wed Feb 13 16:28:48 2008 @@ -627,7 +627,7 @@ /// Mask are known to be either zero or one and return them in the /// KnownZero/KnownOne bitsets. virtual void computeMaskedBitsForTargetNode(const SDOperand Op, - APInt Mask, + const APInt &Mask, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=47096&r1=47095&r2=47096&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Wed Feb 13 16:28:48 2008 @@ -1130,7 +1130,7 @@ /// known to be either zero or one and return them in the KnownZero/KnownOne /// bitsets. This code only analyzes bits in Mask, in order to short-circuit /// processing. -void SelectionDAG::ComputeMaskedBits(SDOperand Op, APInt Mask, +void SelectionDAG::ComputeMaskedBits(SDOperand Op, const APInt &Mask, APInt &KnownZero, APInt &KnownOne, unsigned Depth) const { unsigned BitWidth = Mask.getBitWidth(); @@ -1153,8 +1153,8 @@ case ISD::AND: // If either the LHS or the RHS are Zero, the result is zero. ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); - Mask &= ~KnownZero; - ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1); + ComputeMaskedBits(Op.getOperand(0), Mask & ~KnownZero, + KnownZero2, KnownOne2, Depth+1); assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); @@ -1165,8 +1165,8 @@ return; case ISD::OR: ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); - Mask &= ~KnownOne; - ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1); + ComputeMaskedBits(Op.getOperand(0), Mask & ~KnownOne, + KnownZero2, KnownOne2, Depth+1); assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); @@ -1271,21 +1271,19 @@ return; case ISD::SIGN_EXTEND_INREG: { MVT::ValueType EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); + unsigned EBits = MVT::getSizeInBits(EVT); // Sign extension. Compute the demanded bits in the result that are not // present in the input. - APInt NewBits = ~APInt::getLowBitsSet(BitWidth, - MVT::getSizeInBits(EVT)) & Mask; + APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - EBits) & Mask; - APInt InSignBit = APInt::getSignBit(MVT::getSizeInBits(EVT)); - APInt InputDemandedBits = - Mask & APInt::getLowBitsSet(BitWidth, - MVT::getSizeInBits(EVT)); + APInt InSignBit = APInt::getSignBit(EBits); + APInt InputDemandedBits = Mask & APInt::getLowBitsSet(BitWidth, EBits); // If the sign extended bits are demanded, we know that the sign // bit is demanded. InSignBit.zext(BitWidth); - if (!!NewBits) + if (NewBits.getBoolValue()) InputDemandedBits |= InSignBit; ComputeMaskedBits(Op.getOperand(0), InputDemandedBits, @@ -1318,19 +1316,20 @@ if (ISD::isZEXTLoad(Op.Val)) { LoadSDNode *LD = cast<LoadSDNode>(Op); MVT::ValueType VT = LD->getMemoryVT(); - KnownZero |= ~APInt::getLowBitsSet(BitWidth, MVT::getSizeInBits(VT)) & Mask; + unsigned MemBits = MVT::getSizeInBits(VT); + KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits) & Mask; } return; } case ISD::ZERO_EXTEND: { MVT::ValueType InVT = Op.getOperand(0).getValueType(); unsigned InBits = MVT::getSizeInBits(InVT); - APInt InMask = APInt::getLowBitsSet(BitWidth, InBits); - APInt NewBits = (~InMask) & Mask; - Mask.trunc(InBits); + APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits) & Mask; + APInt InMask = Mask; + InMask.trunc(InBits); KnownZero.trunc(InBits); KnownOne.trunc(InBits); - ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); + ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); KnownZero.zext(BitWidth); KnownOne.zext(BitWidth); KnownZero |= NewBits; @@ -1339,43 +1338,52 @@ case ISD::SIGN_EXTEND: { MVT::ValueType InVT = Op.getOperand(0).getValueType(); unsigned InBits = MVT::getSizeInBits(InVT); - APInt InMask = APInt::getLowBitsSet(BitWidth, InBits); APInt InSignBit = APInt::getSignBit(InBits); - APInt NewBits = (~InMask) & Mask; + APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits) & Mask; + APInt InMask = Mask; + InMask.trunc(InBits); // If any of the sign extended bits are demanded, we know that the sign - // bit is demanded. - InSignBit.zext(BitWidth); - if (!!(NewBits & Mask)) - Mask |= InSignBit; + // bit is demanded. Temporarily set this bit in the mask for our callee. + if (NewBits.getBoolValue()) + InMask |= InSignBit; - Mask.trunc(InBits); KnownZero.trunc(InBits); KnownOne.trunc(InBits); - ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); + ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); + + // Note if the sign bit is known to be zero or one. + bool SignBitKnownZero = KnownZero.isNegative(); + bool SignBitKnownOne = KnownOne.isNegative(); + assert(!(SignBitKnownZero && SignBitKnownOne) && + "Sign bit can't be known to be both zero and one!"); + + // If the sign bit wasn't actually demanded by our caller, we don't + // want it set in the KnownZero and KnownOne result values. Reset the + // mask and reapply it to the result values. + InMask = Mask; + InMask.trunc(InBits); + KnownZero &= InMask; + KnownOne &= InMask; + KnownZero.zext(BitWidth); KnownOne.zext(BitWidth); - // If the sign bit is known zero or one, the top bits match. - if (!!(KnownZero & InSignBit)) { + // If the sign bit is known zero or one, the top bits match. + if (SignBitKnownZero) KnownZero |= NewBits; - KnownOne &= ~NewBits; - } else if (!!(KnownOne & InSignBit)) { + else if (SignBitKnownOne) KnownOne |= NewBits; - KnownZero &= ~NewBits; - } else { // Otherwise, top bits aren't known. - KnownOne &= ~NewBits; - KnownZero &= ~NewBits; - } return; } case ISD::ANY_EXTEND: { MVT::ValueType InVT = Op.getOperand(0).getValueType(); unsigned InBits = MVT::getSizeInBits(InVT); - Mask.trunc(InBits); + APInt InMask = Mask; + InMask.trunc(InBits); KnownZero.trunc(InBits); KnownOne.trunc(InBits); - ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); + ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); KnownZero.zext(BitWidth); KnownOne.zext(BitWidth); return; @@ -1383,10 +1391,11 @@ case ISD::TRUNCATE: { MVT::ValueType InVT = Op.getOperand(0).getValueType(); unsigned InBits = MVT::getSizeInBits(InVT); - Mask.zext(InBits); + APInt InMask = Mask; + InMask.zext(InBits); KnownZero.zext(InBits); KnownOne.zext(InBits); - ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); + ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); KnownZero.trunc(BitWidth); KnownOne.trunc(BitWidth); @@ -1415,8 +1424,8 @@ // Output known-0 bits are known if clear or set in both the low clear bits // common to both LHS & RHS. For example, 8+(X<<3) is known to have the // low 3 bits clear. - unsigned KnownZeroOut = std::min((~KnownZero).countTrailingZeros(), - (~KnownZero2).countTrailingZeros()); + unsigned KnownZeroOut = std::min(KnownZero.countTrailingOnes(), + KnownZero2.countTrailingOnes()); KnownZero = APInt::getLowBitsSet(BitWidth, KnownZeroOut); KnownOne = APInt(BitWidth, 0); @@ -1431,7 +1440,7 @@ // positive if we can prove that X is >= 0 and < 16. // sign bit clear - if (!(CLHS->getAPIntValue() & APInt::getSignBit(BitWidth))) { + if (CLHS->getAPIntValue().isNonNegative()) { unsigned NLZ = (CLHS->getAPIntValue()+1).countLeadingZeros(); // NLZ can't be BitWidth with no sign bit APInt MaskV = APInt::getHighBitsSet(BitWidth, NLZ); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=47096&r1=47095&r2=47096&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Wed Feb 13 16:28:48 2008 @@ -1008,7 +1008,7 @@ /// in Mask are known to be either zero or one and return them in the /// KnownZero/KnownOne bitsets. void TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, - APInt Mask, + const APInt &Mask, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, @@ -1019,8 +1019,7 @@ Op.getOpcode() == ISD::INTRINSIC_VOID) && "Should use MaskedValueIsZero if you don't know whether Op" " is a target node!"); - KnownZero = 0; - KnownOne = 0; + KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); } /// ComputeNumSignBitsForTargetNode - This method can be implemented by Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=47096&r1=47095&r2=47096&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Wed Feb 13 16:28:48 2008 @@ -1762,7 +1762,7 @@ } void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, - APInt Mask, + const APInt &Mask, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.h?rev=47096&r1=47095&r2=47096&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.h (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.h Wed Feb 13 16:28:48 2008 @@ -106,7 +106,7 @@ SelectionDAG &DAG); virtual void computeMaskedBitsForTargetNode(const SDOperand Op, - APInt Mask, + const APInt &Mask, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp?rev=47096&r1=47095&r2=47096&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp Wed Feb 13 16:28:48 2008 @@ -2668,7 +2668,7 @@ void SPUTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, - APInt Mask, + const APInt &Mask, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelLowering.h?rev=47096&r1=47095&r2=47096&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUISelLowering.h (original) +++ llvm/trunk/lib/Target/CellSPU/SPUISelLowering.h Wed Feb 13 16:28:48 2008 @@ -108,7 +108,7 @@ virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; virtual void computeMaskedBitsForTargetNode(const SDOperand Op, - APInt Mask, + const APInt &Mask, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=47096&r1=47095&r2=47096&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Wed Feb 13 16:28:48 2008 @@ -3451,7 +3451,7 @@ //===----------------------------------------------------------------------===// void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, - APInt Mask, + const APInt &Mask, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h?rev=47096&r1=47095&r2=47096&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h (original) +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h Wed Feb 13 16:28:48 2008 @@ -254,7 +254,7 @@ virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; virtual void computeMaskedBitsForTargetNode(const SDOperand Op, - APInt Mask, + const APInt &Mask, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, Modified: llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp?rev=47096&r1=47095&r2=47096&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp Wed Feb 13 16:28:48 2008 @@ -110,7 +110,7 @@ /// in Mask are known to be either zero or one and return them in the /// KnownZero/KnownOne bitsets. virtual void computeMaskedBitsForTargetNode(const SDOperand Op, - APInt Mask, + const APInt &Mask, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, @@ -270,7 +270,7 @@ /// be zero. Op is expected to be a target specific node. Used by DAG /// combiner. void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, - APInt Mask, + const APInt &Mask, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=47096&r1=47095&r2=47096&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Feb 13 16:28:48 2008 @@ -5640,7 +5640,7 @@ //===----------------------------------------------------------------------===// void X86TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, - APInt Mask, + const APInt &Mask, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=47096&r1=47095&r2=47096&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Wed Feb 13 16:28:48 2008 @@ -379,7 +379,7 @@ /// in Mask are known to be either zero or one and return them in the /// KnownZero/KnownOne bitsets. virtual void computeMaskedBitsForTargetNode(const SDOperand Op, - APInt Mask, + const APInt &Mask, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, _______________________________________________ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits