Changes in directory llvm/lib/Target/PowerPC:
PPCAsmPrinter.cpp updated: 1.217 -> 1.218 PPCCodeEmitter.cpp updated: 1.70 -> 1.71 PPCHazardRecognizers.cpp updated: 1.17 -> 1.18 PPCISelDAGToDAG.cpp updated: 1.226 -> 1.227 PPCInstrInfo.cpp updated: 1.35 -> 1.36 PPCJITInfo.cpp updated: 1.30 -> 1.31 PPCRegisterInfo.cpp updated: 1.93 -> 1.94 PPCSubtarget.cpp updated: 1.25 -> 1.26 --- Log message: What should be the last unnecessary <iostream>s in the library. --- Diffs of the changes: (+10 -19) PPCAsmPrinter.cpp | 5 ++--- PPCCodeEmitter.cpp | 3 +-- PPCHazardRecognizers.cpp | 4 +--- PPCISelDAGToDAG.cpp | 1 - PPCInstrInfo.cpp | 1 - PPCJITInfo.cpp | 1 - PPCRegisterInfo.cpp | 5 ++--- PPCSubtarget.cpp | 9 ++++----- 8 files changed, 10 insertions(+), 19 deletions(-) Index: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp diff -u llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.217 llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.218 --- llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.217 Wed Dec 6 11:46:32 2006 +++ llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp Thu Dec 7 16:21:48 2006 @@ -41,7 +41,6 @@ #include "llvm/Target/TargetOptions.h" #include "llvm/ADT/Statistic.h" #include "llvm/ADT/StringExtras.h" -#include <iostream> #include <set> using namespace llvm; @@ -295,7 +294,7 @@ void PPCAsmPrinter::printOp(const MachineOperand &MO) { switch (MO.getType()) { case MachineOperand::MO_Immediate: - std::cerr << "printOp() does not handle immediate values\n"; + cerr << "printOp() does not handle immediate values\n"; abort(); return; @@ -629,7 +628,7 @@ SwitchToDataSection("\t.data", I); break; default: - std::cerr << "Unknown linkage type!"; + cerr << "Unknown linkage type!"; abort(); } Index: llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp diff -u llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp:1.70 llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp:1.71 --- llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp:1.70 Wed Dec 6 13:40:04 2006 +++ llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp Thu Dec 7 16:21:48 2006 @@ -24,7 +24,6 @@ #include "llvm/Support/Debug.h" #include "llvm/Support/Compiler.h" #include "llvm/Target/TargetOptions.h" -#include <iostream> using namespace llvm; namespace { @@ -193,7 +192,7 @@ Reloc, MO.getMachineBasicBlock())); } else { - std::cerr << "ERROR: Unknown type of MachineOperand: " << MO << "\n"; + cerr << "ERROR: Unknown type of MachineOperand: " << MO << "\n"; abort(); } Index: llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp diff -u llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp:1.17 llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp:1.18 --- llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp:1.17 Wed Nov 15 18:57:19 2006 +++ llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp Thu Dec 7 16:21:48 2006 @@ -16,10 +16,8 @@ #include "PPC.h" #include "PPCInstrInfo.h" #include "llvm/Support/Debug.h" -#include <iostream> using namespace llvm; - //===----------------------------------------------------------------------===// // PowerPC 970 Hazard Recognizer // @@ -52,7 +50,7 @@ } void PPCHazardRecognizer970::EndDispatchGroup() { - DEBUG(std::cerr << "=== Start of dispatch group\n"); + DOUT << "=== Start of dispatch group\n"; NumIssued = 0; // Structural hazard info. Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp diff -u llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.226 llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.227 --- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.226 Wed Dec 6 11:46:32 2006 +++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Thu Dec 7 16:21:48 2006 @@ -30,7 +30,6 @@ #include "llvm/Support/Debug.h" #include "llvm/Support/MathExtras.h" #include "llvm/Support/Compiler.h" -#include <iostream> #include <queue> #include <set> using namespace llvm; Index: llvm/lib/Target/PowerPC/PPCInstrInfo.cpp diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:1.35 llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:1.36 --- llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:1.35 Mon Nov 27 17:37:22 2006 +++ llvm/lib/Target/PowerPC/PPCInstrInfo.cpp Thu Dec 7 16:21:48 2006 @@ -16,7 +16,6 @@ #include "PPCGenInstrInfo.inc" #include "PPCTargetMachine.h" #include "llvm/CodeGen/MachineInstrBuilder.h" -#include <iostream> using namespace llvm; PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm) Index: llvm/lib/Target/PowerPC/PPCJITInfo.cpp diff -u llvm/lib/Target/PowerPC/PPCJITInfo.cpp:1.30 llvm/lib/Target/PowerPC/PPCJITInfo.cpp:1.31 --- llvm/lib/Target/PowerPC/PPCJITInfo.cpp:1.30 Thu Sep 28 18:32:43 2006 +++ llvm/lib/Target/PowerPC/PPCJITInfo.cpp Thu Dec 7 16:21:48 2006 @@ -18,7 +18,6 @@ #include "llvm/Config/alloca.h" #include "llvm/Support/Debug.h" #include <set> -#include <iostream> using namespace llvm; static TargetJITInfo::JITCompilerFn JITCompilerFunction; Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.93 llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.94 --- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.93 Thu Dec 7 16:15:58 2006 +++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Thu Dec 7 16:21:48 2006 @@ -36,7 +36,6 @@ #include "llvm/Support/MathExtras.h" #include "llvm/ADT/STLExtras.h" #include <cstdlib> -#include <iostream> using namespace llvm; /// getRegisterNumbering - Given the enum value for some register, e.g. @@ -77,7 +76,7 @@ case R30: case X30: case F30: case V30: return 30; case R31: case X31: case F31: case V31: return 31; default: - std::cerr << "Unhandled reg in PPCRegisterInfo::getRegisterNumbering!\n"; + cerr << "Unhandled reg in PPCRegisterInfo::getRegisterNumbering!\n"; abort(); } } @@ -234,7 +233,7 @@ } else if (RC == PPC::VRRCRegisterClass) { BuildMI(MBB, MI, TII.get(PPC::VOR), DestReg).addReg(SrcReg).addReg(SrcReg); } else { - std::cerr << "Attempt to copy register that is not GPR or FPR"; + cerr << "Attempt to copy register that is not GPR or FPR"; abort(); } } Index: llvm/lib/Target/PowerPC/PPCSubtarget.cpp diff -u llvm/lib/Target/PowerPC/PPCSubtarget.cpp:1.25 llvm/lib/Target/PowerPC/PPCSubtarget.cpp:1.26 --- llvm/lib/Target/PowerPC/PPCSubtarget.cpp:1.25 Fri Jul 14 20:24:23 2006 +++ llvm/lib/Target/PowerPC/PPCSubtarget.cpp Thu Dec 7 16:21:48 2006 @@ -15,7 +15,6 @@ #include "PPC.h" #include "llvm/Module.h" #include "PPCGenSubtarget.inc" -#include <iostream> using namespace llvm; #if defined(__APPLE__) @@ -80,8 +79,8 @@ // If we are generating code for ppc64, verify that options make sense. if (is64Bit) { if (!has64BitSupport()) { - std::cerr << "PPC: Generation of 64-bit code for a 32-bit processor " - "requested. Ignoring 32-bit processor feature.\n"; + cerr << "PPC: Generation of 64-bit code for a 32-bit processor " + << "requested. Ignoring 32-bit processor feature.\n"; Has64BitSupport = true; } // Silently force 64-bit register use on ppc64. @@ -91,8 +90,8 @@ // If the user requested use of 64-bit regs, but the cpu selected doesn't // support it, warn and ignore. if (use64BitRegs() && !has64BitSupport()) { - std::cerr << "PPC: 64-bit registers requested on CPU without support. " - "Disabling 64-bit register use.\n"; + cerr << "PPC: 64-bit registers requested on CPU without support. " + << "Disabling 64-bit register use.\n"; Use64BitRegs = false; } _______________________________________________ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits