Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.272 - 1.273
---
Log message:
If a function is vararg, never pass inreg arguments in registers. Thanks to
Anton for half of this patch.
---
Diffs of the changes: (+2 -1)
PPCISelLowering.cpp |3 ++-
1 files
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.273 - 1.274
---
Log message:
describe an argument, hide it.
---
Diffs of the changes: (+3 -1)
PPCISelLowering.cpp |4 +++-
1 files changed, 3 insertions(+), 1 deletion(-)
Index:
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.270 - 1.271
---
Log message:
Apply this patch:
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20070514/049845.html
---
Diffs of the changes: (+1 -1)
PPCISelLowering.cpp |2 +-
1 files changed, 1
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.269 - 1.270
---
Log message:
fix some subtle inline asm selection issues
---
Diffs of the changes: (+17 -9)
PPCISelLowering.cpp | 26 +-
1 files changed, 17 insertions(+), 9 deletions(-)
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.267 - 1.268
PPCISelLowering.h updated: 1.64 - 1.65
---
Log message:
Starting implementation of the ELF32 ABI specification of varargs handling.
LowerVASTART emits the right code if the subtarget is ELF32, the other
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.264 - 1.265
PPCISelLowering.h updated: 1.63 - 1.64
---
Log message:
implement the new addressing mode description hook.
---
Diffs of the changes: (+38 -1)
PPCISelLowering.cpp | 35
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.263 - 1.264
---
Log message:
The C standards do say that char may either be a signed char or unsigned
char and it is up to the compilers implementation or the platform which is
followed.
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.262 - 1.263
PPCISelLowering.h updated: 1.62 - 1.63
---
Log message:
switch TargetLowering::getConstraintType to take the entire constraint,
not just the first letter. No functionality change.
---
Diffs of the
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.261 - 1.262
---
Log message:
Stack and register alignment of call arguments in the ELF ABI
---
Diffs of the changes: (+52 -6)
PPCISelLowering.cpp | 58 ++--
1
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.260 - 1.261
PPCISelLowering.h updated: 1.61 - 1.62
---
Log message:
More flexible TargetLowering LSR hooks for testing whether an immediate is a
legal target address immediate or scale.
---
Diffs of the changes:
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.257 - 1.258
PPCISelLowering.h updated: 1.59 - 1.60
PPCInstr64Bit.td updated: 1.40 - 1.41
PPCInstrInfo.td updated: 1.275 - 1.276
---
Log message:
Differentiate between the MachO and the ELF ABI the CALL instruction.
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.256 - 1.257
PPCInstrInfo.td updated: 1.274 - 1.275
---
Log message:
always lower to RETFLAG, never leave it as just ret.
---
Diffs of the changes: (+7 -11)
PPCISelLowering.cpp | 15 +++
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.254 - 1.255
---
Log message:
always promote float varargs to double.
---
Diffs of the changes: (+1 -1)
PPCISelLowering.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index:
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.255 - 1.256
---
Log message:
no really, this is the right patch
---
Diffs of the changes: (+1 -1)
PPCISelLowering.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index:
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.252 - 1.253
---
Log message:
Simplify lowering and selection of exception ops.
---
Diffs of the changes: (+15 -34)
PPCISelLowering.cpp | 49 +++--
1 files changed, 15
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.251 - 1.252
PPCRegisterInfo.cpp updated: 1.108 - 1.109
PPCRegisterInfo.h updated: 1.27 - 1.28
---
Log message:
Support to provide exception and selector registers.
---
Diffs of the changes: (+40 -1)
Support to provide exception and selector registers.
Hey Jim,
This behavior:
+/// LowerEXCEPTIONADDR - Replace EXCEPTIONADDR with a copy from
the exception
+/// register. The register was made live in the ISel.
+static SDOperand LowerEXCEPTIONADDR(SDOperand Op, SelectionDAG
DAG) {
+
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.249 - 1.250
---
Log message:
Compile test/CodeGen/PowerPC/LargeAbsoluteAddr.ll to:
_test:
lis r2, 743
li r3, 0
stw r3, 32751(r2)
blr
instead of:
_test:
li r2, 0
stw
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.250 - 1.251
---
Log message:
Fix ixaddrs as well, allowing ppc64 to compile to:
_test2:
li r2, 0
lis r3, 1
std r2, 9024(r3)
blr
instead of:
_test2:
lis r2, 1
li r3,
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.248 - 1.249
---
Log message:
Finish off bug 680: http://llvm.org/PR680 , allowing targets to custom lower
frame and return
address nodes.
---
Diffs of the changes: (+4 -0)
PPCISelLowering.cpp |4
1
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.247 - 1.248
---
Log message:
Propagate changes from my local tree. This patch includes:
1. New parameter attribute called 'inreg'. It has meaning place this
parameter in registers, if possible. This is some
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.245 - 1.246
---
Log message:
setSetCCIsExpensive is gone.
---
Diffs of the changes: (+0 -2)
PPCISelLowering.cpp |2 --
1 files changed, 2 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.244 - 1.245
---
Log message:
Provide support for FP_TO_UINT.
---
Diffs of the changes: (+3 -1)
PPCISelLowering.cpp |4 +++-
1 files changed, 3 insertions(+), 1 deletion(-)
Index:
Should read Provide ppc64 support for FP_TO_UINT
On 15-Dec-06, at 10:33 AM, Jim Laskey wrote:
Provide support for FP_TO_UINT.
smime.p7s
Description: S/MIME cryptographic signature
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.242 - 1.243
---
Log message:
Missing opcode.
---
Diffs of the changes: (+1 -0)
PPCISelLowering.cpp |1 +
1 files changed, 1 insertion(+)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.240 - 1.241
---
Log message:
Fix i64 uint_to_fp on ppc64
---
Diffs of the changes: (+2 -1)
PPCISelLowering.cpp |3 ++-
1 files changed, 2 insertions(+), 1 deletion(-)
Index:
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.239 - 1.240
---
Log message:
Restoration of the stack pointer after a deallocation of a alloca was not
updating the SP link.
---
Diffs of the changes: (+28 -1)
PPCISelLowering.cpp | 29
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.238 - 1.239
---
Log message:
1. In ppc64 mode we need only use one GPR.
2. Float values need to be promoted to double when they are vararg.
---
Diffs of the changes: (+7 -1)
PPCISelLowering.cpp |8 +++-
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.237 - 1.238
---
Log message:
Fix the CodeGen/PowerPC/vec_constants.ll regression.
---
Diffs of the changes: (+9 -6)
PPCISelLowering.cpp | 15 +--
1 files changed, 9 insertions(+), 6 deletions(-)
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.235 - 1.236
---
Log message:
Offset for load of 32-bit arg in 64-bit world was incorrect.
---
Diffs of the changes: (+4 -1)
PPCISelLowering.cpp |5 -
1 files changed, 4 insertions(+), 1 deletion(-)
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.236 - 1.237
---
Log message:
Fix bug codegen'ing FP constant vectors with integer splats. Make sure the
created intrinsics have the right integer types. This fixes
PowerPC/2006-11-29-AltivecFPSplat.ll
---
Diffs
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.233 - 1.234
---
Log message:
32-bit int space was not accounted for properly in lowerCall.
---
Diffs of the changes: (+8 -3)
PPCISelLowering.cpp | 11 ---
1 files changed, 8 insertions(+), 3
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.234 - 1.235
---
Log message:
Remove debug code.
---
Diffs of the changes: (+0 -2)
PPCISelLowering.cpp |2 --
1 files changed, 2 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.231 - 1.232
---
Log message:
on ppc64, float arguments take 8-byte stack slots not 4-byte stack slots.
Also, valist should create a pointer RC reg class value, not a GPRC value.
---
Diffs of the changes: (+8 -3)
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.224 - 1.225
---
Log message:
minor tweaks, reject vector preinc.
---
Diffs of the changes: (+9 -4)
PPCISelLowering.cpp | 13 +
1 files changed, 9 insertions(+), 4 deletions(-)
Index:
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.225 - 1.226
---
Log message:
lower X = seteq Y, Z to '(shr (ctlz (xor Y, Z)), 5)' instead of
'(shr (ctlz (sub Y, Z)), 5)'.
The use of xor better exposes the operation to bit-twiddling logic in the
dag combiner. For
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.223 - 1.224
---
Log message:
ppc64 doesn't have lwau, don't attempt to form it.
---
Diffs of the changes: (+9 -3)
PPCISelLowering.cpp | 12 +---
1 files changed, 9 insertions(+), 3 deletions(-)
Index:
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.219 - 1.220
PPCISelLowering.h updated: 1.55 - 1.56
---
Log message:
Rename ISD::MemOpAddrMode to ISD::MemIndexedMode
---
Diffs of the changes: (+2 -2)
PPCISelLowering.cpp |2 +-
PPCISelLowering.h |2 +-
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.220 - 1.221
---
Log message:
PPC supports i32 / i64 pre-inc load / store.
---
Diffs of the changes: (+6 -0)
PPCISelLowering.cpp |6 ++
1 files changed, 6 insertions(+)
Index:
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.216 - 1.217
PPCISelLowering.h updated: 1.53 - 1.54
---
Log message:
Implement the getRegForInlineAsmConstraint method for PPC. With recent
sdisel changes, this eliminates a ton of copies around common inline asms.
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.215 - 1.216
PPCISelLowering.h updated: 1.52 - 1.53
---
Log message:
Change the prototype for TargetLowering::isOperandValidForConstraint
---
Diffs of the changes: (+20 -12)
PPCISelLowering.cpp | 29
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.214 - 1.215
---
Log message:
All targets expand BR_JT for now.
---
Diffs of the changes: (+2 -0)
PPCISelLowering.cpp |2 ++
1 files changed, 2 insertions(+)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.212 - 1.213
---
Log message:
Expand alloca for ppc64
---
Diffs of the changes: (+2 -1)
PPCISelLowering.cpp |3 ++-
1 files changed, 2 insertions(+), 1 deletion(-)
Index:
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.211 - 1.212
PPCInstr64Bit.td updated: 1.21 - 1.22
PPCInstrInfo.td updated: 1.247 - 1.248
---
Log message:
Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode.
---
Diffs of the changes: (+21 -23)
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.210 - 1.211
PPCInstr64Bit.td updated: 1.20 - 1.21
PPCInstrInfo.td updated: 1.243 - 1.244
---
Log message:
Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes.
---
Diffs of the changes: (+49 -50)
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.209 - 1.210
---
Log message:
Make use of getStore().
---
Diffs of the changes: (+11 -13)
PPCISelLowering.cpp | 24 +++-
1 files changed, 11 insertions(+), 13 deletions(-)
Index:
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.208 - 1.209
---
Log message:
Combine ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD into ISD::LOADX. Add an
extra operand to LOADX to specify the exact value extension type.
---
Diffs of the changes: (+5 -5)
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.207 - 1.208
---
Log message:
Legalize is no longer limited to cleverness with just constant shift amounts.
Allow it to be clever when possible and fall back to the gross code when needed.
This allows us to compile:
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.206 - 1.207
---
Log message:
Fold the PPCISD shifts when presented with 0 inputs. This occurs for code
like:
long long test(long long X, int Y) {
return 1ULL Y;
}
long long test2(long long X, int Y) {
return
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.204 - 1.205
PPCISelLowering.h updated: 1.51 - 1.52
---
Log message:
For PR387: http://llvm.org/PR387 :
Close out this long standing bug by removing the remaining overloaded
virtual functions in LLVM. The
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.203 - 1.204
---
Log message:
Fix a bug in a recent refactoring that broke a bunch of stuff.
---
Diffs of the changes: (+1 -1)
PPCISelLowering.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index:
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.201 - 1.202
---
Log message:
Convert vectors to fixed sized arrays and smallvectors. Eliminate use of
getNode that takes a vector.
---
Diffs of the changes: (+42 -37)
PPCISelLowering.cpp | 79
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.202 - 1.203
---
Log message:
Eliminate use of getNode that takes a vector.
---
Diffs of the changes: (+22 -19)
PPCISelLowering.cpp | 41 ++---
1 files changed, 22
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.193 - 1.194
---
Log message:
Use i32 for shift amounts instead of i64. This gets bisort working.
---
Diffs of the changes: (+1 -0)
PPCISelLowering.cpp |1 +
1 files changed, 1 insertion(+)
Index:
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.195 - 1.196
---
Log message:
PPC doesn't have bit converts to/from i64
---
Diffs of the changes: (+2 -0)
PPCISelLowering.cpp |2 ++
1 files changed, 2 insertions(+)
Index:
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.196 - 1.197
---
Log message:
Implement 64-bit select, bswap, etc.
---
Diffs of the changes: (+4 -0)
PPCISelLowering.cpp |4
1 files changed, 4 insertions(+)
Index:
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.191 - 1.192
---
Log message:
Improve PPC64 calling convention support
---
Diffs of the changes: (+84 -37)
PPCISelLowering.cpp | 121
1 files changed, 84
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.190 - 1.191
---
Log message:
Correct returns of 64-bit values, though they seemed to work before...
---
Diffs of the changes: (+19 -9)
PPCISelLowering.cpp | 28 +++-
1 files changed, 19
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.189 - 1.190
PPCInstr64Bit.td updated: 1.1 - 1.2
PPCInstrInfo.td updated: 1.223 - 1.224
---
Log message:
fix some assumptions that pointers can only be 32-bits. With this, we can
now compile:
static unsigned long X;
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.185 - 1.186
---
Log message:
Always reserve space for 8 spilled GPRs. GCC apparently assumes that this
space will be available, even if the callee isn't varargs.
---
Diffs of the changes: (+7 -12)
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.184 - 1.185
---
Log message:
Change RET node to include signness information of the return values. i.e.
RET chain, value1, sign1, value2, sign2, ...
---
Diffs of the changes: (+3 -3)
PPCISelLowering.cpp |6
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.182 - 1.183
PPCInstrInfo.h updated: 1.14 - 1.15
PPCJITInfo.cpp updated: 1.21 - 1.22
PPCRelocations.h updated: 1.6 - 1.7
---
Log message:
Patches to make the LLVM sources more -pedantic clean. Patch provided
by Anton
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.183 - 1.184
---
Log message:
CALL node change (arg / sign pairs instead of just arguments).
---
Diffs of the changes: (+6 -5)
PPCISelLowering.cpp | 11 ++-
1 files changed, 6 insertions(+), 5
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.180 - 1.181
---
Log message:
Handle SETO* like we handle SET*, restoring behavior after Evan's setcc
change. This fixes PowerPC/fnegsel.ll.
---
Diffs of the changes: (+8 -0)
PPCISelLowering.cpp |8
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.181 - 1.182
---
Log message:
Fix CodeGen/Generic/vector.ll:test_div with altivec.
---
Diffs of the changes: (+1 -0)
PPCISelLowering.cpp |1 +
1 files changed, 1 insertion(+)
Index:
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.171 - 1.172
PPCISelLowering.h updated: 1.47 - 1.48
---
Log message:
Switch the PPC backend over to using FORMAL_ARGUMENTS for formal argument
handling. This makes the lower argument code significantly simpler (we
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.172 - 1.173
---
Log message:
Vector args passed in registers don't reserve stack space.
---
Diffs of the changes: (+26 -11)
PPCISelLowering.cpp | 37 ++---
1 files changed, 26
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.173 - 1.174
---
Log message:
Simplify the dead argument handling code.
---
Diffs of the changes: (+11 -28)
PPCISelLowering.cpp | 39 +++
1 files changed, 11 insertions(+), 28
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.174 - 1.175
---
Log message:
Simplify the argument counting logic by only incrementing the index.
---
Diffs of the changes: (+11 -14)
PPCISelLowering.cpp | 25 +++--
1 files changed, 11
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.175 - 1.176
PPCISelLowering.h updated: 1.48 - 1.49
---
Log message:
Instead of implementing LowerCallTo directly, let the default impl produce an
ISD::CALL node, then custom lower that. This means that we only have
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.177 - 1.178
---
Log message:
3 changes, 2 of which are cleanup one of which changes codegen:
1. Rearrange code a bit so that the special case doesn't require indenting lots
of code.
2. Add comments describing PPC
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.170 - 1.171
---
Log message:
Fit in 80 cols
---
Diffs of the changes: (+3 -3)
PPCISelLowering.cpp |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
Index:
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.168 - 1.169
---
Log message:
Fix CodeGen/Generic/2006-04-28-Sign-extend-bool.ll
---
Diffs of the changes: (+4 -0)
PPCISelLowering.cpp |4
1 files changed, 4 insertions(+)
Index:
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.164 - 1.165
PPCISelLowering.h updated: 1.46 - 1.47
PPCInstrInfo.td updated: 1.215 - 1.216
README_ALTIVEC.txt updated: 1.29 - 1.30
---
Log message:
Implement an important entry from README_ALTIVEC:
If an altivec
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.165 - 1.166
---
Log message:
pretty print node name
---
Diffs of the changes: (+1 -0)
PPCISelLowering.cpp |1 +
1 files changed, 1 insertion(+)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.166 - 1.167
---
Log message:
Fix a crash on:
void foo2(vector float *A, vector float *B) {
vector float C = (vector float)vec_cmpeq(*A, *B);
if (!vec_any_eq(*A, *B))
*B = (vector float){0,0,0,0};
*A = C;
}
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.155 - 1.156
---
Log message:
Pull some code out into a helper function.
Effeciently codegen even splats in the range [-32,30].
This allows us to codegen 30,30,30,30 as:
vspltisw v0, 15
vadduwm v2,
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.156 - 1.157
---
Log message:
Learn how to make odd splatted constants in range [17,29]. This implements
PowerPC/vec_constants.ll:test_29.
---
Diffs of the changes: (+7 -0)
PPCISelLowering.cpp |7 +++
1
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.157 - 1.158
---
Log message:
Make some code more general, adding support for constant formation of several
new patterns.
---
Diffs of the changes: (+78 -22)
PPCISelLowering.cpp | 100
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.158 - 1.159
---
Log message:
Teach the ppc backend to use rol and vsldoi to generate splatted constants.
This implements vec_constants.ll:test_vsldoi and test_rol
---
Diffs of the changes: (+49 -15)
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.159 - 1.160
---
Log message:
Make sure to check splats of every constant we can, handle splat(31) by
being a bit more clever, add support for odd splats from -31 to -17.
---
Diffs of the changes: (+14 -5)
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.161 - 1.162
---
Log message:
Lower v8i16 multiply into this code:
li r5, lo16(LCPI1_0)
lis r6, ha16(LCPI1_0)
lvx v4, r6, r5
vmulouh v5, v3, v2
vmuleuh v2, v3, v2
vperm
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.162 - 1.163
README_ALTIVEC.txt updated: 1.27 - 1.28
---
Log message:
Implement v16i8 multiply with this code:
vmuloub v5, v3, v2
vmuleub v2, v3, v2
vperm v2, v2, v5, v4
This implements
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.163 - 1.164
---
Log message:
Use vmladduhm to do v8i16 multiplies which is faster and simpler than doing
even/odd halves. Thanks to Nate telling me what's what.
---
Diffs of the changes: (+3 -18)
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.154 - 1.155
README_ALTIVEC.txt updated: 1.24 - 1.25
---
Log message:
Implement a TODO: for any shuffle that can be viewed as a v4[if]32 shuffle,
if it can be implemented in 3 or fewer discrete altivec instructions,
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.151 - 1.152
---
Log message:
Fix a crash when faced with a shuffle vector that has an undef in its mask.
---
Diffs of the changes: (+5 -1)
PPCISelLowering.cpp |6 +-
1 files changed, 5 insertions(+), 1
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.153 - 1.154
PPCInstrAltivec.td updated: 1.50 - 1.51
README_ALTIVEC.txt updated: 1.23 - 1.24
---
Log message:
Implement a TODO: have the legalizer canonicalize a bunch of operations to
one type (v4i32) so that we don't
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.149 - 1.150
---
Log message:
Move the rest of the PPCTargetLowering::LowerOperation cases out into
separate functions, for simplicity and code clarity.
---
Diffs of the changes: (+531 -470)
PPCISelLowering.cpp |
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.150 - 1.151
---
Log message:
Allow undef in a shuffle mask
---
Diffs of the changes: (+1 -0)
PPCISelLowering.cpp |1 +
1 files changed, 1 insertion(+)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.144 - 1.145
PPCInstrAltivec.td updated: 1.47 - 1.48
---
Log message:
Ensure that zero vectors are always v4i32, which forces them to CSE with
each other. This implements CodeGen/PowerPC/vxor-canonicalize.ll
---
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.145 - 1.146
PPCISelLowering.h updated: 1.45 - 1.46
PPCInstrAltivec.td updated: 1.48 - 1.49
---
Log message:
Rename get_VSPLI_elt - get_VSPLTI_elt
Canonicalize BUILD_VECTOR's that match VSPLTI's into a single type for
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.146 - 1.147
README_ALTIVEC.txt updated: 1.20 - 1.21
---
Log message:
Add a new way to match vector constants, which make it easier to bang bits of
different types.
Codegen spltw(0x7FFF) and spltw(0x8000)
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.138 - 1.139
PPCISelLowering.h updated: 1.44 - 1.45
PPCInstrAltivec.td updated: 1.46 - 1.47
---
Log message:
Change the interface to the predicate that determines if vsplti* can be used.
No functionality changes.
---
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.139 - 1.140
---
Log message:
Implement PowerPC/CodeGen/vec_splat.ll:spltish to use vsplish instead of a
constant pool load.
---
Diffs of the changes: (+57 -0)
PPCISelLowering.cpp | 57
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.141 - 1.142
---
Log message:
properly mark vector selects as expanded to select_cc
---
Diffs of the changes: (+4 -0)
PPCISelLowering.cpp |4
1 files changed, 4 insertions(+)
Index:
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.132 - 1.133
PPCISelLowering.h updated: 1.39 - 1.40
PPCInstrAltivec.td updated: 1.41 - 1.42
---
Log message:
Compile the vpkuhum/vpkuwum intrinsics into vpkuhum/vpkuwum instead of into
vperm with a perm mask lvx'd from
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.133 - 1.134
PPCISelLowering.h updated: 1.40 - 1.41
PPCInstrAltivec.td updated: 1.42 - 1.43
README_ALTIVEC.txt updated: 1.15 - 1.16
---
Log message:
Support pattern matching vsldoi(x,y) and vsldoi(x,x), which allows
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.134 - 1.135
PPCISelLowering.h updated: 1.41 - 1.42
PPCInstrAltivec.td updated: 1.43 - 1.44
README_ALTIVEC.txt updated: 1.17 - 1.18
---
Log message:
Pattern match vmrg* instructions, which are now lowered by the CFE
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.135 - 1.136
PPCISelLowering.h updated: 1.42 - 1.43
PPCInstrAltivec.td updated: 1.44 - 1.45
---
Log message:
Add support for matching vmrg(x,x) patterns
---
Diffs of the changes: (+81 -41)
PPCISelLowering.cpp |
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.137 - 1.138
---
Log message:
Make sure to return the result in the right type.
---
Diffs of the changes: (+6 -4)
PPCISelLowering.cpp | 10 ++
1 files changed, 6 insertions(+), 4 deletions(-)
Index:
1 - 100 of 156 matches
Mail list logo
