Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.171 -> 1.172 X86InstrX86-64.td updated: 1.6 -> 1.7 X86RegisterInfo.cpp updated: 1.178 -> 1.179 --- Log message: Correct instructions for moving data between GR64 and SSE registers; also correct load i64 / store i64 from v2i64. --- Diffs of the changes: (+34 -6) X86InstrSSE.td | 11 ++++++----- X86InstrX86-64.td | 26 ++++++++++++++++++++++++++ X86RegisterInfo.cpp | 3 ++- 3 files changed, 34 insertions(+), 6 deletions(-) Index: llvm/lib/Target/X86/X86InstrSSE.td diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.171 llvm/lib/Target/X86/X86InstrSSE.td:1.172 --- llvm/lib/Target/X86/X86InstrSSE.td:1.171 Fri Nov 10 15:43:37 2006 +++ llvm/lib/Target/X86/X86InstrSSE.td Thu Nov 16 17:33:25 2006 @@ -1682,17 +1682,18 @@ "movd {$src, $dst|$dst, $src}", [(set VR128:$dst, (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>; + // SSE2 instructions with XS prefix -def MOVQI2PQIrr : I<0x7E, MRMSrcReg, (ops VR128:$dst, VR64:$src), - "movq {$src, $dst|$dst, $src}", - [(set VR128:$dst, - (v2i64 (scalar_to_vector VR64:$src)))]>, XS, - Requires<[HasSSE2]>; def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (ops VR128:$dst, i64mem:$src), "movq {$src, $dst|$dst, $src}", [(set VR128:$dst, (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS, Requires<[HasSSE2]>; +def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (ops i64mem:$dst, VR128:$src), + "movq {$src, $dst|$dst, $src}", + [(store (i64 (vector_extract (v2i64 VR128:$src), + (iPTR 0))), addr:$dst)]>; + // FIXME: may not be able to eliminate this movss with coalescing the src and // dest register classes are different. We really want to write this pattern // like this: Index: llvm/lib/Target/X86/X86InstrX86-64.td diff -u llvm/lib/Target/X86/X86InstrX86-64.td:1.6 llvm/lib/Target/X86/X86InstrX86-64.td:1.7 --- llvm/lib/Target/X86/X86InstrX86-64.td:1.6 Fri Nov 3 17:48:56 2006 +++ llvm/lib/Target/X86/X86InstrX86-64.td Thu Nov 16 17:33:25 2006 @@ -59,6 +59,8 @@ : SSI<o, F, ops, asm, pattern>, REX_W; class RSDI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern> : SDI<o, F, ops, asm, pattern>, REX_W; +class RPDI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern> + : PDI<o, F, ops, asm, pattern>, REX_W; //===----------------------------------------------------------------------===// // Pattern fragments... @@ -1076,3 +1078,27 @@ def : Pat<(store (or (shl (loadi64 addr:$dst), CL:$amt), (srl GR64:$src2, (sub 64, CL:$amt))), addr:$dst), (SHLD64mrCL addr:$dst, GR64:$src2)>; + +//===----------------------------------------------------------------------===// +// X86-64 SSE Instructions +//===----------------------------------------------------------------------===// + +// Move instructions... + +def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (ops VR128:$dst, GR64:$src), + "movq {$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v2i64 (scalar_to_vector GR64:$src)))]>; +def MOV64toPQIrm : RPDI<0x6E, MRMSrcMem, (ops VR128:$dst, i64mem:$src), + "movq {$src, $dst|$dst, $src}", + [(set VR128:$dst, + (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>; + +def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (ops GR64:$dst, VR128:$src), + "movd {$src, $dst|$dst, $src}", + [(set GR64:$dst, (vector_extract (v2i64 VR128:$src), + (iPTR 0)))]>; +def MOVPQIto64mr : RPDI<0x7E, MRMDestMem, (ops i64mem:$dst, VR128:$src), + "movd {$src, $dst|$dst, $src}", + [(store (i64 (vector_extract (v2i64 VR128:$src), + (iPTR 0))), addr:$dst)]>; Index: llvm/lib/Target/X86/X86RegisterInfo.cpp diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.178 llvm/lib/Target/X86/X86RegisterInfo.cpp:1.179 --- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.178 Wed Nov 15 14:58:11 2006 +++ llvm/lib/Target/X86/X86RegisterInfo.cpp Thu Nov 16 17:33:25 2006 @@ -509,6 +509,7 @@ { X86::MOVAPDrr, X86::MOVAPDmr }, { X86::MOVAPSrr, X86::MOVAPSmr }, { X86::MOVPDI2DIrr, X86::MOVPDI2DImr }, + { X86::MOVPQIto64rr,X86::MOVPQIto64mr }, { X86::MOVPS2SSrr, X86::MOVPS2SSmr }, { X86::MOVSDrr, X86::MOVSDmr }, { X86::MOVSSrr, X86::MOVSSmr }, @@ -606,12 +607,12 @@ { X86::MOV16rr, X86::MOV16rm }, { X86::MOV32rr, X86::MOV32rm }, { X86::MOV64rr, X86::MOV64rm }, + { X86::MOV64toPQIrr, X86::MOV64toPQIrm }, { X86::MOV8rr, X86::MOV8rm }, { X86::MOVAPDrr, X86::MOVAPDrm }, { X86::MOVAPSrr, X86::MOVAPSrm }, { X86::MOVDDUPrr, X86::MOVDDUPrm }, { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm }, - { X86::MOVQI2PQIrr, X86::MOVQI2PQIrm }, { X86::MOVSD2PDrr, X86::MOVSD2PDrm }, { X86::MOVSDrr, X86::MOVSDrm }, { X86::MOVSHDUPrr, X86::MOVSHDUPrm }, _______________________________________________ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits