[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrInfo.cpp PPCRegisterInfo.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCInstrInfo.cpp updated: 1.30 - 1.31
PPCRegisterInfo.cpp updated: 1.83 - 1.84
---
Log message:
Properly transfer kill / dead info.
---
Diffs of the changes: (+27 -13)
PPCInstrInfo.cpp| 10 ++
PPCRegisterInfo.cpp | 30 +-
2 files changed, 27 insertions(+), 13 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:1.30
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:1.31
--- llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:1.30 Mon Nov 13 17:36:35 2006
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.cppWed Nov 15 14:58:11 2006
@@ -147,8 +147,18 @@
// Swap op1/op2
unsigned Reg1 = MI-getOperand(1).getReg();
unsigned Reg2 = MI-getOperand(2).getReg();
+ bool Reg1IsKill = MI-getOperand(1).isKill();
+ bool Reg2IsKill = MI-getOperand(2).isKill();
MI-getOperand(2).setReg(Reg1);
MI-getOperand(1).setReg(Reg2);
+ if (Reg1IsKill)
+MI-getOperand(2).setIsKill();
+ else
+MI-getOperand(2).unsetIsKill();
+ if (Reg2IsKill)
+MI-getOperand(1).setIsKill();
+ else
+MI-getOperand(1).unsetIsKill();
// Swap the mask around.
unsigned MB = MI-getOperand(4).getImmedValue();
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.83
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.84
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.83Wed Nov 15 11:40:51 2006
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Wed Nov 15 14:58:11 2006
@@ -337,47 +337,51 @@
// Make sure this is a reg-reg copy. Note that we can't handle MCRF, because
// it takes more than one instruction to store it.
unsigned Opc = MI-getOpcode();
-
+
+ MachineInstr *NewMI = NULL;
if ((Opc == PPC::OR
MI-getOperand(1).getReg() == MI-getOperand(2).getReg())) {
if (OpNum == 0) { // move - store
unsigned InReg = MI-getOperand(1).getReg();
- return addFrameReference(BuildMI(TII, PPC::STW,
- 3).addReg(InReg), FrameIndex);
+ NewMI = addFrameReference(BuildMI(TII, PPC::STW,
+3).addReg(InReg), FrameIndex);
} else { // move - load
unsigned OutReg = MI-getOperand(0).getReg();
- return addFrameReference(BuildMI(TII, PPC::LWZ, 2, OutReg), FrameIndex);
+ NewMI = addFrameReference(BuildMI(TII, PPC::LWZ, 2, OutReg), FrameIndex);
}
} else if ((Opc == PPC::OR8
MI-getOperand(1).getReg() == MI-getOperand(2).getReg())) {
if (OpNum == 0) { // move - store
unsigned InReg = MI-getOperand(1).getReg();
- return addFrameReference(BuildMI(TII, PPC::STD,
- 3).addReg(InReg), FrameIndex);
+ NewMI = addFrameReference(BuildMI(TII, PPC::STD,
+3).addReg(InReg), FrameIndex);
} else { // move - load
unsigned OutReg = MI-getOperand(0).getReg();
- return addFrameReference(BuildMI(TII, PPC::LD, 2, OutReg), FrameIndex);
+ NewMI = addFrameReference(BuildMI(TII, PPC::LD, 2, OutReg), FrameIndex);
}
} else if (Opc == PPC::FMRD) {
if (OpNum == 0) { // move - store
unsigned InReg = MI-getOperand(1).getReg();
- return addFrameReference(BuildMI(TII, PPC::STFD,
- 3).addReg(InReg), FrameIndex);
+ NewMI = addFrameReference(BuildMI(TII, PPC::STFD,
+3).addReg(InReg), FrameIndex);
} else { // move - load
unsigned OutReg = MI-getOperand(0).getReg();
- return addFrameReference(BuildMI(TII, PPC::LFD, 2, OutReg), FrameIndex);
+ NewMI = addFrameReference(BuildMI(TII, PPC::LFD, 2, OutReg), FrameIndex);
}
} else if (Opc == PPC::FMRS) {
if (OpNum == 0) { // move - store
unsigned InReg = MI-getOperand(1).getReg();
- return addFrameReference(BuildMI(TII, PPC::STFS,
+ NewMI = addFrameReference(BuildMI(TII, PPC::STFS,
3).addReg(InReg), FrameIndex);
} else { // move - load
unsigned OutReg = MI-getOperand(0).getReg();
- return addFrameReference(BuildMI(TII, PPC::LFS, 2, OutReg), FrameIndex);
+ NewMI = addFrameReference(BuildMI(TII, PPC::LFS, 2, OutReg), FrameIndex);
}
}
- return 0;
+
+ if (NewMI)
+NewMI-copyKillDeadInfo(MI);
+ return NewMI;
}
//===--===//
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrInfo.cpp PPCRegisterInfo.cpp PPCRegisterInfo.h
Changes in directory llvm/lib/Target/PowerPC:
PPCInstrInfo.cpp updated: 1.29 - 1.30
PPCRegisterInfo.cpp updated: 1.80 - 1.81
PPCRegisterInfo.h updated: 1.16 - 1.17
---
Log message:
Matches MachineInstr changes.
---
Diffs of the changes: (+14 -12)
PPCInstrInfo.cpp|2 +-
PPCRegisterInfo.cpp | 21 +++--
PPCRegisterInfo.h |3 ++-
3 files changed, 14 insertions(+), 12 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:1.29
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:1.30
--- llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:1.29 Sat Oct 28 12:35:02 2006
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.cppMon Nov 13 17:36:35 2006
@@ -20,7 +20,7 @@
PPCInstrInfo::PPCInstrInfo(PPCTargetMachine tm)
: TargetInstrInfo(PPCInsts, sizeof(PPCInsts)/sizeof(PPCInsts[0])), TM(tm),
-RI(*TM.getSubtargetImpl()) {}
+RI(*TM.getSubtargetImpl(), *this) {}
/// getPointerRegClass - Return the register class to use to hold pointers.
/// This is used for addressing modes.
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.80
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.81
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.80Sat Nov 11 16:22:07 2006
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Mon Nov 13 17:36:35 2006
@@ -80,9 +80,10 @@
}
}
-PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget ST)
+PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget ST,
+ const TargetInstrInfo tii)
: PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
-Subtarget(ST) {
+Subtarget(ST), TII(tii) {
ImmToIdxMap[PPC::LD] = PPC::LDX;ImmToIdxMap[PPC::STD] = PPC::STDX;
ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
@@ -322,39 +323,39 @@
MI-getOperand(1).getReg() == MI-getOperand(2).getReg())) {
if (OpNum == 0) { // move - store
unsigned InReg = MI-getOperand(1).getReg();
- return addFrameReference(BuildMI(PPC::STW,
+ return addFrameReference(BuildMI(TII, PPC::STW,
3).addReg(InReg), FrameIndex);
} else { // move - load
unsigned OutReg = MI-getOperand(0).getReg();
- return addFrameReference(BuildMI(PPC::LWZ, 2, OutReg), FrameIndex);
+ return addFrameReference(BuildMI(TII, PPC::LWZ, 2, OutReg), FrameIndex);
}
} else if ((Opc == PPC::OR8
MI-getOperand(1).getReg() == MI-getOperand(2).getReg())) {
if (OpNum == 0) { // move - store
unsigned InReg = MI-getOperand(1).getReg();
- return addFrameReference(BuildMI(PPC::STD,
+ return addFrameReference(BuildMI(TII, PPC::STD,
3).addReg(InReg), FrameIndex);
} else { // move - load
unsigned OutReg = MI-getOperand(0).getReg();
- return addFrameReference(BuildMI(PPC::LD, 2, OutReg), FrameIndex);
+ return addFrameReference(BuildMI(TII, PPC::LD, 2, OutReg), FrameIndex);
}
} else if (Opc == PPC::FMRD) {
if (OpNum == 0) { // move - store
unsigned InReg = MI-getOperand(1).getReg();
- return addFrameReference(BuildMI(PPC::STFD,
+ return addFrameReference(BuildMI(TII, PPC::STFD,
3).addReg(InReg), FrameIndex);
} else { // move - load
unsigned OutReg = MI-getOperand(0).getReg();
- return addFrameReference(BuildMI(PPC::LFD, 2, OutReg), FrameIndex);
+ return addFrameReference(BuildMI(TII, PPC::LFD, 2, OutReg), FrameIndex);
}
} else if (Opc == PPC::FMRS) {
if (OpNum == 0) { // move - store
unsigned InReg = MI-getOperand(1).getReg();
- return addFrameReference(BuildMI(PPC::STFS,
+ return addFrameReference(BuildMI(TII, PPC::STFS,
3).addReg(InReg), FrameIndex);
} else { // move - load
unsigned OutReg = MI-getOperand(0).getReg();
- return addFrameReference(BuildMI(PPC::LFS, 2, OutReg), FrameIndex);
+ return addFrameReference(BuildMI(TII, PPC::LFS, 2, OutReg), FrameIndex);
}
}
return 0;
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.h
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.h:1.16
llvm/lib/Target/PowerPC/PPCRegisterInfo.h:1.17
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.h:1.16 Mon Jul 10 19:48:23 2006
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.h Mon Nov 13 17:36:35 2006
@@ -25,8 +25,9 @@
class PPCRegisterInfo : public PPCGenRegisterInfo {
std::mapunsigned, unsigned ImmToIdxMap;
const PPCSubtarget Subtarget;
+ const TargetInstrInfo TII;
public:
- PPCRegisterInfo(const PPCSubtarget SubTarget);
+ PPCRegisterInfo(const PPCSubtarget SubTarget, const TargetInstrInfo tii);
/// getRegisterNumbering - Given the enum value for some register,
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrInfo.cpp PPCRegisterInfo.cpp PPCRegisterInfo.h
Changes in directory llvm/lib/Target/PowerPC:
PPCInstrInfo.cpp updated: 1.22 - 1.23
PPCRegisterInfo.cpp updated: 1.71 - 1.72
PPCRegisterInfo.h updated: 1.15 - 1.16
---
Log message:
In 64-bit mode, 64-bit GPRs are callee saved, not 32-bit ones.
---
Diffs of the changes: (+99 -62)
PPCInstrInfo.cpp|3 -
PPCRegisterInfo.cpp | 153 +++-
PPCRegisterInfo.h |5 +
3 files changed, 99 insertions(+), 62 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:1.22
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:1.23
--- llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:1.22 Tue Jun 20 18:18:58 2006
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.cppMon Jul 10 19:48:23 2006
@@ -19,7 +19,8 @@
using namespace llvm;
PPCInstrInfo::PPCInstrInfo(PPCTargetMachine tm)
- : TargetInstrInfo(PPCInsts, sizeof(PPCInsts)/sizeof(PPCInsts[0])), TM(tm) {}
+ : TargetInstrInfo(PPCInsts, sizeof(PPCInsts)/sizeof(PPCInsts[0])), TM(tm),
+RI(*TM.getSubtargetImpl()) {}
/// getPointerRegClass - Return the register class to use to hold pointers.
/// This is used for addressing modes.
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.71
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.72
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.71Tue Jun 27 13:55:49 2006
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Mon Jul 10 19:48:23 2006
@@ -15,6 +15,7 @@
#include PPC.h
#include PPCInstrBuilder.h
#include PPCRegisterInfo.h
+#include PPCSubtarget.h
#include llvm/Constants.h
#include llvm/Type.h
#include llvm/CodeGen/ValueTypes.h
@@ -78,8 +79,9 @@
}
}
-PPCRegisterInfo::PPCRegisterInfo()
- : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP) {
+PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget ST)
+ : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
+Subtarget(ST) {
ImmToIdxMap[PPC::LD] = PPC::LDX;ImmToIdxMap[PPC::STD] = PPC::STDX;
ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
@@ -207,70 +209,103 @@
}
const unsigned* PPCRegisterInfo::getCalleeSaveRegs() const {
- static const unsigned CalleeSaveRegs[] = {
-PPC::R1, PPC::R13,
-PPC::R14, PPC::R15,
-PPC::R16, PPC::R17,
-PPC::R18, PPC::R19,
-PPC::R20, PPC::R21,
-PPC::R22, PPC::R23,
-PPC::R24, PPC::R25,
-PPC::R26, PPC::R27,
-PPC::R28, PPC::R29,
-PPC::R30, PPC::R31,
-PPC::F14, PPC::F15,
-PPC::F16, PPC::F17,
-PPC::F18, PPC::F19,
-PPC::F20, PPC::F21,
-PPC::F22, PPC::F23,
-PPC::F24, PPC::F25,
-PPC::F26, PPC::F27,
-PPC::F28, PPC::F29,
+ // 32-bit Darwin calling convention.
+ static const unsigned Darwin32_CalleeSaveRegs[] = {
+PPC::R1 , PPC::R13, PPC::R14, PPC::R15,
+PPC::R16, PPC::R17, PPC::R18, PPC::R19,
+PPC::R20, PPC::R21, PPC::R22, PPC::R23,
+PPC::R24, PPC::R25, PPC::R26, PPC::R27,
+PPC::R28, PPC::R29, PPC::R30, PPC::R31,
+
+PPC::F14, PPC::F15, PPC::F16, PPC::F17,
+PPC::F18, PPC::F19, PPC::F20, PPC::F21,
+PPC::F22, PPC::F23, PPC::F24, PPC::F25,
+PPC::F26, PPC::F27, PPC::F28, PPC::F29,
PPC::F30, PPC::F31,
-PPC::CR2, PPC::CR3,
-PPC::CR4, PPC::V20,
-PPC::V21, PPC::V22,
-PPC::V23, PPC::V24,
-PPC::V25, PPC::V26,
-PPC::V27, PPC::V28,
-PPC::V29, PPC::V30,
-PPC::V31, PPC::LR, 0
+
+PPC::CR2, PPC::CR3, PPC::CR4,
+PPC::V20, PPC::V21, PPC::V22, PPC::V23,
+PPC::V24, PPC::V25, PPC::V26, PPC::V27,
+PPC::V28, PPC::V29, PPC::V30, PPC::V31,
+
+PPC::LR, 0
};
- return CalleeSaveRegs;
+ // 64-bit Darwin calling convention.
+ static const unsigned Darwin64_CalleeSaveRegs[] = {
+PPC::X1 , PPC::X13, PPC::X14, PPC::X15,
+PPC::X16, PPC::X17, PPC::X18, PPC::X19,
+PPC::X20, PPC::X21, PPC::X22, PPC::X23,
+PPC::X24, PPC::X25, PPC::X26, PPC::X27,
+PPC::X28, PPC::X29, PPC::X30, PPC::X31,
+
+PPC::F14, PPC::F15, PPC::F16, PPC::F17,
+PPC::F18, PPC::F19, PPC::F20, PPC::F21,
+PPC::F22, PPC::F23, PPC::F24, PPC::F25,
+PPC::F26, PPC::F27, PPC::F28, PPC::F29,
+PPC::F30, PPC::F31,
+
+PPC::CR2, PPC::CR3, PPC::CR4,
+PPC::V20, PPC::V21, PPC::V22, PPC::V23,
+PPC::V24, PPC::V25, PPC::V26, PPC::V27,
+PPC::V28, PPC::V29, PPC::V30, PPC::V31,
+
+PPC::LR, 0
+ };
+
+ return Subtarget.isPPC64() ? Darwin64_CalleeSaveRegs :
+ Darwin32_CalleeSaveRegs;
}
const TargetRegisterClass* const*
PPCRegisterInfo::getCalleeSaveRegClasses() const {
- static const TargetRegisterClass * const CalleeSaveRegClasses[] = {
-PPC::GPRCRegClass, PPC::GPRCRegClass,
-PPC::GPRCRegClass, PPC::GPRCRegClass,
-PPC::GPRCRegClass, PPC::GPRCRegClass,
-PPC::GPRCRegClass, PPC::GPRCRegClass,
-PPC::GPRCRegClass, PPC::GPRCRegClass,
-
[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrInfo.cpp PPCRegisterInfo.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCInstrInfo.cpp updated: 1.18 - 1.19
PPCRegisterInfo.cpp updated: 1.46 - 1.47
---
Log message:
teach the ppc backend how to spill/reload vector regs
---
Diffs of the changes: (+21 -1)
PPCInstrInfo.cpp|2 +-
PPCRegisterInfo.cpp | 20
2 files changed, 21 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:1.18
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:1.19
--- llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:1.18 Thu Mar 16 14:03:58 2006
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.cppThu Mar 16 16:24:02 2006
@@ -80,7 +80,7 @@
}
unsigned PPCInstrInfo::isLoadFromStackSlot(MachineInstr *MI,
- int FrameIndex) const {
+ int FrameIndex) const {
switch (MI-getOpcode()) {
default: break;
case PPC::LD:
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.46
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.47
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.46Thu Mar 16 15:31:45 2006
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Thu Mar 16 16:24:02 2006
@@ -50,6 +50,9 @@
unsigned SrcReg, int FrameIdx,
const TargetRegisterClass *RC) const {
if (SrcReg == PPC::LR) {
+// FIXME: this spills LR immediately to memory in one step. To do this, we
+// use R11, which we know cannot be used in the prolog/epilog. This is a
+// hack.
BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11);
addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11),
FrameIdx);
} else if (RC == PPC::CRRCRegisterClass) {
@@ -63,6 +66,15 @@
addFrameReference(BuildMI(MBB, MI, PPC::STFD, 3).addReg(SrcReg),FrameIdx);
} else if (RC == PPC::F4RCRegisterClass) {
addFrameReference(BuildMI(MBB, MI, PPC::STFS, 3).addReg(SrcReg),FrameIdx);
+ } else if (RC == PPC::VRRCRegisterClass) {
+// We don't have indexed addressing for vector loads. Emit:
+// R11 = ADDI FI#
+// Dest = LVX R0, R11
+//
+// FIXME: We use R0 here, because it isn't available for RA.
+addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0);
+BuildMI(MBB, MI, PPC::STVX, 3)
+ .addReg(SrcReg).addReg(PPC::R0).addReg(PPC::R0);
} else {
assert(0 Unknown regclass!);
abort();
@@ -88,6 +100,14 @@
addFrameReference(BuildMI(MBB, MI, PPC::LFD, 2, DestReg), FrameIdx);
} else if (RC == PPC::F4RCRegisterClass) {
addFrameReference(BuildMI(MBB, MI, PPC::LFS, 2, DestReg), FrameIdx);
+ } else if (RC == PPC::VRRCRegisterClass) {
+// We don't have indexed addressing for vector loads. Emit:
+// R11 = ADDI FI#
+// Dest = LVX R0, R11
+//
+// FIXME: We use R0 here, because it isn't available for RA.
+addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0);
+BuildMI(MBB, MI, PPC::LVX, 2, DestReg).addReg(PPC::R0).addReg(PPC::R0);
} else {
assert(0 Unknown regclass!);
abort();
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