[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.cpp X86InstrMMX.td
Changes in directory llvm/lib/Target/X86:
X86InstrInfo.cpp updated: 1.81 - 1.82
X86InstrMMX.td updated: 1.28 - 1.29
---
Log message:
Add FEMMS and ADDQ. Renamed MMX recipes to prepend the MMX_ to them.
---
Diffs of the changes: (+85 -69)
X86InstrInfo.cpp | 10 +--
X86InstrMMX.td | 144 ++-
2 files changed, 85 insertions(+), 69 deletions(-)
Index: llvm/lib/Target/X86/X86InstrInfo.cpp
diff -u llvm/lib/Target/X86/X86InstrInfo.cpp:1.81
llvm/lib/Target/X86/X86InstrInfo.cpp:1.82
--- llvm/lib/Target/X86/X86InstrInfo.cpp:1.81 Wed Mar 28 13:12:31 2007
+++ llvm/lib/Target/X86/X86InstrInfo.cppTue Apr 3 01:00:37 2007
@@ -38,7 +38,7 @@
oc == X86::MOVAPSrr || oc == X86::MOVAPDrr ||
oc == X86::MOVSS2PSrr || oc == X86::MOVSD2PDrr ||
oc == X86::MOVPS2SSrr || oc == X86::MOVPD2SDrr ||
- oc == X86::MOVD64rr || oc == X86::MOVQ64rr) {
+ oc == X86::MMX_MOVD64rr || oc == X86::MMX_MOVQ64rr) {
assert(MI.getNumOperands() == 2
MI.getOperand(0).isRegister()
MI.getOperand(1).isRegister()
@@ -65,8 +65,8 @@
case X86::MOVSDrm:
case X86::MOVAPSrm:
case X86::MOVAPDrm:
- case X86::MOVD64rm:
- case X86::MOVQ64rm:
+ case X86::MMX_MOVD64rm:
+ case X86::MMX_MOVQ64rm:
if (MI-getOperand(1).isFrameIndex() MI-getOperand(2).isImmediate()
MI-getOperand(3).isRegister() MI-getOperand(4).isImmediate()
MI-getOperand(2).getImmedValue() == 1
@@ -95,8 +95,8 @@
case X86::MOVSDmr:
case X86::MOVAPSmr:
case X86::MOVAPDmr:
- case X86::MOVD64mr:
- case X86::MOVQ64mr:
+ case X86::MMX_MOVD64mr:
+ case X86::MMX_MOVQ64mr:
if (MI-getOperand(0).isFrameIndex() MI-getOperand(1).isImmediate()
MI-getOperand(2).isRegister() MI-getOperand(3).isImmediate()
MI-getOperand(1).getImmedValue() == 1
Index: llvm/lib/Target/X86/X86InstrMMX.td
diff -u llvm/lib/Target/X86/X86InstrMMX.td:1.28
llvm/lib/Target/X86/X86InstrMMX.td:1.29
--- llvm/lib/Target/X86/X86InstrMMX.td:1.28 Tue Mar 27 19:57:11 2007
+++ llvm/lib/Target/X86/X86InstrMMX.td Tue Apr 3 01:00:37 2007
@@ -118,10 +118,11 @@
}
//===--===//
-// MMX EMMS Instruction
+// MMX EMMS FEMMS Instructions
//===--===//
-def MMX_EMMS : MMXI0x77, RawFrm, (ops), emms, [(int_x86_mmx_emms)];
+def MMX_EMMS : MMXI0x77, RawFrm, (ops), emms, [(int_x86_mmx_emms)];
+def MMX_FEMMS : MMXI0x0E, RawFrm, (ops), femms, [(int_x86_mmx_femms)];
//===--===//
// MMX Scalar Instructions
@@ -130,9 +131,10 @@
// Arithmetic Instructions
// -- Addition
-defm MMX_PADDB : MMXI_binop_rm0xFC, paddb, add, v8i8, 1;
+defm MMX_PADDB : MMXI_binop_rm0xFC, paddb, add, v8i8, 1;
defm MMX_PADDW : MMXI_binop_rm0xFD, paddw, add, v4i16, 1;
defm MMX_PADDD : MMXI_binop_rm0xFE, paddd, add, v2i32, 1;
+defm MMX_PADDQ : MMXI_binop_rm0xD4, paddq, add, v1i64, 1;
defm MMX_PADDSB : MMXI_binop_rm_int0xEC, paddsb , int_x86_mmx_padds_b, 1;
defm MMX_PADDSW : MMXI_binop_rm_int0xED, paddsw , int_x86_mmx_padds_w, 1;
@@ -309,45 +311,52 @@
defm MMX_PACKUSWB : MMXI_binop_rm_int0x67, packuswb, int_x86_mmx_packuswb;
// Data Transfer Instructions
-def MOVD64rr : MMXI0x6E, MRMSrcReg, (ops VR64:$dst, GR32:$src),
-movd {$src, $dst|$dst, $src}, [];
-def MOVD64rm : MMXI0x6E, MRMSrcMem, (ops VR64:$dst, i32mem:$src),
-movd {$src, $dst|$dst, $src}, [];
-def MOVD64mr : MMXI0x7E, MRMDestMem, (ops i32mem:$dst, VR64:$src),
-movd {$src, $dst|$dst, $src}, [];
-
-def MOVQ64rr : MMXI0x6F, MRMSrcReg, (ops VR64:$dst, VR64:$src),
-movq {$src, $dst|$dst, $src}, [];
-def MOVQ64rm : MMXI0x6F, MRMSrcMem, (ops VR64:$dst, i64mem:$src),
-movq {$src, $dst|$dst, $src},
-[(set VR64:$dst, (load_mmx addr:$src))];
-def MOVQ64mr : MMXI0x7F, MRMDestMem, (ops i64mem:$dst, VR64:$src),
-movq {$src, $dst|$dst, $src},
-[(store (v1i64 VR64:$src), addr:$dst)];
+def MMX_MOVD64rr : MMXI0x6E, MRMSrcReg, (ops VR64:$dst, GR32:$src),
+movd {$src, $dst|$dst, $src}, [];
+def MMX_MOVD64rm : MMXI0x6E, MRMSrcMem, (ops VR64:$dst, i32mem:$src),
+movd {$src, $dst|$dst, $src}, [];
+def MMX_MOVD64mr : MMXI0x7E, MRMDestMem, (ops i32mem:$dst, VR64:$src),
+movd {$src, $dst|$dst, $src}, [];
+
+def MMX_MOVQ64rr : MMXI0x6F, MRMSrcReg, (ops VR64:$dst, VR64:$src),
+movq {$src, $dst|$dst, $src}, [];
+def MMX_MOVQ64rm : MMXI0x6F, MRMSrcMem, (ops VR64:$dst, i64mem:$src),
+movq {$src, $dst|$dst, $src},
+[(set VR64:$dst, (load_mmx addr:$src))];
+def MMX_MOVQ64mr : MMXI0x7F, MRMDestMem, (ops i64mem:$dst,
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.cpp X86InstrMMX.td
Changes in directory llvm/lib/Target/X86:
X86InstrInfo.cpp updated: 1.82 - 1.83
X86InstrMMX.td updated: 1.29 - 1.30
---
Log message:
Adding more MMX instructions.
---
Diffs of the changes: (+128 -64)
X86InstrInfo.cpp |4 -
X86InstrMMX.td | 188 ---
2 files changed, 128 insertions(+), 64 deletions(-)
Index: llvm/lib/Target/X86/X86InstrInfo.cpp
diff -u llvm/lib/Target/X86/X86InstrInfo.cpp:1.82
llvm/lib/Target/X86/X86InstrInfo.cpp:1.83
--- llvm/lib/Target/X86/X86InstrInfo.cpp:1.82 Tue Apr 3 01:00:37 2007
+++ llvm/lib/Target/X86/X86InstrInfo.cppTue Apr 3 18:48:32 2007
@@ -38,7 +38,8 @@
oc == X86::MOVAPSrr || oc == X86::MOVAPDrr ||
oc == X86::MOVSS2PSrr || oc == X86::MOVSD2PDrr ||
oc == X86::MOVPS2SSrr || oc == X86::MOVPD2SDrr ||
- oc == X86::MMX_MOVD64rr || oc == X86::MMX_MOVQ64rr) {
+ oc == X86::MMX_MOVD64rr || oc == X86::MMX_MOVQ64rr ||
+ oc == X86::MMX_MOVDQ2Qrr || oc == X86::MMX_MOVQ2DQrr) {
assert(MI.getNumOperands() == 2
MI.getOperand(0).isRegister()
MI.getOperand(1).isRegister()
@@ -97,6 +98,7 @@
case X86::MOVAPDmr:
case X86::MMX_MOVD64mr:
case X86::MMX_MOVQ64mr:
+ case X86::MMX_MOVNTQmr:
if (MI-getOperand(0).isFrameIndex() MI-getOperand(1).isImmediate()
MI-getOperand(2).isRegister() MI-getOperand(3).isImmediate()
MI-getOperand(1).getImmedValue() == 1
Index: llvm/lib/Target/X86/X86InstrMMX.td
diff -u llvm/lib/Target/X86/X86InstrMMX.td:1.29
llvm/lib/Target/X86/X86InstrMMX.td:1.30
--- llvm/lib/Target/X86/X86InstrMMX.td:1.29 Tue Apr 3 01:00:37 2007
+++ llvm/lib/Target/X86/X86InstrMMX.td Tue Apr 3 18:48:32 2007
@@ -20,12 +20,19 @@
// MMXI - MMX instructions with TB prefix.
// MMX2I - MMX / SSE2 instructions with TB and OpSize prefixes.
// MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
+// MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
+// MMXID - MMX instructions with XD prefix.
+// MMXIS - MMX instructions with XS prefix.
class MMXIbits8 o, Format F, dag ops, string asm, listdag pattern
: Io, F, ops, asm, pattern, TB, Requires[HasMMX];
class MMX2Ibits8 o, Format F, dag ops, string asm, listdag pattern
: Io, F, ops, asm, pattern, TB, OpSize, Requires[HasMMX];
class MMXIi8bits8 o, Format F, dag ops, string asm, listdag pattern
: Ii8o, F, ops, asm, pattern, TB, Requires[HasMMX];
+class MMXIDbits8 o, Format F, dag ops, string asm, listdag pattern
+ : Ii8o, F, ops, asm, pattern, XD, Requires[HasMMX];
+class MMXISbits8 o, Format F, dag ops, string asm, listdag pattern
+ : Ii8o, F, ops, asm, pattern, XS, Requires[HasMMX];
// Some 'special' instructions
def IMPLICIT_DEF_VR64 : I0, Pseudo, (ops VR64:$dst),
@@ -51,6 +58,18 @@
def bc_v1i64 : PatFrag(ops node:$in), (v1i64 (bitconvert node:$in));
//===--===//
+// MMX Masks
+//===--===//
+
+def MMX_UNPCKH_shuffle_mask : PatLeaf(build_vector), [{
+ return X86::isUNPCKHMask(N);
+}];
+
+def MMX_UNPCKL_shuffle_mask : PatLeaf(build_vector), [{
+ return X86::isUNPCKLMask(N);
+}];
+
+//===--===//
// MMX Multiclasses
//===--===//
@@ -128,6 +147,35 @@
// MMX Scalar Instructions
//===--===//
+// Data Transfer Instructions
+def MMX_MOVD64rr : MMXI0x6E, MRMSrcReg, (ops VR64:$dst, GR32:$src),
+movd {$src, $dst|$dst, $src}, [];
+def MMX_MOVD64rm : MMXI0x6E, MRMSrcMem, (ops VR64:$dst, i32mem:$src),
+movd {$src, $dst|$dst, $src}, [];
+def MMX_MOVD64mr : MMXI0x7E, MRMDestMem, (ops i32mem:$dst, VR64:$src),
+movd {$src, $dst|$dst, $src}, [];
+
+def MMX_MOVQ64rr : MMXI0x6F, MRMSrcReg, (ops VR64:$dst, VR64:$src),
+movq {$src, $dst|$dst, $src}, [];
+def MMX_MOVQ64rm : MMXI0x6F, MRMSrcMem, (ops VR64:$dst, i64mem:$src),
+movq {$src, $dst|$dst, $src},
+[(set VR64:$dst, (load_mmx addr:$src))];
+def MMX_MOVQ64mr : MMXI0x7F, MRMDestMem, (ops i64mem:$dst, VR64:$src),
+movq {$src, $dst|$dst, $src},
+[(store (v1i64 VR64:$src), addr:$dst)];
+
+def MMX_MOVDQ2Qrr : MMXID0xD6, MRMDestMem, (ops VR64:$dst, VR128:$src),
+ movdq2q {$src, $dst|$dst, $src},
+ [(store (i64 (vector_extract (v2i64 VR128:$src),
+(iPTR 0))), VR64:$dst)];
+def MMX_MOVQ2DQrr : MMXIS0xD6, MRMDestMem, (ops VR128:$dst, VR64:$src),
+ movq2dq {$src, $dst|$dst, $src},
+ [(store (v1i64
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.cpp X86InstrMMX.td X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrInfo.cpp updated: 1.45 - 1.46
X86InstrMMX.td updated: 1.4 - 1.5
X86InstrSSE.td updated: 1.10 - 1.11
---
Log message:
- Remove scalar to vector pseudo ops. They are just wrong.
- Handle FR32 to VR128:v4f32 and FR64 to VR128:v2f64 with aliases of MOVAPS
and MOVAPD. Mark them as move instructions and *hope* they will be deleted.
---
Diffs of the changes: (+17 -56)
X86InstrInfo.cpp |3 ++-
X86InstrMMX.td | 19 ---
X86InstrSSE.td | 51 +++
3 files changed, 17 insertions(+), 56 deletions(-)
Index: llvm/lib/Target/X86/X86InstrInfo.cpp
diff -u llvm/lib/Target/X86/X86InstrInfo.cpp:1.45
llvm/lib/Target/X86/X86InstrInfo.cpp:1.46
--- llvm/lib/Target/X86/X86InstrInfo.cpp:1.45 Thu Feb 16 16:45:16 2006
+++ llvm/lib/Target/X86/X86InstrInfo.cppTue Mar 21 01:09:35 2006
@@ -30,7 +30,8 @@
if (oc == X86::MOV8rr || oc == X86::MOV16rr || oc == X86::MOV32rr ||
oc == X86::FpMOV || oc == X86::MOVSSrr || oc == X86::MOVSDrr ||
oc == X86::FsMOVAPSrr || oc == X86::FsMOVAPDrr ||
- oc == X86::MOVAPSrr || oc == X86::MOVAPDrr) {
+ oc == X86::MOVAPSrr || oc == X86::MOVAPDrr ||
+ oc == X86::FR32ToV4F32 || oc == X86::FR64ToV2F64) {
assert(MI.getNumOperands() == 2
MI.getOperand(0).isRegister()
MI.getOperand(1).isRegister()
Index: llvm/lib/Target/X86/X86InstrMMX.td
diff -u llvm/lib/Target/X86/X86InstrMMX.td:1.4
llvm/lib/Target/X86/X86InstrMMX.td:1.5
--- llvm/lib/Target/X86/X86InstrMMX.td:1.4 Mon Mar 20 18:33:35 2006
+++ llvm/lib/Target/X86/X86InstrMMX.td Tue Mar 21 01:09:35 2006
@@ -22,24 +22,6 @@
def : Pat(v4i16 (undef)), (IMPLICIT_DEF_VR64), Requires[HasMMX];
def : Pat(v2i32 (undef)), (IMPLICIT_DEF_VR64), Requires[HasMMX];
-def SCALAR_TO_VECTOR_V8I8 : I0, Pseudo, (ops VR64:$dst, R8:$src),
- #SCALAR_TO_VECTOR $src,
- [(set VR64:$dst,
-(v8i8 (scalar_to_vector R8:$src)))],
-Requires[HasMMX];
-
-def SCALAR_TO_VECTOR_V4I16 : I0, Pseudo, (ops VR64:$dst, R16:$src),
- #SCALAR_TO_VECTOR $src,
- [(set VR64:$dst,
- (v4i16 (scalar_to_vector R16:$src)))],
- Requires[HasMMX];
-
-def SCALAR_TO_VECTOR_V2I32 : I0, Pseudo, (ops VR64:$dst, R32:$src),
- #SCALAR_TO_VECTOR $src,
- [(set VR64:$dst,
- (v2i32 (scalar_to_vector R32:$src)))],
- Requires[HasMMX];
-
// Move Instructions
def MOVD64rr : I0x6E, MRMSrcReg, (ops VR64:$dst, R32:$src),
movd {$src, $dst|$dst, $src}, [], TB,
@@ -60,4 +42,3 @@
def MOVQ64mr : I0x7F, MRMDestMem, (ops i64mem:$dst, VR64:$src),
movq {$src, $dst|$dst, $src}, [], TB,
Requires[HasMMX];
-
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.10
llvm/lib/Target/X86/X86InstrSSE.td:1.11
--- llvm/lib/Target/X86/X86InstrSSE.td:1.10 Mon Mar 20 18:33:35 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Tue Mar 21 01:09:35 2006
@@ -353,42 +353,6 @@
def : Pat(v4i32 (undef)), (IMPLICIT_DEF_VR128), Requires[HasSSE2];
def : Pat(v2i64 (undef)), (IMPLICIT_DEF_VR128), Requires[HasSSE2];
-def SCALAR_TO_VECTOR_V4F32 : I0, Pseudo, (ops VR128:$dst, FR32:$src),
- #SCALAR_TO_VECTOR $src,
- [(set VR128:$dst,
- (v4f32 (scalar_to_vector FR32:$src)))],
- Requires[HasSSE1];
-
-def SCALAR_TO_VECTOR_V2F64 : I0, Pseudo, (ops VR128:$dst, FR64:$src),
- #SCALAR_TO_VECTOR $src,
- [(set VR128:$dst,
- (v2f64 (scalar_to_vector FR64:$src)))],
- Requires[HasSSE2];
-
-def SCALAR_TO_VECTOR_V16I8 : I0, Pseudo, (ops VR128:$dst, R8:$src),
- #SCALAR_TO_VECTOR $src,
- [(set VR128:$dst,
- (v16i8 (scalar_to_vector R8:$src)))],
- Requires[HasSSE2];
-
-def SCALAR_TO_VECTOR_V8I16 : I0, Pseudo, (ops VR128:$dst, R16:$src),
- #SCALAR_TO_VECTOR $src,
- [(set VR128:$dst,
- (v8i16 (scalar_to_vector R16:$src)))],
- Requires[HasSSE2];
-
-def SCALAR_TO_VECTOR_V4I32 : I0, Pseudo, (ops VR128:$dst, R32:$src),
- #SCALAR_TO_VECTOR $src,
- [(set VR128:$dst,
- (v4i32 (scalar_to_vector R32:$src)))],
- Requires[HasSSE2];
-
-def
