[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86: X86InstrSSE.td updated: 1.184 - 1.185 --- Log message: Fix loadv2i32 to be loadv4i32, though it isn't actually used anywhere yet. --- Diffs of the changes: (+1 -1) X86InstrSSE.td |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/X86/X86InstrSSE.td diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.184 llvm/lib/Target/X86/X86InstrSSE.td:1.185 --- llvm/lib/Target/X86/X86InstrSSE.td:1.184Mon Jun 18 20:48:05 2007 +++ llvm/lib/Target/X86/X86InstrSSE.td Mon Jun 25 10:19:03 2007 @@ -85,7 +85,7 @@ def loadv4f32: PatFrag(ops node:$ptr), (v4f32 (load node:$ptr)); def loadv2f64: PatFrag(ops node:$ptr), (v2f64 (load node:$ptr)); -def loadv2i32: PatFrag(ops node:$ptr), (v2i32 (load node:$ptr)); +def loadv4i32: PatFrag(ops node:$ptr), (v4i32 (load node:$ptr)); def loadv2i64: PatFrag(ops node:$ptr), (v2i64 (load node:$ptr)); def bc_v4f32 : PatFrag(ops node:$in), (v4f32 (bitconvert node:$in)); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.185 - 1.186
---
Log message:
Make minor adjustments to whitespace and comments to reduce differences
between SSE1 instructions and their respective SSE2 analogues.
---
Diffs of the changes: (+28 -25)
X86InstrSSE.td | 53 -
1 files changed, 28 insertions(+), 25 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.185
llvm/lib/Target/X86/X86InstrSSE.td:1.186
--- llvm/lib/Target/X86/X86InstrSSE.td:1.185Mon Jun 25 10:19:03 2007
+++ llvm/lib/Target/X86/X86InstrSSE.td Mon Jun 25 10:44:19 2007
@@ -392,7 +392,6 @@
// Alias bitwise logical operations using SSE logical ops on packed FP values.
let isTwoAddress = 1 in {
-
let isCommutable = 1 in {
def FsANDPSrr : PSI0x54, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
andps {$src2, $dst|$dst, $src2},
@@ -418,9 +417,11 @@
[(set FR32:$dst, (X86fxor FR32:$src1,
(X86loadpf32 addr:$src2)))];
-def FsANDNPSrr : PSI0x55, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
+def FsANDNPSrr : PSI0x55, MRMSrcReg,
+ (ops FR32:$dst, FR32:$src1, FR32:$src2),
andnps {$src2, $dst|$dst, $src2}, [];
-def FsANDNPSrm : PSI0x55, MRMSrcMem, (ops FR32:$dst, FR32:$src1,
f128mem:$src2),
+def FsANDNPSrm : PSI0x55, MRMSrcMem,
+ (ops FR32:$dst, FR32:$src1, f128mem:$src2),
andnps {$src2, $dst|$dst, $src2}, [];
}
@@ -440,8 +441,8 @@
bit Commutable = 0 {
// Scalar operation, reg+reg.
def SSrr : SSIopc, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
- !strconcat(OpcodeStr, ss {$src2, $dst|$dst, $src2}),
- [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))] {
+ !strconcat(OpcodeStr, ss {$src2, $dst|$dst, $src2}),
+ [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))] {
let isCommutable = Commutable;
}
@@ -498,20 +499,22 @@
[(int_x86_sse_storeu_ps addr:$dst, VR128:$src)];
let isTwoAddress = 1 in {
-let AddedComplexity = 20 in {
-def MOVLPSrm : PSI0x12, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
f64mem:$src2),
- movlps {$src2, $dst|$dst, $src2},
- [(set VR128:$dst,
- (v4f32 (vector_shuffle VR128:$src1,
- (bc_v4f32 (v2f64 (scalar_to_vector (loadf64
addr:$src2,
- MOVLP_shuffle_mask)))];
-def MOVHPSrm : PSI0x16, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
f64mem:$src2),
- movhps {$src2, $dst|$dst, $src2},
- [(set VR128:$dst,
- (v4f32 (vector_shuffle VR128:$src1,
- (bc_v4f32 (v2f64 (scalar_to_vector (loadf64
addr:$src2,
- MOVHP_shuffle_mask)))];
-} // AddedComplexity
+ let AddedComplexity = 20 in {
+def MOVLPSrm : PSI0x12, MRMSrcMem,
+ (ops VR128:$dst, VR128:$src1, f64mem:$src2),
+ movlps {$src2, $dst|$dst, $src2},
+ [(set VR128:$dst,
+ (v4f32 (vector_shuffle VR128:$src1,
+ (bc_v4f32 (v2f64 (scalar_to_vector (loadf64
addr:$src2,
+ MOVLP_shuffle_mask)))];
+def MOVHPSrm : PSI0x16, MRMSrcMem,
+ (ops VR128:$dst, VR128:$src1, f64mem:$src2),
+ movhps {$src2, $dst|$dst, $src2},
+ [(set VR128:$dst,
+ (v4f32 (vector_shuffle VR128:$src1,
+ (bc_v4f32 (v2f64 (scalar_to_vector (loadf64
addr:$src2,
+ MOVHP_shuffle_mask)))];
+ } // AddedComplexity
} // isTwoAddress
def MOVLPSmr : PSI0x13, MRMDestMem, (ops f64mem:$dst, VR128:$src),
@@ -955,7 +958,7 @@
comisd {$src2, $src1|$src1, $src2},
[(X86comi (v2f64 VR128:$src1), (load addr:$src2))];
-// Aliases of packed instructions for scalar use. These all have names that
+// Aliases of packed SSE2 instructions for scalar use. These all have names
that
// start with 'Fs'.
// Alias instructions that map fld0 to pxor for sse.
@@ -963,16 +966,16 @@
pxor $dst, $dst, [(set FR64:$dst, fp64imm0)],
Requires[HasSSE2], TB, OpSize;
-// Alias instructions to do FR64 reg-to-reg copy using movapd. Upper bits are
+// Alias instruction to do FR64 reg-to-reg copy using movapd. Upper bits are
// disregarded.
def FsMOVAPDrr : PDI0x28, MRMSrcReg, (ops FR64:$dst, FR64:$src),
- movapd {$src, $dst|$dst, $src}, [];
+ movapd {$src, $dst|$dst, $src}, [];
-// Alias instructions to load FR64 from f128mem using movapd. Upper bits are
+// Alias instruction
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.182 - 1.183
---
Log message:
Added missing patterns for UNPCKH* and PUNPCKH*.
---
Diffs of the changes: (+20 -0)
X86InstrSSE.td | 20
1 files changed, 20 insertions(+)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.182
llvm/lib/Target/X86/X86InstrSSE.td:1.183
--- llvm/lib/Target/X86/X86InstrSSE.td:1.182Wed May 2 18:11:52 2007
+++ llvm/lib/Target/X86/X86InstrSSE.td Thu May 17 13:44:37 2007
@@ -170,6 +170,10 @@
return X86::isUNPCKL_v_undef_Mask(N);
}];
+def UNPCKH_v_undef_shuffle_mask : PatLeaf(build_vector), [{
+ return X86::isUNPCKH_v_undef_Mask(N);
+}];
+
def PSHUFD_shuffle_mask : PatLeaf(build_vector), [{
return X86::isPSHUFDMask(N);
}], SHUFFLE_get_shuf_imm;
@@ -2266,6 +2270,22 @@
(PUNPCKLDQrr VR128:$src, VR128:$src), Requires[HasSSE1];
}
+// vector_shuffle v1, undef, 2, 2, 3, 3, ...
+let AddedComplexity = 10 in {
+def : Pat(v4f32 (vector_shuffle VR128:$src, (undef),
+ UNPCKH_v_undef_shuffle_mask)),
+ (UNPCKHPSrr VR128:$src, VR128:$src), Requires[HasSSE2];
+def : Pat(v16i8 (vector_shuffle VR128:$src, (undef),
+ UNPCKH_v_undef_shuffle_mask)),
+ (PUNPCKHBWrr VR128:$src, VR128:$src), Requires[HasSSE2];
+def : Pat(v8i16 (vector_shuffle VR128:$src, (undef),
+ UNPCKH_v_undef_shuffle_mask)),
+ (PUNPCKHWDrr VR128:$src, VR128:$src), Requires[HasSSE2];
+def : Pat(v4i32 (vector_shuffle VR128:$src, (undef),
+ UNPCKH_v_undef_shuffle_mask)),
+ (PUNPCKHDQrr VR128:$src, VR128:$src), Requires[HasSSE1];
+}
+
let AddedComplexity = 15 in {
// vector_shuffle v1, v2 0, 1, 4, 5 using MOVLHPS
def : Pat(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86: X86InstrSSE.td updated: 1.180 - 1.181 --- Log message: Fix the spelling of the prefetchnta instruction. --- Diffs of the changes: (+1 -1) X86InstrSSE.td |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/X86/X86InstrSSE.td diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.180 llvm/lib/Target/X86/X86InstrSSE.td:1.181 --- llvm/lib/Target/X86/X86InstrSSE.td:1.180Tue Apr 10 17:10:25 2007 +++ llvm/lib/Target/X86/X86InstrSSE.td Wed Apr 18 09:09:14 2007 @@ -1645,7 +1645,7 @@ def PREFETCHT0 : PSI0x18, MRM1m, (ops i8mem:$src), prefetcht0 $src, []; def PREFETCHT1 : PSI0x18, MRM2m, (ops i8mem:$src), prefetcht1 $src, []; def PREFETCHT2 : PSI0x18, MRM3m, (ops i8mem:$src), prefetcht2 $src, []; -def PREFETCHTNTA : PSI0x18, MRM0m, (ops i8mem:$src), prefetchtnta $src, []; +def PREFETCHNTA : PSI0x18, MRM0m, (ops i8mem:$src), prefetchnta $src, []; // Non-temporal stores def MOVNTPSmr : PSI0x2B, MRMDestMem, (ops i128mem:$dst, VR128:$src), ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.177 - 1.178
---
Log message:
add missing braces
---
Diffs of the changes: (+25 -25)
X86InstrSSE.td | 50 +-
1 files changed, 25 insertions(+), 25 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.177
llvm/lib/Target/X86/X86InstrSSE.td:1.178
--- llvm/lib/Target/X86/X86InstrSSE.td:1.177Mon Feb 19 18:39:09 2007
+++ llvm/lib/Target/X86/X86InstrSSE.td Sun Mar 4 00:13:52 2007
@@ -217,19 +217,19 @@
multiclass SS_IntUnarybits8 o, string OpcodeStr, Intrinsic IntId {
def r : SSIo, MRMSrcReg, (ops VR128:$dst, VR128:$src),
- !strconcat(OpcodeStr, {$src, $dst|$dst, $src),
+ !strconcat(OpcodeStr, {$src, $dst|$dst, $src}),
[(set VR128:$dst, (v4f32 (IntId VR128:$src)))];
def m : SSIo, MRMSrcMem, (ops VR128:$dst, ssmem:$src),
- !strconcat(OpcodeStr, {$src, $dst|$dst, $src),
+ !strconcat(OpcodeStr, {$src, $dst|$dst, $src}),
[(set VR128:$dst, (v4f32 (IntId sse_load_f32:$src)))];
}
multiclass SD_IntUnarybits8 o, string OpcodeStr, Intrinsic IntId {
def r : SDIo, MRMSrcReg, (ops VR128:$dst, VR128:$src),
- !strconcat(OpcodeStr, {$src, $dst|$dst, $src),
+ !strconcat(OpcodeStr, {$src, $dst|$dst, $src}),
[(set VR128:$dst, (v2f64 (IntId VR128:$src)))];
def m : SDIo, MRMSrcMem, (ops VR128:$dst, sdmem:$src),
- !strconcat(OpcodeStr, {$src, $dst|$dst, $src),
+ !strconcat(OpcodeStr, {$src, $dst|$dst, $src}),
[(set VR128:$dst, (v2f64 (IntId sse_load_f64:$src)))];
}
@@ -337,41 +337,41 @@
Intrinsic F64Int, bit Commutable = 0 {
// Scalar operation, reg+reg.
def SSrr : SSIopc, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
- !strconcat(OpcodeStr, ss {$src2, $dst|$dst, $src2),
+ !strconcat(OpcodeStr, ss {$src2, $dst|$dst, $src2}),
[(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))] {
let isCommutable = Commutable;
}
def SDrr : SDIopc, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
- !strconcat(OpcodeStr, sd {$src2, $dst|$dst, $src2),
+ !strconcat(OpcodeStr, sd {$src2, $dst|$dst, $src2}),
[(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))] {
let isCommutable = Commutable;
}
// Scalar operation, reg+mem.
def SSrm : SSIopc, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
- !strconcat(OpcodeStr, ss {$src2, $dst|$dst, $src2),
+ !strconcat(OpcodeStr, ss {$src2, $dst|$dst, $src2}),
[(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))];
def SDrm : SDIopc, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2),
- !strconcat(OpcodeStr, sd {$src2, $dst|$dst, $src2),
+ !strconcat(OpcodeStr, sd {$src2, $dst|$dst, $src2}),
[(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))];
// Vector intrinsic operation, reg+reg.
def SSrr_Int : SSIopc, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
VR128:$src2),
- !strconcat(OpcodeStr, ss {$src2, $dst|$dst, $src2),
+ !strconcat(OpcodeStr, ss {$src2, $dst|$dst, $src2}),
[(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))] {
let isCommutable = Commutable;
}
def SDrr_Int : SDIopc, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
VR128:$src2),
- !strconcat(OpcodeStr, sd {$src2, $dst|$dst, $src2),
+ !strconcat(OpcodeStr, sd {$src2, $dst|$dst, $src2}),
[(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))] {
let isCommutable = Commutable;
}
// Vector intrinsic operation, reg+mem.
def SSrm_Int : SSIopc, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
ssmem:$src2),
- !strconcat(OpcodeStr, ss {$src2, $dst|$dst, $src2),
+ !strconcat(OpcodeStr, ss {$src2, $dst|$dst, $src2}),
[(set VR128:$dst, (F32Int VR128:$src1,
sse_load_f32:$src2))];
def SDrm_Int : SDIopc, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
sdmem:$src2),
- !strconcat(OpcodeStr, sd {$src2, $dst|$dst, $src2),
+ !strconcat(OpcodeStr, sd {$src2, $dst|$dst, $src2}),
[(set VR128:$dst, (F64Int VR128:$src1,
sse_load_f64:$src2))];
}
@@ -937,21 +937,21 @@
SDNode OpNode, bit Commutable = 0 {
// Packed operation, reg+reg.
def PSrr : PSIopc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
- !strconcat(OpcodeStr, ps {$src2, $dst|$dst, $src2),
+ !strconcat(OpcodeStr, ps {$src2, $dst|$dst, $src2}),
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.176 - 1.177
---
Log message:
How the heck did I forget patterns for llvm.x86.sse2.cmp.sd?
---
Diffs of the changes: (+6 -2)
X86InstrSSE.td |8 ++--
1 files changed, 6 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.176
llvm/lib/Target/X86/X86InstrSSE.td:1.177
--- llvm/lib/Target/X86/X86InstrSSE.td:1.176Fri Jan 5 15:37:56 2007
+++ llvm/lib/Target/X86/X86InstrSSE.td Mon Feb 19 18:39:09 2007
@@ -544,10 +544,14 @@
(load addr:$src), imm:$cc))];
def Int_CMPSDrr : SDI0xC2, MRMSrcReg,
(ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
- cmp${cc}sd {$src, $dst|$dst, $src}, [];
+ cmp${cc}sd {$src, $dst|$dst, $src},
+ [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
+ VR128:$src, imm:$cc))];
def Int_CMPSDrm : SDI0xC2, MRMSrcMem,
(ops VR128:$dst, VR128:$src1, f64mem:$src, SSECC:$cc),
- cmp${cc}sd {$src, $dst|$dst, $src}, [];
+ cmp${cc}sd {$src, $dst|$dst, $src},
+ [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
+ (load addr:$src), imm:$cc))];
}
def Int_UCOMISSrr: PSI0x2E, MRMSrcReg, (ops VR128:$src1, VR128:$src2),
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.173 - 1.174
---
Log message:
- Rename MOVDSS2DIrr to MOVSS2DIrr for consistency sake.
- Add MOVDI2SSrm and MOVSS2DImr to fold load / store for i32 - f32 bit_convert
patterns.
---
Diffs of the changes: (+9 -3)
X86InstrSSE.td | 12 +---
1 files changed, 9 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.173
llvm/lib/Target/X86/X86InstrSSE.td:1.174
--- llvm/lib/Target/X86/X86InstrSSE.td:1.173Tue Dec 5 12:45:06 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Thu Dec 14 13:43:11 2006
@@ -1687,6 +1687,9 @@
movd {$src, $dst|$dst, $src},
[(set FR32:$dst, (bitconvert GR32:$src))];
+def MOVDI2SSrm : PDI0x6E, MRMSrcMem, (ops FR32:$dst, i32mem:$src),
+ movd {$src, $dst|$dst, $src},
+ [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))];
// SSE2 instructions with XS prefix
def MOVQI2PQIrm : I0x7E, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
@@ -1729,9 +1732,12 @@
[(store (i32 (vector_extract (v4i32 VR128:$src),
(iPTR 0))), addr:$dst)];
-def MOVDSS2DIrr : PDI0x7E, MRMDestReg, (ops GR32:$dst, FR32:$src),
- movd {$src, $dst|$dst, $src},
- [(set GR32:$dst, (bitconvert FR32:$src))];
+def MOVSS2DIrr : PDI0x7E, MRMDestReg, (ops GR32:$dst, FR32:$src),
+ movd {$src, $dst|$dst, $src},
+ [(set GR32:$dst, (bitconvert FR32:$src))];
+def MOVSS2DImr : PDI0x7E, MRMDestMem, (ops i32mem:$dst, FR32:$src),
+ movd {$src, $dst|$dst, $src},
+ [(store (i32 (bitconvert FR32:$src)), addr:$dst)];
// Move to lower bits of a VR128, leaving upper bits alone.
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td X86InstrX86-64.td X86RegisterInfo.cpp
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.171 - 1.172
X86InstrX86-64.td updated: 1.6 - 1.7
X86RegisterInfo.cpp updated: 1.178 - 1.179
---
Log message:
Correct instructions for moving data between GR64 and SSE registers; also
correct load i64 / store i64 from v2i64.
---
Diffs of the changes: (+34 -6)
X86InstrSSE.td | 11 ++-
X86InstrX86-64.td | 26 ++
X86RegisterInfo.cpp |3 ++-
3 files changed, 34 insertions(+), 6 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.171
llvm/lib/Target/X86/X86InstrSSE.td:1.172
--- llvm/lib/Target/X86/X86InstrSSE.td:1.171Fri Nov 10 15:43:37 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Thu Nov 16 17:33:25 2006
@@ -1682,17 +1682,18 @@
movd {$src, $dst|$dst, $src},
[(set VR128:$dst,
(v4i32 (scalar_to_vector (loadi32 addr:$src];
+
// SSE2 instructions with XS prefix
-def MOVQI2PQIrr : I0x7E, MRMSrcReg, (ops VR128:$dst, VR64:$src),
-movq {$src, $dst|$dst, $src},
-[(set VR128:$dst,
- (v2i64 (scalar_to_vector VR64:$src)))], XS,
- Requires[HasSSE2];
def MOVQI2PQIrm : I0x7E, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
movq {$src, $dst|$dst, $src},
[(set VR128:$dst,
(v2i64 (scalar_to_vector (loadi64 addr:$src], XS,
Requires[HasSSE2];
+def MOVPQI2QImr : PDI0xD6, MRMDestMem, (ops i64mem:$dst, VR128:$src),
+ movq {$src, $dst|$dst, $src},
+ [(store (i64 (vector_extract (v2i64 VR128:$src),
+(iPTR 0))), addr:$dst)];
+
// FIXME: may not be able to eliminate this movss with coalescing the src and
// dest register classes are different. We really want to write this pattern
// like this:
Index: llvm/lib/Target/X86/X86InstrX86-64.td
diff -u llvm/lib/Target/X86/X86InstrX86-64.td:1.6
llvm/lib/Target/X86/X86InstrX86-64.td:1.7
--- llvm/lib/Target/X86/X86InstrX86-64.td:1.6 Fri Nov 3 17:48:56 2006
+++ llvm/lib/Target/X86/X86InstrX86-64.td Thu Nov 16 17:33:25 2006
@@ -59,6 +59,8 @@
: SSIo, F, ops, asm, pattern, REX_W;
class RSDIbits8 o, Format F, dag ops, string asm, listdag pattern
: SDIo, F, ops, asm, pattern, REX_W;
+class RPDIbits8 o, Format F, dag ops, string asm, listdag pattern
+ : PDIo, F, ops, asm, pattern, REX_W;
//===--===//
// Pattern fragments...
@@ -1076,3 +1078,27 @@
def : Pat(store (or (shl (loadi64 addr:$dst), CL:$amt),
(srl GR64:$src2, (sub 64, CL:$amt))), addr:$dst),
(SHLD64mrCL addr:$dst, GR64:$src2);
+
+//===--===//
+// X86-64 SSE Instructions
+//===--===//
+
+// Move instructions...
+
+def MOV64toPQIrr : RPDI0x6E, MRMSrcReg, (ops VR128:$dst, GR64:$src),
+movq {$src, $dst|$dst, $src},
+[(set VR128:$dst,
+ (v2i64 (scalar_to_vector GR64:$src)))];
+def MOV64toPQIrm : RPDI0x6E, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
+movq {$src, $dst|$dst, $src},
+[(set VR128:$dst,
+ (v2i64 (scalar_to_vector (loadi64 addr:$src];
+
+def MOVPQIto64rr : RPDI0x7E, MRMDestReg, (ops GR64:$dst, VR128:$src),
+ movd {$src, $dst|$dst, $src},
+ [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
+ (iPTR 0)))];
+def MOVPQIto64mr : RPDI0x7E, MRMDestMem, (ops i64mem:$dst, VR128:$src),
+ movd {$src, $dst|$dst, $src},
+ [(store (i64 (vector_extract (v2i64 VR128:$src),
+ (iPTR 0))), addr:$dst)];
Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.178
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.179
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.178 Wed Nov 15 14:58:11 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Thu Nov 16 17:33:25 2006
@@ -509,6 +509,7 @@
{ X86::MOVAPDrr,X86::MOVAPDmr },
{ X86::MOVAPSrr,X86::MOVAPSmr },
{ X86::MOVPDI2DIrr, X86::MOVPDI2DImr },
+ { X86::MOVPQIto64rr,X86::MOVPQIto64mr },
{ X86::MOVPS2SSrr, X86::MOVPS2SSmr },
{ X86::MOVSDrr, X86::MOVSDmr },
{ X86::MOVSSrr, X86::MOVSSmr },
@@ -606,12 +607,12 @@
{ X86::MOV16rr, X86::MOV16rm },
{ X86::MOV32rr, X86::MOV32rm },
{ X86::MOV64rr, X86::MOV64rm },
+ { X86::MOV64toPQIrr,X86::MOV64toPQIrm },
{ X86::MOV8rr,
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86: X86InstrSSE.td updated: 1.167 - 1.168 --- Log message: Fix ldmxcsr JIT encoding. --- Diffs of the changes: (+4 -6) X86InstrSSE.td | 10 -- 1 files changed, 4 insertions(+), 6 deletions(-) Index: llvm/lib/Target/X86/X86InstrSSE.td diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.167 llvm/lib/Target/X86/X86InstrSSE.td:1.168 --- llvm/lib/Target/X86/X86InstrSSE.td:1.167Fri Oct 27 16:08:32 2006 +++ llvm/lib/Target/X86/X86InstrSSE.td Wed Nov 1 00:53:52 2006 @@ -1653,12 +1653,10 @@ mfence, [(int_x86_sse2_mfence)], TB, Requires[HasSSE2]; // MXCSR register -def LDMXCSR : I0xAE, MRM5m, (ops i32mem:$src), -ldmxcsr $src, -[(int_x86_sse_ldmxcsr addr:$src)], TB, Requires[HasSSE1]; -def STMXCSR : I0xAE, MRM3m, (ops i32mem:$dst), -stmxcsr $dst, -[(int_x86_sse_stmxcsr addr:$dst)], TB, Requires[HasSSE1]; +def LDMXCSR : PSI0xAE, MRM2m, (ops i32mem:$src), + ldmxcsr $src, [(int_x86_sse_ldmxcsr addr:$src)]; +def STMXCSR : PSI0xAE, MRM3m, (ops i32mem:$dst), + stmxcsr $dst, [(int_x86_sse_stmxcsr addr:$dst)]; // Thread synchronization def MONITOR : I0xC8, RawFrm, (ops), monitor, ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.165 - 1.166
---
Log message:
X86ISD::PEXTRW 3rd operand type is always target pointer type.
---
Diffs of the changes: (+1 -1)
X86InstrSSE.td |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.165
llvm/lib/Target/X86/X86InstrSSE.td:1.166
--- llvm/lib/Target/X86/X86InstrSSE.td:1.165Wed Oct 11 16:05:24 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Wed Oct 25 16:35:05 2006
@@ -1580,7 +1580,7 @@
(ops GR32:$dst, VR128:$src1, i32i8imm:$src2),
pextrw {$src2, $src1, $dst|$dst, $src1, $src2},
[(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
- (i32 imm:$src2)))];
+ (iPTR imm:$src2)))];
let isTwoAddress = 1 in {
def PINSRWrri : PDIi80xC4, MRMSrcReg,
(ops VR128:$dst, VR128:$src1, GR32:$src2, i32i8imm:$src3),
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.164 - 1.165
---
Log message:
ComplexPatterns sse_load_f32 and sse_load_f64 returns in / out chain operands.
---
Diffs of the changes: (+4 -2)
X86InstrSSE.td |6 --
1 files changed, 4 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.164
llvm/lib/Target/X86/X86InstrSSE.td:1.165
--- llvm/lib/Target/X86/X86InstrSSE.td:1.164Mon Oct 9 16:42:15 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Wed Oct 11 16:05:24 2006
@@ -39,8 +39,10 @@
// These are 'extloads' from a scalar to the low element of a vector, zeroing
// the top elements. These are used for the SSE 'ss' and 'sd' instruction
// forms.
-def sse_load_f32 : ComplexPatternv4f32, 4, SelectScalarSSELoad, [];
-def sse_load_f64 : ComplexPatternv2f64, 4, SelectScalarSSELoad, [];
+def sse_load_f32 : ComplexPatternv4f32, 4, SelectScalarSSELoad, [],
+ [SDNPHasChain];
+def sse_load_f64 : ComplexPatternv2f64, 4, SelectScalarSSELoad, [],
+ [SDNPHasChain];
def ssmem : Operandv4f32 {
let PrintMethod = printf32mem;
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.163 - 1.164
---
Log message:
Don't go too crazy with these AddComplexity. Try matching shufps with load
folding first.
---
Diffs of the changes: (+19 -8)
X86InstrSSE.td | 27 +++
1 files changed, 19 insertions(+), 8 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.163
llvm/lib/Target/X86/X86InstrSSE.td:1.164
--- llvm/lib/Target/X86/X86InstrSSE.td:1.163Mon Oct 9 15:57:25 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Mon Oct 9 16:42:15 2006
@@ -769,7 +769,7 @@
addr:$dst)];
let isTwoAddress = 1 in {
-let AddedComplexity = 20 in {
+let AddedComplexity = 15 in {
def MOVLHPSrr : PSI0x16, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
VR128:$src2),
movlhps {$src2, $dst|$dst, $src2},
[(set VR128:$dst,
@@ -1753,7 +1753,7 @@
def MOVLSD2PDrr : SDI0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
FR64:$src2),
movsd {$src2, $dst|$dst, $src2}, [];
-let AddedComplexity = 20 in {
+let AddedComplexity = 15 in {
def MOVLPSrr : SSI0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
movss {$src2, $dst|$dst, $src2},
[(set VR128:$dst,
@@ -1785,28 +1785,32 @@
[(set VR128:$dst, (v2f64 (vector_shuffle immAllZerosV,
(v2f64 (scalar_to_vector (loadf64
addr:$src))),
MOVL_shuffle_mask)))];
+}
+let AddedComplexity = 15 in
// movd / movq to XMM register zero-extends
def MOVZDI2PDIrr : PDI0x6E, MRMSrcReg, (ops VR128:$dst, GR32:$src),
movd {$src, $dst|$dst, $src},
[(set VR128:$dst, (v4i32 (vector_shuffle immAllZerosV,
(v4i32 (scalar_to_vector
GR32:$src)),
MOVL_shuffle_mask)))];
+let AddedComplexity = 20 in
def MOVZDI2PDIrm : PDI0x6E, MRMSrcMem, (ops VR128:$dst, i32mem:$src),
movd {$src, $dst|$dst, $src},
[(set VR128:$dst, (v4i32 (vector_shuffle immAllZerosV,
(v4i32 (scalar_to_vector (loadi32
addr:$src))),
MOVL_shuffle_mask)))];
// Moving from XMM to XMM but still clear upper 64 bits.
+let AddedComplexity = 15 in
def MOVZQI2PQIrr : I0x7E, MRMSrcReg, (ops VR128:$dst, VR128:$src),
movq {$src, $dst|$dst, $src},
[(set VR128:$dst, (int_x86_sse2_movl_dq VR128:$src))],
XS, Requires[HasSSE2];
+let AddedComplexity = 20 in
def MOVZQI2PQIrm : I0x7E, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
movq {$src, $dst|$dst, $src},
[(set VR128:$dst, (int_x86_sse2_movl_dq
(bitconvert (loadv2i64 addr:$src],
XS, Requires[HasSSE2];
-}
//===--===//
// Non-Instruction Patterns
@@ -1884,7 +1888,7 @@
// Move scalar to XMM zero-extended
// movd to XMM register zero-extends
-let AddedComplexity = 20 in {
+let AddedComplexity = 15 in {
def : Pat(v8i16 (vector_shuffle immAllZerosV,
(v8i16 (X86s2vec GR32:$src)), MOVL_shuffle_mask)),
(MOVZDI2PDIrr GR32:$src), Requires[HasSSE2];
@@ -1950,25 +1954,27 @@
(PUNPCKLDQrr VR128:$src, VR128:$src), Requires[HasSSE1];
}
-let AddedComplexity = 20 in {
+let AddedComplexity = 15 in
// vector_shuffle v1, undef 1, 1, 3, 3
def : Pat(v4i32 (vector_shuffle VR128:$src, (undef),
MOVSHDUP_shuffle_mask)),
(MOVSHDUPrr VR128:$src), Requires[HasSSE3];
+let AddedComplexity = 20 in
def : Pat(v4i32 (vector_shuffle (bc_v4i32 (loadv2i64 addr:$src)), (undef),
MOVSHDUP_shuffle_mask)),
(MOVSHDUPrm addr:$src), Requires[HasSSE3];
// vector_shuffle v1, undef 0, 0, 2, 2
+let AddedComplexity = 15 in
def : Pat(v4i32 (vector_shuffle VR128:$src, (undef),
MOVSLDUP_shuffle_mask)),
(MOVSLDUPrr VR128:$src), Requires[HasSSE3];
+let AddedComplexity = 20 in
def : Pat(v4i32 (vector_shuffle (bc_v4i32 (loadv2i64 addr:$src)), (undef),
MOVSLDUP_shuffle_mask)),
(MOVSLDUPrm addr:$src), Requires[HasSSE3];
-}
-let AddedComplexity = 20 in {
+let AddedComplexity = 15 in {
// vector_shuffle v1, v2 0, 1, 4, 5 using MOVLHPS
def : Pat(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
MOVHP_shuffle_mask)),
@@ -1986,7 +1992,9 @@
def : Pat(v4i32 (vector_shuffle VR128:$src1, (undef),
UNPCKH_shuffle_mask)),
(MOVHLPSrr VR128:$src1, VR128:$src1);
+}
+ let AddedComplexity = 20 in {
// vector_shuffle v1, (load v2) 4, 5, 2, 3 using MOVLPS
// vector_shuffle
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.141 - 1.142
---
Log message:
remove some unneeded type info
---
Diffs of the changes: (+28 -30)
X86InstrSSE.td | 58 +++--
1 files changed, 28 insertions(+), 30 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.141
llvm/lib/Target/X86/X86InstrSSE.td:1.142
--- llvm/lib/Target/X86/X86InstrSSE.td:1.141Sat Oct 7 00:50:25 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Sat Oct 7 01:17:43 2006
@@ -231,7 +231,7 @@
class PS_Intmbits8 o, string OpcodeStr, Intrinsic IntId
: PSIo, MRMSrcMem, (ops VR128:$dst, f32mem:$src),
!strconcat(OpcodeStr, {$src, $dst|$dst, $src}),
-[(set VR128:$dst, (IntId (loadv4f32 addr:$src)))];
+[(set VR128:$dst, (IntId (load addr:$src)))];
class PD_Intrbits8 o, string OpcodeStr, Intrinsic IntId
: PDIo, MRMSrcReg, (ops VR128:$dst, VR128:$src),
!strconcat(OpcodeStr, {$src, $dst|$dst, $src}),
@@ -239,7 +239,7 @@
class PD_Intmbits8 o, string OpcodeStr, Intrinsic IntId
: PDIo, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
!strconcat(OpcodeStr, {$src, $dst|$dst, $src}),
-[(set VR128:$dst, (IntId (loadv2f64 addr:$src)))];
+[(set VR128:$dst, (IntId (load addr:$src)))];
class PS_Intrrbits8 o, string OpcodeStr, Intrinsic IntId
: PSIo, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
@@ -248,7 +248,7 @@
class PS_Intrmbits8 o, string OpcodeStr, Intrinsic IntId
: PSIo, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f32mem:$src2),
!strconcat(OpcodeStr, {$src2, $dst|$dst, $src2}),
-[(set VR128:$dst, (IntId VR128:$src1, (loadv4f32 addr:$src2)))];
+[(set VR128:$dst, (IntId VR128:$src1, (load addr:$src2)))];
class PD_Intrrbits8 o, string OpcodeStr, Intrinsic IntId
: PDIo, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
!strconcat(OpcodeStr, {$src2, $dst|$dst, $src2}),
@@ -256,22 +256,21 @@
class PD_Intrmbits8 o, string OpcodeStr, Intrinsic IntId
: PDIo, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
!strconcat(OpcodeStr, {$src2, $dst|$dst, $src2}),
-[(set VR128:$dst, (IntId VR128:$src1, (loadv2f64 addr:$src2)))];
+[(set VR128:$dst, (IntId VR128:$src1, (load addr:$src2)))];
class S3D_Intrrbits8 o, string asm, Intrinsic IntId
: S3DIo, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
[(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))];
class S3D_Intrmbits8 o, string asm, Intrinsic IntId
: S3DIo, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2), asm,
- [(set VR128:$dst, (v4f32 (IntId VR128:$src1,
- (loadv4f32 addr:$src2];
+ [(set VR128:$dst, (v4f32 (IntId VR128:$src1, (load addr:$src2];
class S3_Intrrbits8 o, string asm, Intrinsic IntId
: S3Io, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
[(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))];
class S3_Intrmbits8 o, string asm, Intrinsic IntId
: S3Io, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2), asm,
[(set VR128:$dst, (v2f64 (IntId VR128:$src1,
- (loadv2f64 addr:$src2];
+ (load addr:$src2];
// Some 'special' instructions
def IMPLICIT_DEF_FR32 : I0, Pseudo, (ops FR32:$dst),
@@ -490,14 +489,14 @@
def Int_CVTSS2SIrm: SSI0x2D, MRMSrcMem, (ops GR32:$dst, f32mem:$src),
cvtss2si {$src, $dst|$dst, $src},
[(set GR32:$dst, (int_x86_sse_cvtss2si
- (loadv4f32 addr:$src)))];
+ (load addr:$src)))];
def Int_CVTSD2SIrr: SDI0x2D, MRMSrcReg, (ops GR32:$dst, VR128:$src),
cvtsd2si {$src, $dst|$dst, $src},
[(set GR32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))];
def Int_CVTSD2SIrm: SDI0x2D, MRMSrcMem, (ops GR32:$dst, f128mem:$src),
cvtsd2si {$src, $dst|$dst, $src},
[(set GR32:$dst, (int_x86_sse2_cvtsd2si
- (loadv2f64 addr:$src)))];
+ (load addr:$src)))];
// Aliases for intrinsics
def Int_CVTTSS2SIrr: SSI0x2C, MRMSrcReg, (ops GR32:$dst, VR128:$src),
@@ -505,15 +504,14 @@
[(set GR32:$dst, (int_x86_sse_cvttss2si VR128:$src))];
def Int_CVTTSS2SIrm: SSI0x2C, MRMSrcMem, (ops GR32:$dst, f32mem:$src),
cvttss2si {$src, $dst|$dst, $src},
-[(set GR32:$dst, (int_x86_sse_cvttss2si
- (loadv4f32 addr:$src)))];
+[(set GR32:$dst, (int_x86_sse_cvttss2si(load
addr:$src)))];
def Int_CVTTSD2SIrr: SDI0x2C, MRMSrcReg, (ops GR32:$dst, VR128:$src),
cvttsd2si
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86: X86InstrSSE.td updated: 1.142 - 1.143 --- Log message: remove unneeded definitions and type info --- Diffs of the changes: (+0 -3) X86InstrSSE.td |3 --- 1 files changed, 3 deletions(-) Index: llvm/lib/Target/X86/X86InstrSSE.td diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.142 llvm/lib/Target/X86/X86InstrSSE.td:1.143 --- llvm/lib/Target/X86/X86InstrSSE.td:1.142Sat Oct 7 01:17:43 2006 +++ llvm/lib/Target/X86/X86InstrSSE.td Sat Oct 7 01:19:41 2006 @@ -45,9 +45,6 @@ def loadv4f32: PatFrag(ops node:$ptr), (v4f32 (load node:$ptr)); def loadv2f64: PatFrag(ops node:$ptr), (v2f64 (load node:$ptr)); -def loadv16i8: PatFrag(ops node:$ptr), (v16i8 (load node:$ptr)); -def loadv8i16: PatFrag(ops node:$ptr), (v8i16 (load node:$ptr)); -def loadv4i32: PatFrag(ops node:$ptr), (v4i32 (load node:$ptr)); def loadv2i64: PatFrag(ops node:$ptr), (v2i64 (load node:$ptr)); def bc_v4f32 : PatFrag(ops node:$in), (v4f32 (bitconvert node:$in)); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.143 - 1.144
---
Log message:
remove more unneeded type info
---
Diffs of the changes: (+51 -51)
X86InstrSSE.td | 102 -
1 files changed, 51 insertions(+), 51 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.143
llvm/lib/Target/X86/X86InstrSSE.td:1.144
--- llvm/lib/Target/X86/X86InstrSSE.td:1.143Sat Oct 7 01:19:41 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Sat Oct 7 01:27:03 2006
@@ -836,7 +836,7 @@
def Int_CVTDQ2PSrm : I0x5B, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
cvtdq2ps {$src, $dst|$dst, $src},
[(set VR128:$dst, (int_x86_sse2_cvtdq2ps
- (bc_v4i32 (loadv2i64 addr:$src],
+ (bitconvert (loadv2i64
addr:$src],
TB, Requires[HasSSE2];
// SSE2 instructions with XS prefix
@@ -847,7 +847,7 @@
def Int_CVTDQ2PDrm : I0xE6, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
cvtdq2pd {$src, $dst|$dst, $src},
[(set VR128:$dst, (int_x86_sse2_cvtdq2pd
- (bc_v4i32 (loadv2i64 addr:$src],
+ (bitconvert (loadv2i64
addr:$src],
XS, Requires[HasSSE2];
def Int_CVTPS2DQrr : PDI0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
@@ -1061,7 +1061,7 @@
andpd {$src2, $dst|$dst, $src2},
[(set VR128:$dst,
(and (bc_v2i64 (v2f64 VR128:$src1)),
- (bc_v2i64 (v2f64 VR128:$src2];
+ (bc_v2i64 (v2f64 VR128:$src2];
def ORPSrr : PSI0x56, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
orps {$src2, $dst|$dst, $src2},
[(set VR128:$dst, (v2i64 (or VR128:$src1, VR128:$src2)))];
@@ -1069,7 +1069,7 @@
orpd {$src2, $dst|$dst, $src2},
[(set VR128:$dst,
(or (bc_v2i64 (v2f64 VR128:$src1)),
- (bc_v2i64 (v2f64 VR128:$src2];
+(bc_v2i64 (v2f64 VR128:$src2];
def XORPSrr : PSI0x57, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
xorps {$src2, $dst|$dst, $src2},
[(set VR128:$dst, (v2i64 (xor VR128:$src1, VR128:$src2)))];
@@ -1077,7 +1077,7 @@
xorpd {$src2, $dst|$dst, $src2},
[(set VR128:$dst,
(xor (bc_v2i64 (v2f64 VR128:$src1)),
- (bc_v2i64 (v2f64 VR128:$src2];
+ (bc_v2i64 (v2f64 VR128:$src2];
}
def ANDPSrm : PSI0x54, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
f128mem:$src2),
andps {$src2, $dst|$dst, $src2},
@@ -1120,7 +1120,7 @@
andnpd {$src2, $dst|$dst, $src2},
[(set VR128:$dst,
(and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
- (bc_v2i64 (v2f64 VR128:$src2];
+ (bc_v2i64 (v2f64 VR128:$src2];
def ANDNPDrm : PDI0x55, MRMSrcMem, (ops VR128:$dst,
VR128:$src1,f128mem:$src2),
andnpd {$src2, $dst|$dst, $src2},
[(set VR128:$dst,
@@ -1332,19 +1332,19 @@
def PADDSBrm : PDI0xEC, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
paddsb {$src2, $dst|$dst, $src2},
[(set VR128:$dst, (int_x86_sse2_padds_b VR128:$src1,
- (bc_v16i8 (loadv2i64 addr:$src2];
+ (bitconvert (loadv2i64 addr:$src2];
def PADDSWrm : PDI0xED, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
paddsw {$src2, $dst|$dst, $src2},
[(set VR128:$dst, (int_x86_sse2_padds_w VR128:$src1,
- (bc_v8i16 (loadv2i64 addr:$src2];
+ (bitconvert (loadv2i64 addr:$src2];
def PADDUSBrm : PDI0xDC, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
paddusb {$src2, $dst|$dst, $src2},
[(set VR128:$dst, (int_x86_sse2_paddus_b VR128:$src1,
- (bc_v16i8 (loadv2i64 addr:$src2];
+ (bitconvert (loadv2i64 addr:$src2];
def PADDUSWrm : PDI0xDD, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
paddusw {$src2, $dst|$dst, $src2},
[(set VR128:$dst, (int_x86_sse2_paddus_w VR128:$src1,
- (bc_v8i16 (loadv2i64 addr:$src2];
+ (bitconvert (loadv2i64 addr:$src2];
def PSUBBrr : PDI0xF8, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
@@
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.144 - 1.145
---
Log message:
simplify horizontal op definitions
---
Diffs of the changes: (+21 -26)
X86InstrSSE.td | 47 +--
1 files changed, 21 insertions(+), 26 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.144
llvm/lib/Target/X86/X86InstrSSE.td:1.145
--- llvm/lib/Target/X86/X86InstrSSE.td:1.144Sat Oct 7 01:27:03 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Sat Oct 7 01:31:41 2006
@@ -255,19 +255,22 @@
!strconcat(OpcodeStr, {$src2, $dst|$dst, $src2}),
[(set VR128:$dst, (IntId VR128:$src1, (load addr:$src2)))];
-class S3D_Intrrbits8 o, string asm, Intrinsic IntId
- : S3DIo, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
+class S3D_Intrrbits8 o, string OpcodeStr, Intrinsic IntId
+ : S3DIo, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
+ !strconcat(OpcodeStr, {$src2, $dst|$dst, $src2}),
[(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))];
-class S3D_Intrmbits8 o, string asm, Intrinsic IntId
- : S3DIo, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2), asm,
+class S3D_Intrmbits8 o, string OpcodeStr, Intrinsic IntId
+ : S3DIo, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
+ !strconcat(OpcodeStr, {$src2, $dst|$dst, $src2}),
[(set VR128:$dst, (v4f32 (IntId VR128:$src1, (load addr:$src2];
-class S3_Intrrbits8 o, string asm, Intrinsic IntId
- : S3Io, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
+class S3_Intrrbits8 o, string OpcodeStr, Intrinsic IntId
+ : S3Io, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
+ !strconcat(OpcodeStr, {$src2, $dst|$dst, $src2}),
[(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))];
-class S3_Intrmbits8 o, string asm, Intrinsic IntId
- : S3Io, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2), asm,
- [(set VR128:$dst, (v2f64 (IntId VR128:$src1,
- (load addr:$src2];
+class S3_Intrmbits8 o, string OpcodeStr, Intrinsic IntId
+ : S3Io, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
+ !strconcat(OpcodeStr, {$src2, $dst|$dst, $src2}),
+ [(set VR128:$dst, (v2f64 (IntId VR128:$src1, (load addr:$src2];
// Some 'special' instructions
def IMPLICIT_DEF_FR32 : I0, Pseudo, (ops FR32:$dst),
@@ -1234,22 +1237,14 @@
// Horizontal ops
let isTwoAddress = 1 in {
-def HADDPSrr : S3D_Intrr0x7C, haddps {$src2, $dst|$dst, $src2},
- int_x86_sse3_hadd_ps;
-def HADDPSrm : S3D_Intrm0x7C, haddps {$src2, $dst|$dst, $src2},
- int_x86_sse3_hadd_ps;
-def HADDPDrr : S3_Intrr0x7C, haddpd {$src2, $dst|$dst, $src2},
- int_x86_sse3_hadd_pd;
-def HADDPDrm : S3_Intrm0x7C, haddpd {$src2, $dst|$dst, $src2},
- int_x86_sse3_hadd_pd;
-def HSUBPSrr : S3D_Intrr0x7D, hsubps {$src2, $dst|$dst, $src2},
- int_x86_sse3_hsub_ps;
-def HSUBPSrm : S3D_Intrm0x7D, hsubps {$src2, $dst|$dst, $src2},
- int_x86_sse3_hsub_ps;
-def HSUBPDrr : S3_Intrr0x7D, hsubpd {$src2, $dst|$dst, $src2},
- int_x86_sse3_hsub_pd;
-def HSUBPDrm : S3_Intrm0x7D, hsubpd {$src2, $dst|$dst, $src2},
- int_x86_sse3_hsub_pd;
+def HADDPSrr : S3D_Intrr0x7C, haddps, int_x86_sse3_hadd_ps;
+def HADDPSrm : S3D_Intrm0x7C, haddps, int_x86_sse3_hadd_ps;
+def HADDPDrr : S3_Intrr 0x7C, haddpd, int_x86_sse3_hadd_pd;
+def HADDPDrm : S3_Intrm 0x7C, haddpd, int_x86_sse3_hadd_pd;
+def HSUBPSrr : S3D_Intrr0x7D, hsubps, int_x86_sse3_hsub_ps;
+def HSUBPSrm : S3D_Intrm0x7D, hsubps, int_x86_sse3_hsub_ps;
+def HSUBPDrr : S3_Intrr 0x7D, hsubpd, int_x86_sse3_hsub_pd;
+def HSUBPDrm : S3_Intrm 0x7D, hsubpd, int_x86_sse3_hsub_pd;
}
//===--===//
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.145 - 1.146
---
Log message:
move class defns close to uses to make it easier to read
---
Diffs of the changes: (+18 -17)
X86InstrSSE.td | 35 ++-
1 files changed, 18 insertions(+), 17 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.145
llvm/lib/Target/X86/X86InstrSSE.td:1.146
--- llvm/lib/Target/X86/X86InstrSSE.td:1.145Sat Oct 7 01:31:41 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Sat Oct 7 01:33:36 2006
@@ -255,23 +255,6 @@
!strconcat(OpcodeStr, {$src2, $dst|$dst, $src2}),
[(set VR128:$dst, (IntId VR128:$src1, (load addr:$src2)))];
-class S3D_Intrrbits8 o, string OpcodeStr, Intrinsic IntId
- : S3DIo, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
- !strconcat(OpcodeStr, {$src2, $dst|$dst, $src2}),
- [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))];
-class S3D_Intrmbits8 o, string OpcodeStr, Intrinsic IntId
- : S3DIo, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
- !strconcat(OpcodeStr, {$src2, $dst|$dst, $src2}),
- [(set VR128:$dst, (v4f32 (IntId VR128:$src1, (load addr:$src2];
-class S3_Intrrbits8 o, string OpcodeStr, Intrinsic IntId
- : S3Io, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
- !strconcat(OpcodeStr, {$src2, $dst|$dst, $src2}),
- [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))];
-class S3_Intrmbits8 o, string OpcodeStr, Intrinsic IntId
- : S3Io, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
- !strconcat(OpcodeStr, {$src2, $dst|$dst, $src2}),
- [(set VR128:$dst, (v2f64 (IntId VR128:$src1, (load addr:$src2];
-
// Some 'special' instructions
def IMPLICIT_DEF_FR32 : I0, Pseudo, (ops FR32:$dst),
#IMPLICIT_DEF $dst,
@@ -1236,6 +1219,24 @@
}
// Horizontal ops
+
+class S3D_Intrrbits8 o, string OpcodeStr, Intrinsic IntId
+ : S3DIo, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
+ !strconcat(OpcodeStr, {$src2, $dst|$dst, $src2}),
+ [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))];
+class S3D_Intrmbits8 o, string OpcodeStr, Intrinsic IntId
+ : S3DIo, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
+ !strconcat(OpcodeStr, {$src2, $dst|$dst, $src2}),
+ [(set VR128:$dst, (v4f32 (IntId VR128:$src1, (load addr:$src2];
+class S3_Intrrbits8 o, string OpcodeStr, Intrinsic IntId
+ : S3Io, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
+ !strconcat(OpcodeStr, {$src2, $dst|$dst, $src2}),
+ [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))];
+class S3_Intrmbits8 o, string OpcodeStr, Intrinsic IntId
+ : S3Io, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
+ !strconcat(OpcodeStr, {$src2, $dst|$dst, $src2}),
+ [(set VR128:$dst, (v2f64 (IntId VR128:$src1, (load addr:$src2];
+
let isTwoAddress = 1 in {
def HADDPSrr : S3D_Intrr0x7C, haddps, int_x86_sse3_hadd_ps;
def HADDPSrm : S3D_Intrm0x7C, haddps, int_x86_sse3_hadd_ps;
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.146 - 1.147
---
Log message:
Use a multiclass to simplify 'SSE2 Integer comparison'
---
Diffs of the changes: (+19 -61)
X86InstrSSE.td | 80 +
1 files changed, 19 insertions(+), 61 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.146
llvm/lib/Target/X86/X86InstrSSE.td:1.147
--- llvm/lib/Target/X86/X86InstrSSE.td:1.146Sat Oct 7 01:33:36 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Sat Oct 7 01:47:08 2006
@@ -1671,69 +1671,27 @@
(load addr:$src2];
}
+
+let isTwoAddress = 1 in {
+multiclass PDI_binop_rmbits8 opc, string OpcodeStr, Intrinsic IntId {
+ def rr : PDIopc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
+ !strconcat(OpcodeStr, {$src2, $dst|$dst, $src2),
+ [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))];
+ def rm : PDIopc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
+ !strconcat(OpcodeStr, {$src2, $dst|$dst, $src2),
+ [(set VR128:$dst, (IntId VR128:$src1,
+(bitconvert (loadv2i64
addr:$src2];
+}
+}
+
// SSE2 Integer comparison
let isTwoAddress = 1 in {
-def PCMPEQBrr : PDI0x74, MRMSrcReg,
-(ops VR128:$dst, VR128:$src1, VR128:$src2),
-pcmpeqb {$src2, $dst|$dst, $src2},
-[(set VR128:$dst, (int_x86_sse2_pcmpeq_b VR128:$src1,
- VR128:$src2))];
-def PCMPEQBrm : PDI0x74, MRMSrcMem,
-(ops VR128:$dst, VR128:$src1, i128mem:$src2),
-pcmpeqb {$src2, $dst|$dst, $src2},
-[(set VR128:$dst, (int_x86_sse2_pcmpeq_b VR128:$src1,
- (bitconvert (loadv2i64 addr:$src2];
-def PCMPEQWrr : PDI0x75, MRMSrcReg,
-(ops VR128:$dst, VR128:$src1, VR128:$src2),
-pcmpeqw {$src2, $dst|$dst, $src2},
-[(set VR128:$dst, (int_x86_sse2_pcmpeq_w VR128:$src1,
- VR128:$src2))];
-def PCMPEQWrm : PDI0x75, MRMSrcMem,
-(ops VR128:$dst, VR128:$src1, i128mem:$src2),
-pcmpeqw {$src2, $dst|$dst, $src2},
-[(set VR128:$dst, (int_x86_sse2_pcmpeq_w VR128:$src1,
- (bitconvert (loadv2i64 addr:$src2];
-def PCMPEQDrr : PDI0x76, MRMSrcReg,
-(ops VR128:$dst, VR128:$src1, VR128:$src2),
-pcmpeqd {$src2, $dst|$dst, $src2},
-[(set VR128:$dst, (int_x86_sse2_pcmpeq_d VR128:$src1,
- VR128:$src2))];
-def PCMPEQDrm : PDI0x76, MRMSrcMem,
-(ops VR128:$dst, VR128:$src1, i128mem:$src2),
-pcmpeqd {$src2, $dst|$dst, $src2},
-[(set VR128:$dst, (int_x86_sse2_pcmpeq_d VR128:$src1,
- (bitconvert (loadv2i64 addr:$src2];
-
-def PCMPGTBrr : PDI0x64, MRMSrcReg,
-(ops VR128:$dst, VR128:$src1, VR128:$src2),
-pcmpgtb {$src2, $dst|$dst, $src2},
-[(set VR128:$dst, (int_x86_sse2_pcmpgt_b VR128:$src1,
- VR128:$src2))];
-def PCMPGTBrm : PDI0x64, MRMSrcMem,
-(ops VR128:$dst, VR128:$src1, i128mem:$src2),
-pcmpgtb {$src2, $dst|$dst, $src2},
-[(set VR128:$dst, (int_x86_sse2_pcmpgt_b VR128:$src1,
- (bitconvert (loadv2i64 addr:$src2];
-def PCMPGTWrr : PDI0x65, MRMSrcReg,
-(ops VR128:$dst, VR128:$src1, VR128:$src2),
-pcmpgtw {$src2, $dst|$dst, $src2},
-[(set VR128:$dst, (int_x86_sse2_pcmpgt_w VR128:$src1,
- VR128:$src2))];
-def PCMPGTWrm : PDI0x65, MRMSrcMem,
-(ops VR128:$dst, VR128:$src1, i128mem:$src2),
-pcmpgtw {$src2, $dst|$dst, $src2},
-[(set VR128:$dst, (int_x86_sse2_pcmpgt_w VR128:$src1,
- (bitconvert (loadv2i64 addr:$src2];
-def PCMPGTDrr : PDI0x66, MRMSrcReg,
-(ops VR128:$dst, VR128:$src1, VR128:$src2),
-pcmpgtd {$src2, $dst|$dst, $src2},
-[(set VR128:$dst, (int_x86_sse2_pcmpgt_d VR128:$src1,
- VR128:$src2))];
-def PCMPGTDrm : PDI0x66, MRMSrcMem,
-(ops VR128:$dst, VR128:$src1, i128mem:$src2),
-pcmpgtd {$src2, $dst|$dst, $src2},
-[(set VR128:$dst, (int_x86_sse2_pcmpgt_d VR128:$src1,
- (bitconvert (loadv2i64 addr:$src2];
+defm
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.147 - 1.148
---
Log message:
simplify pack and shift intrinsics with multiclasses
---
Diffs of the changes: (+46 -137)
X86InstrSSE.td | 183 ++---
1 files changed, 46 insertions(+), 137 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.147
llvm/lib/Target/X86/X86InstrSSE.td:1.148
--- llvm/lib/Target/X86/X86InstrSSE.td:1.147Sat Oct 7 01:47:08 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Sat Oct 7 02:06:17 2006
@@ -1516,6 +1516,35 @@
(bitconvert (loadv2i64 addr:$src2];
+let isTwoAddress = 1 in {
+multiclass PDI_binop_rmbits8 opc, string OpcodeStr, Intrinsic IntId {
+ def rr : PDIopc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
+ !strconcat(OpcodeStr, {$src2, $dst|$dst, $src2),
+ [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))];
+ def rm : PDIopc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
+ !strconcat(OpcodeStr, {$src2, $dst|$dst, $src2),
+ [(set VR128:$dst, (IntId VR128:$src1,
+(bitconvert (loadv2i64
addr:$src2];
+}
+}
+
+let isTwoAddress = 1 in {
+multiclass PDI_binop_rmibits8 opc, bits8 opc2, Format ImmForm,
+ string OpcodeStr, Intrinsic IntId {
+ def rr : PDIopc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
+ !strconcat(OpcodeStr, {$src2, $dst|$dst, $src2),
+ [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))];
+ def rm : PDIopc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
+ !strconcat(OpcodeStr, {$src2, $dst|$dst, $src2),
+ [(set VR128:$dst, (IntId VR128:$src1,
+(bitconvert (loadv2i64
addr:$src2];
+ def ri : PDIi8opc2, ImmForm, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
+ !strconcat(OpcodeStr, {$src2, $dst|$dst, $src2),
+ [(set VR128:$dst, (IntId VR128:$src1,
+(scalar_to_vector (i32 imm:$src2];
+}
+}
+
let isCommutable = 1 in {
def PSADBWrr : PDI0xE0, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
psadbw {$src2, $dst|$dst, $src2},
@@ -1528,109 +1557,25 @@
(bitconvert (loadv2i64 addr:$src2];
}
+
+defm PSLLW : PDI_binop_rmi0xF1, 0x71, MRM6r, psllw, int_x86_sse2_psll_w;
+defm PSLLD : PDI_binop_rmi0xF2, 0x72, MRM6r, pslld, int_x86_sse2_psll_d;
+defm PSLLQ : PDI_binop_rmi0xF3, 0x73, MRM6r, psllq, int_x86_sse2_psll_q;
+
+defm PSRLW : PDI_binop_rmi0xD1, 0x71, MRM2r, psrlw, int_x86_sse2_psrl_w;
+defm PSRLD : PDI_binop_rmi0xD2, 0x72, MRM2r, psrld, int_x86_sse2_psrl_d;
+defm PSRLQ : PDI_binop_rmi0xD3, 0x73, MRM2r, psrlq, int_x86_sse2_psrl_q;
+
+defm PSRAW : PDI_binop_rmi0xE1, 0x71, MRM4r, psraw, int_x86_sse2_psra_w;
+defm PSRAD : PDI_binop_rmi0xE2, 0x72, MRM4r, psrad, int_x86_sse2_psra_d;
+// PSRAQ doesn't exist in SSE[1-3].
+
let isTwoAddress = 1 in {
-def PSLLWrr : PDI0xF1, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
- psllw {$src2, $dst|$dst, $src2},
- [(set VR128:$dst, (int_x86_sse2_psll_w VR128:$src1,
- VR128:$src2))];
-def PSLLWrm : PDI0xF1, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
- psllw {$src2, $dst|$dst, $src2},
- [(set VR128:$dst, (int_x86_sse2_psll_w VR128:$src1,
- (bitconvert (loadv2i64 addr:$src2];
-def PSLLWri : PDIi80x71, MRM6r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
-psllw {$src2, $dst|$dst, $src2},
-[(set VR128:$dst, (int_x86_sse2_psll_w VR128:$src1,
- (scalar_to_vector (i32 imm:$src2];
-def PSLLDrr : PDI0xF2, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
- pslld {$src2, $dst|$dst, $src2},
- [(set VR128:$dst, (int_x86_sse2_psll_d VR128:$src1,
- VR128:$src2))];
-def PSLLDrm : PDI0xF2, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
- pslld {$src2, $dst|$dst, $src2},
- [(set VR128:$dst, (int_x86_sse2_psll_d VR128:$src1,
- (bitconvert (loadv2i64 addr:$src2];
-def PSLLDri : PDIi80x72, MRM6r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
-pslld {$src2, $dst|$dst, $src2},
-[(set VR128:$dst, (int_x86_sse2_psll_d VR128:$src1,
- (scalar_to_vector (i32 imm:$src2];
-def PSLLQrr : PDI0xF3, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
- psllq {$src2, $dst|$dst, $src2},
- [(set VR128:$dst,
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.148 - 1.149
---
Log message:
handle pmin/pmax with multiclasses
---
Diffs of the changes: (+11 -51)
X86InstrSSE.td | 62 ++---
1 files changed, 11 insertions(+), 51 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.148
llvm/lib/Target/X86/X86InstrSSE.td:1.149
--- llvm/lib/Target/X86/X86InstrSSE.td:1.148Sat Oct 7 02:06:17 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Sat Oct 7 02:49:33 2006
@@ -1476,51 +1476,17 @@
pavgw {$src2, $dst|$dst, $src2},
[(set VR128:$dst, (int_x86_sse2_pavg_w VR128:$src1,
(bitconvert (loadv2i64 addr:$src2];
-
-let isCommutable = 1 in {
-def PMAXUBrr : PDI0xDE, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
- pmaxub {$src2, $dst|$dst, $src2},
- [(set VR128:$dst, (int_x86_sse2_pmaxu_b VR128:$src1,
- VR128:$src2))];
-def PMAXSWrr : PDI0xEE, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
- pmaxsw {$src2, $dst|$dst, $src2},
- [(set VR128:$dst, (int_x86_sse2_pmaxs_w VR128:$src1,
- VR128:$src2))];
-}
-def PMAXUBrm : PDI0xDE, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
- pmaxub {$src2, $dst|$dst, $src2},
- [(set VR128:$dst, (int_x86_sse2_pmaxu_b VR128:$src1,
- (bitconvert (loadv2i64 addr:$src2];
-def PMAXSWrm : PDI0xEE, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
- pmaxsw {$src2, $dst|$dst, $src2},
- [(set VR128:$dst, (int_x86_sse2_pmaxs_w VR128:$src1,
- (bitconvert (loadv2i64 addr:$src2];
-
-let isCommutable = 1 in {
-def PMINUBrr : PDI0xDA, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
- pminub {$src2, $dst|$dst, $src2},
- [(set VR128:$dst, (int_x86_sse2_pminu_b VR128:$src1,
- VR128:$src2))];
-def PMINSWrr : PDI0xEA, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
- pminsw {$src2, $dst|$dst, $src2},
- [(set VR128:$dst, (int_x86_sse2_pmins_w VR128:$src1,
- VR128:$src2))];
-}
-def PMINUBrm : PDI0xDA, MRMSrcMem, (ops VR128:$dst,
VR128:$src1,i128mem:$src2),
- pminub {$src2, $dst|$dst, $src2},
- [(set VR128:$dst, (int_x86_sse2_pminu_b VR128:$src1,
- (bitconvert (loadv2i64 addr:$src2];
-def PMINSWrm : PDI0xEA, MRMSrcMem, (ops VR128:$dst,
VR128:$src1,i128mem:$src2),
- pminsw {$src2, $dst|$dst, $src2},
- [(set VR128:$dst, (int_x86_sse2_pmins_w VR128:$src1,
- (bitconvert (loadv2i64 addr:$src2];
+}
let isTwoAddress = 1 in {
-multiclass PDI_binop_rmbits8 opc, string OpcodeStr, Intrinsic IntId {
+multiclass PDI_binop_rmbits8 opc, string OpcodeStr, Intrinsic IntId,
+bit Commutable = 0 {
def rr : PDIopc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
!strconcat(OpcodeStr, {$src2, $dst|$dst, $src2),
- [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))];
+ [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))] {
+let isCommutable = Commutable;
+ }
def rm : PDIopc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
!strconcat(OpcodeStr, {$src2, $dst|$dst, $src2),
[(set VR128:$dst, (IntId VR128:$src1,
@@ -1545,17 +1511,11 @@
}
}
-let isCommutable = 1 in {
-def PSADBWrr : PDI0xE0, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
- psadbw {$src2, $dst|$dst, $src2},
- [(set VR128:$dst, (int_x86_sse2_psad_bw VR128:$src1,
- VR128:$src2))];
-}
-def PSADBWrm : PDI0xE0, MRMSrcMem, (ops VR128:$dst,
VR128:$src1,i128mem:$src2),
- psadbw {$src2, $dst|$dst, $src2},
- [(set VR128:$dst, (int_x86_sse2_psad_bw VR128:$src1,
- (bitconvert (loadv2i64 addr:$src2];
-}
+defm PMINUB : PDI_binop_rm0xDA, pminub, int_x86_sse2_pminu_b, 1;
+defm PMINSW : PDI_binop_rm0xEA, pminsw, int_x86_sse2_pmins_w, 1;
+defm PMAXUB : PDI_binop_rm0xDE, pmaxub, int_x86_sse2_pmaxu_b, 1;
+defm PMAXSW : PDI_binop_rm0xEE, pmaxsw, int_x86_sse2_pmaxs_w, 1;
+defm PSADBW : PDI_binop_rm0xE0, psadbw, int_x86_sse2_psad_bw, 1;
defm PSLLW : PDI_binop_rmi0xF1, 0x71, MRM6r, psllw, int_x86_sse2_psll_w;
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.152 - 1.153
---
Log message:
rename:
PDI_binop_rm - PDI_binop_rm_int
PDI_binop_rmi - PDI_binop_rmi_int
to make it clear that these are for use with intrinsics.
---
Diffs of the changes: (+40 -40)
X86InstrSSE.td | 80 -
1 files changed, 40 insertions(+), 40 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.152
llvm/lib/Target/X86/X86InstrSSE.td:1.153
--- llvm/lib/Target/X86/X86InstrSSE.td:1.152Sat Oct 7 13:48:46 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Sat Oct 7 14:02:31 2006
@@ -1275,8 +1275,8 @@
let isTwoAddress = 1 in {
-multiclass PDI_binop_rmbits8 opc, string OpcodeStr, Intrinsic IntId,
-bit Commutable = 0 {
+multiclass PDI_binop_rm_intbits8 opc, string OpcodeStr, Intrinsic IntId,
+bit Commutable = 0 {
def rr : PDIopc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
!strconcat(OpcodeStr, {$src2, $dst|$dst, $src2),
[(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))] {
@@ -1290,8 +1290,8 @@
}
let isTwoAddress = 1 in {
-multiclass PDI_binop_rmibits8 opc, bits8 opc2, Format ImmForm,
- string OpcodeStr, Intrinsic IntId {
+multiclass PDI_binop_rmi_intbits8 opc, bits8 opc2, Format ImmForm,
+ string OpcodeStr, Intrinsic IntId {
def rr : PDIopc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
!strconcat(OpcodeStr, {$src2, $dst|$dst, $src2),
[(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))];
@@ -1341,10 +1341,10 @@
(loadv2i64 addr:$src2)))];
-defm PADDSB : PDI_binop_rm0xEC, paddsb , int_x86_sse2_padds_b, 1;
-defm PADDSW : PDI_binop_rm0xED, paddsw , int_x86_sse2_padds_w, 1;
-defm PADDUSB : PDI_binop_rm0xDC, paddusb, int_x86_sse2_paddus_b, 1;
-defm PADDUSW : PDI_binop_rm0xDD, paddusw, int_x86_sse2_paddus_w, 1;
+defm PADDSB : PDI_binop_rm_int0xEC, paddsb , int_x86_sse2_padds_b, 1;
+defm PADDSW : PDI_binop_rm_int0xED, paddsw , int_x86_sse2_padds_w, 1;
+defm PADDUSB : PDI_binop_rm_int0xDC, paddusb, int_x86_sse2_paddus_b, 1;
+defm PADDUSW : PDI_binop_rm_int0xDD, paddusw, int_x86_sse2_paddus_w, 1;
def PSUBBrr : PDI0xF8, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
psubb {$src2, $dst|$dst, $src2},
@@ -1376,10 +1376,10 @@
[(set VR128:$dst, (sub VR128:$src1,
(loadv2i64 addr:$src2)))];
-defm PSUBSB : PDI_binop_rm0xE8, psubsb , int_x86_sse2_psubs_b;
-defm PSUBSW : PDI_binop_rm0xE9, psubsw , int_x86_sse2_psubs_w;
-defm PSUBUSB : PDI_binop_rm0xD8, psubusb, int_x86_sse2_psubus_b;
-defm PSUBUSW : PDI_binop_rm0xD9, psubusw, int_x86_sse2_psubus_w;
+defm PSUBSB : PDI_binop_rm_int0xE8, psubsb , int_x86_sse2_psubs_b;
+defm PSUBSW : PDI_binop_rm_int0xE9, psubsw , int_x86_sse2_psubs_w;
+defm PSUBUSB : PDI_binop_rm_int0xD8, psubusb, int_x86_sse2_psubus_b;
+defm PSUBUSW : PDI_binop_rm_int0xD9, psubusw, int_x86_sse2_psubus_w;
let isCommutable = 1 in {
@@ -1394,33 +1394,33 @@
(bitconvert (loadv2i64
addr:$src2)];
}
-defm PMULHUW : PDI_binop_rm0xE4, pmulhuw, int_x86_sse2_pmulhu_w, 1;
-defm PMULHW : PDI_binop_rm0xE5, pmulhw , int_x86_sse2_pmulh_w , 1;
-defm PMULUDQ : PDI_binop_rm0xF4, pmuludq, int_x86_sse2_pmulu_dq, 1;
+defm PMULHUW : PDI_binop_rm_int0xE4, pmulhuw, int_x86_sse2_pmulhu_w, 1;
+defm PMULHW : PDI_binop_rm_int0xE5, pmulhw , int_x86_sse2_pmulh_w , 1;
+defm PMULUDQ : PDI_binop_rm_int0xF4, pmuludq, int_x86_sse2_pmulu_dq, 1;
-defm PMADDWD : PDI_binop_rm0xF5, pmaddwd, int_x86_sse2_pmadd_wd, 1;
+defm PMADDWD : PDI_binop_rm_int0xF5, pmaddwd, int_x86_sse2_pmadd_wd, 1;
-defm PAVGB : PDI_binop_rm0xE0, pavgb, int_x86_sse2_pavg_b, 1;
-defm PAVGW : PDI_binop_rm0xE3, pavgw, int_x86_sse2_pavg_w, 1;
+defm PAVGB : PDI_binop_rm_int0xE0, pavgb, int_x86_sse2_pavg_b, 1;
+defm PAVGW : PDI_binop_rm_int0xE3, pavgw, int_x86_sse2_pavg_w, 1;
-defm PMINUB : PDI_binop_rm0xDA, pminub, int_x86_sse2_pminu_b, 1;
-defm PMINSW : PDI_binop_rm0xEA, pminsw, int_x86_sse2_pmins_w, 1;
-defm PMAXUB : PDI_binop_rm0xDE, pmaxub, int_x86_sse2_pmaxu_b, 1;
-defm PMAXSW : PDI_binop_rm0xEE, pmaxsw, int_x86_sse2_pmaxs_w, 1;
-defm PSADBW : PDI_binop_rm0xE0, psadbw, int_x86_sse2_psad_bw, 1;
+defm PMINUB : PDI_binop_rm_int0xDA, pminub, int_x86_sse2_pminu_b, 1;
+defm PMINSW : PDI_binop_rm_int0xEA, pminsw, int_x86_sse2_pmins_w, 1;
+defm PMAXUB : PDI_binop_rm_int0xDE, pmaxub, int_x86_sse2_pmaxu_b, 1;
+defm PMAXSW : PDI_binop_rm_int0xEE, pmaxsw, int_x86_sse2_pmaxs_w, 1;
+defm PSADBW : PDI_binop_rm_int0xE0, psadbw, int_x86_sse2_psad_bw, 1;
-defm PSLLW : PDI_binop_rmi0xF1, 0x71, MRM6r, psllw, int_x86_sse2_psll_w;
-defm PSLLD : PDI_binop_rmi0xF2, 0x72, MRM6r, pslld, int_x86_sse2_psll_d;
-defm
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.154 - 1.155
---
Log message:
Fix a bug where PADDQrm printed paddd instead of paddq.
---
Diffs of the changes: (+1 -1)
X86InstrSSE.td |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.154
llvm/lib/Target/X86/X86InstrSSE.td:1.155
--- llvm/lib/Target/X86/X86InstrSSE.td:1.154Sat Oct 7 14:14:49 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Sat Oct 7 14:15:46 2006
@@ -1340,7 +1340,7 @@
[(set VR128:$dst, (v2i64 (add VR128:$src1, VR128:$src2)))];
}
def PADDQrm : PDI0xD4, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
- paddd {$src2, $dst|$dst, $src2},
+ paddq {$src2, $dst|$dst, $src2},
[(set VR128:$dst, (add VR128:$src1,
(loadv2i64 addr:$src2)))];
}
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.153 - 1.154
---
Log message:
Add multiclass for SSE2 instructions that correspond to simple binops.
---
Diffs of the changes: (+35 -56)
X86InstrSSE.td | 91 +
1 files changed, 35 insertions(+), 56 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.153
llvm/lib/Target/X86/X86InstrSSE.td:1.154
--- llvm/lib/Target/X86/X86InstrSSE.td:1.153Sat Oct 7 14:02:31 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Sat Oct 7 14:14:49 2006
@@ -1306,93 +1306,72 @@
}
}
+
+let isTwoAddress = 1 in {
+/// PDI_binop_rm - Simple SSE2 binary operator.
+multiclass PDI_binop_rmbits8 opc, string OpcodeStr, SDNode OpNode,
+ValueType OpVT, bit Commutable = 0 {
+ def rr : PDIopc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
+ !strconcat(OpcodeStr, {$src2, $dst|$dst, $src2),
+ [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))] {
+let isCommutable = Commutable;
+ }
+ def rm : PDIopc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
+ !strconcat(OpcodeStr, {$src2, $dst|$dst, $src2),
+ [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
+ (bitconvert (loadv2i64
addr:$src2)];
+}
+}
+
+
// 128-bit Integer Arithmetic
+
+defm PADDB : PDI_binop_rm0xFC, paddb, add, v16i8, 1;
+defm PADDW : PDI_binop_rm0xFD, paddw, add, v8i16, 1;
+defm PADDD : PDI_binop_rm0xFE, paddd, add, v4i32, 1;
+
+//defm PADDQ : PDI_binop_rm0xD4, paddq, add, v2i64, 1;
+
let isTwoAddress = 1 in {
-let isCommutable = 1 in {
-def PADDBrr : PDI0xFC, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
- paddb {$src2, $dst|$dst, $src2},
- [(set VR128:$dst, (v16i8 (add VR128:$src1, VR128:$src2)))];
-def PADDWrr : PDI0xFD, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
- paddw {$src2, $dst|$dst, $src2},
- [(set VR128:$dst, (v8i16 (add VR128:$src1, VR128:$src2)))];
-def PADDDrr : PDI0xFE, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
- paddd {$src2, $dst|$dst, $src2},
- [(set VR128:$dst, (v4i32 (add VR128:$src1, VR128:$src2)))];
+let isCommutable = 1 in {
def PADDQrr : PDI0xD4, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
paddq {$src2, $dst|$dst, $src2},
[(set VR128:$dst, (v2i64 (add VR128:$src1, VR128:$src2)))];
}
-def PADDBrm : PDI0xFC, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
- paddb {$src2, $dst|$dst, $src2},
- [(set VR128:$dst, (add VR128:$src1,
- (bc_v16i8 (loadv2i64 addr:$src2];
-def PADDWrm : PDI0xFD, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
- paddw {$src2, $dst|$dst, $src2},
- [(set VR128:$dst, (add VR128:$src1,
- (bc_v8i16 (loadv2i64 addr:$src2];
-def PADDDrm : PDI0xFE, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
- paddd {$src2, $dst|$dst, $src2},
- [(set VR128:$dst, (add VR128:$src1,
- (bc_v4i32 (loadv2i64 addr:$src2];
def PADDQrm : PDI0xD4, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
paddd {$src2, $dst|$dst, $src2},
[(set VR128:$dst, (add VR128:$src1,
(loadv2i64 addr:$src2)))];
-
+}
defm PADDSB : PDI_binop_rm_int0xEC, paddsb , int_x86_sse2_padds_b, 1;
defm PADDSW : PDI_binop_rm_int0xED, paddsw , int_x86_sse2_padds_w, 1;
defm PADDUSB : PDI_binop_rm_int0xDC, paddusb, int_x86_sse2_paddus_b, 1;
defm PADDUSW : PDI_binop_rm_int0xDD, paddusw, int_x86_sse2_paddus_w, 1;
-def PSUBBrr : PDI0xF8, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
- psubb {$src2, $dst|$dst, $src2},
- [(set VR128:$dst, (v16i8 (sub VR128:$src1, VR128:$src2)))];
-def PSUBWrr : PDI0xF9, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
- psubw {$src2, $dst|$dst, $src2},
- [(set VR128:$dst, (v8i16 (sub VR128:$src1, VR128:$src2)))];
-def PSUBDrr : PDI0xFA, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
- psubd {$src2, $dst|$dst, $src2},
- [(set VR128:$dst, (v4i32 (sub VR128:$src1, VR128:$src2)))];
+defm PSUBB : PDI_binop_rm0xF8, psubb, sub, v16i8;
+defm PSUBW : PDI_binop_rm0xF9, psubw, sub, v8i16;
+defm PSUBD : PDI_binop_rm0xFA, psubd, sub, v4i32;
+
+
+let isTwoAddress = 1 in {
def PSUBQrr : PDI0xFB, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
psubq {$src2, $dst|$dst, $src2},
[(set VR128:$dst, (v2i64 (sub VR128:$src1, VR128:$src2)))];
-def PSUBBrm : PDI0xF8, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
-
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.155 - 1.156
---
Log message:
Convert some more instructions over to use a new multiclass.
Fix a bug where the asmstring for PSUBQrm was wrong.
---
Diffs of the changes: (+19 -27)
X86InstrSSE.td | 46 +++---
1 files changed, 19 insertions(+), 27 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.155
llvm/lib/Target/X86/X86InstrSSE.td:1.156
--- llvm/lib/Target/X86/X86InstrSSE.td:1.155Sat Oct 7 14:15:46 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Sat Oct 7 14:34:33 2006
@@ -1321,6 +1321,23 @@
[(set VR128:$dst, (OpVT (OpNode VR128:$src1,
(bitconvert (loadv2i64
addr:$src2)];
}
+
+/// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
+///
+/// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
+/// to collapse (bitconvert VT to VT) into its operand.
+///
+multiclass PDI_binop_rm_v2i64bits8 opc, string OpcodeStr, SDNode OpNode,
+ bit Commutable = 0 {
+ def rr : PDIopc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
+ !strconcat(OpcodeStr, {$src2, $dst|$dst, $src2),
+ [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))] {
+let isCommutable = Commutable;
+ }
+ def rm : PDIopc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
+ !strconcat(OpcodeStr, {$src2, $dst|$dst, $src2),
+ [(set VR128:$dst, (OpNode VR128:$src1,(loadv2i64
addr:$src2)))];
+}
}
@@ -1329,21 +1346,7 @@
defm PADDB : PDI_binop_rm0xFC, paddb, add, v16i8, 1;
defm PADDW : PDI_binop_rm0xFD, paddw, add, v8i16, 1;
defm PADDD : PDI_binop_rm0xFE, paddd, add, v4i32, 1;
-
-//defm PADDQ : PDI_binop_rm0xD4, paddq, add, v2i64, 1;
-
-let isTwoAddress = 1 in {
-
-let isCommutable = 1 in {
-def PADDQrr : PDI0xD4, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
- paddq {$src2, $dst|$dst, $src2},
- [(set VR128:$dst, (v2i64 (add VR128:$src1, VR128:$src2)))];
-}
-def PADDQrm : PDI0xD4, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
- paddq {$src2, $dst|$dst, $src2},
- [(set VR128:$dst, (add VR128:$src1,
- (loadv2i64 addr:$src2)))];
-}
+defm PADDQ : PDI_binop_rm_v2i640xD4, paddq, add, 1;
defm PADDSB : PDI_binop_rm_int0xEC, paddsb , int_x86_sse2_padds_b, 1;
defm PADDSW : PDI_binop_rm_int0xED, paddsw , int_x86_sse2_padds_w, 1;
@@ -1353,18 +1356,7 @@
defm PSUBB : PDI_binop_rm0xF8, psubb, sub, v16i8;
defm PSUBW : PDI_binop_rm0xF9, psubw, sub, v8i16;
defm PSUBD : PDI_binop_rm0xFA, psubd, sub, v4i32;
-
-
-let isTwoAddress = 1 in {
-def PSUBQrr : PDI0xFB, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
- psubq {$src2, $dst|$dst, $src2},
- [(set VR128:$dst, (v2i64 (sub VR128:$src1, VR128:$src2)))];
-
-def PSUBQrm : PDI0xFB, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
- psubd {$src2, $dst|$dst, $src2},
- [(set VR128:$dst, (sub VR128:$src1,
- (loadv2i64 addr:$src2)))];
-}
+defm PSUBQ : PDI_binop_rm_v2i640xFB, psubq, sub;
defm PSUBSB : PDI_binop_rm_int0xE8, psubsb , int_x86_sse2_psubs_b;
defm PSUBSW : PDI_binop_rm_int0xE9, psubsw , int_x86_sse2_psubs_w;
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.156 - 1.157
---
Log message:
Convert pand/por/pxor to use multiclass
---
Diffs of the changes: (+4 -25)
X86InstrSSE.td | 29 -
1 files changed, 4 insertions(+), 25 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.156
llvm/lib/Target/X86/X86InstrSSE.td:1.157
--- llvm/lib/Target/X86/X86InstrSSE.td:1.156Sat Oct 7 14:34:33 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Sat Oct 7 14:37:30 2006
@@ -1403,32 +1403,11 @@
}
// Logical
-let isTwoAddress = 1 in {
-let isCommutable = 1 in {
-def PANDrr : PDI0xDB, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
- pand {$src2, $dst|$dst, $src2},
- [(set VR128:$dst, (v2i64 (and VR128:$src1, VR128:$src2)))];
-def PORrr : PDI0xEB, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
- por {$src2, $dst|$dst, $src2},
- [(set VR128:$dst, (v2i64 (or VR128:$src1, VR128:$src2)))];
-def PXORrr : PDI0xEF, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
- pxor {$src2, $dst|$dst, $src2},
- [(set VR128:$dst, (v2i64 (xor VR128:$src1, VR128:$src2)))];
-}
-
-def PANDrm : PDI0xDB, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
- pand {$src2, $dst|$dst, $src2},
- [(set VR128:$dst, (v2i64 (and VR128:$src1,
- (load addr:$src2];
-def PORrm : PDI0xEB, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
- por {$src2, $dst|$dst, $src2},
- [(set VR128:$dst, (v2i64 (or VR128:$src1,
- (load addr:$src2];
-def PXORrm : PDI0xEF, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
- pxor {$src2, $dst|$dst, $src2},
- [(set VR128:$dst, (v2i64 (xor VR128:$src1,
- (load addr:$src2];
+defm PAND : PDI_binop_rm_v2i640xDB, pand, and, 1;
+defm POR : PDI_binop_rm_v2i640xEB, por , or , 1;
+defm PXOR : PDI_binop_rm_v2i640xEF, pxor, xor, 1;
+let isTwoAddress = 1 in {
def PANDNrr : PDI0xDF, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
pandn {$src2, $dst|$dst, $src2},
[(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.157 - 1.158
---
Log message:
Random acts of shrinkage
---
Diffs of the changes: (+24 -34)
X86InstrSSE.td | 58 +++--
1 files changed, 24 insertions(+), 34 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.157
llvm/lib/Target/X86/X86InstrSSE.td:1.158
--- llvm/lib/Target/X86/X86InstrSSE.td:1.157Sat Oct 7 14:37:30 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Sat Oct 7 14:49:05 2006
@@ -17,10 +17,8 @@
// SSE specific DAG Nodes.
//===--===//
-def X86loadp : SDNodeX86ISD::LOAD_PACK, SDTLoad,
-[SDNPHasChain];
-def X86loadu : SDNodeX86ISD::LOAD_UA, SDTLoad,
-[SDNPHasChain];
+def X86loadp : SDNodeX86ISD::LOAD_PACK, SDTLoad, [SDNPHasChain];
+def X86loadu : SDNodeX86ISD::LOAD_UA, SDTLoad, [SDNPHasChain];
def X86fand: SDNodeX86ISD::FAND, SDTFPBinOp,
[SDNPCommutative, SDNPAssociative];
def X86fxor: SDNodeX86ISD::FXOR, SDTFPBinOp,
@@ -29,12 +27,9 @@
[SDNPHasChain, SDNPOutFlag];
def X86ucomi : SDNodeX86ISD::UCOMI, SDTX86CmpTest,
[SDNPHasChain, SDNPOutFlag];
-def X86s2vec : SDNodeX86ISD::S2VEC,
-SDTypeProfile1, 1, [], [];
-def X86pextrw : SDNodeX86ISD::PEXTRW,
-SDTypeProfile1, 2, [], [];
-def X86pinsrw : SDNodeX86ISD::PINSRW,
-SDTypeProfile1, 3, [], [];
+def X86s2vec : SDNodeX86ISD::S2VEC, SDTypeProfile1, 1, [], [];
+def X86pextrw : SDNodeX86ISD::PEXTRW, SDTypeProfile1, 2, [], [];
+def X86pinsrw : SDNodeX86ISD::PINSRW, SDTypeProfile1, 3, [], [];
//===--===//
// SSE pattern fragments
@@ -1394,6 +1389,8 @@
defm PSRAD : PDI_binop_rmi_int0xE2, 0x72, MRM4r, psrad,
int_x86_sse2_psra_d;
// PSRAQ doesn't exist in SSE[1-3].
+
+// 128-bit logical shifts.
let isTwoAddress = 1 in {
def PSLLDQri : PDIi80x73, MRM7r, (ops VR128:$dst, VR128:$src1,
i32i8imm:$src2),
pslldq {$src2, $dst|$dst, $src2}, [];
@@ -1402,6 +1399,13 @@
// PSRADQri doesn't exist in SSE[1-3].
}
+let Predicates = [HasSSE2] in {
+ def : Pat(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
+(v2i64 (PSLLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)));
+ def : Pat(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
+(v2i64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)));
+}
+
// Logical
defm PAND : PDI_binop_rm_v2i640xDB, pand, and, 1;
defm POR : PDI_binop_rm_v2i640xEB, por , or , 1;
@@ -1632,15 +1636,12 @@
[(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask,
EDI)],
Imp[EDI],[];
-// Prefetching loads
-def PREFETCHT0 : PSI0x18, MRM1m, (ops i8mem:$src),
- prefetcht0 $src, [];
-def PREFETCHT1 : PSI0x18, MRM2m, (ops i8mem:$src),
- prefetcht1 $src, [];
-def PREFETCHT2 : PSI0x18, MRM3m, (ops i8mem:$src),
- prefetcht2 $src, [];
-def PREFETCHTNTA : PSI0x18, MRM0m, (ops i8mem:$src),
- prefetchtnta $src, [];
+// Prefetching loads.
+// TODO: no intrinsics for these?
+def PREFETCHT0 : PSI0x18, MRM1m, (ops i8mem:$src), prefetcht0 $src, [];
+def PREFETCHT1 : PSI0x18, MRM2m, (ops i8mem:$src), prefetcht1 $src, [];
+def PREFETCHT2 : PSI0x18, MRM3m, (ops i8mem:$src), prefetcht2 $src, [];
+def PREFETCHTNTA : PSI0x18, MRM0m, (ops i8mem:$src), prefetchtnta $src, [];
// Non-temporal stores
def MOVNTPSmr : PSI0x2B, MRMDestMem, (ops i128mem:$dst, VR128:$src),
@@ -1663,8 +1664,7 @@
TB, Requires[HasSSE2];
// Load, store, and memory fence
-def SFENCE : I0xAE, MRM7m, (ops),
- sfence, [(int_x86_sse_sfence)], TB, Requires[HasSSE1];
+def SFENCE : PSI0xAE, MRM7m, (ops), sfence, [(int_x86_sse_sfence)];
def LFENCE : I0xAE, MRM5m, (ops),
lfence, [(int_x86_sse2_lfence)], TB, Requires[HasSSE2];
def MFENCE : I0xAE, MRM6m, (ops),
@@ -1680,11 +1680,9 @@
// Thread synchronization
def MONITOR : I0xC8, RawFrm, (ops), monitor,
-[(int_x86_sse3_monitor EAX, ECX, EDX)],
- TB, Requires[HasSSE3];
-def MWAIT : I0xC9, RawFrm, (ops), mwait,
-[(int_x86_sse3_mwait ECX, EAX)],
- TB, Requires[HasSSE3];
+[(int_x86_sse3_monitor EAX, ECX, EDX)],TB,
Requires[HasSSE3];
+def MWAIT : I0xC9, RawFrm, (ops), mwait,
+[(int_x86_sse3_mwait ECX, EAX)], TB, Requires[HasSSE3];
//===--===//
// Alias Instructions
@@ -2090,14 +2088,6 @@
def : Pat(int_x86_sse2_punpckl_qdq VR128:$src1, (load addr:$src2)),
(PUNPCKLQDQrm VR128:$src1, addr:$src2),
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.159 - 1.160
---
Log message:
one multiclass now defines all 8 variants of binary-scalar-sse-fp operations.
---
Diffs of the changes: (+66 -51)
X86InstrSSE.td | 117 -
1 files changed, 66 insertions(+), 51 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.159
llvm/lib/Target/X86/X86InstrSSE.td:1.160
--- llvm/lib/Target/X86/X86InstrSSE.td:1.159Sat Oct 7 15:35:44 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Sat Oct 7 15:55:57 2006
@@ -199,23 +199,6 @@
[(set VR128:$dst, (v2f64 (IntId (load addr:$src];
}
-class SS_Intrrbits8 o, string OpcodeStr, Intrinsic IntId
- : SSIo, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
-!strconcat(OpcodeStr, {$src2, $dst|$dst, $src2}),
-[(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))];
-class SS_Intrmbits8 o, string OpcodeStr, Intrinsic IntId
- : SSIo, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f32mem:$src2),
-!strconcat(OpcodeStr, {$src2, $dst|$dst, $src2}),
-[(set VR128:$dst, (v4f32 (IntId VR128:$src1, (load addr:$src2];
-class SD_Intrrbits8 o, string OpcodeStr, Intrinsic IntId
- : SDIo, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
-!strconcat(OpcodeStr, {$src2, $dst|$dst, $src2}),
-[(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))];
-class SD_Intrmbits8 o, string OpcodeStr, Intrinsic IntId
- : SDIo, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
-!strconcat(OpcodeStr, {$src2, $dst|$dst, $src2}),
-[(set VR128:$dst, (v2f64 (IntId VR128:$src1, (load addr:$src2];
-
class PS_Intrbits8 o, string OpcodeStr, Intrinsic IntId
: PSIo, MRMSrcReg, (ops VR128:$dst, VR128:$src),
!strconcat(OpcodeStr, {$src, $dst|$dst, $src}),
@@ -306,9 +289,20 @@
[(store FR64:$src, addr:$dst)];
let isTwoAddress = 1 in {
-/// scalar_sse12_fp_binop_rm - Define 4 scalar sse instructions.
+
+/// scalar_sse12_fp_binop_rm - Scalar SSE binops come in four basic forms:
+/// 1. f32 vs f64 - These come in SSE1/SSE2 forms for float/doubles.
+/// 2. rr vs rm - They include a reg+reg form and a ref+mem form.
+///
+/// In addition, scalar SSE ops have an intrinsic form. This form is unlike
the
+/// normal form, in that they take an entire vector (instead of a scalar) and
+/// leave the top elements undefined. This adds another two variants of the
+/// above permutations, giving us 8 forms for 'instruction'.
+///
multiclass scalar_sse12_fp_binop_rmbits8 opc, string OpcodeStr,
-SDNode OpNode, bit Commutable = 0 {
+SDNode OpNode, Intrinsic F32Int,
+Intrinsic F64Int, bit Commutable = 0 {
+ // Scalar operation, reg+reg.
def SSrr : SSIopc, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
!strconcat(OpcodeStr, ss {$src2, $dst|$dst, $src2),
[(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))] {
@@ -319,21 +313,47 @@
[(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))] {
let isCommutable = Commutable;
}
+ // Scalar operation, reg+mem.
def SSrm : SSIopc, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
!strconcat(OpcodeStr, ss {$src2, $dst|$dst, $src2),
[(set FR32:$dst, (OpNode FR32:$src1, (loadf32 addr:$src2)))];
def SDrm : SDIopc, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2),
!strconcat(OpcodeStr, sd {$src2, $dst|$dst, $src2),
[(set FR64:$dst, (OpNode FR64:$src1, (loadf64 addr:$src2)))];
+
+ // Vector intrinsic operation, reg+reg.
+ def SSrr_Int : SSIopc, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
VR128:$src2),
+ !strconcat(OpcodeStr, ss {$src2, $dst|$dst, $src2),
+ [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))] {
+let isCommutable = Commutable;
+ }
+ def SDrr_Int : SDIopc, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
VR128:$src2),
+ !strconcat(OpcodeStr, sd {$src2, $dst|$dst, $src2),
+ [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))] {
+let isCommutable = Commutable;
+ }
+ // Vector intrinsic operation, reg+mem.
+ def SSrm_Int : SSIopc, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
f32mem:$src2),
+ !strconcat(OpcodeStr, ss {$src2, $dst|$dst, $src2),
+ [(set VR128:$dst, (F32Int VR128:$src1,
+ (load addr:$src2)))];
+ def SDrm_Int : SDIopc, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
f64mem:$src2),
+ !strconcat(OpcodeStr, sd {$src2, $dst|$dst, $src2),
+ [(set VR128:$dst, (F64Int VR128:$src1,
+ (load addr:$src2)))];
}
}
//
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.160 - 1.161
---
Log message:
convert packed FP add/sub/mul/div to use a multiclass.
---
Diffs of the changes: (+34 -65)
X86InstrSSE.td | 99 +++--
1 files changed, 34 insertions(+), 65 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.160
llvm/lib/Target/X86/X86InstrSSE.td:1.161
--- llvm/lib/Target/X86/X86InstrSSE.td:1.160Sat Oct 7 15:55:57 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Sat Oct 7 16:17:13 2006
@@ -288,8 +288,6 @@
movsd {$src, $dst|$dst, $src},
[(store FR64:$src, addr:$dst)];
-let isTwoAddress = 1 in {
-
/// scalar_sse12_fp_binop_rm - Scalar SSE binops come in four basic forms:
/// 1. f32 vs f64 - These come in SSE1/SSE2 forms for float/doubles.
/// 2. rr vs rm - They include a reg+reg form and a ref+mem form.
@@ -299,6 +297,7 @@
/// leave the top elements undefined. This adds another two variants of the
/// above permutations, giving us 8 forms for 'instruction'.
///
+let isTwoAddress = 1 in {
multiclass scalar_sse12_fp_binop_rmbits8 opc, string OpcodeStr,
SDNode OpNode, Intrinsic F32Int,
Intrinsic F64Int, bit Commutable = 0 {
@@ -573,7 +572,6 @@
// start with 'Fs'.
// Alias instructions that map fld0 to pxor for sse.
-// FIXME: remove when we can teach regalloc that xor reg, reg is ok.
def FsFLD0SS : I0xEF, MRMInitReg, (ops FR32:$dst),
pxor $dst, $dst, [(set FR32:$dst, fp32imm0)],
Requires[HasSSE1], TB, OpSize;
@@ -912,70 +910,41 @@
Requires[HasSSE2];
}
-// Arithmetic
+/// packed_sse12_fp_binop_rm - Packed SSE binops come in four basic forms:
+/// 1. v4f32 vs v2f64 - These come in SSE1/SSE2 forms for float/doubles.
+/// 2. rr vs rm - They include a reg+reg form and a ref+mem form.
+///
let isTwoAddress = 1 in {
-let isCommutable = 1 in {
-def ADDPSrr : PSI0x58, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
- addps {$src2, $dst|$dst, $src2},
- [(set VR128:$dst, (v4f32 (fadd VR128:$src1, VR128:$src2)))];
-def ADDPDrr : PDI0x58, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
- addpd {$src2, $dst|$dst, $src2},
- [(set VR128:$dst, (v2f64 (fadd VR128:$src1, VR128:$src2)))];
-def MULPSrr : PSI0x59, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
- mulps {$src2, $dst|$dst, $src2},
- [(set VR128:$dst, (v4f32 (fmul VR128:$src1, VR128:$src2)))];
-def MULPDrr : PDI0x59, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
- mulpd {$src2, $dst|$dst, $src2},
- [(set VR128:$dst, (v2f64 (fmul VR128:$src1, VR128:$src2)))];
-}
-
-def ADDPSrm : PSI0x58, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
f128mem:$src2),
- addps {$src2, $dst|$dst, $src2},
- [(set VR128:$dst, (v4f32 (fadd VR128:$src1,
-(load addr:$src2];
-def ADDPDrm : PDI0x58, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
f128mem:$src2),
- addpd {$src2, $dst|$dst, $src2},
- [(set VR128:$dst, (v2f64 (fadd VR128:$src1,
-(load addr:$src2];
-def MULPSrm : PSI0x59, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
f128mem:$src2),
- mulps {$src2, $dst|$dst, $src2},
- [(set VR128:$dst, (v4f32 (fmul VR128:$src1,
-(load addr:$src2];
-def MULPDrm : PDI0x59, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
f128mem:$src2),
- mulpd {$src2, $dst|$dst, $src2},
- [(set VR128:$dst, (v2f64 (fmul VR128:$src1,
-(load addr:$src2];
-
-def DIVPSrr : PSI0x5E, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
- divps {$src2, $dst|$dst, $src2},
- [(set VR128:$dst, (v4f32 (fdiv VR128:$src1, VR128:$src2)))];
-def DIVPSrm : PSI0x5E, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
f128mem:$src2),
- divps {$src2, $dst|$dst, $src2},
- [(set VR128:$dst, (v4f32 (fdiv VR128:$src1,
-(load addr:$src2];
-def DIVPDrr : PDI0x5E, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
-divpd {$src2, $dst|$dst, $src2},
- [(set VR128:$dst, (v2f64 (fdiv VR128:$src1, VR128:$src2)))];
-def DIVPDrm : PDI0x5E, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
f128mem:$src2),
-divpd {$src2, $dst|$dst, $src2},
- [(set VR128:$dst, (v2f64 (fdiv VR128:$src1,
-(load addr:$src2];
-
-def SUBPSrr : PSI0x5C, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.133 - 1.134
---
Log message:
eliminate redundancy
---
Diffs of the changes: (+32 -60)
X86InstrSSE.td | 92 +++--
1 files changed, 32 insertions(+), 60 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.133
llvm/lib/Target/X86/X86InstrSSE.td:1.134
--- llvm/lib/Target/X86/X86InstrSSE.td:1.133Tue Oct 3 01:55:11 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Fri Oct 6 23:52:09 2006
@@ -2289,66 +2289,38 @@
Requires[HasSSE2];
// bit_convert
-def : Pat(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src),
- Requires[HasSSE2];
-def : Pat(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src),
- Requires[HasSSE2];
-def : Pat(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src),
- Requires[HasSSE2];
-def : Pat(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src),
- Requires[HasSSE2];
-def : Pat(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src),
- Requires[HasSSE2];
-def : Pat(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src),
- Requires[HasSSE2];
-def : Pat(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src),
- Requires[HasSSE2];
-def : Pat(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src),
- Requires[HasSSE2];
-def : Pat(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src),
- Requires[HasSSE2];
-def : Pat(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src),
- Requires[HasSSE2];
-def : Pat(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src),
- Requires[HasSSE2];
-def : Pat(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src),
- Requires[HasSSE2];
-def : Pat(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src),
- Requires[HasSSE2];
-def : Pat(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src),
- Requires[HasSSE2];
-def : Pat(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src),
- Requires[HasSSE2];
-def : Pat(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src),
- Requires[HasSSE2];
-def : Pat(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src),
- Requires[HasSSE2];
-def : Pat(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src),
- Requires[HasSSE2];
-def : Pat(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src),
- Requires[HasSSE2];
-def : Pat(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src),
- Requires[HasSSE2];
-def : Pat(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src),
- Requires[HasSSE2];
-def : Pat(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src),
- Requires[HasSSE2];
-def : Pat(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src),
- Requires[HasSSE2];
-def : Pat(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src),
- Requires[HasSSE2];
-def : Pat(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src),
- Requires[HasSSE2];
-def : Pat(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src),
- Requires[HasSSE2];
-def : Pat(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src),
- Requires[HasSSE2];
-def : Pat(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src),
- Requires[HasSSE2];
-def : Pat(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src),
- Requires[HasSSE2];
-def : Pat(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src),
- Requires[HasSSE2];
+let Predicates = [HasSSE2] in {
+ def : Pat(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src);
+ def : Pat(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src);
+ def : Pat(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src);
+ def : Pat(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src);
+ def : Pat(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src);
+ def : Pat(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src);
+ def : Pat(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src);
+ def : Pat(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src);
+ def : Pat(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src);
+ def : Pat(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src);
+ def : Pat(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src);
+ def : Pat(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src);
+ def : Pat(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src);
+ def : Pat(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src);
+ def : Pat(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src);
+ def : Pat(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src);
+ def : Pat(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src);
+ def : Pat(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src);
+ def : Pat(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src);
+ def : Pat(v16i8 (bitconvert
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.134 - 1.135
---
Log message:
Remove RSQRTSS[rm] RCPSS[rm], which are dead.
Introduce SS_IntUnary, a multiclass to replace SS_Int[rm].
---
Diffs of the changes: (+16 -21)
X86InstrSSE.td | 37 -
1 files changed, 16 insertions(+), 21 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.134
llvm/lib/Target/X86/X86InstrSSE.td:1.135
--- llvm/lib/Target/X86/X86InstrSSE.td:1.134Fri Oct 6 23:52:09 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Sat Oct 7 00:09:48 2006
@@ -194,6 +194,15 @@
class SS_Intmbits8 o, string asm, Intrinsic IntId
: SSIo, MRMSrcMem, (ops VR128:$dst, f32mem:$src), asm,
[(set VR128:$dst, (v4f32 (IntId (load addr:$src];
+
+
+multiclass SS_IntUnarybits8 o, string asm, Intrinsic IntId {
+ def r : SSIo, MRMSrcReg, (ops VR128:$dst, VR128:$src), asm,
+ [(set VR128:$dst, (v4f32 (IntId VR128:$src)))];
+ def m : SSIo, MRMSrcMem, (ops VR128:$dst, f32mem:$src), asm,
+ [(set VR128:$dst, (v4f32 (IntId (load addr:$src];
+}
+
class SD_Intrbits8 o, string asm, Intrinsic IntId
: SDIo, MRMSrcReg, (ops VR128:$dst, VR128:$src), asm,
[(set VR128:$dst, (v2f64 (IntId VR128:$src)))];
@@ -380,15 +389,6 @@
sqrtsd {$src, $dst|$dst, $src},
[(set FR64:$dst, (fsqrt (loadf64 addr:$src)))];
-def RSQRTSSr : SSI0x52, MRMSrcReg, (ops FR32:$dst, FR32:$src),
- rsqrtss {$src, $dst|$dst, $src}, [];
-def RSQRTSSm : SSI0x52, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
- rsqrtss {$src, $dst|$dst, $src}, [];
-def RCPSSr : SSI0x53, MRMSrcReg, (ops FR32:$dst, FR32:$src),
- rcpss {$src, $dst|$dst, $src}, [];
-def RCPSSm : SSI0x53, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
- rcpss {$src, $dst|$dst, $src}, [];
-
let isTwoAddress = 1 in {
let isCommutable = 1 in {
def MAXSSrr : SSI0x5F, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
@@ -451,23 +451,18 @@
int_x86_sse2_sub_sd;
}
-def Int_SQRTSSr : SS_Intr0x51, sqrtss {$src, $dst|$dst, $src},
- int_x86_sse_sqrt_ss;
-def Int_SQRTSSm : SS_Intm0x51, sqrtss {$src, $dst|$dst, $src},
- int_x86_sse_sqrt_ss;
+defm Int_SQRTSS : SS_IntUnary0x51, sqrtss {$src, $dst|$dst, $src},
+ int_x86_sse_sqrt_ss;
+
def Int_SQRTSDr : SD_Intr0x51, sqrtsd {$src, $dst|$dst, $src},
int_x86_sse2_sqrt_sd;
def Int_SQRTSDm : SD_Intm0x51, sqrtsd {$src, $dst|$dst, $src},
int_x86_sse2_sqrt_sd;
-def Int_RSQRTSSr : SS_Intr0x52, rsqrtss {$src, $dst|$dst, $src},
- int_x86_sse_rsqrt_ss;
-def Int_RSQRTSSm : SS_Intm0x52, rsqrtss {$src, $dst|$dst, $src},
- int_x86_sse_rsqrt_ss;
-def Int_RCPSSr : SS_Intr0x53, rcpss {$src, $dst|$dst, $src},
- int_x86_sse_rcp_ss;
-def Int_RCPSSm : SS_Intm0x53, rcpss {$src, $dst|$dst, $src},
- int_x86_sse_rcp_ss;
+defm Int_RSQRTSS : SS_IntUnary0x52, rsqrtss {$src, $dst|$dst, $src},
+ int_x86_sse_rsqrt_ss;
+defm Int_RCPSS : SS_IntUnary0x53, rcpss {$src, $dst|$dst, $src},
+ int_x86_sse_rcp_ss;
let isTwoAddress = 1 in {
let isCommutable = 1 in {
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.135 - 1.136
---
Log message:
pull operand string into the multiclass
---
Diffs of the changes: (+9 -10)
X86InstrSSE.td | 19 +--
1 files changed, 9 insertions(+), 10 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.135
llvm/lib/Target/X86/X86InstrSSE.td:1.136
--- llvm/lib/Target/X86/X86InstrSSE.td:1.135Sat Oct 7 00:09:48 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Sat Oct 7 00:13:26 2006
@@ -196,10 +196,12 @@
[(set VR128:$dst, (v4f32 (IntId (load addr:$src];
-multiclass SS_IntUnarybits8 o, string asm, Intrinsic IntId {
- def r : SSIo, MRMSrcReg, (ops VR128:$dst, VR128:$src), asm,
+multiclass SS_IntUnarybits8 o, string OpcodeStr, Intrinsic IntId {
+ def r : SSIo, MRMSrcReg, (ops VR128:$dst, VR128:$src),
+ !strconcat(OpcodeStr, {$src, $dst|$dst, $src),
[(set VR128:$dst, (v4f32 (IntId VR128:$src)))];
- def m : SSIo, MRMSrcMem, (ops VR128:$dst, f32mem:$src), asm,
+ def m : SSIo, MRMSrcMem, (ops VR128:$dst, f32mem:$src),
+ !strconcat(OpcodeStr, {$src, $dst|$dst, $src),
[(set VR128:$dst, (v4f32 (IntId (load addr:$src];
}
@@ -451,19 +453,16 @@
int_x86_sse2_sub_sd;
}
-defm Int_SQRTSS : SS_IntUnary0x51, sqrtss {$src, $dst|$dst, $src},
- int_x86_sse_sqrt_ss;
+defm Int_SQRTSS : SS_IntUnary0x51, sqrtss , int_x86_sse_sqrt_ss;
+defm Int_RSQRTSS : SS_IntUnary0x52, rsqrtss, int_x86_sse_rsqrt_ss;
+defm Int_RCPSS : SS_IntUnary0x53, rcpss , int_x86_sse_rcp_ss;
+
def Int_SQRTSDr : SD_Intr0x51, sqrtsd {$src, $dst|$dst, $src},
int_x86_sse2_sqrt_sd;
def Int_SQRTSDm : SD_Intm0x51, sqrtsd {$src, $dst|$dst, $src},
int_x86_sse2_sqrt_sd;
-defm Int_RSQRTSS : SS_IntUnary0x52, rsqrtss {$src, $dst|$dst, $src},
- int_x86_sse_rsqrt_ss;
-defm Int_RCPSS : SS_IntUnary0x53, rcpss {$src, $dst|$dst, $src},
- int_x86_sse_rcp_ss;
-
let isTwoAddress = 1 in {
let isCommutable = 1 in {
def Int_MAXSSrr : SS_Intrr0x5F, maxss {$src2, $dst|$dst, $src2},
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.136 - 1.137
---
Log message:
convert the sole sd unary intrinsic to a multiclass for consistency
---
Diffs of the changes: (+9 -19)
X86InstrSSE.td | 28 +---
1 files changed, 9 insertions(+), 19 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.136
llvm/lib/Target/X86/X86InstrSSE.td:1.137
--- llvm/lib/Target/X86/X86InstrSSE.td:1.136Sat Oct 7 00:13:26 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Sat Oct 7 00:19:31 2006
@@ -188,13 +188,6 @@
//===--===//
// Helpers for defining instructions that directly correspond to intrinsics.
-class SS_Intrbits8 o, string asm, Intrinsic IntId
- : SSIo, MRMSrcReg, (ops VR128:$dst, VR128:$src), asm,
-[(set VR128:$dst, (v4f32 (IntId VR128:$src)))];
-class SS_Intmbits8 o, string asm, Intrinsic IntId
- : SSIo, MRMSrcMem, (ops VR128:$dst, f32mem:$src), asm,
-[(set VR128:$dst, (v4f32 (IntId (load addr:$src];
-
multiclass SS_IntUnarybits8 o, string OpcodeStr, Intrinsic IntId {
def r : SSIo, MRMSrcReg, (ops VR128:$dst, VR128:$src),
@@ -205,12 +198,14 @@
[(set VR128:$dst, (v4f32 (IntId (load addr:$src];
}
-class SD_Intrbits8 o, string asm, Intrinsic IntId
- : SDIo, MRMSrcReg, (ops VR128:$dst, VR128:$src), asm,
-[(set VR128:$dst, (v2f64 (IntId VR128:$src)))];
-class SD_Intmbits8 o, string asm, Intrinsic IntId
- : SDIo, MRMSrcMem, (ops VR128:$dst, f64mem:$src), asm,
-[(set VR128:$dst, (v2f64 (IntId (load addr:$src];
+multiclass SD_IntUnarybits8 o, string OpcodeStr, Intrinsic IntId {
+ def r : SDIo, MRMSrcReg, (ops VR128:$dst, VR128:$src),
+ !strconcat(OpcodeStr, {$src, $dst|$dst, $src),
+ [(set VR128:$dst, (v2f64 (IntId VR128:$src)))];
+ def m : SDIo, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
+ !strconcat(OpcodeStr, {$src, $dst|$dst, $src),
+ [(set VR128:$dst, (v2f64 (IntId (load addr:$src];
+}
class SS_Intrrbits8 o, string asm, Intrinsic IntId
: SSIo, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
@@ -454,15 +449,10 @@
}
defm Int_SQRTSS : SS_IntUnary0x51, sqrtss , int_x86_sse_sqrt_ss;
+defm Int_SQRTSD : SD_IntUnary0x51, sqrtsd , int_x86_sse2_sqrt_sd;
defm Int_RSQRTSS : SS_IntUnary0x52, rsqrtss, int_x86_sse_rsqrt_ss;
defm Int_RCPSS : SS_IntUnary0x53, rcpss , int_x86_sse_rcp_ss;
-
-def Int_SQRTSDr : SD_Intr0x51, sqrtsd {$src, $dst|$dst, $src},
- int_x86_sse2_sqrt_sd;
-def Int_SQRTSDm : SD_Intm0x51, sqrtsd {$src, $dst|$dst, $src},
- int_x86_sse2_sqrt_sd;
-
let isTwoAddress = 1 in {
let isCommutable = 1 in {
def Int_MAXSSrr : SS_Intrr0x5F, maxss {$src2, $dst|$dst, $src2},
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.137 - 1.138
---
Log message:
Pull operand info up into parent class for scalar sse intrinsics.
---
Diffs of the changes: (+41 -61)
X86InstrSSE.td | 102 ++---
1 files changed, 41 insertions(+), 61 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.137
llvm/lib/Target/X86/X86InstrSSE.td:1.138
--- llvm/lib/Target/X86/X86InstrSSE.td:1.137Sat Oct 7 00:19:31 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Sat Oct 7 00:26:13 2006
@@ -207,17 +207,21 @@
[(set VR128:$dst, (v2f64 (IntId (load addr:$src];
}
-class SS_Intrrbits8 o, string asm, Intrinsic IntId
- : SSIo, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
+class SS_Intrrbits8 o, string OpcodeStr, Intrinsic IntId
+ : SSIo, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
+!strconcat(OpcodeStr, {$src2, $dst|$dst, $src2}),
[(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))];
-class SS_Intrmbits8 o, string asm, Intrinsic IntId
- : SSIo, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f32mem:$src2), asm,
+class SS_Intrmbits8 o, string OpcodeStr, Intrinsic IntId
+ : SSIo, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f32mem:$src2),
+!strconcat(OpcodeStr, {$src2, $dst|$dst, $src2}),
[(set VR128:$dst, (v4f32 (IntId VR128:$src1, (load addr:$src2];
-class SD_Intrrbits8 o, string asm, Intrinsic IntId
- : SDIo, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
+class SD_Intrrbits8 o, string OpcodeStr, Intrinsic IntId
+ : SDIo, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
+!strconcat(OpcodeStr, {$src2, $dst|$dst, $src2}),
[(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))];
-class SD_Intrmbits8 o, string asm, Intrinsic IntId
- : SDIo, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2), asm,
+class SD_Intrmbits8 o, string OpcodeStr, Intrinsic IntId
+ : SDIo, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
+!strconcat(OpcodeStr, {$src2, $dst|$dst, $src2}),
[(set VR128:$dst, (v2f64 (IntId VR128:$src1, (load addr:$src2];
class PS_Intrbits8 o, string asm, Intrinsic IntId
@@ -410,42 +414,26 @@
// Aliases to match intrinsics which expect XMM operand(s).
let isTwoAddress = 1 in {
let isCommutable = 1 in {
-def Int_ADDSSrr : SS_Intrr0x58, addss {$src2, $dst|$dst, $src2},
- int_x86_sse_add_ss;
-def Int_ADDSDrr : SD_Intrr0x58, addsd {$src2, $dst|$dst, $src2},
- int_x86_sse2_add_sd;
-def Int_MULSSrr : SS_Intrr0x59, mulss {$src2, $dst|$dst, $src2},
- int_x86_sse_mul_ss;
-def Int_MULSDrr : SD_Intrr0x59, mulsd {$src2, $dst|$dst, $src2},
- int_x86_sse2_mul_sd;
-}
-
-def Int_ADDSSrm : SS_Intrm0x58, addss {$src2, $dst|$dst, $src2},
- int_x86_sse_add_ss;
-def Int_ADDSDrm : SD_Intrm0x58, addsd {$src2, $dst|$dst, $src2},
- int_x86_sse2_add_sd;
-def Int_MULSSrm : SS_Intrm0x59, mulss {$src2, $dst|$dst, $src2},
- int_x86_sse_mul_ss;
-def Int_MULSDrm : SD_Intrm0x59, mulsd {$src2, $dst|$dst, $src2},
- int_x86_sse2_mul_sd;
-
-def Int_DIVSSrr : SS_Intrr0x5E, divss {$src2, $dst|$dst, $src2},
- int_x86_sse_div_ss;
-def Int_DIVSSrm : SS_Intrm0x5E, divss {$src2, $dst|$dst, $src2},
- int_x86_sse_div_ss;
-def Int_DIVSDrr : SD_Intrr0x5E, divsd {$src2, $dst|$dst, $src2},
- int_x86_sse2_div_sd;
-def Int_DIVSDrm : SD_Intrm0x5E, divsd {$src2, $dst|$dst, $src2},
- int_x86_sse2_div_sd;
-
-def Int_SUBSSrr : SS_Intrr0x5C, subss {$src2, $dst|$dst, $src2},
- int_x86_sse_sub_ss;
-def Int_SUBSSrm : SS_Intrm0x5C, subss {$src2, $dst|$dst, $src2},
- int_x86_sse_sub_ss;
-def Int_SUBSDrr : SD_Intrr0x5C, subsd {$src2, $dst|$dst, $src2},
- int_x86_sse2_sub_sd;
-def Int_SUBSDrm : SD_Intrm0x5C, subsd {$src2, $dst|$dst, $src2},
- int_x86_sse2_sub_sd;
+def Int_ADDSSrr : SS_Intrr0x58, addss, int_x86_sse_add_ss;
+def Int_ADDSDrr : SD_Intrr0x58, addsd, int_x86_sse2_add_sd;
+def Int_MULSSrr : SS_Intrr0x59, mulss, int_x86_sse_mul_ss;
+def Int_MULSDrr : SD_Intrr0x59, mulsd, int_x86_sse2_mul_sd;
+}
+
+def Int_ADDSSrm : SS_Intrm0x58, addss, int_x86_sse_add_ss;
+def Int_ADDSDrm : SD_Intrm0x58, addsd, int_x86_sse2_add_sd;
+def Int_MULSSrm : SS_Intrm0x59, mulss, int_x86_sse_mul_ss;
+def Int_MULSDrm : SD_Intrm0x59, mulsd, int_x86_sse2_mul_sd;
+
+def Int_DIVSSrr : SS_Intrr0x5E, divss, int_x86_sse_div_ss;
+def Int_DIVSSrm : SS_Intrm0x5E, divss, int_x86_sse_div_ss;
+def Int_DIVSDrr : SD_Intrr0x5E, divsd, int_x86_sse2_div_sd;
+def Int_DIVSDrm : SD_Intrm0x5E, divsd,
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.138 - 1.139
---
Log message:
remove dead/duplicate instructions
---
Diffs of the changes: (+0 -21)
X86InstrSSE.td | 21 -
1 files changed, 21 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.138
llvm/lib/Target/X86/X86InstrSSE.td:1.139
--- llvm/lib/Target/X86/X86InstrSSE.td:1.138Sat Oct 7 00:26:13 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Sat Oct 7 00:41:52 2006
@@ -390,27 +390,6 @@
sqrtsd {$src, $dst|$dst, $src},
[(set FR64:$dst, (fsqrt (loadf64 addr:$src)))];
-let isTwoAddress = 1 in {
-let isCommutable = 1 in {
-def MAXSSrr : SSI0x5F, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
- maxss {$src2, $dst|$dst, $src2}, [];
-def MAXSDrr : SDI0x5F, MRMSrcReg, (ops FR64:$dst, FR32:$src1, FR64:$src2),
- maxsd {$src2, $dst|$dst, $src2}, [];
-def MINSSrr : SSI0x5D, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
- minss {$src2, $dst|$dst, $src2}, [];
-def MINSDrr : SDI0x5D, MRMSrcReg, (ops FR64:$dst, FR32:$src1, FR64:$src2),
- minsd {$src2, $dst|$dst, $src2}, [];
-}
-def MAXSSrm : SSI0x5F, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
- maxss {$src2, $dst|$dst, $src2}, [];
-def MAXSDrm : SDI0x5F, MRMSrcMem, (ops FR64:$dst, FR32:$src1, f64mem:$src2),
- maxsd {$src2, $dst|$dst, $src2}, [];
-def MINSSrm : SSI0x5D, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
- minss {$src2, $dst|$dst, $src2}, [];
-def MINSDrm : SDI0x5D, MRMSrcMem, (ops FR64:$dst, FR32:$src1, f64mem:$src2),
- minsd {$src2, $dst|$dst, $src2}, [];
-}
-
// Aliases to match intrinsics which expect XMM operand(s).
let isTwoAddress = 1 in {
let isCommutable = 1 in {
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.139 - 1.140
---
Log message:
Factor operands into packed unary classes
---
Diffs of the changes: (+21 -25)
X86InstrSSE.td | 46 +-
1 files changed, 21 insertions(+), 25 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.139
llvm/lib/Target/X86/X86InstrSSE.td:1.140
--- llvm/lib/Target/X86/X86InstrSSE.td:1.139Sat Oct 7 00:41:52 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Sat Oct 7 00:47:20 2006
@@ -237,17 +237,21 @@
: PDIo, MRMSrcMem, (ops VR128:$dst, f64mem:$src), asm,
[(set VR128:$dst, (IntId (loadv2f64 addr:$src)))];
-class PS_Intrrbits8 o, string asm, Intrinsic IntId
- : PSIo, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
+class PS_Intrrbits8 o, string OpcodeStr, Intrinsic IntId
+ : PSIo, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
+!strconcat(OpcodeStr, {$src2, $dst|$dst, $src2}),
[(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))];
-class PS_Intrmbits8 o, string asm, Intrinsic IntId
- : PSIo, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f32mem:$src2), asm,
+class PS_Intrmbits8 o, string OpcodeStr, Intrinsic IntId
+ : PSIo, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f32mem:$src2),
+!strconcat(OpcodeStr, {$src2, $dst|$dst, $src2}),
[(set VR128:$dst, (IntId VR128:$src1, (loadv4f32 addr:$src2)))];
-class PD_Intrrbits8 o, string asm, Intrinsic IntId
- : PDIo, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
+class PD_Intrrbits8 o, string OpcodeStr, Intrinsic IntId
+ : PDIo, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
+!strconcat(OpcodeStr, {$src2, $dst|$dst, $src2}),
[(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))];
-class PD_Intrmbits8 o, string asm, Intrinsic IntId
- : PDIo, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2), asm,
+class PD_Intrmbits8 o, string OpcodeStr, Intrinsic IntId
+ : PDIo, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
+!strconcat(OpcodeStr, {$src2, $dst|$dst, $src2}),
[(set VR128:$dst, (IntId VR128:$src1, (loadv2f64 addr:$src2)))];
class S3D_Intrrbits8 o, string asm, Intrinsic IntId
@@ -1045,23 +1049,15 @@
let isTwoAddress = 1 in {
let isCommutable = 1 in {
-def MAXPSrr : PS_Intrr0x5F, maxps {$src2, $dst|$dst, $src2},
- int_x86_sse_max_ps;
-def MAXPDrr : PD_Intrr0x5F, maxpd {$src2, $dst|$dst, $src2},
- int_x86_sse2_max_pd;
-def MINPSrr : PS_Intrr0x5D, minps {$src2, $dst|$dst, $src2},
- int_x86_sse_min_ps;
-def MINPDrr : PD_Intrr0x5D, minpd {$src2, $dst|$dst, $src2},
- int_x86_sse2_min_pd;
-}
-def MAXPSrm : PS_Intrm0x5F, maxps {$src2, $dst|$dst, $src2},
- int_x86_sse_max_ps;
-def MAXPDrm : PD_Intrm0x5F, maxpd {$src2, $dst|$dst, $src2},
- int_x86_sse2_max_pd;
-def MINPSrm : PS_Intrm0x5D, minps {$src2, $dst|$dst, $src2},
- int_x86_sse_min_ps;
-def MINPDrm : PD_Intrm0x5D, minpd {$src2, $dst|$dst, $src2},
- int_x86_sse2_min_pd;
+def MAXPSrr : PS_Intrr0x5F, maxps, int_x86_sse_max_ps;
+def MAXPDrr : PD_Intrr0x5F, maxpd, int_x86_sse2_max_pd;
+def MINPSrr : PS_Intrr0x5D, minps, int_x86_sse_min_ps;
+def MINPDrr : PD_Intrr0x5D, minpd, int_x86_sse2_min_pd;
+}
+def MAXPSrm : PS_Intrm0x5F, maxps, int_x86_sse_max_ps;
+def MAXPDrm : PD_Intrm0x5F, maxpd, int_x86_sse2_max_pd;
+def MINPSrm : PS_Intrm0x5D, minps, int_x86_sse_min_ps;
+def MINPDrm : PD_Intrm0x5D, minpd, int_x86_sse2_min_pd;
}
// Logical
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.140 - 1.141
---
Log message:
simplify patterns by merging in operand info
---
Diffs of the changes: (+30 -34)
X86InstrSSE.td | 64 ++---
1 files changed, 30 insertions(+), 34 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.140
llvm/lib/Target/X86/X86InstrSSE.td:1.141
--- llvm/lib/Target/X86/X86InstrSSE.td:1.140Sat Oct 7 00:47:20 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Sat Oct 7 00:50:25 2006
@@ -224,17 +224,21 @@
!strconcat(OpcodeStr, {$src2, $dst|$dst, $src2}),
[(set VR128:$dst, (v2f64 (IntId VR128:$src1, (load addr:$src2];
-class PS_Intrbits8 o, string asm, Intrinsic IntId
- : PSIo, MRMSrcReg, (ops VR128:$dst, VR128:$src), asm,
+class PS_Intrbits8 o, string OpcodeStr, Intrinsic IntId
+ : PSIo, MRMSrcReg, (ops VR128:$dst, VR128:$src),
+!strconcat(OpcodeStr, {$src, $dst|$dst, $src}),
[(set VR128:$dst, (IntId VR128:$src))];
-class PS_Intmbits8 o, string asm, Intrinsic IntId
- : PSIo, MRMSrcMem, (ops VR128:$dst, f32mem:$src), asm,
+class PS_Intmbits8 o, string OpcodeStr, Intrinsic IntId
+ : PSIo, MRMSrcMem, (ops VR128:$dst, f32mem:$src),
+!strconcat(OpcodeStr, {$src, $dst|$dst, $src}),
[(set VR128:$dst, (IntId (loadv4f32 addr:$src)))];
-class PD_Intrbits8 o, string asm, Intrinsic IntId
- : PDIo, MRMSrcReg, (ops VR128:$dst, VR128:$src), asm,
+class PD_Intrbits8 o, string OpcodeStr, Intrinsic IntId
+ : PDIo, MRMSrcReg, (ops VR128:$dst, VR128:$src),
+!strconcat(OpcodeStr, {$src, $dst|$dst, $src}),
[(set VR128:$dst, (IntId VR128:$src))];
-class PD_Intmbits8 o, string asm, Intrinsic IntId
- : PDIo, MRMSrcMem, (ops VR128:$dst, f64mem:$src), asm,
+class PD_Intmbits8 o, string OpcodeStr, Intrinsic IntId
+ : PDIo, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
+!strconcat(OpcodeStr, {$src, $dst|$dst, $src}),
[(set VR128:$dst, (IntId (loadv2f64 addr:$src)))];
class PS_Intrrbits8 o, string OpcodeStr, Intrinsic IntId
@@ -1029,35 +1033,27 @@
(loadv2f64 addr:$src2)))];
}
-def SQRTPSr : PS_Intr0x51, sqrtps {$src, $dst|$dst, $src},
- int_x86_sse_sqrt_ps;
-def SQRTPSm : PS_Intm0x51, sqrtps {$src, $dst|$dst, $src},
- int_x86_sse_sqrt_ps;
-def SQRTPDr : PD_Intr0x51, sqrtpd {$src, $dst|$dst, $src},
- int_x86_sse2_sqrt_pd;
-def SQRTPDm : PD_Intm0x51, sqrtpd {$src, $dst|$dst, $src},
- int_x86_sse2_sqrt_pd;
-
-def RSQRTPSr : PS_Intr0x52, rsqrtps {$src, $dst|$dst, $src},
- int_x86_sse_rsqrt_ps;
-def RSQRTPSm : PS_Intm0x52, rsqrtps {$src, $dst|$dst, $src},
- int_x86_sse_rsqrt_ps;
-def RCPPSr : PS_Intr0x53, rcpps {$src, $dst|$dst, $src},
- int_x86_sse_rcp_ps;
-def RCPPSm : PS_Intm0x53, rcpps {$src, $dst|$dst, $src},
- int_x86_sse_rcp_ps;
+def SQRTPSr : PS_Intr0x51, sqrtps, int_x86_sse_sqrt_ps;
+def SQRTPSm : PS_Intm0x51, sqrtps, int_x86_sse_sqrt_ps;
+def SQRTPDr : PD_Intr0x51, sqrtpd, int_x86_sse2_sqrt_pd;
+def SQRTPDm : PD_Intm0x51, sqrtpd, int_x86_sse2_sqrt_pd;
+
+def RSQRTPSr : PS_Intr0x52, rsqrtps, int_x86_sse_rsqrt_ps;
+def RSQRTPSm : PS_Intm0x52, rsqrtps, int_x86_sse_rsqrt_ps;
+def RCPPSr : PS_Intr0x53, rcpps, int_x86_sse_rcp_ps;
+def RCPPSm : PS_Intm0x53, rcpps, int_x86_sse_rcp_ps;
let isTwoAddress = 1 in {
let isCommutable = 1 in {
-def MAXPSrr : PS_Intrr0x5F, maxps, int_x86_sse_max_ps;
-def MAXPDrr : PD_Intrr0x5F, maxpd, int_x86_sse2_max_pd;
-def MINPSrr : PS_Intrr0x5D, minps, int_x86_sse_min_ps;
-def MINPDrr : PD_Intrr0x5D, minpd, int_x86_sse2_min_pd;
-}
-def MAXPSrm : PS_Intrm0x5F, maxps, int_x86_sse_max_ps;
-def MAXPDrm : PD_Intrm0x5F, maxpd, int_x86_sse2_max_pd;
-def MINPSrm : PS_Intrm0x5D, minps, int_x86_sse_min_ps;
-def MINPDrm : PD_Intrm0x5D, minpd, int_x86_sse2_min_pd;
+def MAXPSrr : PS_Intrr0x5F, maxps, int_x86_sse_max_ps;
+def MAXPDrr : PD_Intrr0x5F, maxpd, int_x86_sse2_max_pd;
+def MINPSrr : PS_Intrr0x5D, minps, int_x86_sse_min_ps;
+def MINPDrr : PD_Intrr0x5D, minpd, int_x86_sse2_min_pd;
+}
+def MAXPSrm : PS_Intrm0x5F, maxps, int_x86_sse_max_ps;
+def MAXPDrm : PD_Intrm0x5F, maxpd, int_x86_sse2_max_pd;
+def MINPSrm : PS_Intrm0x5D, minps, int_x86_sse_min_ps;
+def MINPDrm : PD_Intrm0x5D, minpd, int_x86_sse2_min_pd;
}
// Logical
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.132 - 1.133
---
Log message:
These don't have immediate operands.
---
Diffs of the changes: (+64 -64)
X86InstrSSE.td | 128 -
1 files changed, 64 insertions(+), 64 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.132
llvm/lib/Target/X86/X86InstrSSE.td:1.133
--- llvm/lib/Target/X86/X86InstrSSE.td:1.132Sun Sep 10 21:19:56 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Tue Oct 3 01:55:11 2006
@@ -1603,38 +1603,38 @@
}
let isTwoAddress = 1 in {
-def PSLLWrr : PDIi80xF1, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
VR128:$src2),
-psllw {$src2, $dst|$dst, $src2},
-[(set VR128:$dst, (int_x86_sse2_psll_w VR128:$src1,
- VR128:$src2))];
-def PSLLWrm : PDIi80xF1, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
-psllw {$src2, $dst|$dst, $src2},
-[(set VR128:$dst, (int_x86_sse2_psll_w VR128:$src1,
- (bc_v4i32 (loadv2i64 addr:$src2];
+def PSLLWrr : PDI0xF1, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
+ psllw {$src2, $dst|$dst, $src2},
+ [(set VR128:$dst, (int_x86_sse2_psll_w VR128:$src1,
+ VR128:$src2))];
+def PSLLWrm : PDI0xF1, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
+ psllw {$src2, $dst|$dst, $src2},
+ [(set VR128:$dst, (int_x86_sse2_psll_w VR128:$src1,
+ (bc_v4i32 (loadv2i64 addr:$src2];
def PSLLWri : PDIi80x71, MRM6r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
psllw {$src2, $dst|$dst, $src2},
[(set VR128:$dst, (int_x86_sse2_psll_w VR128:$src1,
(scalar_to_vector (i32 imm:$src2];
-def PSLLDrr : PDIi80xF2, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
VR128:$src2),
-pslld {$src2, $dst|$dst, $src2},
-[(set VR128:$dst, (int_x86_sse2_psll_d VR128:$src1,
- VR128:$src2))];
-def PSLLDrm : PDIi80xF2, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
-pslld {$src2, $dst|$dst, $src2},
-[(set VR128:$dst, (int_x86_sse2_psll_d VR128:$src1,
- (bc_v4i32 (loadv2i64 addr:$src2];
+def PSLLDrr : PDI0xF2, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
+ pslld {$src2, $dst|$dst, $src2},
+ [(set VR128:$dst, (int_x86_sse2_psll_d VR128:$src1,
+ VR128:$src2))];
+def PSLLDrm : PDI0xF2, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
+ pslld {$src2, $dst|$dst, $src2},
+ [(set VR128:$dst, (int_x86_sse2_psll_d VR128:$src1,
+ (bc_v4i32 (loadv2i64 addr:$src2];
def PSLLDri : PDIi80x72, MRM6r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
pslld {$src2, $dst|$dst, $src2},
[(set VR128:$dst, (int_x86_sse2_psll_d VR128:$src1,
(scalar_to_vector (i32 imm:$src2];
-def PSLLQrr : PDIi80xF3, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
VR128:$src2),
-psllq {$src2, $dst|$dst, $src2},
-[(set VR128:$dst, (int_x86_sse2_psll_q VR128:$src1,
- VR128:$src2))];
-def PSLLQrm : PDIi80xF3, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
-psllq {$src2, $dst|$dst, $src2},
-[(set VR128:$dst, (int_x86_sse2_psll_q VR128:$src1,
- (bc_v4i32 (loadv2i64 addr:$src2];
+def PSLLQrr : PDI0xF3, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
+ psllq {$src2, $dst|$dst, $src2},
+ [(set VR128:$dst, (int_x86_sse2_psll_q VR128:$src1,
+ VR128:$src2))];
+def PSLLQrm : PDI0xF3, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
+ psllq {$src2, $dst|$dst, $src2},
+ [(set VR128:$dst, (int_x86_sse2_psll_q VR128:$src1,
+ (bc_v4i32 (loadv2i64 addr:$src2];
def PSLLQri : PDIi80x73, MRM6r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
psllq {$src2, $dst|$dst, $src2},
[(set VR128:$dst, (int_x86_sse2_psll_q VR128:$src1,
@@ -1642,38 +1642,38 @@
def PSLLDQri : PDIi80x73, MRM7r, (ops VR128:$dst, VR128:$src1,
i32i8imm:$src2),
pslldq {$src2, $dst|$dst, $src2}, [];
-def PSRLWrr : PDIi80xD1, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
VR128:$src2),
-psrlw {$src2, $dst|$dst, $src2},
-
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.127 - 1.128
---
Log message:
Should just use xorps to clear XMM registers for all data types. pxor is also
one byte longer.
---
Diffs of the changes: (+10 -14)
X86InstrSSE.td | 24 ++--
1 files changed, 10 insertions(+), 14 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.127
llvm/lib/Target/X86/X86InstrSSE.td:1.128
--- llvm/lib/Target/X86/X86InstrSSE.td:1.127Wed Jun 28 19:34:23 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Thu Jun 29 13:04:54 2006
@@ -2109,15 +2109,9 @@
// Alias instructions that map zero vector to pxor / xorp* for sse.
// FIXME: remove when we can teach regalloc that xor reg, reg is ok.
-def V_SET0_PI : PDI0xEF, MRMInitReg, (ops VR128:$dst),
-pxor $dst, $dst,
-[(set VR128:$dst, (v2i64 immAllZerosV))];
-def V_SET0_PS : PSI0x57, MRMInitReg, (ops VR128:$dst),
-xorps $dst, $dst,
-[(set VR128:$dst, (v4f32 immAllZerosV))];
-def V_SET0_PD : PDI0x57, MRMInitReg, (ops VR128:$dst),
-xorps $dst, $dst,
-[(set VR128:$dst, (v2f64 immAllZerosV))];
+def V_SET0 : PSI0x57, MRMInitReg, (ops VR128:$dst),
+ xorps $dst, $dst,
+ [(set VR128:$dst, (v4f32 immAllZerosV))];
def V_SETALLONES : PDI0x76, MRMInitReg, (ops VR128:$dst),
pcmpeqd $dst, $dst,
@@ -2265,9 +2259,11 @@
def : Pat(v2i64 (undef)), (IMPLICIT_DEF_VR128), Requires[HasSSE2];
// 128-bit vector all zero's.
-def : Pat(v16i8 immAllZerosV), (V_SET0_PI), Requires[HasSSE2];
-def : Pat(v8i16 immAllZerosV), (V_SET0_PI), Requires[HasSSE2];
-def : Pat(v4i32 immAllZerosV), (V_SET0_PI), Requires[HasSSE2];
+def : Pat(v16i8 immAllZerosV), (V_SET0), Requires[HasSSE2];
+def : Pat(v8i16 immAllZerosV), (V_SET0), Requires[HasSSE2];
+def : Pat(v4i32 immAllZerosV), (V_SET0), Requires[HasSSE2];
+def : Pat(v2i64 immAllZerosV), (V_SET0), Requires[HasSSE2];
+def : Pat(v2f64 immAllZerosV), (V_SET0), Requires[HasSSE2];
// 128-bit vector all one's.
def : Pat(v16i8 immAllOnesV), (V_SETALLONES), Requires[HasSSE2];
@@ -2365,10 +2361,10 @@
// Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
def : Pat(v2f64 (vector_shuffle immAllZerosV,
(v2f64 (scalar_to_vector FR64:$src)), MOVL_shuffle_mask)),
- (MOVLSD2PDrr (V_SET0_PD), FR64:$src), Requires[HasSSE2];
+ (MOVLSD2PDrr (V_SET0), FR64:$src), Requires[HasSSE2];
def : Pat(v4f32 (vector_shuffle immAllZerosV,
(v4f32 (scalar_to_vector FR32:$src)), MOVL_shuffle_mask)),
- (MOVLSS2PSrr (V_SET0_PS), FR32:$src), Requires[HasSSE2];
+ (MOVLSS2PSrr (V_SET0), FR32:$src), Requires[HasSSE2];
}
// Splat v2f64 / v2i64
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86: X86InstrSSE.td updated: 1.126 - 1.127 --- Log message: Always use xorps to clear XMM registers. --- Diffs of the changes: (+1 -1) X86InstrSSE.td |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/X86/X86InstrSSE.td diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.126 llvm/lib/Target/X86/X86InstrSSE.td:1.127 --- llvm/lib/Target/X86/X86InstrSSE.td:1.126Mon Jun 19 19:25:29 2006 +++ llvm/lib/Target/X86/X86InstrSSE.td Wed Jun 28 19:34:23 2006 @@ -2116,7 +2116,7 @@ xorps $dst, $dst, [(set VR128:$dst, (v4f32 immAllZerosV))]; def V_SET0_PD : PDI0x57, MRMInitReg, (ops VR128:$dst), -xorpd $dst, $dst, +xorps $dst, $dst, [(set VR128:$dst, (v2f64 immAllZerosV))]; def V_SETALLONES : PDI0x76, MRMInitReg, (ops VR128:$dst), ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.123 - 1.124
---
Log message:
Minor clean up.
---
Diffs of the changes: (+3 -6)
X86InstrSSE.td |9 +++--
1 files changed, 3 insertions(+), 6 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.123
llvm/lib/Target/X86/X86InstrSSE.td:1.124
--- llvm/lib/Target/X86/X86InstrSSE.td:1.123Thu Jun 15 03:14:54 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Mon Jun 19 14:25:30 2006
@@ -173,13 +173,10 @@
class PDIbits8 o, Format F, dag ops, string asm, listdag pattern
: Io, F, ops, asm, pattern, TB, OpSize, Requires[HasSSE2];
class PSIi8bits8 o, Format F, dag ops, string asm, listdag pattern
- : X86Insto, F, Imm8, ops, asm, TB, Requires[HasSSE1] {
- let Pattern = pattern;
-}
+ : Ii8o, F, ops, asm, pattern, TB, Requires[HasSSE1];
class PDIi8bits8 o, Format F, dag ops, string asm, listdag pattern
- : X86Insto, F, Imm8, ops, asm, TB, OpSize, Requires[HasSSE2] {
- let Pattern = pattern;
-}
+ : Ii8o, F, ops, asm, pattern, TB, OpSize, Requires[HasSSE2];
+
class S3SIbits8 o, Format F, dag ops, string asm, listdag pattern
: Io, F, ops, asm, pattern, XS, Requires[HasSSE3];
class S3DIbits8 o, Format F, dag ops, string asm, listdag pattern
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86: X86InstrSSE.td updated: 1.124 - 1.125 --- Log message: Fix some mismatched type constraints --- Diffs of the changes: (+6 -6) X86InstrSSE.td | 12 ++-- 1 files changed, 6 insertions(+), 6 deletions(-) Index: llvm/lib/Target/X86/X86InstrSSE.td diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.124 llvm/lib/Target/X86/X86InstrSSE.td:1.125 --- llvm/lib/Target/X86/X86InstrSSE.td:1.124Mon Jun 19 14:25:30 2006 +++ llvm/lib/Target/X86/X86InstrSSE.td Mon Jun 19 19:12:37 2006 @@ -2312,21 +2312,21 @@ Requires[HasSSE2]; def : Pat(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src), Requires[HasSSE2]; -def : Pat(v8i16 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src), +def : Pat(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src), Requires[HasSSE2]; -def : Pat(v8i16 (bitconvert (v4i32 VR128:$src))), (v4i32 VR128:$src), +def : Pat(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src), Requires[HasSSE2]; -def : Pat(v8i16 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src), +def : Pat(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src), Requires[HasSSE2]; def : Pat(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src), Requires[HasSSE2]; def : Pat(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src), Requires[HasSSE2]; -def : Pat(v16i8 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src), +def : Pat(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src), Requires[HasSSE2]; -def : Pat(v16i8 (bitconvert (v4i32 VR128:$src))), (v4i32 VR128:$src), +def : Pat(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src), Requires[HasSSE2]; -def : Pat(v16i8 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src), +def : Pat(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src), Requires[HasSSE2]; def : Pat(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src), Requires[HasSSE2]; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.125 - 1.126
---
Log message:
Remove some ugly now-redundant casts.
---
Diffs of the changes: (+54 -54)
X86InstrSSE.td | 108 -
1 files changed, 54 insertions(+), 54 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.125
llvm/lib/Target/X86/X86InstrSSE.td:1.126
--- llvm/lib/Target/X86/X86InstrSSE.td:1.125Mon Jun 19 19:12:37 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Mon Jun 19 19:25:29 2006
@@ -2265,16 +2265,16 @@
def : Pat(v2i64 (undef)), (IMPLICIT_DEF_VR128), Requires[HasSSE2];
// 128-bit vector all zero's.
-def : Pat(v16i8 immAllZerosV), (v16i8 (V_SET0_PI)), Requires[HasSSE2];
-def : Pat(v8i16 immAllZerosV), (v8i16 (V_SET0_PI)), Requires[HasSSE2];
-def : Pat(v4i32 immAllZerosV), (v4i32 (V_SET0_PI)), Requires[HasSSE2];
+def : Pat(v16i8 immAllZerosV), (V_SET0_PI), Requires[HasSSE2];
+def : Pat(v8i16 immAllZerosV), (V_SET0_PI), Requires[HasSSE2];
+def : Pat(v4i32 immAllZerosV), (V_SET0_PI), Requires[HasSSE2];
// 128-bit vector all one's.
-def : Pat(v16i8 immAllOnesV), (v16i8 (V_SETALLONES)), Requires[HasSSE2];
-def : Pat(v8i16 immAllOnesV), (v8i16 (V_SETALLONES)), Requires[HasSSE2];
-def : Pat(v4i32 immAllOnesV), (v4i32 (V_SETALLONES)), Requires[HasSSE2];
-def : Pat(v2i64 immAllOnesV), (v2i64 (V_SETALLONES)), Requires[HasSSE2];
-def : Pat(v4f32 immAllOnesV), (v4f32 (V_SETALLONES)), Requires[HasSSE1];
+def : Pat(v16i8 immAllOnesV), (V_SETALLONES), Requires[HasSSE2];
+def : Pat(v8i16 immAllOnesV), (V_SETALLONES), Requires[HasSSE2];
+def : Pat(v4i32 immAllOnesV), (V_SETALLONES), Requires[HasSSE2];
+def : Pat(v2i64 immAllOnesV), (V_SETALLONES), Requires[HasSSE2];
+def : Pat(v4f32 immAllOnesV), (V_SETALLONES), Requires[HasSSE1];
// Store 128-bit integer vector values.
def : Pat(store (v16i8 VR128:$src), addr:$dst),
@@ -2286,9 +2286,9 @@
// Scalar to v8i16 / v16i8. The source may be a GR32, but only the lower 8 or
// 16-bits matter.
-def : Pat(v8i16 (X86s2vec GR32:$src)), (v8i16 (MOVDI2PDIrr GR32:$src)),
+def : Pat(v8i16 (X86s2vec GR32:$src)), (MOVDI2PDIrr GR32:$src),
Requires[HasSSE2];
-def : Pat(v16i8 (X86s2vec GR32:$src)), (v16i8 (MOVDI2PDIrr GR32:$src)),
+def : Pat(v16i8 (X86s2vec GR32:$src)), (MOVDI2PDIrr GR32:$src),
Requires[HasSSE2];
// bit_convert
@@ -2358,155 +2358,155 @@
let AddedComplexity = 20 in {
def : Pat(v8i16 (vector_shuffle immAllZerosV,
(v8i16 (X86s2vec GR32:$src)), MOVL_shuffle_mask)),
- (v8i16 (MOVZDI2PDIrr GR32:$src)), Requires[HasSSE2];
+ (MOVZDI2PDIrr GR32:$src), Requires[HasSSE2];
def : Pat(v16i8 (vector_shuffle immAllZerosV,
(v16i8 (X86s2vec GR32:$src)), MOVL_shuffle_mask)),
- (v16i8 (MOVZDI2PDIrr GR32:$src)), Requires[HasSSE2];
+ (MOVZDI2PDIrr GR32:$src), Requires[HasSSE2];
// Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
def : Pat(v2f64 (vector_shuffle immAllZerosV,
(v2f64 (scalar_to_vector FR64:$src)), MOVL_shuffle_mask)),
- (v2f64 (MOVLSD2PDrr (V_SET0_PD), FR64:$src)), Requires[HasSSE2];
+ (MOVLSD2PDrr (V_SET0_PD), FR64:$src), Requires[HasSSE2];
def : Pat(v4f32 (vector_shuffle immAllZerosV,
(v4f32 (scalar_to_vector FR32:$src)), MOVL_shuffle_mask)),
- (v4f32 (MOVLSS2PSrr (V_SET0_PS), FR32:$src)), Requires[HasSSE2];
+ (MOVLSS2PSrr (V_SET0_PS), FR32:$src), Requires[HasSSE2];
}
// Splat v2f64 / v2i64
let AddedComplexity = 10 in {
def : Pat(vector_shuffle (v2f64 VR128:$src), (undef), SSE_splat_v2_mask:$sm),
- (v2f64 (UNPCKLPDrr VR128:$src, VR128:$src)), Requires[HasSSE2];
+ (UNPCKLPDrr VR128:$src, VR128:$src), Requires[HasSSE2];
def : Pat(vector_shuffle (v2i64 VR128:$src), (undef), SSE_splat_v2_mask:$sm),
- (v2i64 (PUNPCKLQDQrr VR128:$src, VR128:$src)), Requires[HasSSE2];
+ (PUNPCKLQDQrr VR128:$src, VR128:$src), Requires[HasSSE2];
}
// Splat v4f32
def : Pat(vector_shuffle (v4f32 VR128:$src), (undef), SSE_splat_mask:$sm),
- (v4f32 (SHUFPSrri VR128:$src, VR128:$src, SSE_splat_mask:$sm)),
+ (SHUFPSrri VR128:$src, VR128:$src, SSE_splat_mask:$sm),
Requires[HasSSE1];
// Special unary SHUFPSrri case.
// FIXME: when we want non two-address code, then we should use PSHUFD?
def : Pat(vector_shuffle (v4f32 VR128:$src1), (undef),
SHUFP_unary_shuffle_mask:$sm),
- (v4f32 (SHUFPSrri VR128:$src1, VR128:$src1,
SHUFP_unary_shuffle_mask:$sm)),
+ (SHUFPSrri VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm),
Requires[HasSSE1];
// Unary v4f32 shuffle with PSHUF* in order to fold a load.
def : Pat(vector_shuffle (loadv4f32 addr:$src1), (undef),
SHUFP_unary_shuffle_mask:$sm),
- (v4f32 (PSHUFDmi addr:$src1, SHUFP_unary_shuffle_mask:$sm)),
+ (PSHUFDmi addr:$src1,
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td X86RegisterInfo.cpp
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.121 - 1.122
X86RegisterInfo.cpp updated: 1.154 - 1.155
---
Log message:
Rename instructions for consistency sake.
---
Diffs of the changes: (+102 -92)
X86InstrSSE.td | 164 ++--
X86RegisterInfo.cpp | 30 ++---
2 files changed, 102 insertions(+), 92 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.121
llvm/lib/Target/X86/X86InstrSSE.td:1.122
--- llvm/lib/Target/X86/X86InstrSSE.td:1.121Tue May 30 19:51:37 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Wed May 31 14:00:07 2006
@@ -534,20 +534,20 @@
Requires[HasSSE2];
// Match intrinsics which expect XMM operand(s).
-def CVTSS2SIrr: SSI0x2D, MRMSrcReg, (ops GR32:$dst, VR128:$src),
-cvtss2si {$src, $dst|$dst, $src},
-[(set GR32:$dst, (int_x86_sse_cvtss2si VR128:$src))];
-def CVTSS2SIrm: SSI0x2D, MRMSrcMem, (ops GR32:$dst, f32mem:$src),
-cvtss2si {$src, $dst|$dst, $src},
-[(set GR32:$dst, (int_x86_sse_cvtss2si
- (loadv4f32 addr:$src)))];
-def CVTSD2SIrr: SDI0x2D, MRMSrcReg, (ops GR32:$dst, VR128:$src),
-cvtsd2si {$src, $dst|$dst, $src},
-[(set GR32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))];
-def CVTSD2SIrm: SDI0x2D, MRMSrcMem, (ops GR32:$dst, f128mem:$src),
-cvtsd2si {$src, $dst|$dst, $src},
-[(set GR32:$dst, (int_x86_sse2_cvtsd2si
- (loadv2f64 addr:$src)))];
+def Int_CVTSS2SIrr: SSI0x2D, MRMSrcReg, (ops GR32:$dst, VR128:$src),
+cvtss2si {$src, $dst|$dst, $src},
+[(set GR32:$dst, (int_x86_sse_cvtss2si VR128:$src))];
+def Int_CVTSS2SIrm: SSI0x2D, MRMSrcMem, (ops GR32:$dst, f32mem:$src),
+cvtss2si {$src, $dst|$dst, $src},
+[(set GR32:$dst, (int_x86_sse_cvtss2si
+ (loadv4f32 addr:$src)))];
+def Int_CVTSD2SIrr: SDI0x2D, MRMSrcReg, (ops GR32:$dst, VR128:$src),
+cvtsd2si {$src, $dst|$dst, $src},
+[(set GR32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))];
+def Int_CVTSD2SIrm: SDI0x2D, MRMSrcMem, (ops GR32:$dst, f128mem:$src),
+cvtsd2si {$src, $dst|$dst, $src},
+[(set GR32:$dst, (int_x86_sse2_cvtsd2si
+ (loadv2f64 addr:$src)))];
// Aliases for intrinsics
def Int_CVTTSS2SIrr: SSI0x2C, MRMSrcReg, (ops GR32:$dst, VR128:$src),
@@ -884,81 +884,81 @@
SSE_splat_v2_mask)))];
// SSE2 instructions without OpSize prefix
-def CVTDQ2PSrr : I0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
- cvtdq2ps {$src, $dst|$dst, $src},
- [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))],
- TB, Requires[HasSSE2];
-def CVTDQ2PSrm : I0x5B, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
- cvtdq2ps {$src, $dst|$dst, $src},
- [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
- (bc_v4i32 (loadv2i64 addr:$src],
- TB, Requires[HasSSE2];
+def Int_CVTDQ2PSrr : I0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
+ cvtdq2ps {$src, $dst|$dst, $src},
+ [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))],
+ TB, Requires[HasSSE2];
+def Int_CVTDQ2PSrm : I0x5B, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
+ cvtdq2ps {$src, $dst|$dst, $src},
+ [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
+ (bc_v4i32 (loadv2i64 addr:$src],
+ TB, Requires[HasSSE2];
// SSE2 instructions with XS prefix
-def CVTDQ2PDrr : I0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
- cvtdq2pd {$src, $dst|$dst, $src},
- [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))],
- XS, Requires[HasSSE2];
-def CVTDQ2PDrm : I0xE6, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
- cvtdq2pd {$src, $dst|$dst, $src},
- [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
- (bc_v4i32 (loadv2i64 addr:$src],
- XS, Requires[HasSSE2];
-
-def CVTPS2DQrr : PDI0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
- cvtps2dq {$src, $dst|$dst, $src},
- [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))];
-def CVTPS2DQrm : PDI0x5B, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
- cvtps2dq {$src, $dst|$dst, $src},
- [(set VR128:$dst, (int_x86_sse2_cvtps2dq
-(loadv4f32 addr:$src)))];
+def
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.119 - 1.120
---
Log message:
MAXP{D|S} and MINP{D|S} are commutable.
---
Diffs of the changes: (+24 -18)
X86InstrSSE.td | 42 --
1 files changed, 24 insertions(+), 18 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.119
llvm/lib/Target/X86/X86InstrSSE.td:1.120
--- llvm/lib/Target/X86/X86InstrSSE.td:1.119Tue May 30 18:34:30 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Tue May 30 18:47:30 2006
@@ -391,20 +391,22 @@
rcpss {$src, $dst|$dst, $src}, [];
let isTwoAddress = 1 in {
+let isCommutable = 1 in {
def MAXSSrr : SSI0x5F, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
maxss {$src2, $dst|$dst, $src2}, [];
-def MAXSSrm : SSI0x5F, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
- maxss {$src2, $dst|$dst, $src2}, [];
def MAXSDrr : SDI0x5F, MRMSrcReg, (ops FR64:$dst, FR32:$src1, FR64:$src2),
maxsd {$src2, $dst|$dst, $src2}, [];
-def MAXSDrm : SDI0x5F, MRMSrcMem, (ops FR64:$dst, FR32:$src1, f64mem:$src2),
- maxsd {$src2, $dst|$dst, $src2}, [];
def MINSSrr : SSI0x5D, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
minss {$src2, $dst|$dst, $src2}, [];
-def MINSSrm : SSI0x5D, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
- minss {$src2, $dst|$dst, $src2}, [];
def MINSDrr : SDI0x5D, MRMSrcReg, (ops FR64:$dst, FR32:$src1, FR64:$src2),
minsd {$src2, $dst|$dst, $src2}, [];
+}
+def MAXSSrm : SSI0x5F, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
+ maxss {$src2, $dst|$dst, $src2}, [];
+def MAXSDrm : SDI0x5F, MRMSrcMem, (ops FR64:$dst, FR32:$src1, f64mem:$src2),
+ maxsd {$src2, $dst|$dst, $src2}, [];
+def MINSSrm : SSI0x5D, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
+ minss {$src2, $dst|$dst, $src2}, [];
def MINSDrm : SDI0x5D, MRMSrcMem, (ops FR64:$dst, FR32:$src1, f64mem:$src2),
minsd {$src2, $dst|$dst, $src2}, [];
}
@@ -469,20 +471,22 @@
int_x86_sse_rcp_ss;
let isTwoAddress = 1 in {
+let isCommutable = 1 in {
def Int_MAXSSrr : SS_Intrr0x5F, maxss {$src2, $dst|$dst, $src2},
int_x86_sse_max_ss;
-def Int_MAXSSrm : SS_Intrm0x5F, maxss {$src2, $dst|$dst, $src2},
- int_x86_sse_max_ss;
def Int_MAXSDrr : SD_Intrr0x5F, maxsd {$src2, $dst|$dst, $src2},
int_x86_sse2_max_sd;
-def Int_MAXSDrm : SD_Intrm0x5F, maxsd {$src2, $dst|$dst, $src2},
- int_x86_sse2_max_sd;
def Int_MINSSrr : SS_Intrr0x5D, minss {$src2, $dst|$dst, $src2},
int_x86_sse_min_ss;
-def Int_MINSSrm : SS_Intrm0x5D, minss {$src2, $dst|$dst, $src2},
- int_x86_sse_min_ss;
def Int_MINSDrr : SD_Intrr0x5D, minsd {$src2, $dst|$dst, $src2},
int_x86_sse2_min_sd;
+}
+def Int_MAXSSrm : SS_Intrm0x5F, maxss {$src2, $dst|$dst, $src2},
+ int_x86_sse_max_ss;
+def Int_MAXSDrm : SD_Intrm0x5F, maxsd {$src2, $dst|$dst, $src2},
+ int_x86_sse2_max_sd;
+def Int_MINSSrm : SS_Intrm0x5D, minss {$src2, $dst|$dst, $src2},
+ int_x86_sse_min_ss;
def Int_MINSDrm : SD_Intrm0x5D, minsd {$src2, $dst|$dst, $src2},
int_x86_sse2_min_sd;
}
@@ -1098,20 +1102,22 @@
int_x86_sse_rcp_ps;
let isTwoAddress = 1 in {
+let isCommutable = 1 in {
def MAXPSrr : PS_Intrr0x5F, maxps {$src2, $dst|$dst, $src2},
int_x86_sse_max_ps;
-def MAXPSrm : PS_Intrm0x5F, maxps {$src2, $dst|$dst, $src2},
- int_x86_sse_max_ps;
def MAXPDrr : PD_Intrr0x5F, maxpd {$src2, $dst|$dst, $src2},
int_x86_sse2_max_pd;
-def MAXPDrm : PD_Intrm0x5F, maxpd {$src2, $dst|$dst, $src2},
- int_x86_sse2_max_pd;
def MINPSrr : PS_Intrr0x5D, minps {$src2, $dst|$dst, $src2},
int_x86_sse_min_ps;
-def MINPSrm : PS_Intrm0x5D, minps {$src2, $dst|$dst, $src2},
- int_x86_sse_min_ps;
def MINPDrr : PD_Intrr0x5D, minpd {$src2, $dst|$dst, $src2},
int_x86_sse2_min_pd;
+}
+def MAXPSrm : PS_Intrm0x5F, maxps {$src2, $dst|$dst, $src2},
+ int_x86_sse_max_ps;
+def MAXPDrm : PD_Intrm0x5F, maxpd {$src2, $dst|$dst, $src2},
+ int_x86_sse2_max_pd;
+def MINPSrm : PS_Intrm0x5D, minps {$src2, $dst|$dst, $src2},
+ int_x86_sse_min_ps;
def MINPDrm : PD_Intrm0x5D, minpd {$src2, $dst|$dst, $src2},
int_x86_sse2_min_pd;
}
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86: X86InstrSSE.td updated: 1.120 - 1.121 --- Log message: Select vector_shuffle v1, undef 2, 3, ?, ? to MOVHLPS. --- Diffs of the changes: (+8 -0) X86InstrSSE.td |8 1 files changed, 8 insertions(+) Index: llvm/lib/Target/X86/X86InstrSSE.td diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.120 llvm/lib/Target/X86/X86InstrSSE.td:1.121 --- llvm/lib/Target/X86/X86InstrSSE.td:1.120Tue May 30 18:47:30 2006 +++ llvm/lib/Target/X86/X86InstrSSE.td Tue May 30 19:51:37 2006 @@ -2453,6 +2453,14 @@ MOVHLPS_shuffle_mask)), (v4i32 (MOVHLPSrr VR128:$src1, VR128:$src2)); +// vector_shuffle v1, undef 2, 3, ?, ? using MOVHLPS +def : Pat(v4f32 (vector_shuffle VR128:$src1, (undef), + UNPCKH_shuffle_mask)), + (v4f32 (MOVHLPSrr VR128:$src1, VR128:$src1)); +def : Pat(v4i32 (vector_shuffle VR128:$src1, (undef), + UNPCKH_shuffle_mask)), + (v4i32 (MOVHLPSrr VR128:$src1, VR128:$src1)); + // vector_shuffle v1, (load v2) 4, 5, 2, 3 using MOVLPS // vector_shuffle v1, (load v2) 0, 1, 4, 5 using MOVHPS def : Pat(v4f32 (vector_shuffle VR128:$src1, (loadv4f32 addr:$src2), ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.113 - 1.114
---
Log message:
Fix a typo.
---
Diffs of the changes: (+1 -1)
X86InstrSSE.td |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.113
llvm/lib/Target/X86/X86InstrSSE.td:1.114
--- llvm/lib/Target/X86/X86InstrSSE.td:1.113Mon Apr 24 19:50:01 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Tue Apr 25 12:48:41 2006
@@ -1988,7 +1988,7 @@
UNPCKH_shuffle_mask)))];
def PUNPCKHQDQrr : PDI0x6D, MRMSrcReg,
(ops VR128:$dst, VR128:$src1, VR128:$src2),
- punpckhdq {$src2, $dst|$dst, $src2},
+ punpckhqdq {$src2, $dst|$dst, $src2},
[(set VR128:$dst,
(v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
UNPCKH_shuffle_mask)))];
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.111 - 1.112
---
Log message:
Added X86 SSE2 intrinsics which can be represented as vector_shuffles. This is
a temporary workaround for the 2-wide vector_shuffle problem (i.e. its mask
would have type v2i32 which is not legal).
---
Diffs of the changes: (+44 -12)
X86InstrSSE.td | 56
1 files changed, 44 insertions(+), 12 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.111
llvm/lib/Target/X86/X86InstrSSE.td:1.112
--- llvm/lib/Target/X86/X86InstrSSE.td:1.111Mon Apr 24 16:58:20 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Mon Apr 24 18:34:56 2006
@@ -2212,11 +2212,6 @@
movq {$src, $dst|$dst, $src},
[(int_x86_sse2_storel_dq addr:$dst, VR128:$src)];
-// FIXME: Temporary workaround since 2-wide shuffle is broken.
-def MOVLQ128rr : PDI0xD6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
- movq {$src, $dst|$dst, $src},
- [(set VR128:$dst, (int_x86_sse2_movl_dq VR128:$src))];
-
// Move to lower bits of a VR128 and zeroing upper bits.
// Loading from memory automatically zeroing upper bits.
let AddedComplexity = 20 in {
@@ -2241,13 +2236,16 @@
[(set VR128:$dst, (v4i32 (vector_shuffle immAllZerosV,
(v4i32 (scalar_to_vector (loadi32
addr:$src))),
MOVL_shuffle_mask)))];
-def MOVZQI2PQIrr : PDI0x7E, MRMSrcMem, (ops VR128:$dst, VR64:$src),
- movq {$src, $dst|$dst, $src}, [];
-def MOVZQI2PQIrm : PDI0x7E, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
- movq {$src, $dst|$dst, $src},
- [(set VR128:$dst, (bc_v2i64 (vector_shuffle
immAllZerosV,
- (v2f64 (scalar_to_vector (loadf64
addr:$src))),
- MOVL_shuffle_mask)))];
+// Moving from XMM to XMM but still clear upper 64 bits.
+def MOVZQI2PQIrr : I0x7E, MRMSrcReg, (ops VR128:$dst, VR128:$src),
+ movq {$src, $dst|$dst, $src},
+ [(set VR128:$dst, (int_x86_sse2_movl_dq VR128:$src))],
+ XS, Requires[HasSSE2];
+def MOVZQI2PQIrm : I0x7E, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
+ movq {$src, $dst|$dst, $src},
+ [(set VR128:$dst, (int_x86_sse2_movl_dq
+ (bc_v4i32 (loadv2i64 addr:$src],
+ XS, Requires[HasSSE2];
}
//===--===//
@@ -2482,8 +2480,42 @@
def : Pat(v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
MOVL_shuffle_mask)),
(MOVLPDrr VR128:$src1, VR128:$src2), Requires[HasSSE2];
+
+// Set lowest element and zero upper elements.
+def : Pat(bc_v2i64 (vector_shuffle immAllZerosV,
+ (v2f64 (scalar_to_vector (loadf64 addr:$src))),
+ MOVL_shuffle_mask)),
+ (MOVZQI2PQIrm addr:$src), Requires[HasSSE2];
}
+// FIXME: Temporary workaround since 2-wide shuffle is broken.
+def : Pat(int_x86_sse2_movs_d VR128:$src1, VR128:$src2),
+ (MOVLPDrr VR128:$src1, VR128:$src2), Requires[HasSSE2];
+def : Pat(int_x86_sse2_loadh_pd VR128:$src1, addr:$src2),
+ (MOVHPDrm VR128:$src1, addr:$src2), Requires[HasSSE2];
+def : Pat(int_x86_sse2_loadl_pd VR128:$src1, addr:$src2),
+ (MOVLPDrm VR128:$src1, addr:$src2), Requires[HasSSE2];
+def : Pat(int_x86_sse2_shuf_pd VR128:$src1, VR128:$src2, imm:$src3),
+ (SHUFPDrri VR128:$src1, VR128:$src2, imm:$src3),
Requires[HasSSE2];
+def : Pat(int_x86_sse2_shuf_pd VR128:$src1, (load addr:$src2), imm:$src3),
+ (SHUFPDrmi VR128:$src1, addr:$src2, imm:$src3), Requires[HasSSE2];
+def : Pat(int_x86_sse2_unpckh_pd VR128:$src1, VR128:$src2),
+ (UNPCKHPDrr VR128:$src1, VR128:$src2), Requires[HasSSE2];
+def : Pat(int_x86_sse2_unpckh_pd VR128:$src1, (load addr:$src2)),
+ (UNPCKHPDrm VR128:$src1, addr:$src2), Requires[HasSSE2];
+def : Pat(int_x86_sse2_unpckl_pd VR128:$src1, VR128:$src2),
+ (UNPCKLPDrr VR128:$src1, VR128:$src2), Requires[HasSSE2];
+def : Pat(int_x86_sse2_unpckl_pd VR128:$src1, (load addr:$src2)),
+ (UNPCKLPDrm VR128:$src1, addr:$src2), Requires[HasSSE2];
+def : Pat(int_x86_sse2_punpckh_qdq VR128:$src1, VR128:$src2),
+ (PUNPCKHQDQrr VR128:$src1, VR128:$src2), Requires[HasSSE2];
+def : Pat(int_x86_sse2_punpckh_qdq VR128:$src1, (load addr:$src2)),
+ (PUNPCKHQDQrm VR128:$src1, addr:$src2), Requires[HasSSE2];
+def : Pat(int_x86_sse2_punpckl_qdq VR128:$src1, VR128:$src2),
+ (PUNPCKLQDQrr VR128:$src1, VR128:$src2), Requires[HasSSE2];
+def : Pat(int_x86_sse2_punpckl_qdq VR128:$src1, (load addr:$src2)),
+ (PUNPCKLQDQrm VR128:$src1, addr:$src2),
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.112 - 1.113
---
Log message:
Explicitly specify result type for def : Pat patterns (if it produces a vector
result). Otherwise tblgen will pick the default (v16i8 for 128-bit vector).
---
Diffs of the changes: (+47 -45)
X86InstrSSE.td | 92 +
1 files changed, 47 insertions(+), 45 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.112
llvm/lib/Target/X86/X86InstrSSE.td:1.113
--- llvm/lib/Target/X86/X86InstrSSE.td:1.112Mon Apr 24 18:34:56 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Mon Apr 24 19:50:01 2006
@@ -2281,9 +2281,9 @@
// Scalar to v8i16 / v16i8. The source may be a R32, but only the lower 8 or
// 16-bits matter.
-def : Pat(v8i16 (X86s2vec R32:$src)), (MOVDI2PDIrr R32:$src),
+def : Pat(v8i16 (X86s2vec R32:$src)), (v8i16 (MOVDI2PDIrr R32:$src)),
Requires[HasSSE2];
-def : Pat(v16i8 (X86s2vec R32:$src)), (MOVDI2PDIrr R32:$src),
+def : Pat(v16i8 (X86s2vec R32:$src)), (v16i8 (MOVDI2PDIrr R32:$src)),
Requires[HasSSE2];
// bit_convert
@@ -2353,17 +2353,17 @@
let AddedComplexity = 20 in {
def : Pat(v8i16 (vector_shuffle immAllZerosV,
(v8i16 (X86s2vec R32:$src)), MOVL_shuffle_mask)),
- (MOVZDI2PDIrr R32:$src), Requires[HasSSE2];
+ (v8i16 (MOVZDI2PDIrr R32:$src)), Requires[HasSSE2];
def : Pat(v16i8 (vector_shuffle immAllZerosV,
(v16i8 (X86s2vec R32:$src)), MOVL_shuffle_mask)),
- (MOVZDI2PDIrr R32:$src), Requires[HasSSE2];
+ (v16i8 (MOVZDI2PDIrr R32:$src)), Requires[HasSSE2];
// Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
def : Pat(v2f64 (vector_shuffle immAllZerosV,
(v2f64 (scalar_to_vector FR64:$src)), MOVL_shuffle_mask)),
- (MOVLSD2PDrr (V_SET0_PD), FR64:$src), Requires[HasSSE2];
+ (v2f64 (MOVLSD2PDrr (V_SET0_PD), FR64:$src)), Requires[HasSSE2];
def : Pat(v4f32 (vector_shuffle immAllZerosV,
(v4f32 (scalar_to_vector FR32:$src)), MOVL_shuffle_mask)),
- (MOVLSS2PSrr (V_SET0_PS), FR32:$src), Requires[HasSSE2];
+ (v4f32 (MOVLSS2PSrr (V_SET0_PS), FR32:$src)), Requires[HasSSE2];
}
// Splat v2f64 / v2i64
@@ -2404,115 +2404,117 @@
let AddedComplexity = 10 in {
def : Pat(v4f32 (vector_shuffle VR128:$src, (undef),
UNPCKL_v_undef_shuffle_mask)),
- (UNPCKLPSrr VR128:$src, VR128:$src), Requires[HasSSE2];
+ (v4f32 (UNPCKLPSrr VR128:$src, VR128:$src)), Requires[HasSSE2];
def : Pat(v16i8 (vector_shuffle VR128:$src, (undef),
UNPCKL_v_undef_shuffle_mask)),
- (PUNPCKLBWrr VR128:$src, VR128:$src), Requires[HasSSE2];
+ (v16i8 (PUNPCKLBWrr VR128:$src, VR128:$src)), Requires[HasSSE2];
def : Pat(v8i16 (vector_shuffle VR128:$src, (undef),
UNPCKL_v_undef_shuffle_mask)),
- (PUNPCKLWDrr VR128:$src, VR128:$src), Requires[HasSSE2];
+ (v8i16 (PUNPCKLWDrr VR128:$src, VR128:$src)), Requires[HasSSE2];
def : Pat(v4i32 (vector_shuffle VR128:$src, (undef),
UNPCKL_v_undef_shuffle_mask)),
- (PUNPCKLDQrr VR128:$src, VR128:$src), Requires[HasSSE1];
+ (v4i32 (PUNPCKLDQrr VR128:$src, VR128:$src)), Requires[HasSSE1];
}
let AddedComplexity = 20 in {
// vector_shuffle v1, undef 1, 1, 3, 3
def : Pat(v4i32 (vector_shuffle VR128:$src, (undef),
MOVSHDUP_shuffle_mask)),
- (MOVSHDUPrr VR128:$src), Requires[HasSSE3];
+ (v4i32 (MOVSHDUPrr VR128:$src)), Requires[HasSSE3];
def : Pat(v4i32 (vector_shuffle (bc_v4i32 (loadv2i64 addr:$src)), (undef),
MOVSHDUP_shuffle_mask)),
- (MOVSHDUPrm addr:$src), Requires[HasSSE3];
+ (v4i32 (MOVSHDUPrm addr:$src)), Requires[HasSSE3];
// vector_shuffle v1, undef 0, 0, 2, 2
def : Pat(v4i32 (vector_shuffle VR128:$src, (undef),
MOVSLDUP_shuffle_mask)),
- (MOVSLDUPrr VR128:$src), Requires[HasSSE3];
+ (v4i32 (MOVSLDUPrr VR128:$src)), Requires[HasSSE3];
def : Pat(v4i32 (vector_shuffle (bc_v4i32 (loadv2i64 addr:$src)), (undef),
MOVSLDUP_shuffle_mask)),
- (MOVSLDUPrm addr:$src), Requires[HasSSE3];
+ (v4i32 (MOVSLDUPrm addr:$src)), Requires[HasSSE3];
}
let AddedComplexity = 20 in {
// vector_shuffle v1, v2 0, 1, 4, 5 using MOVLHPS
def : Pat(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
MOVHP_shuffle_mask)),
- (MOVLHPSrr VR128:$src1, VR128:$src2);
+ (v4i32 (MOVLHPSrr VR128:$src1, VR128:$src2));
// vector_shuffle v1, v2 6, 7, 2, 3 using MOVHLPS
def : Pat(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
MOVHLPS_shuffle_mask)),
- (MOVHLPSrr VR128:$src1, VR128:$src2);
+ (v4i32 (MOVHLPSrr VR128:$src1, VR128:$src2));
// vector_shuffle v1, (load v2) 4, 5, 2, 3 using MOVLPS
//
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.105 - 1.106
---
Log message:
- More mov{h|l}ps patterns.
- Increase cost (complexity) of patterns which match mov{h|l}ps ops. These
are preferred over shufps in most cases.
---
Diffs of the changes: (+25 -2)
X86InstrSSE.td | 27 +--
1 files changed, 25 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.105
llvm/lib/Target/X86/X86InstrSSE.td:1.106
--- llvm/lib/Target/X86/X86InstrSSE.td:1.105Tue Apr 18 16:59:43 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Wed Apr 19 13:11:52 2006
@@ -782,12 +782,13 @@
[(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)];
let isTwoAddress = 1 in {
+let AddedCost = 10 in {
def MOVLPSrm : PSI0x12, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
f64mem:$src2),
movlps {$src2, $dst|$dst, $src2},
[(set VR128:$dst,
(v4f32 (vector_shuffle VR128:$src1,
(bc_v4f32 (v2f64 (scalar_to_vector (loadf64
addr:$src2,
- MOVLP_shuffle_mask)))];
+ MOVLP_shuffle_mask)))], Cost20;
def MOVLPDrm : PDI0x12, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
f64mem:$src2),
movlpd {$src2, $dst|$dst, $src2},
[(set VR128:$dst,
@@ -799,13 +800,14 @@
[(set VR128:$dst,
(v4f32 (vector_shuffle VR128:$src1,
(bc_v4f32 (v2f64 (scalar_to_vector (loadf64
addr:$src2,
- MOVHP_shuffle_mask)))];
+ MOVHP_shuffle_mask)))], Cost20;
def MOVHPDrm : PDI0x16, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
f64mem:$src2),
movhpd {$src2, $dst|$dst, $src2},
[(set VR128:$dst,
(v2f64 (vector_shuffle VR128:$src1,
(scalar_to_vector (loadf64 addr:$src2)),
MOVHP_shuffle_mask)))];
+} // AddedCost
}
def MOVLPSmr : PSI0x13, MRMDestMem, (ops f64mem:$dst, VR128:$src),
@@ -834,6 +836,7 @@
addr:$dst)];
let isTwoAddress = 1 in {
+let AddedCost = 10 in {
def MOVLHPSrr : PSI0x16, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
VR128:$src2),
movlhps {$src2, $dst|$dst, $src2},
[(set VR128:$dst,
@@ -845,6 +848,7 @@
[(set VR128:$dst,
(v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
MOVHLPS_shuffle_mask)))];
+} // AddedCost
}
def MOVSHDUPrr : S3SI0x16, MRMSrcReg, (ops VR128:$dst, VR128:$src),
@@ -2349,6 +2353,22 @@
def : Pat(v16i8 (X86zexts2vec R8:$src)),
(MOVLDI2PDIrr (V_SET0_PI), (MOVZX32rr8 R8:$src)),
Requires[HasSSE2];
+// MOVLP{S|D}rm / MOVHP{S|D}rm.
+let AddedCost = 10 in {
+def : Pat(v4f32 (vector_shuffle VR128:$src1, (loadv4f32 addr:$src2),
+ MOVLP_shuffle_mask)),
+ (MOVLPSrm VR128:$src1, addr:$src2), Requires[HasSSE1];
+def : Pat(v2f64 (vector_shuffle VR128:$src1, (loadv2f64 addr:$src2),
+ MOVLP_shuffle_mask)),
+ (MOVLPDrm VR128:$src1, addr:$src2), Requires[HasSSE2];
+def : Pat(v4f32 (vector_shuffle VR128:$src1, (loadv4f32 addr:$src2),
+ MOVHP_shuffle_mask)),
+ (MOVHPSrm VR128:$src1, addr:$src2), Requires[HasSSE1];
+def : Pat(v2f64 (vector_shuffle VR128:$src1, (loadv2f64 addr:$src2),
+ MOVHP_shuffle_mask)),
+ (MOVHPDrm VR128:$src1, addr:$src2), Requires[HasSSE2];
+}
+
// Splat v2f64 / v2i64
def : Pat(vector_shuffle (v2f64 VR128:$src), (undef), SSE_splat_v2_mask:$sm),
(v2f64 (UNPCKLPDrr VR128:$src, VR128:$src)), Requires[HasSSE2];
@@ -2415,6 +2435,9 @@
def : Pat(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
MOVS_shuffle_mask)),
(MOVLPSrr VR128:$src1, VR128:$src2);
+def : Pat(v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
+ MOVS_shuffle_mask)),
+ (MOVLPDrr VR128:$src1, VR128:$src2);
// 128-bit logical shifts
def : Pat(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.106 - 1.107
---
Log message:
More mov{h|l}p{d|s} patterns.
---
Diffs of the changes: (+26 -21)
X86InstrSSE.td | 47 ++-
1 files changed, 26 insertions(+), 21 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.106
llvm/lib/Target/X86/X86InstrSSE.td:1.107
--- llvm/lib/Target/X86/X86InstrSSE.td:1.106Wed Apr 19 13:11:52 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Wed Apr 19 13:20:17 2006
@@ -788,7 +788,7 @@
[(set VR128:$dst,
(v4f32 (vector_shuffle VR128:$src1,
(bc_v4f32 (v2f64 (scalar_to_vector (loadf64
addr:$src2,
- MOVLP_shuffle_mask)))], Cost20;
+ MOVLP_shuffle_mask)))];
def MOVLPDrm : PDI0x12, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
f64mem:$src2),
movlpd {$src2, $dst|$dst, $src2},
[(set VR128:$dst,
@@ -800,7 +800,7 @@
[(set VR128:$dst,
(v4f32 (vector_shuffle VR128:$src1,
(bc_v4f32 (v2f64 (scalar_to_vector (loadf64
addr:$src2,
- MOVHP_shuffle_mask)))], Cost20;
+ MOVHP_shuffle_mask)))];
def MOVHPDrm : PDI0x16, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
f64mem:$src2),
movhpd {$src2, $dst|$dst, $src2},
[(set VR128:$dst,
@@ -2353,22 +2353,6 @@
def : Pat(v16i8 (X86zexts2vec R8:$src)),
(MOVLDI2PDIrr (V_SET0_PI), (MOVZX32rr8 R8:$src)),
Requires[HasSSE2];
-// MOVLP{S|D}rm / MOVHP{S|D}rm.
-let AddedCost = 10 in {
-def : Pat(v4f32 (vector_shuffle VR128:$src1, (loadv4f32 addr:$src2),
- MOVLP_shuffle_mask)),
- (MOVLPSrm VR128:$src1, addr:$src2), Requires[HasSSE1];
-def : Pat(v2f64 (vector_shuffle VR128:$src1, (loadv2f64 addr:$src2),
- MOVLP_shuffle_mask)),
- (MOVLPDrm VR128:$src1, addr:$src2), Requires[HasSSE2];
-def : Pat(v4f32 (vector_shuffle VR128:$src1, (loadv4f32 addr:$src2),
- MOVHP_shuffle_mask)),
- (MOVHPSrm VR128:$src1, addr:$src2), Requires[HasSSE1];
-def : Pat(v2f64 (vector_shuffle VR128:$src1, (loadv2f64 addr:$src2),
- MOVHP_shuffle_mask)),
- (MOVHPDrm VR128:$src1, addr:$src2), Requires[HasSSE2];
-}
-
// Splat v2f64 / v2i64
def : Pat(vector_shuffle (v2f64 VR128:$src), (undef), SSE_splat_v2_mask:$sm),
(v2f64 (UNPCKLPDrr VR128:$src, VR128:$src)), Requires[HasSSE2];
@@ -2431,13 +2415,34 @@
MOVSLDUP_shuffle_mask)),
(MOVSLDUPrm addr:$src), Requires[HasSSE3];
-// vector_shuffle v1, v2 4, 1, 2, 3
+// vector_shuffle v1, v2 4, 1, 2, 3 using MOV{H|L}P{S|D}
+let AddedCost = 10 in {
+def : Pat(v4f32 (vector_shuffle VR128:$src1, (loadv4f32 addr:$src2),
+ MOVLP_shuffle_mask)),
+ (MOVLPSrm VR128:$src1, addr:$src2), Requires[HasSSE1];
+def : Pat(v2f64 (vector_shuffle VR128:$src1, (loadv2f64 addr:$src2),
+ MOVLP_shuffle_mask)),
+ (MOVLPDrm VR128:$src1, addr:$src2), Requires[HasSSE2];
+def : Pat(v4f32 (vector_shuffle VR128:$src1, (loadv4f32 addr:$src2),
+ MOVHP_shuffle_mask)),
+ (MOVHPSrm VR128:$src1, addr:$src2), Requires[HasSSE1];
+def : Pat(v2f64 (vector_shuffle VR128:$src1, (loadv2f64 addr:$src2),
+ MOVHP_shuffle_mask)),
+ (MOVHPDrm VR128:$src1, addr:$src2), Requires[HasSSE2];
+
def : Pat(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
MOVS_shuffle_mask)),
- (MOVLPSrr VR128:$src1, VR128:$src2);
+ (MOVLPSrr VR128:$src1, VR128:$src2), Requires[HasSSE2];
+def : Pat(v4i32 (vector_shuffle VR128:$src1, (bc_v4i32 (loadv2i64
addr:$src2)),
+ MOVLP_shuffle_mask)),
+ (MOVLPSrm VR128:$src1, addr:$src2), Requires[HasSSE2];
def : Pat(v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
MOVS_shuffle_mask)),
- (MOVLPDrr VR128:$src1, VR128:$src2);
+ (MOVLPDrr VR128:$src1, VR128:$src2), Requires[HasSSE2];
+def : Pat(v2i64 (vector_shuffle VR128:$src1, (loadv2i64 addr:$src2),
+ MOVHP_shuffle_mask)),
+ (MOVHPDrm VR128:$src1, addr:$src2), Requires[HasSSE2];
+}
// 128-bit logical shifts
def : Pat(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.107 - 1.108
---
Log message:
- Renamed AddedCost to AddedComplexity.
- Added more movhlps and movlhps patterns.
---
Diffs of the changes: (+18 -11)
X86InstrSSE.td | 29 ++---
1 files changed, 18 insertions(+), 11 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.107
llvm/lib/Target/X86/X86InstrSSE.td:1.108
--- llvm/lib/Target/X86/X86InstrSSE.td:1.107Wed Apr 19 13:20:17 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Wed Apr 19 15:37:34 2006
@@ -92,10 +92,6 @@
return X86::isSplatMask(N);
}];
-def MOVLHPS_shuffle_mask : PatLeaf(build_vector), [{
- return X86::isMOVLHPSMask(N);
-}];
-
def MOVHLPS_shuffle_mask : PatLeaf(build_vector), [{
return X86::isMOVHLPSMask(N);
}];
@@ -782,7 +778,7 @@
[(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)];
let isTwoAddress = 1 in {
-let AddedCost = 10 in {
+let AddedComplexity = 10 in {
def MOVLPSrm : PSI0x12, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
f64mem:$src2),
movlps {$src2, $dst|$dst, $src2},
[(set VR128:$dst,
@@ -807,7 +803,7 @@
(v2f64 (vector_shuffle VR128:$src1,
(scalar_to_vector (loadf64 addr:$src2)),
MOVHP_shuffle_mask)))];
-} // AddedCost
+} // AddedComplexity
}
def MOVLPSmr : PSI0x13, MRMDestMem, (ops f64mem:$dst, VR128:$src),
@@ -836,19 +832,19 @@
addr:$dst)];
let isTwoAddress = 1 in {
-let AddedCost = 10 in {
+let AddedComplexity = 10 in {
def MOVLHPSrr : PSI0x16, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
VR128:$src2),
movlhps {$src2, $dst|$dst, $src2},
[(set VR128:$dst,
(v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
- MOVLHPS_shuffle_mask)))];
+ MOVHP_shuffle_mask)))];
def MOVHLPSrr : PSI0x12, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
VR128:$src2),
movhlps {$src2, $dst|$dst, $src2},
[(set VR128:$dst,
(v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
MOVHLPS_shuffle_mask)))];
-} // AddedCost
+} // AddedComplexity
}
def MOVSHDUPrr : S3SI0x16, MRMSrcReg, (ops VR128:$dst, VR128:$src),
@@ -2415,8 +2411,19 @@
MOVSLDUP_shuffle_mask)),
(MOVSLDUPrm addr:$src), Requires[HasSSE3];
-// vector_shuffle v1, v2 4, 1, 2, 3 using MOV{H|L}P{S|D}
-let AddedCost = 10 in {
+let AddedComplexity = 10 in {
+// vector_shuffle v1, v2 0, 1, 4, 5 using MOVLHPS
+def : Pat(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
+ MOVHP_shuffle_mask)),
+ (MOVLHPSrr VR128:$src1, VR128:$src2);
+
+// vector_shuffle v1, v2 6, 7, 2, 3 using MOVHLPS
+def : Pat(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
+ MOVHLPS_shuffle_mask)),
+ (MOVHLPSrr VR128:$src1, VR128:$src2);
+
+// vector_shuffle v1, (load v2) 4, 5, 2, 3 using MOVLPS
+// vector_shuffle v1, (load v2) 0, 1, 4, 5 using MOVHPS
def : Pat(v4f32 (vector_shuffle VR128:$src1, (loadv4f32 addr:$src2),
MOVLP_shuffle_mask)),
(MOVLPSrm VR128:$src1, addr:$src2), Requires[HasSSE1];
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.100 - 1.101
---
Log message:
Fixed an encoding bug: movd from XMM to R32.
---
Diffs of the changes: (+1 -1)
X86InstrSSE.td |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.100
llvm/lib/Target/X86/X86InstrSSE.td:1.101
--- llvm/lib/Target/X86/X86InstrSSE.td:1.100Mon Apr 17 17:45:49 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Tue Apr 18 13:19:00 2006
@@ -2179,7 +2179,7 @@
movsd {$src, $dst|$dst, $src},
[(set FR64:$dst, (vector_extract (v2f64 VR128:$src),
(i32 0)))];
-def MOVPDI2DIrr : PDI0x7E, MRMSrcReg, (ops R32:$dst, VR128:$src),
+def MOVPDI2DIrr : PDI0x7E, MRMDestReg, (ops R32:$dst, VR128:$src),
movd {$src, $dst|$dst, $src},
[(set R32:$dst, (vector_extract (v4i32 VR128:$src),
(i32 0)))];
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.101 - 1.102
---
Log message:
Left a pattern out
---
Diffs of the changes: (+4 -0)
X86InstrSSE.td |4
1 files changed, 4 insertions(+)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.101
llvm/lib/Target/X86/X86InstrSSE.td:1.102
--- llvm/lib/Target/X86/X86InstrSSE.td:1.101Tue Apr 18 13:19:00 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Tue Apr 18 16:29:08 2006
@@ -2179,6 +2179,10 @@
movsd {$src, $dst|$dst, $src},
[(set FR64:$dst, (vector_extract (v2f64 VR128:$src),
(i32 0)))];
+def MOVPD2SDmr : SDI0x11, MRMDestMem, (ops f64mem:$dst, VR128:$src),
+ movsd {$src, $dst|$dst, $src},
+ [(store (f64 (vector_extract (v2f64 VR128:$src),
+ (i32 0))), addr:$dst)];
def MOVPDI2DIrr : PDI0x7E, MRMDestReg, (ops R32:$dst, VR128:$src),
movd {$src, $dst|$dst, $src},
[(set R32:$dst, (vector_extract (v4i32 VR128:$src),
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.102 - 1.103
---
Log message:
Name change for clarity sake
---
Diffs of the changes: (+4 -4)
X86InstrSSE.td |8
1 files changed, 4 insertions(+), 4 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.102
llvm/lib/Target/X86/X86InstrSSE.td:1.103
--- llvm/lib/Target/X86/X86InstrSSE.td:1.102Tue Apr 18 16:29:08 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Tue Apr 18 16:29:50 2006
@@ -1196,22 +1196,22 @@
}
let isTwoAddress = 1 in {
-def CMPPSrr : PSIi80xC2, MRMSrcReg,
+def CMPPSrri : PSIi80xC2, MRMSrcReg,
(ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
cmp${cc}ps {$src, $dst|$dst, $src},
[(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
VR128:$src, imm:$cc))];
-def CMPPSrm : PSIi80xC2, MRMSrcMem,
+def CMPPSrmi : PSIi80xC2, MRMSrcMem,
(ops VR128:$dst, VR128:$src1, f128mem:$src, SSECC:$cc),
cmp${cc}ps {$src, $dst|$dst, $src},
[(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
(load addr:$src), imm:$cc))];
-def CMPPDrr : PDIi80xC2, MRMSrcReg,
+def CMPPDrri : PDIi80xC2, MRMSrcReg,
(ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
cmp${cc}pd {$src, $dst|$dst, $src},
[(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
VR128:$src, imm:$cc))];
-def CMPPDrm : PDIi80xC2, MRMSrcMem,
+def CMPPDrmi : PDIi80xC2, MRMSrcMem,
(ops VR128:$dst, VR128:$src1, f128mem:$src, SSECC:$cc),
cmp${cc}pd {$src, $dst|$dst, $src},
[(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.103 - 1.104
---
Log message:
Name change for clarity sake
---
Diffs of the changes: (+9 -9)
X86InstrSSE.td | 18 +-
1 files changed, 9 insertions(+), 9 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.103
llvm/lib/Target/X86/X86InstrSSE.td:1.104
--- llvm/lib/Target/X86/X86InstrSSE.td:1.103Tue Apr 18 16:29:50 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Tue Apr 18 16:55:35 2006
@@ -1220,25 +1220,25 @@
// Shuffle and unpack instructions
let isTwoAddress = 1 in {
-def SHUFPSrr : PSIi80xC6, MRMSrcReg,
+def SHUFPSrri : PSIi80xC6, MRMSrcReg,
(ops VR128:$dst, VR128:$src1, VR128:$src2,
i32i8imm:$src3),
shufps {$src3, $src2, $dst|$dst, $src2, $src3},
[(set VR128:$dst, (v4f32 (vector_shuffle
VR128:$src1, VR128:$src2,
SHUFP_shuffle_mask:$src3)))];
-def SHUFPSrm : PSIi80xC6, MRMSrcMem,
+def SHUFPSrmi : PSIi80xC6, MRMSrcMem,
(ops VR128:$dst, VR128:$src1, f128mem:$src2,
i32i8imm:$src3),
shufps {$src3, $src2, $dst|$dst, $src2, $src3},
[(set VR128:$dst, (v4f32 (vector_shuffle
VR128:$src1, (load addr:$src2),
SHUFP_shuffle_mask:$src3)))];
-def SHUFPDrr : PDIi80xC6, MRMSrcReg,
+def SHUFPDrri : PDIi80xC6, MRMSrcReg,
(ops VR128:$dst, VR128:$src1, VR128:$src2, i8imm:$src3),
shufpd {$src3, $src2, $dst|$dst, $src2, $src3},
[(set VR128:$dst, (v2f64 (vector_shuffle
VR128:$src1, VR128:$src2,
SHUFP_shuffle_mask:$src3)))];
-def SHUFPDrm : PDIi80xC6, MRMSrcMem,
+def SHUFPDrmi : PDIi80xC6, MRMSrcMem,
(ops VR128:$dst, VR128:$src1, f128mem:$src2, i8imm:$src3),
shufpd {$src3, $src2, $dst|$dst, $src2, $src3},
[(set VR128:$dst, (v2f64 (vector_shuffle
@@ -2364,14 +2364,14 @@
// Splat v4f32
def : Pat(vector_shuffle (v4f32 VR128:$src), (undef), SSE_splat_mask:$sm),
- (v4f32 (SHUFPSrr VR128:$src, VR128:$src, SSE_splat_mask:$sm)),
+ (v4f32 (SHUFPSrri VR128:$src, VR128:$src, SSE_splat_mask:$sm)),
Requires[HasSSE1];
-// Special unary SHUFPSrr case.
+// Special unary SHUFPSrri case.
// FIXME: when we want non two-address code, then we should use PSHUFD?
def : Pat(vector_shuffle (v4f32 VR128:$src1), (undef),
SHUFP_unary_shuffle_mask:$sm),
- (v4f32 (SHUFPSrr VR128:$src1, VR128:$src1,
SHUFP_unary_shuffle_mask:$sm)),
+ (v4f32 (SHUFPSrri VR128:$src1, VR128:$src1,
SHUFP_unary_shuffle_mask:$sm)),
Requires[HasSSE1];
// Unary v4f32 shuffle with PSHUF* in order to fold a load.
def : Pat(vector_shuffle (loadv4f32 addr:$src1), (undef),
@@ -2381,11 +2381,11 @@
// Special binary v4i32 shuffle cases with SHUFPS.
def : Pat(vector_shuffle (v4i32 VR128:$src1), (v4i32 VR128:$src2),
PSHUFD_binary_shuffle_mask:$sm),
- (v4i32 (SHUFPSrr VR128:$src1, VR128:$src2,
+ (v4i32 (SHUFPSrri VR128:$src1, VR128:$src2,
PSHUFD_binary_shuffle_mask:$sm)), Requires[HasSSE2];
def : Pat(vector_shuffle (v4i32 VR128:$src1),
(bc_v4i32 (loadv2i64 addr:$src2)), PSHUFD_binary_shuffle_mask:$sm),
- (v4i32 (SHUFPSrm VR128:$src1, addr:$src2,
+ (v4i32 (SHUFPSrmi VR128:$src1, addr:$src2,
PSHUFD_binary_shuffle_mask:$sm)), Requires[HasSSE2];
// vector_shuffle v1, undef, 0, 0, 1, 1, ...
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.98 - 1.99
---
Log message:
Encoding bug
---
Diffs of the changes: (+1 -1)
X86InstrSSE.td |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.98
llvm/lib/Target/X86/X86InstrSSE.td:1.99
--- llvm/lib/Target/X86/X86InstrSSE.td:1.98 Mon Apr 17 13:05:01 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Mon Apr 17 16:33:57 2006
@@ -2179,7 +2179,7 @@
movsd {$src, $dst|$dst, $src},
[(set FR64:$dst, (vector_extract (v2f64 VR128:$src),
(i32 0)))];
-def MOVPDI2DIrr : PDI0x6E, MRMSrcReg, (ops R32:$dst, VR128:$src),
+def MOVPDI2DIrr : PDI0x7E, MRMSrcReg, (ops R32:$dst, VR128:$src),
movd {$src, $dst|$dst, $src},
[(set R32:$dst, (vector_extract (v4i32 VR128:$src),
(i32 0)))];
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.96 - 1.97
---
Log message:
movduprm, movshduprm bugs
---
Diffs of the changes: (+5 -4)
X86InstrSSE.td |9 +
1 files changed, 5 insertions(+), 4 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.96
llvm/lib/Target/X86/X86InstrSSE.td:1.97
--- llvm/lib/Target/X86/X86InstrSSE.td:1.96 Sun Apr 16 02:02:22 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Sun Apr 16 13:11:28 2006
@@ -852,7 +852,7 @@
[(set VR128:$dst, (v4f32 (vector_shuffle
VR128:$src, (undef),
MOVSHDUP_shuffle_mask)))];
-def MOVSHDUPrm : S3SI0x16, MRMSrcReg, (ops VR128:$dst, f128mem:$src),
+def MOVSHDUPrm : S3SI0x16, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
movshdup {$src, $dst|$dst, $src},
[(set VR128:$dst, (v4f32 (vector_shuffle
(loadv4f32 addr:$src), (undef),
@@ -863,7 +863,7 @@
[(set VR128:$dst, (v4f32 (vector_shuffle
VR128:$src, (undef),
MOVSLDUP_shuffle_mask)))];
-def MOVSLDUPrm : S3SI0x12, MRMSrcReg, (ops VR128:$dst, f128mem:$src),
+def MOVSLDUPrm : S3SI0x12, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
movsldup {$src, $dst|$dst, $src},
[(set VR128:$dst, (v4f32 (vector_shuffle
(loadv4f32 addr:$src), (undef),
@@ -874,10 +874,11 @@
[(set VR128:$dst, (v2f64 (vector_shuffle
VR128:$src, (undef),
SSE_splat_v2_mask)))];
-def MOVDDUPrm : S3DI0x12, MRMSrcReg, (ops VR128:$dst, f64mem:$src),
+def MOVDDUPrm : S3DI0x12, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
movddup {$src, $dst|$dst, $src},
[(set VR128:$dst, (v2f64 (vector_shuffle
-(loadv2f64 addr:$src), (undef),
+ (scalar_to_vector (loadf64
addr:$src)),
+ (undef),
SSE_splat_v2_mask)))];
// SSE2 instructions without OpSize prefix
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.93 - 1.94
---
Log message:
pslldrm, psrawrm, etc. encoding bug
---
Diffs of the changes: (+8 -8)
X86InstrSSE.td | 16
1 files changed, 8 insertions(+), 8 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.93
llvm/lib/Target/X86/X86InstrSSE.td:1.94
--- llvm/lib/Target/X86/X86InstrSSE.td:1.93 Sat Apr 15 00:52:42 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Sat Apr 15 00:59:08 2006
@@ -1600,7 +1600,7 @@
psllw {$src2, $dst|$dst, $src2},
[(set VR128:$dst, (int_x86_sse2_psll_w VR128:$src1,
VR128:$src2))];
-def PSLLWrm : PDIi80xF1, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
+def PSLLWrm : PDIi80xF1, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
psllw {$src2, $dst|$dst, $src2},
[(set VR128:$dst, (int_x86_sse2_psll_w VR128:$src1,
(bc_v4i32 (loadv2i64 addr:$src2];
@@ -1612,7 +1612,7 @@
pslld {$src2, $dst|$dst, $src2},
[(set VR128:$dst, (int_x86_sse2_psll_d VR128:$src1,
VR128:$src2))];
-def PSLLDrm : PDIi80xF2, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
+def PSLLDrm : PDIi80xF2, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
pslld {$src2, $dst|$dst, $src2},
[(set VR128:$dst, (int_x86_sse2_psll_d VR128:$src1,
(bc_v4i32 (loadv2i64 addr:$src2];
@@ -1624,7 +1624,7 @@
psllq {$src2, $dst|$dst, $src2},
[(set VR128:$dst, (int_x86_sse2_psll_q VR128:$src1,
VR128:$src2))];
-def PSLLQrm : PDIi80xF3, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
+def PSLLQrm : PDIi80xF3, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
psllq {$src2, $dst|$dst, $src2},
[(set VR128:$dst, (int_x86_sse2_psll_q VR128:$src1,
(bc_v4i32 (loadv2i64 addr:$src2];
@@ -1639,7 +1639,7 @@
psrlw {$src2, $dst|$dst, $src2},
[(set VR128:$dst, (int_x86_sse2_psrl_w VR128:$src1,
VR128:$src2))];
-def PSRLWrm : PDIi80xD1, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
+def PSRLWrm : PDIi80xD1, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
psrlw {$src2, $dst|$dst, $src2},
[(set VR128:$dst, (int_x86_sse2_psrl_w VR128:$src1,
(bc_v4i32 (loadv2i64 addr:$src2];
@@ -1651,7 +1651,7 @@
psrld {$src2, $dst|$dst, $src2},
[(set VR128:$dst, (int_x86_sse2_psrl_d VR128:$src1,
VR128:$src2))];
-def PSRLDrm : PDIi80xD2, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
+def PSRLDrm : PDIi80xD2, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
psrld {$src2, $dst|$dst, $src2},
[(set VR128:$dst, (int_x86_sse2_psrl_d VR128:$src1,
(bc_v4i32 (loadv2i64 addr:$src2];
@@ -1663,7 +1663,7 @@
psrlq {$src2, $dst|$dst, $src2},
[(set VR128:$dst, (int_x86_sse2_psrl_q VR128:$src1,
VR128:$src2))];
-def PSRLQrm : PDIi80xD3, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
+def PSRLQrm : PDIi80xD3, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
psrlq {$src2, $dst|$dst, $src2},
[(set VR128:$dst, (int_x86_sse2_psrl_q VR128:$src1,
(bc_v4i32 (loadv2i64 addr:$src2];
@@ -1678,7 +1678,7 @@
psraw {$src2, $dst|$dst, $src2},
[(set VR128:$dst, (int_x86_sse2_psra_w VR128:$src1,
VR128:$src2))];
-def PSRAWrm : PDIi80xE1, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
+def PSRAWrm : PDIi80xE1, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
psraw {$src2, $dst|$dst, $src2},
[(set VR128:$dst, (int_x86_sse2_psra_w VR128:$src1,
(bc_v4i32 (loadv2i64 addr:$src2];
@@ -1690,7 +1690,7 @@
psrad {$src2, $dst|$dst, $src2},
[(set VR128:$dst, (int_x86_sse2_psra_d VR128:$src1,
VR128:$src2))];
-def PSRADrm : PDIi80xE2, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
+def PSRADrm : PDIi80xE2, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
psrad {$src2, $dst|$dst,
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.94 - 1.95
---
Log message:
More encoding bugs
---
Diffs of the changes: (+8 -8)
X86InstrSSE.td | 16
1 files changed, 8 insertions(+), 8 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.94
llvm/lib/Target/X86/X86InstrSSE.td:1.95
--- llvm/lib/Target/X86/X86InstrSSE.td:1.94 Sat Apr 15 00:59:08 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Sat Apr 15 01:10:09 2006
@@ -1745,7 +1745,7 @@
pcmpeqb {$src2, $dst|$dst, $src2},
[(set VR128:$dst, (int_x86_sse2_pcmpeq_b VR128:$src1,
VR128:$src2))];
-def PCMPEQBrm : PDI0x74, MRMSrcReg,
+def PCMPEQBrm : PDI0x74, MRMSrcMem,
(ops VR128:$dst, VR128:$src1, i128mem:$src2),
pcmpeqb {$src2, $dst|$dst, $src2},
[(set VR128:$dst, (int_x86_sse2_pcmpeq_b VR128:$src1,
@@ -1755,7 +1755,7 @@
pcmpeqw {$src2, $dst|$dst, $src2},
[(set VR128:$dst, (int_x86_sse2_pcmpeq_w VR128:$src1,
VR128:$src2))];
-def PCMPEQWrm : PDI0x75, MRMSrcReg,
+def PCMPEQWrm : PDI0x75, MRMSrcMem,
(ops VR128:$dst, VR128:$src1, i128mem:$src2),
pcmpeqw {$src2, $dst|$dst, $src2},
[(set VR128:$dst, (int_x86_sse2_pcmpeq_w VR128:$src1,
@@ -1765,7 +1765,7 @@
pcmpeqd {$src2, $dst|$dst, $src2},
[(set VR128:$dst, (int_x86_sse2_pcmpeq_d VR128:$src1,
VR128:$src2))];
-def PCMPEQDrm : PDI0x76, MRMSrcReg,
+def PCMPEQDrm : PDI0x76, MRMSrcMem,
(ops VR128:$dst, VR128:$src1, i128mem:$src2),
pcmpeqd {$src2, $dst|$dst, $src2},
[(set VR128:$dst, (int_x86_sse2_pcmpeq_d VR128:$src1,
@@ -1776,7 +1776,7 @@
pcmpgtb {$src2, $dst|$dst, $src2},
[(set VR128:$dst, (int_x86_sse2_pcmpgt_b VR128:$src1,
VR128:$src2))];
-def PCMPGTBrm : PDI0x64, MRMSrcReg,
+def PCMPGTBrm : PDI0x64, MRMSrcMem,
(ops VR128:$dst, VR128:$src1, i128mem:$src2),
pcmpgtb {$src2, $dst|$dst, $src2},
[(set VR128:$dst, (int_x86_sse2_pcmpgt_b VR128:$src1,
@@ -1786,7 +1786,7 @@
pcmpgtw {$src2, $dst|$dst, $src2},
[(set VR128:$dst, (int_x86_sse2_pcmpgt_w VR128:$src1,
VR128:$src2))];
-def PCMPGTWrm : PDI0x65, MRMSrcReg,
+def PCMPGTWrm : PDI0x65, MRMSrcMem,
(ops VR128:$dst, VR128:$src1, i128mem:$src2),
pcmpgtw {$src2, $dst|$dst, $src2},
[(set VR128:$dst, (int_x86_sse2_pcmpgt_w VR128:$src1,
@@ -1796,7 +1796,7 @@
pcmpgtd {$src2, $dst|$dst, $src2},
[(set VR128:$dst, (int_x86_sse2_pcmpgt_d VR128:$src1,
VR128:$src2))];
-def PCMPGTDrm : PDI0x66, MRMSrcReg,
+def PCMPGTDrm : PDI0x66, MRMSrcMem,
(ops VR128:$dst, VR128:$src1, i128mem:$src2),
pcmpgtd {$src2, $dst|$dst, $src2},
[(set VR128:$dst, (int_x86_sse2_pcmpgt_d VR128:$src1,
@@ -1823,7 +1823,7 @@
[(set VR128:$dst, (v4i32 (int_x86_sse2_packssdw_128
VR128:$src1,
VR128:$src2)))];
-def PACKSSDWrm : PDI0x6B, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
+def PACKSSDWrm : PDI0x6B, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
packssdw {$src2, $dst|$dst, $src2},
[(set VR128:$dst, (v4i32 (int_x86_sse2_packssdw_128
@@ -1835,7 +1835,7 @@
[(set VR128:$dst, (v8i16 (int_x86_sse2_packuswb_128
VR128:$src1,
VR128:$src2)))];
-def PACKUSWBrm : PDI0x67, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
+def PACKUSWBrm : PDI0x67, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
packuswb {$src2, $dst|$dst, $src2},
[(set VR128:$dst, (v8i16 (int_x86_sse2_packuswb_128
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86: X86InstrSSE.td updated: 1.88 - 1.89 --- Log message: Misc. SSE2 intrinsics: clflush, lfench, mfence --- Diffs of the changes: (+11 -2) X86InstrSSE.td | 13 +++-- 1 files changed, 11 insertions(+), 2 deletions(-) Index: llvm/lib/Target/X86/X86InstrSSE.td diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.88 llvm/lib/Target/X86/X86InstrSSE.td:1.89 --- llvm/lib/Target/X86/X86InstrSSE.td:1.88 Thu Apr 13 20:39:53 2006 +++ llvm/lib/Target/X86/X86InstrSSE.td Fri Apr 14 02:43:12 2006 @@ -2002,12 +2002,21 @@ [(int_x86_sse2_movnt_i addr:$dst, R32:$src)], TB, Requires[HasSSE2]; -// Store fence +// Flush cache +def CLFLUSH : I0xAE, MRM7m, (ops i8mem:$src), + clflush $src, [(int_x86_sse2_clflush addr:$src)], + TB, Requires[HasSSE2]; + +// Load, store, and memory fence def SFENCE : I0xAE, MRM7m, (ops), sfence, [(int_x86_sse_sfence)], TB, Requires[HasSSE1]; +def LFENCE : I0xAE, MRM5m, (ops), + lfence, [(int_x86_sse2_lfence)], TB, Requires[HasSSE2]; +def MFENCE : I0xAE, MRM6m, (ops), + mfence, [(int_x86_sse2_mfence)], TB, Requires[HasSSE2]; // MXCSR register -def LDMXCSR : I0xAE, MRM2m, (ops i32mem:$src), +def LDMXCSR : I0xAE, MRM5m, (ops i32mem:$src), ldmxcsr $src, [(int_x86_sse_ldmxcsr addr:$src)], TB, Requires[HasSSE1]; def STMXCSR : I0xAE, MRM3m, (ops i32mem:$dst), ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.92 - 1.93
---
Log message:
hsubp{s|d} encoding bug
---
Diffs of the changes: (+4 -4)
X86InstrSSE.td |8
1 files changed, 4 insertions(+), 4 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.92
llvm/lib/Target/X86/X86InstrSSE.td:1.93
--- llvm/lib/Target/X86/X86InstrSSE.td:1.92 Sat Apr 15 00:37:34 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Sat Apr 15 00:52:42 2006
@@ -1305,13 +1305,13 @@
int_x86_sse3_hadd_pd;
def HADDPDrm : S3_Intrm0x7C, haddpd {$src2, $dst|$dst, $src2},
int_x86_sse3_hadd_pd;
-def HSUBPSrr : S3D_Intrr0x7C, hsubps {$src2, $dst|$dst, $src2},
+def HSUBPSrr : S3D_Intrr0x7D, hsubps {$src2, $dst|$dst, $src2},
int_x86_sse3_hsub_ps;
-def HSUBPSrm : S3D_Intrm0x7C, hsubps {$src2, $dst|$dst, $src2},
+def HSUBPSrm : S3D_Intrm0x7D, hsubps {$src2, $dst|$dst, $src2},
int_x86_sse3_hsub_ps;
-def HSUBPDrr : S3_Intrr0x7C, hsubpd {$src2, $dst|$dst, $src2},
+def HSUBPDrr : S3_Intrr0x7D, hsubpd {$src2, $dst|$dst, $src2},
int_x86_sse3_hsub_pd;
-def HSUBPDrm : S3_Intrm0x7C, hsubpd {$src2, $dst|$dst, $src2},
+def HSUBPDrm : S3_Intrm0x7D, hsubpd {$src2, $dst|$dst, $src2},
int_x86_sse3_hsub_pd;
}
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.84 - 1.85
---
Log message:
psad, pmax, pmin intrinsics.
---
Diffs of the changes: (+54 -1)
X86InstrSSE.td | 55 ++-
1 files changed, 54 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.84
llvm/lib/Target/X86/X86InstrSSE.td:1.85
--- llvm/lib/Target/X86/X86InstrSSE.td:1.84 Thu Apr 13 00:24:54 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Thu Apr 13 01:11:45 2006
@@ -1421,7 +1421,6 @@
[(set VR128:$dst, (int_x86_sse2_pmulu_dq VR128:$src1,
VR128:$src2))];
}
-
def PMULHUWrm : PDI0xE4, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
pmulhuw {$src2, $dst|$dst, $src2},
[(set VR128:$dst, (int_x86_sse2_pmulhu_w VR128:$src1,
@@ -1440,16 +1439,19 @@
[(set VR128:$dst, (int_x86_sse2_pmulu_dq VR128:$src1,
(bc_v4i32 (loadv2i64
addr:$src2];
+let isCommutable = 1 in {
def PMADDWDrr : PDI0xF5, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
VR128:$src2),
pmaddwd {$src2, $dst|$dst, $src2},
[(set VR128:$dst, (int_x86_sse2_pmadd_wd VR128:$src1,
VR128:$src2))];
+}
def PMADDWDrm : PDI0xF5, MRMSrcMem,
(ops VR128:$dst, VR128:$src1, i128mem:$src2),
pmaddwd {$src2, $dst|$dst, $src2},
[(set VR128:$dst, (int_x86_sse2_pmadd_wd VR128:$src1,
(bc_v8i16 (loadv2i64 addr:$src2];
+let isCommutable = 1 in {
def PAVGBrr : PDI0xE0, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
pavgb {$src2, $dst|$dst, $src2},
[(set VR128:$dst, (int_x86_sse2_pavg_b VR128:$src1,
@@ -1458,6 +1460,7 @@
pavgw {$src2, $dst|$dst, $src2},
[(set VR128:$dst, (int_x86_sse2_pavg_w VR128:$src1,
VR128:$src2))];
+}
def PAVGBrm : PDI0xE0, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
pavgb {$src2, $dst|$dst, $src2},
[(set VR128:$dst, (int_x86_sse2_pavg_b VR128:$src1,
@@ -1466,6 +1469,56 @@
pavgw {$src2, $dst|$dst, $src2},
[(set VR128:$dst, (int_x86_sse2_pavg_w VR128:$src1,
(bc_v8i16 (loadv2i64 addr:$src2];
+
+let isCommutable = 1 in {
+def PMAXUBrr : PDI0xDE, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
+ pmaxub {$src2, $dst|$dst, $src2},
+ [(set VR128:$dst, (int_x86_sse2_pmaxu_b VR128:$src1,
+ VR128:$src2))];
+def PMAXSWrr : PDI0xEE, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
+ pmaxsw {$src2, $dst|$dst, $src2},
+ [(set VR128:$dst, (int_x86_sse2_pmaxs_w VR128:$src1,
+ VR128:$src2))];
+}
+def PMAXUBrm : PDI0xDE, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
+ pmaxub {$src2, $dst|$dst, $src2},
+ [(set VR128:$dst, (int_x86_sse2_pmaxu_b VR128:$src1,
+ (bc_v16i8 (loadv2i64 addr:$src2];
+def PMAXSWrm : PDI0xEE, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
+ pmaxsw {$src2, $dst|$dst, $src2},
+ [(set VR128:$dst, (int_x86_sse2_pmaxs_w VR128:$src1,
+ (bc_v8i16 (loadv2i64 addr:$src2];
+
+let isCommutable = 1 in {
+def PMINUBrr : PDI0xDA, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
+ pminub {$src2, $dst|$dst, $src2},
+ [(set VR128:$dst, (int_x86_sse2_pminu_b VR128:$src1,
+ VR128:$src2))];
+def PMINSWrr : PDI0xEA, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
+ pminsw {$src2, $dst|$dst, $src2},
+ [(set VR128:$dst, (int_x86_sse2_pmins_w VR128:$src1,
+ VR128:$src2))];
+}
+def PMINUBrm : PDI0xDA, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
+ pminub {$src2, $dst|$dst, $src2},
+ [(set VR128:$dst, (int_x86_sse2_pminu_b VR128:$src1,
+ (bc_v16i8 (loadv2i64 addr:$src2];
+def PMINSWrm : PDI0xEA, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
+ pminsw {$src2, $dst|$dst, $src2},
+ [(set VR128:$dst, (int_x86_sse2_pmins_w VR128:$src1,
+ (bc_v8i16 (loadv2i64 addr:$src2];
+
+
+let isCommutable = 1 in {
+def PSADBWrr : PDI0xE0, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
+
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.86 - 1.87
---
Log message:
psll*, psrl*, and psra* intrinsics.
---
Diffs of the changes: (+99 -1)
X86InstrSSE.td | 100 -
1 files changed, 99 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.86
llvm/lib/Target/X86/X86InstrSSE.td:1.87
--- llvm/lib/Target/X86/X86InstrSSE.td:1.86 Thu Apr 13 13:11:28 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Thu Apr 13 19:14:05 2006
@@ -1522,10 +1522,108 @@
}
let isTwoAddress = 1 in {
+def PSLLWrr : PDIi80xF1, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
VR128:$src2),
+psllw {$src2, $dst|$dst, $src2},
+[(set VR128:$dst, (int_x86_sse2_psll_w VR128:$src1,
+ VR128:$src2))];
+def PSLLWrm : PDIi80xF1, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
+psllw {$src2, $dst|$dst, $src2},
+[(set VR128:$dst, (int_x86_sse2_psll_w VR128:$src1,
+ (bc_v4i32 (loadv2i64 addr:$src2];
+def PSLLWri : PDIi80x71, MRM6r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
+psllw {$src2, $dst|$dst, $src2},
+[(set VR128:$dst, (int_x86_sse2_psll_w VR128:$src1,
+ (scalar_to_vector (i32 imm:$src2];
+def PSLLDrr : PDIi80xF2, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
VR128:$src2),
+pslld {$src2, $dst|$dst, $src2},
+[(set VR128:$dst, (int_x86_sse2_psll_d VR128:$src1,
+ VR128:$src2))];
+def PSLLDrm : PDIi80xF2, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
+pslld {$src2, $dst|$dst, $src2},
+[(set VR128:$dst, (int_x86_sse2_psll_d VR128:$src1,
+ (bc_v4i32 (loadv2i64 addr:$src2];
+def PSLLDri : PDIi80x72, MRM6r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
+pslld {$src2, $dst|$dst, $src2},
+[(set VR128:$dst, (int_x86_sse2_psll_d VR128:$src1,
+ (scalar_to_vector (i32 imm:$src2];
+def PSLLQrr : PDIi80xF3, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
VR128:$src2),
+psllq {$src2, $dst|$dst, $src2},
+[(set VR128:$dst, (int_x86_sse2_psll_q VR128:$src1,
+ VR128:$src2))];
+def PSLLQrm : PDIi80xF3, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
+psllq {$src2, $dst|$dst, $src2},
+[(set VR128:$dst, (int_x86_sse2_psll_q VR128:$src1,
+ (bc_v4i32 (loadv2i64 addr:$src2];
+def PSLLQri : PDIi80x73, MRM6r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
+psllq {$src2, $dst|$dst, $src2},
+[(set VR128:$dst, (int_x86_sse2_psll_q VR128:$src1,
+ (scalar_to_vector (i32 imm:$src2];
def PSLLDQri : PDIi80x73, MRM7r, (ops VR128:$dst, VR128:$src1,
i32i8imm:$src2),
pslldq {$src2, $dst|$dst, $src2}, [];
-def PSRLDQri : PDIi80x73, MRM7r, (ops VR128:$dst, VR128:$src1,
i32i8imm:$src2),
+
+def PSRLWrr : PDIi80xD1, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
VR128:$src2),
+psrlw {$src2, $dst|$dst, $src2},
+[(set VR128:$dst, (int_x86_sse2_psrl_w VR128:$src1,
+ VR128:$src2))];
+def PSRLWrm : PDIi80xD1, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
+psrlw {$src2, $dst|$dst, $src2},
+[(set VR128:$dst, (int_x86_sse2_psrl_w VR128:$src1,
+ (bc_v4i32 (loadv2i64 addr:$src2];
+def PSRLWri : PDIi80x71, MRM2r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
+psrlw {$src2, $dst|$dst, $src2},
+[(set VR128:$dst, (int_x86_sse2_psrl_w VR128:$src1,
+ (scalar_to_vector (i32 imm:$src2];
+def PSRLDrr : PDIi80xD2, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
VR128:$src2),
+psrld {$src2, $dst|$dst, $src2},
+[(set VR128:$dst, (int_x86_sse2_psrl_d VR128:$src1,
+ VR128:$src2))];
+def PSRLDrm : PDIi80xD2, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
+psrld {$src2, $dst|$dst, $src2},
+[(set VR128:$dst, (int_x86_sse2_psrl_d VR128:$src1,
+ (bc_v4i32 (loadv2i64 addr:$src2];
+def PSRLDri : PDIi80x72, MRM2r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
+psrld {$src2, $dst|$dst, $src2},
+[(set VR128:$dst, (int_x86_sse2_psrl_d VR128:$src1,
+
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.87 - 1.88
---
Log message:
pcmpeq* and pcmpgt* intrinsics.
---
Diffs of the changes: (+68 -2)
X86InstrSSE.td | 70 +++--
1 files changed, 68 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.87
llvm/lib/Target/X86/X86InstrSSE.td:1.88
--- llvm/lib/Target/X86/X86InstrSSE.td:1.87 Thu Apr 13 19:14:05 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Thu Apr 13 20:39:53 2006
@@ -1148,10 +1148,76 @@
(load addr:$src), imm:$cc))];
def CMPPDrr : PDIi80xC2, MRMSrcReg,
(ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
-cmp${cc}pd {$src, $dst|$dst, $src}, [];
+cmp${cc}pd {$src, $dst|$dst, $src},
+[(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
+ VR128:$src, imm:$cc))];
def CMPPDrm : PDIi80xC2, MRMSrcMem,
(ops VR128:$dst, VR128:$src1, f128mem:$src, SSECC:$cc),
-cmp${cc}pd {$src, $dst|$dst, $src}, [];
+cmp${cc}pd {$src, $dst|$dst, $src},
+[(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
+ (load addr:$src), imm:$cc))];
+
+def PCMPEQBrr : PDI0x74, MRMSrcReg,
+(ops VR128:$dst, VR128:$src1, VR128:$src2),
+pcmpeqb {$src2, $dst|$dst, $src2},
+[(set VR128:$dst, (int_x86_sse2_pcmpeq_b VR128:$src1,
+ VR128:$src2))];
+def PCMPEQBrm : PDI0x74, MRMSrcReg,
+(ops VR128:$dst, VR128:$src1, i128mem:$src2),
+pcmpeqb {$src2, $dst|$dst, $src2},
+[(set VR128:$dst, (int_x86_sse2_pcmpeq_b VR128:$src1,
+ (bc_v16i8 (loadv2i64 addr:$src2];
+def PCMPEQWrr : PDI0x75, MRMSrcReg,
+(ops VR128:$dst, VR128:$src1, VR128:$src2),
+pcmpeqw {$src2, $dst|$dst, $src2},
+[(set VR128:$dst, (int_x86_sse2_pcmpeq_w VR128:$src1,
+ VR128:$src2))];
+def PCMPEQWrm : PDI0x75, MRMSrcReg,
+(ops VR128:$dst, VR128:$src1, i128mem:$src2),
+pcmpeqw {$src2, $dst|$dst, $src2},
+[(set VR128:$dst, (int_x86_sse2_pcmpeq_w VR128:$src1,
+ (bc_v8i16 (loadv2i64 addr:$src2];
+def PCMPEQDrr : PDI0x76, MRMSrcReg,
+(ops VR128:$dst, VR128:$src1, VR128:$src2),
+pcmpeqd {$src2, $dst|$dst, $src2},
+[(set VR128:$dst, (int_x86_sse2_pcmpeq_d VR128:$src1,
+ VR128:$src2))];
+def PCMPEQDrm : PDI0x76, MRMSrcReg,
+(ops VR128:$dst, VR128:$src1, i128mem:$src2),
+pcmpeqd {$src2, $dst|$dst, $src2},
+[(set VR128:$dst, (int_x86_sse2_pcmpeq_d VR128:$src1,
+ (bc_v4i32 (loadv2i64 addr:$src2];
+
+def PCMPGTBrr : PDI0x64, MRMSrcReg,
+(ops VR128:$dst, VR128:$src1, VR128:$src2),
+pcmpgtb {$src2, $dst|$dst, $src2},
+[(set VR128:$dst, (int_x86_sse2_pcmpgt_b VR128:$src1,
+ VR128:$src2))];
+def PCMPGTBrm : PDI0x64, MRMSrcReg,
+(ops VR128:$dst, VR128:$src1, i128mem:$src2),
+pcmpgtb {$src2, $dst|$dst, $src2},
+[(set VR128:$dst, (int_x86_sse2_pcmpgt_b VR128:$src1,
+ (bc_v16i8 (loadv2i64 addr:$src2];
+def PCMPGTWrr : PDI0x65, MRMSrcReg,
+(ops VR128:$dst, VR128:$src1, VR128:$src2),
+pcmpgtw {$src2, $dst|$dst, $src2},
+[(set VR128:$dst, (int_x86_sse2_pcmpgt_w VR128:$src1,
+ VR128:$src2))];
+def PCMPGTWrm : PDI0x65, MRMSrcReg,
+(ops VR128:$dst, VR128:$src1, i128mem:$src2),
+pcmpgtw {$src2, $dst|$dst, $src2},
+[(set VR128:$dst, (int_x86_sse2_pcmpgt_w VR128:$src1,
+ (bc_v8i16 (loadv2i64 addr:$src2];
+def PCMPGTDrr : PDI0x66, MRMSrcReg,
+(ops VR128:$dst, VR128:$src1, VR128:$src2),
+pcmpgtd {$src2, $dst|$dst, $src2},
+[(set VR128:$dst, (int_x86_sse2_pcmpgt_d VR128:$src1,
+ VR128:$src2))];
+def PCMPGTDrm : PDI0x66, MRMSrcReg,
+(ops VR128:$dst, VR128:$src1, i128mem:$src2),
+pcmpgtd {$src2, $dst|$dst, $src2},
+[(set VR128:$dst, (int_x86_sse2_pcmpgt_d VR128:$src1,
+
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.81 - 1.82
---
Log message:
Naming inconsistency.
---
Diffs of the changes: (+1 -1)
X86InstrSSE.td |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.81
llvm/lib/Target/X86/X86InstrSSE.td:1.82
--- llvm/lib/Target/X86/X86InstrSSE.td:1.81 Wed Apr 12 18:42:44 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Wed Apr 12 19:00:23 2006
@@ -1613,7 +1613,7 @@
[(set R32:$dst, (int_x86_sse_movmsk_ps VR128:$src))];
def MOVMSKPDrr : PSI0x50, MRMSrcReg, (ops R32:$dst, VR128:$src),
movmskpd {$src, $dst|$dst, $src},
- [(set R32:$dst, (int_x86_sse2_movmskpd VR128:$src))];
+ [(set R32:$dst, (int_x86_sse2_movmsk_pd VR128:$src))];
def PMOVMSKBrr : PDI0xD7, MRMSrcReg, (ops R32:$dst, VR128:$src),
pmovmskb {$src, $dst|$dst, $src},
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.82 - 1.83
---
Log message:
padds{b|w}, paddus{b|w}, psubs{b|w}, psubus{b|w} intrinsics.
---
Diffs of the changes: (+78 -8)
X86InstrSSE.td | 86 +++--
1 files changed, 78 insertions(+), 8 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.82
llvm/lib/Target/X86/X86InstrSSE.td:1.83
--- llvm/lib/Target/X86/X86InstrSSE.td:1.82 Wed Apr 12 19:00:23 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Wed Apr 12 19:43:35 2006
@@ -1283,23 +1283,59 @@
paddq {$src2, $dst|$dst, $src2},
[(set VR128:$dst, (v2i64 (add VR128:$src1, VR128:$src2)))];
}
-def PADDBrm : PDI0xFC, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
f128mem:$src2),
+def PADDBrm : PDI0xFC, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
paddb {$src2, $dst|$dst, $src2},
[(set VR128:$dst, (v16i8 (add VR128:$src1,
(load addr:$src2];
-def PADDWrm : PDI0xFD, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
f128mem:$src2),
+def PADDWrm : PDI0xFD, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
paddw {$src2, $dst|$dst, $src2},
[(set VR128:$dst, (v8i16 (add VR128:$src1,
(load addr:$src2];
-def PADDDrm : PDI0xFE, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
f128mem:$src2),
+def PADDDrm : PDI0xFE, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
paddd {$src2, $dst|$dst, $src2},
[(set VR128:$dst, (v4i32 (add VR128:$src1,
(load addr:$src2];
-def PADDQrm : PDI0xD4, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
f128mem:$src2),
+def PADDQrm : PDI0xD4, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
paddd {$src2, $dst|$dst, $src2},
[(set VR128:$dst, (v2i64 (add VR128:$src1,
(load addr:$src2];
+let isCommutable = 1 in {
+def PADDSBrr : PDI0xEC, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
+ paddsb {$src2, $dst|$dst, $src2},
+ [(set VR128:$dst, (int_x86_sse2_padds_b VR128:$src1,
+ VR128:$src2))];
+def PADDSWrr : PDI0xED, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
+ paddsw {$src2, $dst|$dst, $src2},
+ [(set VR128:$dst, (int_x86_sse2_padds_w VR128:$src1,
+ VR128:$src2))];
+def PADDUSBrr : PDI0xDC, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
VR128:$src2),
+paddusb {$src2, $dst|$dst, $src2},
+[(set VR128:$dst, (int_x86_sse2_paddus_b VR128:$src1,
+ VR128:$src2))];
+def PADDUSWrr : PDI0xDD, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
VR128:$src2),
+ paddusw {$src2, $dst|$dst, $src2},
+[(set VR128:$dst, (int_x86_sse2_paddus_w VR128:$src1,
+ VR128:$src2))];
+}
+def PADDSBrm : PDI0xEC, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
+ paddsb {$src2, $dst|$dst, $src2},
+ [(set VR128:$dst, (int_x86_sse2_padds_b VR128:$src1,
+ (bc_v16i8 (loadv2i64 addr:$src2];
+def PADDSWrm : PDI0xED, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
+ paddsw {$src2, $dst|$dst, $src2},
+ [(set VR128:$dst, (int_x86_sse2_padds_w VR128:$src1,
+ (bc_v8i16 (loadv2i64 addr:$src2];
+def PADDUSBrm : PDI0xDC, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
+paddusb {$src2, $dst|$dst, $src2},
+[(set VR128:$dst, (int_x86_sse2_paddus_b VR128:$src1,
+ (bc_v16i8 (loadv2i64 addr:$src2];
+def PADDUSWrm : PDI0xDD, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
+ paddusw {$src2, $dst|$dst, $src2},
+[(set VR128:$dst, (int_x86_sse2_paddus_w VR128:$src1,
+ (bc_v8i16 (loadv2i64 addr:$src2];
+
+
def PSUBBrr : PDI0xF8, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
psubb {$src2, $dst|$dst, $src2},
[(set VR128:$dst, (v16i8 (sub VR128:$src1, VR128:$src2)))];
@@ -1313,22 +1349,56 @@
psubq {$src2, $dst|$dst, $src2},
[(set VR128:$dst, (v2i64 (sub VR128:$src1, VR128:$src2)))];
-def PSUBBrm : PDI0xF8, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
f128mem:$src2),
+def PSUBBrm : PDI0xF8, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
psubb {$src2, $dst|$dst, $src2},
[(set VR128:$dst, (v16i8 (sub VR128:$src1,
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.83 - 1.84
---
Log message:
Various SSE2 packed integer intrinsics: pmulhuw, pavgw, etc.
---
Diffs of the changes: (+71 -4)
X86InstrSSE.td | 75 +
1 files changed, 71 insertions(+), 4 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.83
llvm/lib/Target/X86/X86InstrSSE.td:1.84
--- llvm/lib/Target/X86/X86InstrSSE.td:1.83 Wed Apr 12 19:43:35 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Thu Apr 13 00:24:54 2006
@@ -1383,22 +1383,89 @@
[(set VR128:$dst, (int_x86_sse2_psubus_w VR128:$src1,
VR128:$src2))];
-def PSUBSBrm : PDI0xE8, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
+def PSUBSBrm : PDI0xE8, MRMSrcMem,
+ (ops VR128:$dst, VR128:$src1, i128mem:$src2),
psubsb {$src2, $dst|$dst, $src2},
[(set VR128:$dst, (int_x86_sse2_psubs_b VR128:$src1,
(bc_v16i8 (loadv2i64 addr:$src2];
-def PSUBSWrm : PDI0xE9, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
+def PSUBSWrm : PDI0xE9, MRMSrcMem,
+ (ops VR128:$dst, VR128:$src1, i128mem:$src2),
psubsw {$src2, $dst|$dst, $src2},
[(set VR128:$dst, (int_x86_sse2_psubs_w VR128:$src1,
(bc_v8i16 (loadv2i64 addr:$src2];
-def PSUBUSBrm : PDI0xD8, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
+def PSUBUSBrm : PDI0xD8, MRMSrcMem,
+(ops VR128:$dst, VR128:$src1, i128mem:$src2),
psubusb {$src2, $dst|$dst, $src2},
[(set VR128:$dst, (int_x86_sse2_psubus_b VR128:$src1,
(bc_v16i8 (loadv2i64 addr:$src2];
-def PSUBUSWrm : PDI0xD9, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
+def PSUBUSWrm : PDI0xD9, MRMSrcMem,
+(ops VR128:$dst, VR128:$src1, i128mem:$src2),
psubusw {$src2, $dst|$dst, $src2},
[(set VR128:$dst, (int_x86_sse2_psubus_w VR128:$src1,
(bc_v8i16 (loadv2i64 addr:$src2];
+
+let isCommutable = 1 in {
+def PMULHUWrr : PDI0xE4, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
VR128:$src2),
+pmulhuw {$src2, $dst|$dst, $src2},
+[(set VR128:$dst, (int_x86_sse2_pmulhu_w VR128:$src1,
+ VR128:$src2))];
+def PMULHWrr : PDI0xE5, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
+pmulhw {$src2, $dst|$dst, $src2},
+[(set VR128:$dst, (int_x86_sse2_pmulh_w VR128:$src1,
+ VR128:$src2))];
+def PMULLWrr : PDI0xD5, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
+ pmullw {$src2, $dst|$dst, $src2},
+ [(set VR128:$dst, (v8i16 (mul VR128:$src1, VR128:$src2)))];
+def PMULUDQrr : PDI0xF4, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
VR128:$src2),
+pmuludq {$src2, $dst|$dst, $src2},
+[(set VR128:$dst, (int_x86_sse2_pmulu_dq VR128:$src1,
+ VR128:$src2))];
+}
+
+def PMULHUWrm : PDI0xE4, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
+pmulhuw {$src2, $dst|$dst, $src2},
+[(set VR128:$dst, (int_x86_sse2_pmulhu_w VR128:$src1,
+ (bc_v8i16 (loadv2i64 addr:$src2];
+def PMULHWrm : PDI0xE5, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
+pmulhw {$src2, $dst|$dst, $src2},
+[(set VR128:$dst, (int_x86_sse2_pmulh_w VR128:$src1,
+ (bc_v8i16 (loadv2i64 addr:$src2];
+def PMULLWrm : PDI0xD5, MRMSrcMem,
+ (ops VR128:$dst, VR128:$src1, i128mem:$src2),
+ pmullw {$src2, $dst|$dst, $src2},
+ [(set VR128:$dst, (v8i16 (mul VR128:$src1,
+ (bc_v8i16 (loadv2i64
addr:$src2)];
+def PMULUDQrm : PDI0xF4, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
+pmuludq {$src2, $dst|$dst, $src2},
+[(set VR128:$dst, (int_x86_sse2_pmulu_dq VR128:$src1,
+ (bc_v4i32 (loadv2i64
addr:$src2];
+
+def PMADDWDrr : PDI0xF5, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
VR128:$src2),
+pmaddwd {$src2, $dst|$dst, $src2},
+[(set VR128:$dst, (int_x86_sse2_pmadd_wd VR128:$src1,
+ VR128:$src2))];
+def PMADDWDrm : PDI0xF5, MRMSrcMem,
+(ops VR128:$dst, VR128:$src1, i128mem:$src2),
+pmaddwd {$src2, $dst|$dst, $src2},
+
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86: X86InstrSSE.td updated: 1.75 - 1.76 --- Log message: gcc lower SSE prefetch into generic prefetch intrinsic. Need to add support later. --- Diffs of the changes: (+4 -8) X86InstrSSE.td | 12 1 files changed, 4 insertions(+), 8 deletions(-) Index: llvm/lib/Target/X86/X86InstrSSE.td diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.75 llvm/lib/Target/X86/X86InstrSSE.td:1.76 --- llvm/lib/Target/X86/X86InstrSSE.td:1.75 Tue Apr 11 12:35:57 2006 +++ llvm/lib/Target/X86/X86InstrSSE.td Tue Apr 11 13:04:57 2006 @@ -1517,17 +1517,13 @@ // Prefetching loads def PREFETCHT0 : PSI0x18, MRM1m, (ops i8mem:$src), - prefetcht0 $src, - [(int_x86_sse_prefetch addr:$src, 1)]; + prefetcht0 $src, []; def PREFETCHT1 : PSI0x18, MRM2m, (ops i8mem:$src), - prefetcht1 $src, - [(int_x86_sse_prefetch addr:$src, 2)]; + prefetcht1 $src, []; def PREFETCHT2 : PSI0x18, MRM3m, (ops i8mem:$src), - prefetcht2 $src, - [(int_x86_sse_prefetch addr:$src, 3)]; + prefetcht2 $src, []; def PREFETCHTNTA : PSI0x18, MRM0m, (ops i8mem:$src), - prefetchtnta $src, - [(int_x86_sse_prefetch addr:$src, 0)]; + prefetchtnta $src, []; // Non-temporal stores def MOVNTPSmr : PSI0x2B, MRMDestMem, (ops i128mem:$dst, VR128:$src), ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.76 - 1.77
---
Log message:
Added __builtin_ia32_storelv4si, __builtin_ia32_movqv4si,
__builtin_ia32_loadlv4si, __builtin_ia32_loaddqu, __builtin_ia32_storedqu.
---
Diffs of the changes: (+21 -2)
X86InstrSSE.td | 23 +--
1 files changed, 21 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.76
llvm/lib/Target/X86/X86InstrSSE.td:1.77
--- llvm/lib/Target/X86/X86InstrSSE.td:1.76 Tue Apr 11 13:04:57 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Tue Apr 11 17:28:25 2006
@@ -724,6 +724,14 @@
def MOVUPDmr : PDI0x11, MRMDestMem, (ops f128mem:$dst, VR128:$src),
movupd {$src, $dst|$dst, $src},
[(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)];
+def MOVDQUrm : I0x6F, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
+ movdqu {$src, $dst|$dst, $src},
+ [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))],
+ XS, Requires[HasSSE2];
+def MOVDQUmr : I0x7F, MRMDestMem, (ops i128mem:$dst, VR128:$src),
+ movdqu {$src, $dst|$dst, $src},
+ [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)],
+ XS, Requires[HasSSE2];
let isTwoAddress = 1 in {
def MOVLPSrm : PSI0x12, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
f64mem:$src2),
@@ -1657,6 +1665,16 @@
MOVS_shuffle_mask)))];
}
+// Store / copy lower 64-bits of a XMM register.
+def MOVLQ128mr : PDI0xD6, MRMDestMem, (ops i64mem:$dst, VR128:$src),
+ movq {$src, $dst|$dst, $src},
+ [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)];
+
+// FIXME: Temporary workaround since 2-wide shuffle is broken.
+def MOVLQ128rr : PDI0xD6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
+ movq {$src, $dst|$dst, $src},
+ [(set VR128:$dst, (int_x86_sse2_movl_dq VR128:$src))];
+
// Move to lower bits of a VR128 and zeroing upper bits.
// Loading from memory automatically zeroing upper bits.
def MOVZSS2PSrm : SSI0x10, MRMSrcMem, (ops VR128:$dst, f32mem:$src),
@@ -1672,9 +1690,10 @@
[(set VR128:$dst,
(v4i32 (X86zexts2vec (loadi32 addr:$src];
def MOVZQI2PQIrm : PDI0x7E, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
- movd {$src, $dst|$dst, $src},
+ movq {$src, $dst|$dst, $src},
[(set VR128:$dst,
- (v2i64 (X86zexts2vec (loadi64 addr:$src];
+ (bc_v2i64 (v2f64 (X86zexts2vec
+ (loadf64 addr:$src)];
//===--===//
// Non-Instruction Patterns
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.77 - 1.78
---
Log message:
Various SSE2 conversion intrinsics
---
Diffs of the changes: (+94 -39)
X86InstrSSE.td | 133 -
1 files changed, 94 insertions(+), 39 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.77
llvm/lib/Target/X86/X86InstrSSE.td:1.78
--- llvm/lib/Target/X86/X86InstrSSE.td:1.77 Tue Apr 11 17:28:25 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Wed Apr 12 00:20:24 2006
@@ -524,6 +524,23 @@
[(set FR64:$dst, (fextend (loadf32 addr:$src)))], XS,
Requires[HasSSE2];
+// Aliases to match intrinsics which expect XMM operand(s).
+def Int_CVTTSD2SIrr: SDI0x2C, MRMSrcReg, (ops R32:$dst, VR128:$src),
+ cvttsd2si {$src, $dst|$dst, $src},
+ [(set R32:$dst, (int_x86_sse2_cvttsd2si
VR128:$src))];
+def Int_CVTTSD2SIrm: SDI0x2C, MRMSrcMem, (ops R32:$dst, f128mem:$src),
+ cvttsd2si {$src, $dst|$dst, $src},
+ [(set R32:$dst, (int_x86_sse2_cvttsd2si
+ (load addr:$src)))];
+
+def CVTSD2SIrr: SDI0x2D, MRMSrcReg, (ops R32:$dst, VR128:$src),
+cvtsd2si {$src, $dst|$dst, $src},
+[(set R32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))];
+def CVTSD2SIrm: SDI0x2D, MRMSrcMem, (ops R32:$dst, f128mem:$src),
+cvtsd2si {$src, $dst|$dst, $src},
+[(set R32:$dst, (int_x86_sse2_cvtsd2si
+ (load addr:$src)))];
+
// Comparison instructions
let isTwoAddress = 1 in {
def CMPSSrr : SSI0xC2, MRMSrcReg,
@@ -800,62 +817,100 @@
}
// Conversion instructions
-def CVTPI2PSr : PSI0x2A, MRMSrcReg, (ops VR128:$dst, VR64:$src),
+def CVTPI2PSrr : PSI0x2A, MRMSrcReg, (ops VR128:$dst, VR64:$src),
cvtpi2ps {$src, $dst|$dst, $src}, [];
-def CVTPI2PSm : PSI0x2A, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
+def CVTPI2PSrm : PSI0x2A, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
cvtpi2ps {$src, $dst|$dst, $src}, [];
-def CVTPI2PDr : PDI0x2A, MRMSrcReg, (ops VR128:$dst, VR64:$src),
+def CVTPI2PDrr : PDI0x2A, MRMSrcReg, (ops VR128:$dst, VR64:$src),
cvtpi2pd {$src, $dst|$dst, $src}, [];
-def CVTPI2PDm : PDI0x2A, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
+def CVTPI2PDrm : PDI0x2A, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
cvtpi2pd {$src, $dst|$dst, $src}, [];
// SSE2 instructions without OpSize prefix
-def CVTDQ2PSr : I0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
- cvtdq2ps {$src, $dst|$dst, $src}, [], TB,
-Requires[HasSSE2];
-def CVTDQ2PSm : I0x5B, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
- cvtdq2ps {$src, $dst|$dst, $src}, [], TB,
-Requires[HasSSE2];
+def CVTDQ2PSrr : I0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
+ cvtdq2ps {$src, $dst|$dst, $src},
+ [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))],
+ TB, Requires[HasSSE2];
+def CVTDQ2PSrm : I0x5B, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
+ cvtdq2ps {$src, $dst|$dst, $src},
+ [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
+ (load addr:$src)))],
+ TB, Requires[HasSSE2];
// SSE2 instructions with XS prefix
-def CVTDQ2PDr : I0xE6, MRMSrcReg, (ops VR128:$dst, VR64:$src),
- cvtdq2pd {$src, $dst|$dst, $src}, [],
-XS, Requires[HasSSE2];
-def CVTDQ2PDm : I0xE6, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
- cvtdq2pd {$src, $dst|$dst, $src}, [],
-XS, Requires[HasSSE2];
+def CVTDQ2PDrr : I0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
+ cvtdq2pd {$src, $dst|$dst, $src},
+ [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))],
+ XS, Requires[HasSSE2];
+def CVTDQ2PDrm : I0xE6, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
+ cvtdq2pd {$src, $dst|$dst, $src},
+ [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
+ (load addr:$src)))],
+ XS, Requires[HasSSE2];
-def CVTPS2PIr : PSI0x2D, MRMSrcReg, (ops VR64:$dst, VR128:$src),
+def CVTPS2PIrr : PSI0x2D, MRMSrcReg, (ops VR64:$dst, VR128:$src),
cvtps2pi {$src, $dst|$dst, $src}, [];
-def CVTPS2PIm : PSI0x2D, MRMSrcMem, (ops VR64:$dst, f64mem:$src),
+def CVTPS2PIrm : PSI0x2D, MRMSrcMem, (ops VR64:$dst, f64mem:$src),
cvtps2pi {$src, $dst|$dst, $src}, [];
-def CVTPD2PIr : PDI0x2D, MRMSrcReg, (ops VR64:$dst, VR128:$src),
+def CVTPD2PIrr : PDI0x2D, MRMSrcReg, (ops VR64:$dst, VR128:$src),
cvtpd2pi {$src, $dst|$dst, $src}, [];
-def CVTPD2PIm : PDI0x2D, MRMSrcMem,
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.69 - 1.70
---
Log message:
movups / movupd
---
Diffs of the changes: (+10 -6)
X86InstrSSE.td | 16 ++--
1 files changed, 10 insertions(+), 6 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.69
llvm/lib/Target/X86/X86InstrSSE.td:1.70
--- llvm/lib/Target/X86/X86InstrSSE.td:1.69 Mon Apr 10 02:23:14 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Mon Apr 10 16:11:06 2006
@@ -722,16 +722,20 @@
def MOVUPSrr : PSI0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src),
movups {$src, $dst|$dst, $src}, [];
-def MOVUPSrm : PSI0x10, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
- movups {$src, $dst|$dst, $src}, [];
-def MOVUPSmr : PSI0x11, MRMDestMem, (ops f128mem:$dst, VR128:$src),
- movups {$src, $dst|$dst, $src}, [];
+def MOVUPSrm : PDI0x10, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
+ movups {$src, $dst|$dst, $src},
+ [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))];
+def MOVUPSmr : PDI0x11, MRMDestMem, (ops f128mem:$dst, VR128:$src),
+ movups {$src, $dst|$dst, $src},
+ [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)];
def MOVUPDrr : PDI0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src),
movupd {$src, $dst|$dst, $src}, [];
def MOVUPDrm : PDI0x10, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
- movupd {$src, $dst|$dst, $src}, [];
+ movupd {$src, $dst|$dst, $src},
+ [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))];
def MOVUPDmr : PDI0x11, MRMDestMem, (ops f128mem:$dst, VR128:$src),
- movupd {$src, $dst|$dst, $src}, [];
+ movupd {$src, $dst|$dst, $src},
+ [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)];
let isTwoAddress = 1 in {
def MOVLPSrm : PSI0x12, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
f64mem:$src2),
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.70 - 1.71
---
Log message:
Added some missing shuffle patterns.
---
Diffs of the changes: (+22 -5)
X86InstrSSE.td | 27 ++-
1 files changed, 22 insertions(+), 5 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.70
llvm/lib/Target/X86/X86InstrSSE.td:1.71
--- llvm/lib/Target/X86/X86InstrSSE.td:1.70 Mon Apr 10 16:11:06 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Mon Apr 10 16:42:19 2006
@@ -1365,7 +1365,7 @@
(ops VR128:$dst, i128mem:$src1, i8imm:$src2),
pshufhw {$src2, $src1, $dst|$dst, $src1, $src2},
[(set VR128:$dst, (v8i16 (vector_shuffle
- (bc_v8i16 (loadv2i64 addr:$src1)),
(undef),
+ (load addr:$src1), (undef),
PSHUFHW_shuffle_mask:$src2)))],
XS, Requires[HasSSE2];
@@ -1381,7 +1381,7 @@
(ops VR128:$dst, i128mem:$src1, i32i8imm:$src2),
pshuflw {$src2, $src1, $dst|$dst, $src1, $src2},
[(set VR128:$dst, (v8i16 (vector_shuffle
- (bc_v8i16 (loadv2i64 addr:$src1)),
(undef),
+ (load addr:$src1), (undef),
PSHUFLW_shuffle_mask:$src2)))],
XD, Requires[HasSSE2];
@@ -1823,11 +1823,28 @@
(v4i32 (SHUFPSrm VR128:$src1, addr:$src2,
SHUFP_int_shuffle_mask:$sm)), Requires[HasSSE2];
-// Shuffle v4f32 with PSHUF* if others do not match.
+// Special pshuf* cases: folding (bit_convert (loadv2i64 addr)).
+def : Pat(v4i32 (vector_shuffle (bc_v4i32 (loadv2i64 addr:$src1)), (undef),
+ PSHUFD_shuffle_mask:$src2)),
+ (PSHUFDmi addr:$src1, PSHUFD_shuffle_mask:$src2),
+ Requires[HasSSE2];
+def : Pat(v8i16 (vector_shuffle (bc_v8i16 (loadv2i64 addr:$src1)), (undef),
+ PSHUFHW_shuffle_mask:$src2)),
+ (PSHUFHWmi addr:$src1, PSHUFHW_shuffle_mask:$src2),
+ Requires[HasSSE2];
+def : Pat(v8i16 (vector_shuffle (bc_v8i16 (loadv2i64 addr:$src1)), (undef),
+ PSHUFLW_shuffle_mask:$src2)),
+ (PSHUFLWmi addr:$src1, PSHUFHW_shuffle_mask:$src2),
+ Requires[HasSSE2];
+
+
+// Special SHUFPSrr case: looks like a PSHUFD, like make both operands src1.
+// FIXME: when we want non two-address code, then we should use PSHUFD!
def : Pat(vector_shuffle (v4f32 VR128:$src1), (undef),
PSHUFD_fp_shuffle_mask:$sm),
- (v4f32 (PSHUFDri VR128:$src1, PSHUFD_fp_shuffle_mask:$sm)),
- Requires[HasSSE2];
+ (v4f32 (SHUFPSrr VR128:$src1, VR128:$src1,
PSHUFD_fp_shuffle_mask:$sm)),
+ Requires[HasSSE1];
+// Shuffle v4f32 with PSHUF* if others do not match.
def : Pat(vector_shuffle (loadv4f32 addr:$src1), (undef),
PSHUFD_fp_shuffle_mask:$sm),
(v4f32 (PSHUFDmi addr:$src1, PSHUFD_fp_shuffle_mask:$sm)),
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.71 - 1.72
---
Log message:
Remove some bogus patterns; clean up.
---
Diffs of the changes: (+20 -53)
X86InstrSSE.td | 73 +++--
1 files changed, 20 insertions(+), 53 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.71
llvm/lib/Target/X86/X86InstrSSE.td:1.72
--- llvm/lib/Target/X86/X86InstrSSE.td:1.71 Mon Apr 10 16:42:19 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Mon Apr 10 17:35:16 2006
@@ -128,32 +128,16 @@
return X86::isPSHUFLWMask(N);
}], SHUFFLE_get_pshuflw_imm;
-// Only use PSHUF* for v4f32 if SHUFP does not match.
-def PSHUFD_fp_shuffle_mask : PatLeaf(build_vector), [{
- return !X86::isSHUFPMask(N)
- X86::isPSHUFDMask(N);
+def SHUFP_unary_shuffle_mask : PatLeaf(build_vector), [{
+ return X86::isPSHUFDMask(N);
}], SHUFFLE_get_shuf_imm;
-def PSHUFHW_fp_shuffle_mask : PatLeaf(build_vector), [{
- return !X86::isSHUFPMask(N)
- X86::isPSHUFHWMask(N);
-}], SHUFFLE_get_pshufhw_imm;
-
-def PSHUFLW_fp_shuffle_mask : PatLeaf(build_vector), [{
- return !X86::isSHUFPMask(N)
- X86::isPSHUFLWMask(N);
-}], SHUFFLE_get_pshuflw_imm;
-
def SHUFP_shuffle_mask : PatLeaf(build_vector), [{
return X86::isSHUFPMask(N);
}], SHUFFLE_get_shuf_imm;
-// Only use SHUFP for v4i32 if PSHUF* do not match.
-def SHUFP_int_shuffle_mask : PatLeaf(build_vector), [{
- return !X86::isPSHUFDMask(N)
- !X86::isPSHUFHWMask(N)
- !X86::isPSHUFLWMask(N)
- X86::isSHUFPMask(N);
+def PSHUFD_binary_shuffle_mask : PatLeaf(build_vector), [{
+ return X86::isSHUFPMask(N);
}], SHUFFLE_get_shuf_imm;
//===--===//
@@ -1813,16 +1797,6 @@
(v4f32 (SHUFPSrr VR128:$src, VR128:$src, SSE_splat_mask:$sm)),
Requires[HasSSE1];
-// Shuffle v4i32 with SHUFP* if others do not match.
-def : Pat(vector_shuffle (v4i32 VR128:$src1), (v4i32 VR128:$src2),
- SHUFP_int_shuffle_mask:$sm),
- (v4i32 (SHUFPSrr VR128:$src1, VR128:$src2,
- SHUFP_int_shuffle_mask:$sm)), Requires[HasSSE2];
-def : Pat(vector_shuffle (v4i32 VR128:$src1), (load addr:$src2),
- SHUFP_int_shuffle_mask:$sm),
- (v4i32 (SHUFPSrm VR128:$src1, addr:$src2,
- SHUFP_int_shuffle_mask:$sm)), Requires[HasSSE2];
-
// Special pshuf* cases: folding (bit_convert (loadv2i64 addr)).
def : Pat(v4i32 (vector_shuffle (bc_v4i32 (loadv2i64 addr:$src1)), (undef),
PSHUFD_shuffle_mask:$src2)),
@@ -1838,33 +1812,26 @@
Requires[HasSSE2];
-// Special SHUFPSrr case: looks like a PSHUFD, like make both operands src1.
-// FIXME: when we want non two-address code, then we should use PSHUFD!
+// Special unary SHUFPSrr case.
+// FIXME: when we want non two-address code, then we should use PSHUFD?
def : Pat(vector_shuffle (v4f32 VR128:$src1), (undef),
- PSHUFD_fp_shuffle_mask:$sm),
- (v4f32 (SHUFPSrr VR128:$src1, VR128:$src1,
PSHUFD_fp_shuffle_mask:$sm)),
+ SHUFP_unary_shuffle_mask:$sm),
+ (v4f32 (SHUFPSrr VR128:$src1, VR128:$src1,
SHUFP_unary_shuffle_mask:$sm)),
Requires[HasSSE1];
-// Shuffle v4f32 with PSHUF* if others do not match.
+// Unary v4f32 shuffle with PSHUF* in order to fold a load.
def : Pat(vector_shuffle (loadv4f32 addr:$src1), (undef),
- PSHUFD_fp_shuffle_mask:$sm),
- (v4f32 (PSHUFDmi addr:$src1, PSHUFD_fp_shuffle_mask:$sm)),
- Requires[HasSSE2];
-def : Pat(vector_shuffle (v4f32 VR128:$src1), (undef),
- PSHUFHW_fp_shuffle_mask:$sm),
- (v4f32 (PSHUFHWri VR128:$src1, PSHUFHW_fp_shuffle_mask:$sm)),
- Requires[HasSSE2];
-def : Pat(vector_shuffle (loadv4f32 addr:$src1), (undef),
- PSHUFHW_fp_shuffle_mask:$sm),
- (v4f32 (PSHUFHWmi addr:$src1, PSHUFHW_fp_shuffle_mask:$sm)),
- Requires[HasSSE2];
-def : Pat(vector_shuffle (v4f32 VR128:$src1), (undef),
- PSHUFLW_fp_shuffle_mask:$sm),
- (v4f32 (PSHUFLWri VR128:$src1, PSHUFLW_fp_shuffle_mask:$sm)),
- Requires[HasSSE2];
-def : Pat(vector_shuffle (loadv4f32 addr:$src1), (undef),
- PSHUFLW_fp_shuffle_mask:$sm),
- (v4f32 (PSHUFLWmi addr:$src1, PSHUFLW_fp_shuffle_mask:$sm)),
+ SHUFP_unary_shuffle_mask:$sm),
+ (v4f32 (PSHUFDmi addr:$src1, SHUFP_unary_shuffle_mask:$sm)),
Requires[HasSSE2];
+// Special binary v4i32 shuffle cases with SHUFPS.
+def : Pat(vector_shuffle (v4i32 VR128:$src1), (v4i32 VR128:$src2),
+ PSHUFD_binary_shuffle_mask:$sm),
+ (v4i32 (SHUFPSrr VR128:$src1, VR128:$src2,
+ PSHUFD_binary_shuffle_mask:$sm)), Requires[HasSSE2];
+def : Pat(vector_shuffle (v4i32 VR128:$src1), (load addr:$src2),
+ PSHUFD_binary_shuffle_mask:$sm),
+ (v4i32 (SHUFPSrm VR128:$src1, addr:$src2,
+
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.66 - 1.67
---
Log message:
Added patterns for MOVHPSmr and MOVLPSmr.
---
Diffs of the changes: (+42 -4)
X86InstrSSE.td | 46 ++
1 files changed, 42 insertions(+), 4 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.66
llvm/lib/Target/X86/X86InstrSSE.td:1.67
--- llvm/lib/Target/X86/X86InstrSSE.td:1.66 Thu Apr 6 18:53:29 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Fri Apr 7 16:20:58 2006
@@ -746,14 +746,23 @@
}
def MOVLPSmr : PSI0x13, MRMDestMem, (ops f64mem:$dst, VR128:$src),
- movlps {$src, $dst|$dst, $src}, [];
+ movlps {$src, $dst|$dst, $src},
+ [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
+ (i32 0))), addr:$dst)];
def MOVLPDmr : PDI0x13, MRMDestMem, (ops f64mem:$dst, VR128:$src),
movlpd {$src, $dst|$dst, $src},
[(store (f64 (vector_extract (v2f64 VR128:$src),
(i32 0))), addr:$dst)];
+// v2f64 extract element 1 is always custom lowered to unpack high to low
+// and extract element 0 so the non-store version isn't too horrible.
def MOVHPSmr : PSI0x17, MRMDestMem, (ops f64mem:$dst, VR128:$src),
- movhps {$src, $dst|$dst, $src}, [];
+ movhps {$src, $dst|$dst, $src},
+ [(store (f64 (vector_extract
+ (v2f64 (vector_shuffle
+ (bc_v2f64 (v4f32 VR128:$src)),
(undef),
+ UNPCKH_shuffle_mask)), (i32 0))),
+ addr:$dst)];
def MOVHPDmr : PDI0x17, MRMDestMem, (ops f64mem:$dst, VR128:$src),
movhpd {$src, $dst|$dst, $src},
[(store (f64 (vector_extract
@@ -1703,31 +1712,60 @@
Requires[HasSSE2];
def : Pat(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src),
Requires[HasSSE2];
+def : Pat(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src),
+ Requires[HasSSE2];
+def : Pat(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src),
+ Requires[HasSSE2];
def : Pat(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src),
Requires[HasSSE2];
def : Pat(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src),
Requires[HasSSE2];
def : Pat(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src),
Requires[HasSSE2];
+def : Pat(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src),
+ Requires[HasSSE2];
+def : Pat(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src),
+ Requires[HasSSE2];
def : Pat(v8i16 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src),
Requires[HasSSE2];
def : Pat(v8i16 (bitconvert (v4i32 VR128:$src))), (v4i32 VR128:$src),
Requires[HasSSE2];
def : Pat(v8i16 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src),
Requires[HasSSE2];
+def : Pat(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src),
+ Requires[HasSSE2];
+def : Pat(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src),
+ Requires[HasSSE2];
def : Pat(v16i8 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src),
Requires[HasSSE2];
def : Pat(v16i8 (bitconvert (v4i32 VR128:$src))), (v4i32 VR128:$src),
Requires[HasSSE2];
def : Pat(v16i8 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src),
Requires[HasSSE2];
-
-def : Pat(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src),
+def : Pat(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src),
+ Requires[HasSSE2];
+def : Pat(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src),
+ Requires[HasSSE2];
+def : Pat(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src),
Requires[HasSSE2];
def : Pat(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src),
Requires[HasSSE2];
+def : Pat(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src),
+ Requires[HasSSE2];
+def : Pat(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src),
+ Requires[HasSSE2];
def : Pat(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src),
Requires[HasSSE2];
+def : Pat(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src),
+ Requires[HasSSE2];
+def : Pat(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src),
+ Requires[HasSSE2];
+def : Pat(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src),
+ Requires[HasSSE2];
+def : Pat(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src),
+ Requires[HasSSE2];
+def : Pat(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src),
+ Requires[HasSSE2];
// Zeroing a VR128 then do a MOVS* to the lower bits.
def : Pat(v2f64 (X86zexts2vec FR64:$src)),
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.67 - 1.68
---
Log message:
ldmxcsr and stmxcsr.
---
Diffs of the changes: (+6 -2)
X86InstrSSE.td |8 ++--
1 files changed, 6 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.67
llvm/lib/Target/X86/X86InstrSSE.td:1.68
--- llvm/lib/Target/X86/X86InstrSSE.td:1.67 Fri Apr 7 16:20:58 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Fri Apr 7 19:47:44 2006
@@ -1538,9 +1538,13 @@
def SFENCE : I0xAE, MRM7m, (ops),
sfence, [], TB, Requires[HasSSE1];
-// Load MXCSR register
+// MXCSR register
def LDMXCSR : I0xAE, MRM2m, (ops i32mem:$src),
-ldmxcsr {$src|$src}, [], TB, Requires[HasSSE1];
+ldmxcsr $src,
+[(int_x86_sse_ldmxcsr addr:$src)], TB, Requires[HasSSE1];
+def STMXCSR : I0xAE, MRM3m, (ops i32mem:$dst),
+stmxcsr $dst,
+[(int_x86_sse_stmxcsr addr:$dst)], TB, Requires[HasSSE1];
//===--===//
// Alias Instructions
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.58 - 1.59
---
Log message:
PSHUF* encoding bugs.
---
Diffs of the changes: (+6 -6)
X86InstrSSE.td | 12 ++--
1 files changed, 6 insertions(+), 6 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.58
llvm/lib/Target/X86/X86InstrSSE.td:1.59
--- llvm/lib/Target/X86/X86InstrSSE.td:1.58 Mon Apr 3 22:04:07 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Tue Apr 4 13:40:36 2006
@@ -1239,14 +1239,14 @@
}
// Shuffle and unpack instructions
-def PSHUFWrr : PSIi80x70, MRMDestReg,
+def PSHUFWrr : PSIi80x70, MRMSrcReg,
(ops VR64:$dst, VR64:$src1, i8imm:$src2),
pshufw {$src2, $src1, $dst|$dst, $src1, $src2}, [];
def PSHUFWrm : PSIi80x70, MRMSrcMem,
(ops VR64:$dst, i64mem:$src1, i8imm:$src2),
pshufw {$src2, $src1, $dst|$dst, $src1, $src2}, [];
-def PSHUFDrr : PDIi80x70, MRMDestReg,
+def PSHUFDrr : PDIi80x70, MRMSrcReg,
(ops VR128:$dst, VR128:$src1, i8imm:$src2),
pshufd {$src2, $src1, $dst|$dst, $src1, $src2},
[(set VR128:$dst, (v4i32 (vector_shuffle
@@ -1260,14 +1260,14 @@
PSHUFD_shuffle_mask:$src2)))];
// SSE2 with ImmT == Imm8 and XS prefix.
-def PSHUFHWrr : Ii80x70, MRMDestReg,
+def PSHUFHWrr : Ii80x70, MRMSrcReg,
(ops VR128:$dst, VR128:$src1, i8imm:$src2),
pshufhw {$src2, $src1, $dst|$dst, $src1, $src2},
[(set VR128:$dst, (v8i16 (vector_shuffle
VR128:$src1, (undef),
PSHUFHW_shuffle_mask:$src2)))],
XS, Requires[HasSSE2];
-def PSHUFHWrm : Ii80x70, MRMDestMem,
+def PSHUFHWrm : Ii80x70, MRMSrcMem,
(ops VR128:$dst, i128mem:$src1, i8imm:$src2),
pshufhw {$src2, $src1, $dst|$dst, $src1, $src2},
[(set VR128:$dst, (v8i16 (vector_shuffle
@@ -1276,14 +1276,14 @@
XS, Requires[HasSSE2];
// SSE2 with ImmT == Imm8 and XD prefix.
-def PSHUFLWrr : Ii80x70, MRMDestReg,
+def PSHUFLWrr : Ii80x70, MRMSrcReg,
(ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
pshuflw {$src2, $src1, $dst|$dst, $src1, $src2},
[(set VR128:$dst, (v8i16 (vector_shuffle
VR128:$src1, (undef),
PSHUFLW_shuffle_mask:$src2)))],
XD, Requires[HasSSE2];
-def PSHUFLWrm : Ii80x70, MRMDestMem,
+def PSHUFLWrm : Ii80x70, MRMSrcMem,
(ops VR128:$dst, i128mem:$src1, i32i8imm:$src2),
pshuflw {$src2, $src1, $dst|$dst, $src1, $src2},
[(set VR128:$dst, (v8i16 (vector_shuffle
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td X86RegisterInfo.cpp
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.59 - 1.60
X86RegisterInfo.cpp updated: 1.133 - 1.134
---
Log message:
Minor fixes + naming changes.
---
Diffs of the changes: (+157 -156)
X86InstrSSE.td | 309 ++--
X86RegisterInfo.cpp |4
2 files changed, 157 insertions(+), 156 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.59
llvm/lib/Target/X86/X86InstrSSE.td:1.60
--- llvm/lib/Target/X86/X86InstrSSE.td:1.59 Tue Apr 4 13:40:36 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Tue Apr 4 14:12:30 2006
@@ -335,45 +335,46 @@
[(set FR64:$dst, (fsub FR64:$src1, (loadf64 addr:$src2)))];
}
-def SQRTSSrr : SSI0x51, MRMSrcReg, (ops FR32:$dst, FR32:$src),
- sqrtss {$src, $dst|$dst, $src},
- [(set FR32:$dst, (fsqrt FR32:$src))];
-def SQRTSSrm : SSI0x51, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
+def SQRTSSr : SSI0x51, MRMSrcReg, (ops FR32:$dst, FR32:$src),
+sqrtss {$src, $dst|$dst, $src},
+[(set FR32:$dst, (fsqrt FR32:$src))];
+def SQRTSSm : SSI0x51, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
sqrtss {$src, $dst|$dst, $src},
[(set FR32:$dst, (fsqrt (loadf32 addr:$src)))];
-def SQRTSDrr : SDI0x51, MRMSrcReg, (ops FR64:$dst, FR64:$src),
+def SQRTSDr : SDI0x51, MRMSrcReg, (ops FR64:$dst, FR64:$src),
sqrtsd {$src, $dst|$dst, $src},
[(set FR64:$dst, (fsqrt FR64:$src))];
-def SQRTSDrm : SDI0x51, MRMSrcMem, (ops FR64:$dst, f64mem:$src),
+def SQRTSDm : SDI0x51, MRMSrcMem, (ops FR64:$dst, f64mem:$src),
sqrtsd {$src, $dst|$dst, $src},
[(set FR64:$dst, (fsqrt (loadf64 addr:$src)))];
-def RSQRTSSrr : SSI0x52, MRMSrcReg, (ops FR32:$dst, FR32:$src),
+def RSQRTSSr : SSI0x52, MRMSrcReg, (ops FR32:$dst, FR32:$src),
rsqrtss {$src, $dst|$dst, $src}, [];
-def RSQRTSSrm : SSI0x52, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
+def RSQRTSSm : SSI0x52, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
rsqrtss {$src, $dst|$dst, $src}, [];
-def RCPSSrr : SSI0x53, MRMSrcReg, (ops FR32:$dst, FR32:$src),
- rcpss {$src, $dst|$dst, $src}, [];
-def RCPSSrm : SSI0x53, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
- rcpss {$src, $dst|$dst, $src}, [];
-
-def MAXSSrr : SSI0x5F, MRMSrcReg, (ops FR32:$dst, FR32:$src),
- maxss {$src, $dst|$dst, $src}, [];
-def MAXSSrm : SSI0x5F, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
- maxss {$src, $dst|$dst, $src}, [];
-def MAXSDrr : SDI0x5F, MRMSrcReg, (ops FR64:$dst, FR64:$src),
- maxsd {$src, $dst|$dst, $src}, [];
-def MAXSDrm : SDI0x5F, MRMSrcMem, (ops FR64:$dst, f64mem:$src),
- maxsd {$src, $dst|$dst, $src}, [];
-def MINSSrr : SSI0x5D, MRMSrcReg, (ops FR32:$dst, FR32:$src),
- minss {$src, $dst|$dst, $src}, [];
-def MINSSrm : SSI0x5D, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
- minss {$src, $dst|$dst, $src}, [];
-def MINSDrr : SDI0x5D, MRMSrcReg, (ops FR64:$dst, FR64:$src),
- minsd {$src, $dst|$dst, $src}, [];
-def MINSDrm : SDI0x5D, MRMSrcMem, (ops FR64:$dst, f64mem:$src),
- minsd {$src, $dst|$dst, $src}, [];
+def RCPSSr : SSI0x53, MRMSrcReg, (ops FR32:$dst, FR32:$src),
+ rcpss {$src, $dst|$dst, $src}, [];
+def RCPSSm : SSI0x53, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
+ rcpss {$src, $dst|$dst, $src}, [];
+let isTwoAddress = 1 in {
+def MAXSSrr : SSI0x5F, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
+ maxss {$src2, $dst|$dst, $src2}, [];
+def MAXSSrm : SSI0x5F, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
+ maxss {$src2, $dst|$dst, $src2}, [];
+def MAXSDrr : SDI0x5F, MRMSrcReg, (ops FR64:$dst, FR32:$src1, FR64:$src2),
+ maxsd {$src2, $dst|$dst, $src2}, [];
+def MAXSDrm : SDI0x5F, MRMSrcMem, (ops FR64:$dst, FR32:$src1, f64mem:$src2),
+ maxsd {$src2, $dst|$dst, $src2}, [];
+def MINSSrr : SSI0x5D, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
+ minss {$src2, $dst|$dst, $src2}, [];
+def MINSSrm : SSI0x5D, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
+ minss {$src2, $dst|$dst, $src2}, [];
+def MINSDrr : SDI0x5D, MRMSrcReg, (ops FR64:$dst, FR32:$src1, FR64:$src2),
+ minsd {$src2, $dst|$dst, $src2}, [];
+def MINSDrm : SDI0x5D, MRMSrcMem, (ops FR64:$dst, FR32:$src1, f64mem:$src2),
+ minsd {$src2, $dst|$dst, $src2}, [];
+}
// Aliases to match intrinsics which expect XMM operand(s).
let isTwoAddress = 1 in {
@@ -416,23 +417,23 @@
int_x86_sse2_sub_sd;
}
-def Int_SQRTSSrr : SS_Intr0x51, sqrtss {$src, $dst|$dst, $src},
-int_x86_sse_sqrt_ss;
-def
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.60 - 1.61
---
Log message:
Added pslldq and psrldq.
---
Diffs of the changes: (+18 -0)
X86InstrSSE.td | 18 ++
1 files changed, 18 insertions(+)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.60
llvm/lib/Target/X86/X86InstrSSE.td:1.61
--- llvm/lib/Target/X86/X86InstrSSE.td:1.60 Tue Apr 4 14:12:30 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Tue Apr 4 16:49:39 2006
@@ -57,6 +57,11 @@
return N-isExactlyValue(+0.0);
}];
+def PSxLDQ_imm : SDNodeXFormimm, [{
+ // Transformation function: imm 3
+ return getI32Imm(N-getValue() 3);
+}];
+
// SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,
// SHUFP* etc. imm.
def SHUFFLE_get_shuf_imm : SDNodeXFormbuild_vector, [{
@@ -1159,6 +1164,13 @@
(load addr:$src2];
}
+let isTwoAddress = 1 in {
+def PSLLDQri : PDIi80x73, MRM7r, (ops VR128:$dst, VR128:$src1,
i32i8imm:$src2),
+ pslldq {$src2, $dst|$dst, $src2}, [];
+def PSRLDQri : PDIi80x73, MRM7r, (ops VR128:$dst, VR128:$src1,
i32i8imm:$src2),
+ psrldq {$src2, $dst|$dst, $src2}, [];
+}
+
// Logical
let isTwoAddress = 1 in {
let isCommutable = 1 in {
@@ -1721,6 +1733,12 @@
(v4f32 (PSHUFLWmi addr:$src1, PSHUFLW_fp_shuffle_mask:$sm)),
Requires[HasSSE2];
+// 128-bit logical shifts
+def : Pat(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
+ (v2i64 (PSLLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)));
+def : Pat(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
+ (v2i64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)));
+
// Logical ops
def : Pat(and (bc_v4i32 (v4f32 VR128:$src1)), (loadv4i32 addr:$src2)),
(ANDPSrm VR128:$src1, addr:$src2);
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.55 - 1.56
---
Log message:
Some SSE1 intrinsics: min, max, sqrt, etc.
---
Diffs of the changes: (+91 -78)
X86InstrSSE.td | 169 ++---
1 files changed, 91 insertions(+), 78 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.55
llvm/lib/Target/X86/X86InstrSSE.td:1.56
--- llvm/lib/Target/X86/X86InstrSSE.td:1.55 Mon Apr 3 17:30:54 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Mon Apr 3 18:49:17 2006
@@ -171,6 +171,45 @@
//===--===//
// Helpers for defining instructions that directly correspond to intrinsics.
+class SS_Intrrbits8 o, string asm, Intrinsic IntId, ValueType Ty
+ : SSIo, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
+[(set VR128:$dst, (Ty (IntId VR128:$src1, VR128:$src2)))];
+class SS_Intrmbits8 o, string asm, Intrinsic IntId, ValueType Ty
+ : SSIo, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f32mem:$src2), asm,
+[(set VR128:$dst, (Ty (IntId VR128:$src1, (load addr:$src2];
+class SD_Intrrbits8 o, string asm, Intrinsic IntId, ValueType Ty
+ : SDIo, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
+[(set VR128:$dst, (Ty (IntId VR128:$src1, VR128:$src2)))];
+class SD_Intrmbits8 o, string asm, Intrinsic IntId, ValueType Ty
+ : SDIo, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2), asm,
+[(set VR128:$dst, (Ty (IntId VR128:$src1, (load addr:$src2];
+
+class PS_Intrbits8 o, string asm, Intrinsic IntId
+ : PSIo, MRMSrcReg, (ops VR128:$dst, VR128:$src), asm,
+[(set VR128:$dst, (IntId VR128:$src))];
+class PS_Intmbits8 o, string asm, Intrinsic IntId
+ : PSIo, MRMSrcMem, (ops VR128:$dst, f32mem:$src), asm,
+[(set VR128:$dst, (IntId (loadv4f32 addr:$src)))];
+class PD_Intrbits8 o, string asm, Intrinsic IntId
+ : PDIo, MRMSrcReg, (ops VR128:$dst, VR128:$src), asm,
+[(set VR128:$dst, (IntId VR128:$src))];
+class PD_Intmbits8 o, string asm, Intrinsic IntId
+ : PDIo, MRMSrcMem, (ops VR128:$dst, f64mem:$src), asm,
+[(set VR128:$dst, (IntId (loadv2f64 addr:$src)))];
+
+class PS_Intrrbits8 o, string asm, Intrinsic IntId
+ : PSIo, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
+[(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))];
+class PS_Intrmbits8 o, string asm, Intrinsic IntId
+ : PSIo, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f32mem:$src2), asm,
+[(set VR128:$dst, (IntId VR128:$src1, (loadv4f32 addr:$src2)))];
+class PD_Intrrbits8 o, string asm, Intrinsic IntId
+ : PDIo, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
+[(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))];
+class PD_Intrmbits8 o, string asm, Intrinsic IntId
+ : PDIo, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2), asm,
+[(set VR128:$dst, (IntId VR128:$src1, (loadv2f64 addr:$src2)))];
+
class S3S_Intrrbits8 o, string asm, Intrinsic IntId
: S3SIo, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
[(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))];
@@ -435,46 +474,22 @@
(load addr:$src)))];
let isTwoAddress = 1 in {
-def Int_MAXSSrr : SSI0x5F, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
-VR128:$src2),
- maxss {$src2, $dst|$dst, $src2},
- [(set VR128:$dst, (int_x86_sse_max_ss VR128:$src1,
- VR128:$src2))];
-def Int_MAXSSrm : SSI0x5F, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
-f32mem:$src2),
- maxss {$src2, $dst|$dst, $src2},
- [(set VR128:$dst, (int_x86_sse_max_ss VR128:$src1,
- (load addr:$src2)))];
-def Int_MAXSDrr : SDI0x5F, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
-VR128:$src2),
- maxsd {$src2, $dst|$dst, $src2},
- [(set VR128:$dst, (int_x86_sse2_max_sd VR128:$src1,
- VR128:$src2))];
-def Int_MAXSDrm : SDI0x5F, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
-f64mem:$src2),
- maxsd {$src2, $dst|$dst, $src2},
- [(set VR128:$dst, (int_x86_sse2_max_sd VR128:$src1,
- (load addr:$src2)))];
-def Int_MINSSrr : SSI0x5D, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
-VR128:$src2),
- minss {$src2, $dst|$dst, $src2},
- [(set VR128:$dst, (int_x86_sse_min_ss VR128:$src1,
- VR128:$src2))];
-def Int_MINSSrm : SSI0x5D, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
-
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.56 - 1.57
---
Log message:
Compact some intrinsic definitions.
---
Diffs of the changes: (+84 -123)
X86InstrSSE.td | 207 +++--
1 files changed, 84 insertions(+), 123 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.56
llvm/lib/Target/X86/X86InstrSSE.td:1.57
--- llvm/lib/Target/X86/X86InstrSSE.td:1.56 Mon Apr 3 18:49:17 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Mon Apr 3 19:10:53 2006
@@ -171,18 +171,31 @@
//===--===//
// Helpers for defining instructions that directly correspond to intrinsics.
-class SS_Intrrbits8 o, string asm, Intrinsic IntId, ValueType Ty
+class SS_Intrbits8 o, string asm, Intrinsic IntId
+ : SSIo, MRMSrcReg, (ops VR128:$dst, VR128:$src), asm,
+[(set VR128:$dst, (v4f32 (IntId VR128:$src)))];
+class SS_Intmbits8 o, string asm, Intrinsic IntId
+ : SSIo, MRMSrcMem, (ops VR128:$dst, f32mem:$src), asm,
+[(set VR128:$dst, (v4f32 (IntId (load addr:$src];
+class SD_Intrbits8 o, string asm, Intrinsic IntId
+ : SDIo, MRMSrcReg, (ops VR128:$dst, VR128:$src), asm,
+[(set VR128:$dst, (v2f64 (IntId VR128:$src)))];
+class SD_Intmbits8 o, string asm, Intrinsic IntId
+ : SDIo, MRMSrcMem, (ops VR128:$dst, f64mem:$src), asm,
+[(set VR128:$dst, (v2f64 (IntId (load addr:$src];
+
+class SS_Intrrbits8 o, string asm, Intrinsic IntId
: SSIo, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
-[(set VR128:$dst, (Ty (IntId VR128:$src1, VR128:$src2)))];
-class SS_Intrmbits8 o, string asm, Intrinsic IntId, ValueType Ty
+[(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))];
+class SS_Intrmbits8 o, string asm, Intrinsic IntId
: SSIo, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f32mem:$src2), asm,
-[(set VR128:$dst, (Ty (IntId VR128:$src1, (load addr:$src2];
-class SD_Intrrbits8 o, string asm, Intrinsic IntId, ValueType Ty
+[(set VR128:$dst, (v4f32 (IntId VR128:$src1, (load addr:$src2];
+class SD_Intrrbits8 o, string asm, Intrinsic IntId
: SDIo, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
-[(set VR128:$dst, (Ty (IntId VR128:$src1, VR128:$src2)))];
-class SD_Intrmbits8 o, string asm, Intrinsic IntId, ValueType Ty
+[(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))];
+class SD_Intrmbits8 o, string asm, Intrinsic IntId
: SDIo, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2), asm,
-[(set VR128:$dst, (Ty (IntId VR128:$src1, (load addr:$src2];
+[(set VR128:$dst, (v2f64 (IntId VR128:$src1, (load addr:$src2];
class PS_Intrbits8 o, string asm, Intrinsic IntId
: PSIo, MRMSrcReg, (ops VR128:$dst, VR128:$src), asm,
@@ -365,131 +378,79 @@
// Aliases to match intrinsics which expect XMM operand(s).
let isTwoAddress = 1 in {
let isCommutable = 1 in {
-def Int_ADDSSrr : SSI0x58, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
-VR128:$src2),
-addss {$src2, $dst|$dst, $src2},
-[(set VR128:$dst, (int_x86_sse_add_ss VR128:$src1,
- VR128:$src2))];
-def Int_ADDSDrr : SDI0x58, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
-VR128:$src2),
-addsd {$src2, $dst|$dst, $src2},
-[(set VR128:$dst, (int_x86_sse2_add_sd VR128:$src1,
- VR128:$src2))];
-def Int_MULSSrr : SSI0x59, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
-VR128:$src2),
-mulss {$src2, $dst|$dst, $src2},
-[(set VR128:$dst, (int_x86_sse_mul_ss VR128:$src1,
- VR128:$src2))];
-def Int_MULSDrr : SDI0x59, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
-VR128:$src2),
-mulsd {$src2, $dst|$dst, $src2},
-[(set VR128:$dst, (int_x86_sse2_mul_sd VR128:$src1,
- VR128:$src2))];
-}
-
-def Int_ADDSSrm : SSI0x58, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
-f32mem:$src2),
-addss {$src2, $dst|$dst, $src2},
-[(set VR128:$dst, (int_x86_sse_add_ss VR128:$src1,
- (load addr:$src2)))];
-def Int_ADDSDrm : SDI0x58, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
-f64mem:$src2),
-addsd {$src2, $dst|$dst, $src2},
-[(set VR128:$dst, (int_x86_sse2_add_sd VR128:$src1,
- (load addr:$src2)))];
-def Int_MULSSrm : SSI0x59, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
-f32mem:$src2),
-mulss {$src2, $dst|$dst, $src2},
-
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.51 - 1.52
---
Log message:
Added support for SSE3 horizontal ops: haddp{s|d} and hsub{s|d}.
---
Diffs of the changes: (+43 -0)
X86InstrSSE.td | 43 +++
1 files changed, 43 insertions(+)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.51
llvm/lib/Target/X86/X86InstrSSE.td:1.52
--- llvm/lib/Target/X86/X86InstrSSE.td:1.51 Fri Mar 31 13:22:53 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Fri Mar 31 15:29:33 2006
@@ -145,6 +145,8 @@
// PDI - SSE2 instructions with TB and OpSize prefixes.
// PSIi8 - SSE1 instructions with ImmT == Imm8 and TB prefix.
// PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
+// S3SI - SSE3 instructions with XD prefix.
+// S3DI - SSE3 instructions with TB and OpSize prefixes.
class SSIbits8 o, Format F, dag ops, string asm, listdag pattern
: Io, F, ops, asm, pattern, XS, Requires[HasSSE1];
class SDIbits8 o, Format F, dag ops, string asm, listdag pattern
@@ -161,6 +163,27 @@
: X86Insto, F, Imm8, ops, asm, TB, OpSize, Requires[HasSSE2] {
let Pattern = pattern;
}
+class S3SIbits8 o, Format F, dag ops, string asm, listdag pattern
+ : Io, F, ops, asm, pattern, XD, Requires[HasSSE3];
+class S3DIbits8 o, Format F, dag ops, string asm, listdag pattern
+ : Io, F, ops, asm, pattern, TB, OpSize, Requires[HasSSE3];
+
+//===--===//
+// Helpers for defining instructions that directly correspond to intrinsics.
+class S3S_Intrrbits8 o, string asm, Intrinsic IntId
+ : S3SIo, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
+ [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))];
+class S3S_Intrmbits8 o, string asm, Intrinsic IntId
+ : S3SIo, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2), asm,
+ [(set VR128:$dst, (v4f32 (IntId VR128:$src1,
+ (loadv4f32 addr:$src2];
+class S3D_Intrrbits8 o, string asm, Intrinsic IntId
+ : S3DIo, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
+ [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))];
+class S3D_Intrmbits8 o, string asm, Intrinsic IntId
+ : S3DIo, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2), asm,
+ [(set VR128:$dst, (v2f64 (IntId VR128:$src1,
+ (loadv2f64 addr:$src2];
// Some 'special' instructions
def IMPLICIT_DEF_FR32 : I0, Pseudo, (ops FR32:$dst),
@@ -1073,6 +1096,26 @@
UNPCKL_shuffle_mask)))];
}
+// Horizontal ops
+let isTwoAddress = 1 in {
+def HADDPSrr : S3S_Intrr0x7C, haddps {$src2, $dst|$dst, $src2},
+ int_x86_sse3_hadd_ps;
+def HADDPSrm : S3S_Intrm0x7C, haddps {$src2, $dst|$dst, $src2},
+ int_x86_sse3_hadd_ps;
+def HADDPDrr : S3D_Intrr0x7C, haddpd {$src2, $dst|$dst, $src2},
+ int_x86_sse3_hadd_pd;
+def HADDPDrm : S3D_Intrm0x7C, haddpd {$src2, $dst|$dst, $src2},
+ int_x86_sse3_hadd_pd;
+def HSUBPSrr : S3S_Intrr0x7C, hsubps {$src2, $dst|$dst, $src2},
+ int_x86_sse3_hsub_ps;
+def HSUBPSrm : S3S_Intrm0x7C, hsubps {$src2, $dst|$dst, $src2},
+ int_x86_sse3_hsub_ps;
+def HSUBPDrr : S3D_Intrr0x7C, hsubpd {$src2, $dst|$dst, $src2},
+ int_x86_sse3_hsub_pd;
+def HSUBPDrm : S3D_Intrm0x7C, hsubpd {$src2, $dst|$dst, $src2},
+ int_x86_sse3_hsub_pd;
+}
+
//===--===//
// SSE integer instructions
//===--===//
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.42 - 1.43
---
Log message:
Floating point logical operation patterns should match bit_convert. Or else
integer vector logical operations would match andp{s|d} instead of pand.
---
Diffs of the changes: (+53 -29)
X86InstrSSE.td | 82 -
1 files changed, 53 insertions(+), 29 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.42
llvm/lib/Target/X86/X86InstrSSE.td:1.43
--- llvm/lib/Target/X86/X86InstrSSE.td:1.42 Tue Mar 28 21:04:49 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Wed Mar 29 12:47:40 2006
@@ -45,6 +45,9 @@
def loadv4i32: PatFrag(ops node:$ptr), (v4i32 (load node:$ptr));
def loadv2i64: PatFrag(ops node:$ptr), (v2i64 (load node:$ptr));
+def bc_v4i32 : PatFrag(ops node:$in), (v4i32 (bitconvert node:$in));
+def bc_v2i64 : PatFrag(ops node:$in), (v2i64 (bitconvert node:$in));
+
def fp32imm0 : PatLeaf(f32 fpimm), [{
return N-isExactlyValue(+0.0);
}];
@@ -835,64 +838,85 @@
let isCommutable = 1 in {
def ANDPSrr : PSI0x54, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
andps {$src2, $dst|$dst, $src2},
- [(set VR128:$dst, (v4i32 (and VR128:$src1, VR128:$src2)))];
+ [(set VR128:$dst,
+(and (bc_v4i32 (v4f32 VR128:$src1)),
+ (bc_v4i32 (v4f32 VR128:$src2];
def ANDPDrr : PDI0x54, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
andpd {$src2, $dst|$dst, $src2},
- [(set VR128:$dst, (v2i64 (and VR128:$src1, VR128:$src2)))];
+ [(set VR128:$dst,
+(and (bc_v2i64 (v2f64 VR128:$src1)),
+ (bc_v2i64 (v2f64 VR128:$src2];
def ORPSrr : PSI0x56, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
orps {$src2, $dst|$dst, $src2},
- [(set VR128:$dst, (v4i32 (or VR128:$src1, VR128:$src2)))];
+ [(set VR128:$dst,
+(or (bc_v4i32 (v4f32 VR128:$src1)),
+ (bc_v4i32 (v4f32 VR128:$src2];
def ORPDrr : PDI0x56, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
orpd {$src2, $dst|$dst, $src2},
- [(set VR128:$dst, (v2i64 (or VR128:$src1, VR128:$src2)))];
+ [(set VR128:$dst,
+(or (bc_v2i64 (v2f64 VR128:$src1)),
+ (bc_v2i64 (v2f64 VR128:$src2];
def XORPSrr : PSI0x57, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
xorps {$src2, $dst|$dst, $src2},
- [(set VR128:$dst, (v4i32 (xor VR128:$src1, VR128:$src2)))];
+ [(set VR128:$dst,
+(xor (bc_v4i32 (v4f32 VR128:$src1)),
+ (bc_v4i32 (v4f32 VR128:$src2];
def XORPDrr : PDI0x57, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
xorpd {$src2, $dst|$dst, $src2},
- [(set VR128:$dst, (v2i64 (xor VR128:$src1, VR128:$src2)))];
+ [(set VR128:$dst,
+(xor (bc_v2i64 (v2f64 VR128:$src1)),
+ (bc_v2i64 (v2f64 VR128:$src2];
}
def ANDPSrm : PSI0x54, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
f128mem:$src2),
andps {$src2, $dst|$dst, $src2},
- [(set VR128:$dst, (v4i32 (and VR128:$src1,
-(load addr:$src2];
+[(set VR128:$dst,
+ (and (bc_v4i32 (v4f32 VR128:$src1)),
+ (bc_v4i32 (loadv4f32 addr:$src2];
def ANDPDrm : PDI0x54, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
f128mem:$src2),
andpd {$src2, $dst|$dst, $src2},
- [(set VR128:$dst, (v2i64 (and VR128:$src1,
-(load addr:$src2];
+[(set VR128:$dst,
+ (and (bc_v2i64 (v2f64 VR128:$src1)),
+ (bc_v2i64 (loadv2f64 addr:$src2];
def ORPSrm : PSI0x56, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
f128mem:$src2),
orps {$src2, $dst|$dst, $src2},
- [(set VR128:$dst, (v4i32 (or VR128:$src1,
-(load addr:$src2];
+ [(set VR128:$dst,
+ (or (bc_v4i32 (v4f32 VR128:$src1)),
+(bc_v4i32 (loadv4f32 addr:$src2];
def ORPDrm : PDI0x56, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
f128mem:$src2),
orpd {$src2, $dst|$dst, $src2},
- [(set VR128:$dst, (v2i64 (or VR128:$src1,
-(load addr:$src2];
+ [(set VR128:$dst,
+ (or (bc_v2i64 (v2f64 VR128:$src1)),
+(bc_v2i64 (loadv2f64 addr:$src2];
def XORPSrm : PSI0x57, MRMSrcMem, (ops VR128:$dst,
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.45 - 1.46
---
Log message:
Change SSE pack operation definitions to fit what the intrinsics expected.
For example, packsswb actually creates a v16i8 from a pair of v8i16. But since
the intrinsic specification forces the output type to match the operands.
---
Diffs of the changes: (+20 -20)
X86InstrSSE.td | 40
1 files changed, 20 insertions(+), 20 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.45
llvm/lib/Target/X86/X86InstrSSE.td:1.46
--- llvm/lib/Target/X86/X86InstrSSE.td:1.45 Wed Mar 29 17:07:14 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Wed Mar 29 17:52:48 2006
@@ -1182,39 +1182,39 @@
def PACKSSWBrr : PDI0x63, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
VR128:$src2),
packsswb {$src2, $dst|$dst, $src2},
- [(set VR128:$dst, (v16i8 (int_x86_sse2_packsswb_128
- (v8i16 VR128:$src1),
- (v8i16 VR128:$src2];
+ [(set VR128:$dst, (v8i16 (int_x86_sse2_packsswb_128
+ VR128:$src1,
+ VR128:$src2)))];
def PACKSSWBrm : PDI0x63, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
packsswb {$src2, $dst|$dst, $src2},
- [(set VR128:$dst, (v16i8 (int_x86_sse2_packsswb_128
- (v8i16 VR128:$src1),
- (loadv8i16 addr:$src2];
+ [(set VR128:$dst, (v8i16 (int_x86_sse2_packsswb_128
+ VR128:$src1,
+ (bc_v8i16 (loadv2f64
addr:$src2)];
def PACKSSDWrr : PDI0x6B, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
VR128:$src2),
- packsswb {$src2, $dst|$dst, $src2},
- [(set VR128:$dst, (v8i16 (int_x86_sse2_packssdw_128
- (v4i32 VR128:$src1),
- (v4i32 VR128:$src2];
+ packssdw {$src2, $dst|$dst, $src2},
+ [(set VR128:$dst, (v4i32 (int_x86_sse2_packssdw_128
+ VR128:$src1,
+ VR128:$src2)))];
def PACKSSDWrm : PDI0x6B, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
- packsswb {$src2, $dst|$dst, $src2},
- [(set VR128:$dst, (v8i16 (int_x86_sse2_packssdw_128
- (v4i32 VR128:$src1),
- (loadv4i32 addr:$src2];
+ packssdw {$src2, $dst|$dst, $src2},
+ [(set VR128:$dst, (v4i32 (int_x86_sse2_packssdw_128
+ VR128:$src1,
+ (bc_v4i32 (loadv2i64
addr:$src2)];
def PACKUSWBrr : PDI0x67, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
VR128:$src2),
packuswb {$src2, $dst|$dst, $src2},
- [(set VR128:$dst, (v16i8 (int_x86_sse2_packuswb_128
- (v8i16 VR128:$src1),
- (v8i16 VR128:$src2];
+ [(set VR128:$dst, (v8i16 (int_x86_sse2_packuswb_128
+ VR128:$src1,
+ VR128:$src2)))];
def PACKUSWBrm : PDI0x67, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
i128mem:$src2),
packuswb {$src2, $dst|$dst, $src2},
- [(set VR128:$dst, (v16i8 (int_x86_sse2_packuswb_128
- (v8i16 VR128:$src1),
- (loadv8i16 addr:$src2];
+ [(set VR128:$dst, (v8i16 (int_x86_sse2_packuswb_128
+ VR128:$src1,
+ (bc_v8i16 (loadv2i64
addr:$src2)];
}
// Shuffle and unpack instructions
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.46 - 1.47
---
Log message:
Add 128-bit pmovmskb intrinsic support.
---
Diffs of the changes: (+12 -7)
X86InstrSSE.td | 19 ---
1 files changed, 12 insertions(+), 7 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.46
llvm/lib/Target/X86/X86InstrSSE.td:1.47
--- llvm/lib/Target/X86/X86InstrSSE.td:1.46 Wed Mar 29 17:52:48 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Wed Mar 29 18:33:26 2006
@@ -686,13 +686,6 @@
MOVHLPS_shuffle_mask)))];
}
-def MOVMSKPSrr : PSI0x50, MRMSrcReg, (ops R32:$dst, VR128:$src),
- movmskps {$src, $dst|$dst, $src},
- [(set R32:$dst, (int_x86_sse_movmsk_ps VR128:$src))];
-def MOVMSKPDrr : PSI0x50, MRMSrcReg, (ops R32:$dst, VR128:$src),
- movmskpd {$src, $dst|$dst, $src},
- [(set R32:$dst, (int_x86_sse2_movmskpd VR128:$src))];
-
// Conversion instructions
def CVTPI2PSrr : PSI0x2A, MRMSrcReg, (ops VR128:$dst, VR64:$src),
cvtpi2ps {$src, $dst|$dst, $src}, [];
@@ -1374,6 +1367,18 @@
// Miscellaneous Instructions
//===--===//
+// Mask creation
+def MOVMSKPSrr : PSI0x50, MRMSrcReg, (ops R32:$dst, VR128:$src),
+ movmskps {$src, $dst|$dst, $src},
+ [(set R32:$dst, (int_x86_sse_movmsk_ps VR128:$src))];
+def MOVMSKPDrr : PSI0x50, MRMSrcReg, (ops R32:$dst, VR128:$src),
+ movmskpd {$src, $dst|$dst, $src},
+ [(set R32:$dst, (int_x86_sse2_movmskpd VR128:$src))];
+
+def PMOVMSKBrr : PDI0xD7, MRMSrcReg, (ops R32:$dst, VR128:$src),
+ pmovmskb {$src, $dst|$dst, $src},
+ [(set R32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))];
+
// Prefetching loads
def PREFETCHT0 : I0x18, MRM1m, (ops i8mem:$src),
prefetcht0 $src, [], TB,
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.47 - 1.48
---
Log message:
Add support for _mm_cmp{cc}_ss and _mm_cmp{cc}_ps intrinsics
---
Diffs of the changes: (+35 -9)
X86InstrSSE.td | 44 +++-
1 files changed, 35 insertions(+), 9 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.47
llvm/lib/Target/X86/X86InstrSSE.td:1.48
--- llvm/lib/Target/X86/X86InstrSSE.td:1.47 Wed Mar 29 18:33:26 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Thu Mar 30 00:21:22 2006
@@ -501,7 +501,8 @@
let isTwoAddress = 1 in {
def CMPSSrr : SSI0xC2, MRMSrcReg,
(ops FR32:$dst, FR32:$src1, FR32:$src, SSECC:$cc),
-cmp${cc}ss {$src, $dst|$dst, $src}, [];
+cmp${cc}ss {$src, $dst|$dst, $src},
+ [];
def CMPSSrm : SSI0xC2, MRMSrcMem,
(ops FR32:$dst, FR32:$src1, f32mem:$src, SSECC:$cc),
cmp${cc}ss {$src, $dst|$dst, $src}, [];
@@ -526,6 +527,27 @@
ucomisd {$src2, $src1|$src1, $src2},
[(X86cmp FR64:$src1, (loadf64 addr:$src2))];
+// Aliases to match intrinsics which expect XMM operand(s).
+let isTwoAddress = 1 in {
+def Int_CMPSSrr : SSI0xC2, MRMSrcReg,
+ (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
+ cmp${cc}ss {$src, $dst|$dst, $src},
+ [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
+ VR128:$src, imm:$cc))];
+def Int_CMPSSrm : SSI0xC2, MRMSrcMem,
+ (ops VR128:$dst, VR128:$src1, f32mem:$src, SSECC:$cc),
+ cmp${cc}ss {$src, $dst|$dst, $src},
+ [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
+ (load addr:$src), imm:$cc))];
+def Int_CMPSDrr : SDI0xC2, MRMSrcReg,
+ (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
+ cmp${cc}sd {$src, $dst|$dst, $src}, [];
+def Int_CMPSDrm : SDI0xC2, MRMSrcMem,
+ (ops VR128:$dst, VR128:$src1, f64mem:$src, SSECC:$cc),
+ cmp${cc}sd {$src, $dst|$dst, $src}, [];
+}
+
+
// Aliases of packed instructions for scalar use. These all have names that
// start with 'Fs'.
@@ -936,17 +958,21 @@
let isTwoAddress = 1 in {
def CMPPSrr : PSI0xC2, MRMSrcReg,
-(ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
-cmp${cc}ps {$src, $dst|$dst, $src}, [];
+ (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
+ cmp${cc}ps {$src, $dst|$dst, $src},
+ [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
+ VR128:$src, imm:$cc))];
def CMPPSrm : PSI0xC2, MRMSrcMem,
-(ops VR128:$dst, VR128:$src1, f128mem:$src, SSECC:$cc),
-cmp${cc}ps {$src, $dst|$dst, $src}, [];
+ (ops VR128:$dst, VR128:$src1, f128mem:$src, SSECC:$cc),
+ cmp${cc}ps {$src, $dst|$dst, $src},
+ [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
+ (load addr:$src), imm:$cc))];
def CMPPDrr : PDI0xC2, MRMSrcReg,
-(ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
-cmp${cc}pd {$src, $dst|$dst, $src}, [];
+ (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
+ cmp${cc}pd {$src, $dst|$dst, $src}, [];
def CMPPDrm : PDI0xC2, MRMSrcMem,
-(ops VR128:$dst, VR128:$src1, f128mem:$src, SSECC:$cc),
-cmp${cc}pd {$src, $dst|$dst, $src}, [];
+ (ops VR128:$dst, VR128:$src1, f128mem:$src, SSECC:$cc),
+ cmp${cc}pd {$src, $dst|$dst, $src}, [];
}
// Shuffle and unpack instructions
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86: X86InstrSSE.td updated: 1.48 - 1.49 --- Log message: More logical ops patterns --- Diffs of the changes: (+106 -0) X86InstrSSE.td | 106 + 1 files changed, 106 insertions(+) Index: llvm/lib/Target/X86/X86InstrSSE.td diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.48 llvm/lib/Target/X86/X86InstrSSE.td:1.49 --- llvm/lib/Target/X86/X86InstrSSE.td:1.48 Thu Mar 30 00:21:22 2006 +++ llvm/lib/Target/X86/X86InstrSSE.td Thu Mar 30 01:33:32 2006 @@ -45,6 +45,8 @@ def loadv4i32: PatFrag(ops node:$ptr), (v4i32 (load node:$ptr)); def loadv2i64: PatFrag(ops node:$ptr), (v2i64 (load node:$ptr)); +def bc_v4f32 : PatFrag(ops node:$in), (v4f32 (bitconvert node:$in)); +def bc_v2f64 : PatFrag(ops node:$in), (v2f64 (bitconvert node:$in)); def bc_v16i8 : PatFrag(ops node:$in), (v16i8 (bitconvert node:$in)); def bc_v8i16 : PatFrag(ops node:$in), (v8i16 (bitconvert node:$in)); def bc_v4i32 : PatFrag(ops node:$in), (v4i32 (bitconvert node:$in)); @@ -1600,3 +1602,107 @@ SHUFP_shuffle_mask:$sm), (v4i32 (SHUFPSrm VR128:$src1, addr:$src2, SHUFP_v4i32_shuffle_mask:$sm)), Requires[HasSSE2]; + +// Logical ops +def : Pat(and (bc_v4i32 (v4f32 VR128:$src1)), (loadv4i32 addr:$src2)), + (ANDPSrm VR128:$src1, addr:$src2); +def : Pat(and (bc_v2i64 (v2f64 VR128:$src1)), (loadv2i64 addr:$src2)), + (ANDPDrm VR128:$src1, addr:$src2); +def : Pat(or (bc_v4i32 (v4f32 VR128:$src1)), (loadv4i32 addr:$src2)), + (ORPSrm VR128:$src1, addr:$src2); +def : Pat(or (bc_v2i64 (v2f64 VR128:$src1)), (loadv2i64 addr:$src2)), + (ORPDrm VR128:$src1, addr:$src2); +def : Pat(xor (bc_v4i32 (v4f32 VR128:$src1)), (loadv4i32 addr:$src2)), + (XORPSrm VR128:$src1, addr:$src2); +def : Pat(xor (bc_v2i64 (v2f64 VR128:$src1)), (loadv2i64 addr:$src2)), + (XORPDrm VR128:$src1, addr:$src2); +def : Pat(and (vnot (bc_v4i32 (v4f32 VR128:$src1))), (loadv4i32 addr:$src2)), + (ANDNPSrm VR128:$src1, addr:$src2); +def : Pat(and (vnot (bc_v2i64 (v2f64 VR128:$src1))), (loadv2i64 addr:$src2)), + (ANDNPDrm VR128:$src1, addr:$src2); + +def : Pat(bc_v4f32 (v4i32 (and VR128:$src1, VR128:$src2))), + (ANDPSrr VR128:$src1, VR128:$src2); +def : Pat(bc_v4f32 (v4i32 (or VR128:$src1, VR128:$src2))), + (ORPSrr VR128:$src1, VR128:$src2); +def : Pat(bc_v4f32 (v4i32 (xor VR128:$src1, VR128:$src2))), + (XORPSrr VR128:$src1, VR128:$src2); +def : Pat(bc_v4f32 (v4i32 (and (vnot VR128:$src1), VR128:$src2))), + (ANDNPSrr VR128:$src1, VR128:$src2); + +def : Pat(bc_v4f32 (v4i32 (and VR128:$src1, (load addr:$src2, + (ANDPSrm (v4i32 VR128:$src1), addr:$src2); +def : Pat(bc_v4f32 (v4i32 (or VR128:$src1, (load addr:$src2, + (ORPSrm VR128:$src1, addr:$src2); +def : Pat(bc_v4f32 (v4i32 (xor VR128:$src1, (load addr:$src2, + (XORPSrm VR128:$src1, addr:$src2); +def : Pat(bc_v4f32 (v4i32 (and (vnot VR128:$src1), (load addr:$src2, + (ANDNPSrm VR128:$src1, addr:$src2); + +def : Pat(bc_v2f64 (v2i64 (and VR128:$src1, VR128:$src2))), + (ANDPDrr VR128:$src1, VR128:$src2); +def : Pat(bc_v2f64 (v2i64 (or VR128:$src1, VR128:$src2))), + (ORPDrr VR128:$src1, VR128:$src2); +def : Pat(bc_v2f64 (v2i64 (xor VR128:$src1, VR128:$src2))), + (XORPDrr VR128:$src1, VR128:$src2); +def : Pat(bc_v2f64 (v2i64 (and (vnot VR128:$src1), VR128:$src2))), + (ANDNPDrr VR128:$src1, VR128:$src2); + +def : Pat(bc_v2f64 (v2i64 (and VR128:$src1, (load addr:$src2, + (ANDPSrm (v2i64 VR128:$src1), addr:$src2); +def : Pat(bc_v2f64 (v2i64 (or VR128:$src1, (load addr:$src2, + (ORPSrm VR128:$src1, addr:$src2); +def : Pat(bc_v2f64 (v2i64 (xor VR128:$src1, (load addr:$src2, + (XORPSrm VR128:$src1, addr:$src2); +def : Pat(bc_v2f64 (v2i64 (and (vnot VR128:$src1), (load addr:$src2, + (ANDNPSrm VR128:$src1, addr:$src2); + +def : Pat(v4i32 (and VR128:$src1, VR128:$src2)), + (PANDrr VR128:$src1, VR128:$src2); +def : Pat(v8i16 (and VR128:$src1, VR128:$src2)), + (PANDrr VR128:$src1, VR128:$src2); +def : Pat(v16i8 (and VR128:$src1, VR128:$src2)), + (PANDrr VR128:$src1, VR128:$src2); +def : Pat(v4i32 (or VR128:$src1, VR128:$src2)), + (PORrr VR128:$src1, VR128:$src2); +def : Pat(v8i16 (or VR128:$src1, VR128:$src2)), + (PORrr VR128:$src1, VR128:$src2); +def : Pat(v16i8 (or VR128:$src1, VR128:$src2)), + (PORrr VR128:$src1, VR128:$src2); +def : Pat(v4i32 (xor VR128:$src1, VR128:$src2)), + (PXORrr VR128:$src1, VR128:$src2); +def : Pat(v8i16 (xor VR128:$src1, VR128:$src2)), + (PXORrr VR128:$src1, VR128:$src2); +def : Pat(v16i8 (xor VR128:$src1, VR128:$src2)), + (PXORrr VR128:$src1, VR128:$src2); +def : Pat(v4i32 (and (vnot VR128:$src1), VR128:$src2)), + (PANDNrr VR128:$src1,
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.39 - 1.40
---
Log message:
Added aliases to scalar SSE instructions, e.g. addss, to match x86 intrinsics.
The source operands type are v4sf with upper bits passes through.
Added matching code for these.
---
Diffs of the changes: (+201 -47)
X86InstrSSE.td | 248 ++---
1 files changed, 201 insertions(+), 47 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.39
llvm/lib/Target/X86/X86InstrSSE.td:1.40
--- llvm/lib/Target/X86/X86InstrSSE.td:1.39 Tue Mar 28 01:01:28 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Tue Mar 28 17:51:43 2006
@@ -174,53 +174,6 @@
[(set VR128:$dst,
(v2f64 (scalar_to_vector (loadf64 addr:$src];
-
-// Conversion instructions
-def CVTSS2SIrr: SSI0x2D, MRMSrcReg, (ops R32:$dst, FR32:$src),
- cvtss2si {$src, $dst|$dst, $src}, [];
-def CVTSS2SIrm: SSI0x2D, MRMSrcMem, (ops R32:$dst, f32mem:$src),
- cvtss2si {$src, $dst|$dst, $src}, [];
-
-def CVTTSS2SIrr: SSI0x2C, MRMSrcReg, (ops R32:$dst, FR32:$src),
- cvttss2si {$src, $dst|$dst, $src},
- [(set R32:$dst, (fp_to_sint FR32:$src))];
-def CVTTSS2SIrm: SSI0x2C, MRMSrcMem, (ops R32:$dst, f32mem:$src),
- cvttss2si {$src, $dst|$dst, $src},
- [(set R32:$dst, (fp_to_sint (loadf32 addr:$src)))];
-def CVTTSD2SIrr: SDI0x2C, MRMSrcReg, (ops R32:$dst, FR64:$src),
- cvttsd2si {$src, $dst|$dst, $src},
- [(set R32:$dst, (fp_to_sint FR64:$src))];
-def CVTTSD2SIrm: SDI0x2C, MRMSrcMem, (ops R32:$dst, f64mem:$src),
- cvttsd2si {$src, $dst|$dst, $src},
- [(set R32:$dst, (fp_to_sint (loadf64 addr:$src)))];
-def CVTSD2SSrr: SDI0x5A, MRMSrcReg, (ops FR32:$dst, FR64:$src),
- cvtsd2ss {$src, $dst|$dst, $src},
- [(set FR32:$dst, (fround FR64:$src))];
-def CVTSD2SSrm: SDI0x5A, MRMSrcMem, (ops FR32:$dst, f64mem:$src),
- cvtsd2ss {$src, $dst|$dst, $src},
- [(set FR32:$dst, (fround (loadf64 addr:$src)))];
-def CVTSI2SSrr: SSI0x2A, MRMSrcReg, (ops FR32:$dst, R32:$src),
- cvtsi2ss {$src, $dst|$dst, $src},
- [(set FR32:$dst, (sint_to_fp R32:$src))];
-def CVTSI2SSrm: SSI0x2A, MRMSrcMem, (ops FR32:$dst, i32mem:$src),
- cvtsi2ss {$src, $dst|$dst, $src},
- [(set FR32:$dst, (sint_to_fp (loadi32 addr:$src)))];
-def CVTSI2SDrr: SDI0x2A, MRMSrcReg, (ops FR64:$dst, R32:$src),
- cvtsi2sd {$src, $dst|$dst, $src},
- [(set FR64:$dst, (sint_to_fp R32:$src))];
-def CVTSI2SDrm: SDI0x2A, MRMSrcMem, (ops FR64:$dst, i32mem:$src),
- cvtsi2sd {$src, $dst|$dst, $src},
- [(set FR64:$dst, (sint_to_fp (loadi32 addr:$src)))];
-// SSE2 instructions with XS prefix
-def CVTSS2SDrr: I0x5A, MRMSrcReg, (ops FR64:$dst, FR32:$src),
- cvtss2sd {$src, $dst|$dst, $src},
- [(set FR64:$dst, (fextend FR32:$src))], XS,
-Requires[HasSSE2];
-def CVTSS2SDrm: I0x5A, MRMSrcMem, (ops FR64:$dst, f32mem:$src),
- cvtss2sd {$src, $dst|$dst, $src},
- [(set FR64:$dst, (fextend (loadf32 addr:$src)))], XS,
-Requires[HasSSE2];
-
// Arithmetic instructions
let isTwoAddress = 1 in {
let isCommutable = 1 in {
@@ -317,6 +270,207 @@
def MINSDrm : SDI0x5D, MRMSrcMem, (ops FR64:$dst, f64mem:$src),
minsd {$src, $dst|$dst, $src}, [];
+
+// Aliases to match intrinsics which expect XMM operand(s).
+let isTwoAddress = 1 in {
+let isCommutable = 1 in {
+def Int_ADDSSrr : SSI0x58, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
+VR128:$src2),
+addss {$src2, $dst|$dst, $src2},
+[(set VR128:$dst, (int_x86_sse_add_ss VR128:$src1,
+ VR128:$src2))];
+def Int_ADDSDrr : SDI0x58, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
+VR128:$src2),
+addsd {$src2, $dst|$dst, $src2},
+[(set VR128:$dst, (int_x86_sse2_add_sd VR128:$src1,
+ VR128:$src2))];
+def Int_MULSSrr : SSI0x59, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
+VR128:$src2),
+mulss {$src2, $dst|$dst, $src2},
+[(set VR128:$dst, (int_x86_sse_mul_ss VR128:$src1,
+ VR128:$src2))];
+def Int_MULSDrr : SDI0x59, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
+VR128:$src2),
+mulsd {$src2, $dst|$dst, $src2},
+[(set VR128:$dst, (int_x86_sse2_mul_sd VR128:$src1,
+ VR128:$src2))];
+}
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.33 - 1.34
---
Log message:
unbreak the build
---
Diffs of the changes: (+1 -1)
X86InstrSSE.td |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.33
llvm/lib/Target/X86/X86InstrSSE.td:1.34
--- llvm/lib/Target/X86/X86InstrSSE.td:1.33 Mon Mar 27 01:00:16 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Mon Mar 27 10:52:45 2006
@@ -493,7 +493,7 @@
def MOVMSKPSrr : PSI0x50, MRMSrcReg, (ops R32:$dst, VR128:$src),
movmskps {$src, $dst|$dst, $src},
- [(set R32:$dst, (int_x86_sse_movmskps VR128:$src))];
+ [(set R32:$dst, (int_x86_sse_movmsk_ps VR128:$src))];
def MOVMSKPDrr : PSI0x50, MRMSrcReg, (ops R32:$dst, VR128:$src),
movmskpd {$src, $dst|$dst, $src},
[(set R32:$dst, (int_x86_sse2_movmskpd VR128:$src))];
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.37 - 1.38
---
Log message:
Typo
---
Diffs of the changes: (+1 -1)
X86InstrSSE.td |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.37
llvm/lib/Target/X86/X86InstrSSE.td:1.38
--- llvm/lib/Target/X86/X86InstrSSE.td:1.37 Tue Mar 28 00:50:32 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Tue Mar 28 00:53:49 2006
@@ -500,7 +500,7 @@
MOVLHPS_shuffle_mask)))];
def MOVHLPSrr : PSI0x12, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
VR128:$src2),
-movlhps {$src2, $dst|$dst, $src2},
+movhlps {$src2, $dst|$dst, $src2},
[(set VR128:$dst,
(v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
MOVHLPS_shuffle_mask)))];
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.38 - 1.39
---
Log message:
movlps and movlpd should be modeled as two address code.
---
Diffs of the changes: (+9 -9)
X86InstrSSE.td | 18 +-
1 files changed, 9 insertions(+), 9 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.38
llvm/lib/Target/X86/X86InstrSSE.td:1.39
--- llvm/lib/Target/X86/X86InstrSSE.td:1.38 Tue Mar 28 00:53:49 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Tue Mar 28 01:01:28 2006
@@ -467,16 +467,11 @@
def MOVUPDmr : PDI0x11, MRMDestMem, (ops f128mem:$dst, VR128:$src),
movupd {$src, $dst|$dst, $src}, [];
-def MOVLPSrm : PSI0x12, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
- movlps {$src, $dst|$dst, $src}, [];
-def MOVLPSmr : PSI0x13, MRMDestMem, (ops f64mem:$dst, VR128:$src),
- movlps {$src, $dst|$dst, $src}, [];
-def MOVLPDrm : PDI0x12, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
- movlpd {$src, $dst|$dst, $src}, [];
-def MOVLPDmr : PDI0x13, MRMDestMem, (ops f64mem:$dst, VR128:$src),
- movlpd {$src, $dst|$dst, $src}, [];
-
let isTwoAddress = 1 in {
+def MOVLPSrm : PSI0x12, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
f64mem:$src2),
+ movlps {$src2, $dst|$dst, $src2}, [];
+def MOVLPDrm : PDI0x12, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
f64mem:$src2),
+ movlpd {$src2, $dst|$dst, $src2}, [];
def MOVHPSrm : PSI0x16, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
f64mem:$src2),
movhps {$src2, $dst|$dst, $src2}, [];
def MOVHPDrm : PDI0x16, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
f64mem:$src2),
@@ -487,6 +482,11 @@
UNPCKL_shuffle_mask)))];
}
+def MOVLPSmr : PSI0x13, MRMDestMem, (ops f64mem:$dst, VR128:$src),
+ movlps {$src, $dst|$dst, $src}, [];
+def MOVLPDmr : PDI0x13, MRMDestMem, (ops f64mem:$dst, VR128:$src),
+ movlpd {$src, $dst|$dst, $src}, [];
+
def MOVHPSmr : PSI0x17, MRMDestMem, (ops f64mem:$dst, VR128:$src),
movhps {$src, $dst|$dst, $src}, [];
def MOVHPDmr : PDI0x17, MRMDestMem, (ops f64mem:$dst, VR128:$src),
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.24 - 1.25
---
Log message:
plug the intrinsics into the patterns for movmsk*
---
Diffs of the changes: (+4 -2)
X86InstrSSE.td |6 --
1 files changed, 4 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.24
llvm/lib/Target/X86/X86InstrSSE.td:1.25
--- llvm/lib/Target/X86/X86InstrSSE.td:1.24 Fri Mar 24 01:29:27 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Fri Mar 24 15:49:18 2006
@@ -470,9 +470,11 @@
}
def MOVMSKPSrr : PSI0x50, MRMSrcReg, (ops R32:$dst, VR128:$src),
- movmskps {$src, $dst|$dst, $src}, [];
+ movmskps {$src, $dst|$dst, $src},
+ [(set R32:$dst, (int_x86_sse_movmskps VR128:$src))];
def MOVMSKPDrr : PSI0x50, MRMSrcReg, (ops R32:$dst, VR128:$src),
- movmskpd {$src, $dst|$dst, $src}, [];
+ movmskpd {$src, $dst|$dst, $src},
+ [(set R32:$dst, (int_x86_sse2_movmskpd VR128:$src))];
// Conversion instructions
def CVTPI2PSrr : PSI0x2A, MRMSrcReg, (ops VR128:$dst, VR64:$src),
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.25 - 1.26
---
Log message:
Added LDMXCSR
---
Diffs of the changes: (+7 -0)
X86InstrSSE.td |7 +++
1 files changed, 7 insertions(+)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.25
llvm/lib/Target/X86/X86InstrSSE.td:1.26
--- llvm/lib/Target/X86/X86InstrSSE.td:1.25 Fri Mar 24 15:49:18 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Fri Mar 24 16:28:37 2006
@@ -841,6 +841,13 @@
}
//===--===//
+// Miscellaneous Instructions
+//===--===//
+
+def LDMXCSR : I0xAE, MRM2m, (ops i32mem:$src),
+ldmxcsr {$src|$src}, [], TB, Requires[HasSSE1];
+
+//===--===//
// Alias Instructions
//===--===//
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.27 - 1.28
---
Log message:
Added CVTSS2SI.
---
Diffs of the changes: (+5 -0)
X86InstrSSE.td |5 +
1 files changed, 5 insertions(+)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.27
llvm/lib/Target/X86/X86InstrSSE.td:1.28
--- llvm/lib/Target/X86/X86InstrSSE.td:1.27 Fri Mar 24 17:15:12 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Fri Mar 24 19:00:18 2006
@@ -173,6 +173,11 @@
// Conversion instructions
+def CVTSS2SIrr: SSI0x2D, MRMSrcReg, (ops R32:$dst, FR32:$src),
+ cvtss2si {$src, $dst|$dst, $src}, [];
+def CVTSS2SIrm: SSI0x2D, MRMSrcMem, (ops R32:$dst, f32mem:$src),
+ cvtss2si {$src, $dst|$dst, $src}, [];
+
def CVTTSS2SIrr: SSI0x2C, MRMSrcReg, (ops R32:$dst, FR32:$src),
cvttss2si {$src, $dst|$dst, $src},
[(set R32:$dst, (fp_to_sint FR32:$src))];
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.17 - 1.18
---
Log message:
SHUFP* are two address code.
---
Diffs of the changes: (+2 -0)
X86InstrSSE.td |2 ++
1 files changed, 2 insertions(+)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.17
llvm/lib/Target/X86/X86InstrSSE.td:1.18
--- llvm/lib/Target/X86/X86InstrSSE.td:1.17 Wed Mar 22 13:16:21 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Wed Mar 22 14:08:18 2006
@@ -704,6 +704,7 @@
(ops VR128:$dst, i128mem:$src1, i8imm:$src2),
pshufd {$src2, $src1, $dst|$dst, $src1, $src2}, [];
+let isTwoAddress = 1 in {
def SHUFPSrr : PSIi80xC6, MRMSrcReg,
(ops VR128:$dst, VR128:$src1, VR128:$src2, i8imm:$src3),
shufps {$src3, $src2, $dst|$dst, $src2, $src3}, [];
@@ -716,6 +717,7 @@
def SHUFPDrm : PDIi80xC6, MRMSrcMem,
(ops VR128:$dst, VR128:$src1, f128mem:$src2, i8imm:$src3),
shufpd {$src3, $src2, $dst|$dst, $src2, $src3}, [];
+}
def UNPCKHPSrr : PSI0x15, MRMSrcReg,
(ops VR128:$dst, VR128:$src1, VR128:$src2),
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86: X86InstrSSE.td updated: 1.19 - 1.20 --- Log message: Add v4i32 - v4f32 bitconvert patterns. --- Diffs of the changes: (+4 -0) X86InstrSSE.td |4 1 files changed, 4 insertions(+) Index: llvm/lib/Target/X86/X86InstrSSE.td diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.19 llvm/lib/Target/X86/X86InstrSSE.td:1.20 --- llvm/lib/Target/X86/X86InstrSSE.td:1.19 Wed Mar 22 19:57:24 2006 +++ llvm/lib/Target/X86/X86InstrSSE.td Wed Mar 22 20:36:37 2006 @@ -871,3 +871,7 @@ def : Pat(vector_shuffle (v4i32 VR128:$src), (undef), PSHUFD_shuffle_mask:$sm), (v4i32 (PSHUFDrr VR128:$src, PSHUFD_shuffle_mask:$sm)), Requires[HasSSE2]; + +// bit_convert +def : Pat(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src); +def : Pat(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.20 - 1.21
---
Log message:
Following icc's lead: use movdqa to load / store 128-bit integer vectors
---
Diffs of the changes: (+29 -16)
X86InstrSSE.td | 45 +
1 files changed, 29 insertions(+), 16 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.20
llvm/lib/Target/X86/X86InstrSSE.td:1.21
--- llvm/lib/Target/X86/X86InstrSSE.td:1.20 Wed Mar 22 20:36:37 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Thu Mar 23 01:44:07 2006
@@ -40,6 +40,10 @@
def loadv4f32: PatFrag(ops node:$ptr), (v4f32 (load node:$ptr));
def loadv2f64: PatFrag(ops node:$ptr), (v2f64 (load node:$ptr));
+def loadv16i8: PatFrag(ops node:$ptr), (v16i8 (load node:$ptr));
+def loadv8i16: PatFrag(ops node:$ptr), (v8i16 (load node:$ptr));
+def loadv4i32: PatFrag(ops node:$ptr), (v4i32 (load node:$ptr));
+def loadv2i64: PatFrag(ops node:$ptr), (v2i64 (load node:$ptr));
// SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,
// SHUFP* etc. imm.
@@ -750,7 +754,7 @@
// Move Instructions
def MOVD128rr : PDI0x6E, MRMSrcReg, (ops VR128:$dst, R32:$src),
- movd {$src, $dst|$dst, $src},
+movd {$src, $dst|$dst, $src},
[(set VR128:$dst,
(v4i32 (scalar_to_vector R32:$src)))];
def MOVD128rm : PDI0x6E, MRMSrcMem, (ops VR128:$dst, i32mem:$src),
@@ -758,6 +762,15 @@
def MOVD128mr : PDI0x7E, MRMDestMem, (ops i32mem:$dst, VR128:$src),
movd {$src, $dst|$dst, $src}, [];
+def MOVDQArr : PDI0x6F, MRMSrcReg, (ops VR128:$dst, VR128:$src),
+ movdqa {$src, $dst|$dst, $src}, [];
+def MOVDQArm : PDI0x6F, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
+ movdqa {$src, $dst|$dst, $src},
+ [(set VR128:$dst, (loadv4i32 addr:$src))];
+def MOVDQAmr : PDI0x7F, MRMDestMem, (ops i128mem:$dst, VR128:$src),
+ movdqa {$src, $dst|$dst, $src},
+ [(store (v4i32 VR128:$src), addr:$dst)];
+
// SSE2 instructions with XS prefix
def MOVQ128rr : I0x7E, MRMSrcReg, (ops VR128:$dst, VR64:$src),
movq {$src, $dst|$dst, $src},
@@ -823,24 +836,24 @@
def : Pat(v2i64 (undef)), (IMPLICIT_DEF_VR128), Requires[HasSSE2];
// Load 128-bit integer vector values.
-def : Pat(v16i8 (load addr:$src)), (MOVAPSrm addr:$src),
- Requires[HasSSE1];
-def : Pat(v8i16 (load addr:$src)), (MOVAPSrm addr:$src),
- Requires[HasSSE1];
-def : Pat(v4i32 (load addr:$src)), (MOVAPSrm addr:$src),
- Requires[HasSSE1];
-def : Pat(v2i64 (load addr:$src)), (MOVAPDrm addr:$src),
+def : Pat(v16i8 (load addr:$src)), (MOVDQArm addr:$src),
+ Requires[HasSSE2];
+def : Pat(v8i16 (load addr:$src)), (MOVDQArm addr:$src),
+ Requires[HasSSE2];
+def : Pat(v4i32 (load addr:$src)), (MOVDQArm addr:$src),
+ Requires[HasSSE2];
+def : Pat(v2i64 (load addr:$src)), (MOVDQArm addr:$src),
Requires[HasSSE2];
// Store 128-bit integer vector values.
-def : Pat(store (v16i8 VR128:$src), addr:$dst), (MOVAPSmr addr:$dst,
VR128:$src),
- Requires[HasSSE1];
-def : Pat(store (v8i16 VR128:$src), addr:$dst), (MOVAPSmr addr:$dst,
VR128:$src),
- Requires[HasSSE1];
-def : Pat(store (v4i32 VR128:$src), addr:$dst), (MOVAPSmr addr:$dst,
VR128:$src),
- Requires[HasSSE1];
-def : Pat(store (v2i64 VR128:$src), addr:$dst), (MOVAPDmr addr:$dst,
VR128:$src),
- Requires[HasSSE2];
+def : Pat(store (v16i8 VR128:$src), addr:$dst),
+ (MOVDQAmr addr:$dst, VR128:$src), Requires[HasSSE1];
+def : Pat(store (v8i16 VR128:$src), addr:$dst),
+ (MOVDQAmr addr:$dst, VR128:$src), Requires[HasSSE1];
+def : Pat(store (v4i32 VR128:$src), addr:$dst),
+ (MOVDQAmr addr:$dst, VR128:$src), Requires[HasSSE1];
+def : Pat(store (v2i64 VR128:$src), addr:$dst),
+ (MOVDQAmr addr:$dst, VR128:$src), Requires[HasSSE2];
// Scalar to v8i16 / v16i8. The source may be a R32, but only the lower 8 or
// 16-bits matter.
___
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[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.13 - 1.14
---
Log message:
Fix PSHUF* and SHUF* jit code emission problems
---
Diffs of the changes: (+35 -25)
X86InstrSSE.td | 60 +
1 files changed, 35 insertions(+), 25 deletions(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.13
llvm/lib/Target/X86/X86InstrSSE.td:1.14
--- llvm/lib/Target/X86/X86InstrSSE.td:1.13 Tue Mar 21 20:53:00 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Wed Mar 22 01:10:28 2006
@@ -64,6 +64,8 @@
// SDI - SSE2 instructions with XD prefix.
// PSI - SSE1 instructions with TB prefix.
// PDI - SSE2 instructions with TB and OpSize prefixes.
+// PSIi8 - SSE1 instructions with ImmT == Imm8 and TB prefix.
+// PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
class SSIbits8 o, Format F, dag ops, string asm, listdag pattern
: Io, F, ops, asm, pattern, XS, Requires[HasSSE1];
class SDIbits8 o, Format F, dag ops, string asm, listdag pattern
@@ -72,6 +74,14 @@
: Io, F, ops, asm, pattern, TB, Requires[HasSSE1];
class PDIbits8 o, Format F, dag ops, string asm, listdag pattern
: Io, F, ops, asm, pattern, TB, OpSize, Requires[HasSSE2];
+class PSIi8bits8 o, Format F, dag ops, string asm, listdag pattern
+ : X86Insto, F, Imm8, ops, asm, TB, Requires[HasSSE1] {
+ let Pattern = pattern;
+}
+class PDIi8bits8 o, Format F, dag ops, string asm, listdag pattern
+ : X86Insto, F, Imm8, ops, asm, TB, OpSize, Requires[HasSSE2] {
+ let Pattern = pattern;
+}
// Some 'special' instructions
def IMPLICIT_DEF_FR32 : I0, Pseudo, (ops FR32:$dst),
@@ -671,33 +681,33 @@
}
// Shuffle and unpack instructions
-def PSHUFWrr : PSI0x70, AddRegFrm,
- (ops VR64:$dst, VR64:$src1, i8imm:$src2),
- pshufw {$src2, $src1, $dst|$dst, $src1, $src2}, [];
-def PSHUFWrm : PSI0x70, MRMSrcMem,
- (ops VR64:$dst, i64mem:$src1, i8imm:$src2),
- pshufw {$src2, $src1, $dst|$dst, $src1, $src2}, [];
-def PSHUFDrr : PDI0x70, AddRegFrm,
- (ops VR128:$dst, VR128:$src1, i8imm:$src2),
- pshufd {$src2, $src1, $dst|$dst, $src1, $src2},
+def PSHUFWrr : PSIi80x70, MRMDestReg,
+ (ops VR64:$dst, VR64:$src1, i8imm:$src2),
+ pshufw {$src2, $src1, $dst|$dst, $src1, $src2}, [];
+def PSHUFWrm : PSIi80x70, MRMSrcMem,
+ (ops VR64:$dst, i64mem:$src1, i8imm:$src2),
+ pshufw {$src2, $src1, $dst|$dst, $src1, $src2}, [];
+def PSHUFDrr : PDIi80x70, MRMDestReg,
+ (ops VR128:$dst, VR128:$src1, i8imm:$src2),
+ pshufd {$src2, $src1, $dst|$dst, $src1, $src2},
[(set VR128:$dst, (vector_shuffle (v4f32 VR128:$src1),
(undef),
PSHUFD_shuffle_mask:$src2))];
-def PSHUFDrm : PDI0x70, MRMSrcMem,
- (ops VR128:$dst, i128mem:$src1, i8imm:$src2),
- pshufd {$src2, $src1, $dst|$dst, $src1, $src2}, [];
-
-def SHUFPSrr : PSI0xC6, MRMSrcReg,
- (ops VR128:$dst, VR128:$src1, VR128:$src2, i8imm:$src3),
- shufps {$src3, $src2, $dst|$dst, $src2, $src3}, [];
-def SHUFPSrm : PSI0xC6, MRMSrcMem,
- (ops VR128:$dst, VR128:$src1, f128mem:$src2, i8imm:$src3),
- shufps {$src3, $src2, $dst|$dst, $src2, $src3}, [];
-def SHUFPDrr : PDI0xC6, MRMSrcReg,
- (ops VR128:$dst, VR128:$src1, VR128:$src2, i8imm:$src3),
- shufpd {$src3, $src2, $dst|$dst, $src2, $src3}, [];
-def SHUFPDrm : PDI0xC6, MRMSrcMem,
- (ops VR128:$dst, VR128:$src1, f128mem:$src2, i8imm:$src3),
- shufpd {$src3, $src2, $dst|$dst, $src2, $src3}, [];
+def PSHUFDrm : PDIi80x70, MRMSrcMem,
+ (ops VR128:$dst, i128mem:$src1, i8imm:$src2),
+ pshufd {$src2, $src1, $dst|$dst, $src1, $src2}, [];
+
+def SHUFPSrr : PSIi80xC6, MRMSrcReg,
+ (ops VR128:$dst, VR128:$src1, VR128:$src2, i8imm:$src3),
+ shufps {$src3, $src2, $dst|$dst, $src2, $src3}, [];
+def SHUFPSrm : PSIi80xC6, MRMSrcMem,
+ (ops VR128:$dst, VR128:$src1, f128mem:$src2, i8imm:$src3),
+ shufps {$src3, $src2, $dst|$dst, $src2, $src3}, [];
+def SHUFPDrr : PDIi80xC6, MRMSrcReg,
+ (ops VR128:$dst, VR128:$src1, VR128:$src2, i8imm:$src3),
+ shufpd {$src3, $src2, $dst|$dst, $src2, $src3}, [];
+def SHUFPDrm : PDIi80xC6, MRMSrcMem,
+ (ops VR128:$dst, VR128:$src1, f128mem:$src2, i8imm:$src3),
+ shufpd {$src3, $src2, $dst|$dst, $src2, $src3}, [];
def UNPCKHPSrr : PSI0x15, MRMSrcReg,
(ops VR128:$dst, VR128:$src1, VR128:$src2),
___
