Doing the cache invalidation is best for speed.
I am personally the type of person who thinks that every problem needs two
fixes, first is the fix for the problem, second is the fix as to why the
problem came into existence and/or was not found earlier. Hence I like to
know that when I
Hello,
Beware that everything should be cache line aligned!
To be future proof assume cache size is 64 bytes, even if it's 32 bytes.
I recommend making the TX descriptors non-cacheable, bufferable
and the RX descriptors non-cacheable, non-bufferable and the DMA
buffers fully cacheable and use
Am 25.03.2021 um 12:44 schrieb Trampas Stern:
> Rather than flushing cache you can create a non-cached section of RAM in
> the linker script and put buffers there.
But be aware that using non-cached buffers might be slow. While putting
the DMA descriptors into uncached memory is a good solution
Rather than flushing cache you can create a non-cached section of RAM in
the linker script and put buffers there.
.ram_nocache (NOLOAD):
{
. = ALIGN(4);
_s_ram_nocache = .;
*(.ram_nocache)
. = ALIGN(4);
_e_ram_nocache = .;
} > ram_nocache
.ram_nocache_data : AT (_etext + SIZEOF(.relocate))
{
. =
Damn you L1 cache! I would disable you permanently if you weren’t so damn
fast. :)
It appears cleaning the cache over the tx buffers address space has fixed the
issue. My only concern is, it shouldn’t have. The tx buffers are set up as
Normal Write through memory (T=0, C=1, B=0, S=0). I
