Re: [lwip-users] lwip+gprs+ppp over serial

Hi, On Tue, Jun 21, 2016 at 05:53:05PM +0200, Gennaro Zazo wrote: > > Attached the log, I apologize if it is rude. If you need to change the > debug mask let me know. The garbaged log probably means you are violating lwIP threading constraints. You can notice that PPP negotiated up to a

[lwip-users] lwip+gprs+ppp over serial

Hi guys, I'm really sorry but after 10 days spent with lwip stack, it's time to ask help. I'm working with a custom board based on stm32f103 and on ublox Leon-G100. My first attempt was to connect the board trough the serial with pc and use pppd to connect. the test was successfully passed, I

Re: [lwip-users] [Free Webinar] Digital Power for Xilinx Zynq Free Webinar 12th July

This is spam which is normally filtered out by the system. Don't know why this one made it through. I'll check the sender email... Simon Gesendet mit AquaMail für Android http://www.aqua-mail.com Am 21. Juni 2016 7:45:43 nachm. schrieb Patrick Klos : Hi ,

Re: [lwip-users] [Free Webinar] Digital Power for Xilinx Zynq Free Webinar 12th July

Hi , Digital Power on the Xilinx Zynq Webinar As an electronics engineer, you will no doubt be switched on to ELMG Digital Power’s stellar reputation as specialists in FPGA and power electronics. This coming month, on Tuesday 12^th July, they are offering you the

[lwip-users] [Free Webinar] Digital Power for Xilinx Zynq Free Webinar 12th July

ELMG Digital Power, a Xilinx Alliance Program member, is hosting a webinar on using the Xilinx Zynq SoC as a digital power platform Hi , Digital Power on the Xilinx Zynq Webinar As an electronics engineer, you will no doubt be switched on to ELMG Digital Power’s stellar reputation as

[lwip-users] R: [lwip-devel] 2.0.0 Beta2?

I had too problem with "timers" files, not directly during compilation because if files are in different folders there is no obvious problem, but during debugging. Debugger was always opening wrong timers file. Please rename it. Da: lwip-users