If a write happens to a cache line with the modified bit, the write just
completes without consulting the protocol table at all. The protocol tables
are only used when a miss happens and the cache needs to know what kind of
request to send, or when a response or snoop packet comes in from the bus.
I'm trying to add a cache coherence protocol to add write-update to
an existing once. (IE, When a shared cache line recieves a write from a
cpu, it broadcasts the write to other shared caches lined, instead of
invalidating them.)
I added a packet to packet.hh and packet.cc:
/* WriteUpdateReq *
