How about a diff? :)
Nate
I followed Steve's suggestion and created a prefetch() path similar to the
path that read() takes to the LSQ. The code is a little streamlined because
there are Fault conditions and memory dependence issues that are important
for loads but are not relevant for pref
Thanks for the guidance, Steve. I was able to get this to work.
For anyone else who is interested, this is what I did:
I followed Steve's suggestion and created a prefetch() path similar to
the path that read() takes to the LSQ. The code is a little streamlined
because there are Fault conditio
Hi Russ,
It shouldn't be too hard.. basically you'd have to duplicate the path that
read() takes from BaseDynInst through the CPU object (e.g., AlphaO3CPU) to
the o3 LSQ with prefetch() functions that will be similar. Once you get to
the LSQ then the key difference is to set the command field of
Hi,
It looks as if software prefetch instructions are ignored by the O3 model
in the m5 2.0 release (e.g. they 'execute' and 'commit' but do not impact
the microarchitectural state). In particular,
BaseDynInst::prefetch(Addr addr, unsigned flags) does nothing.
How difficult would it be to re
