Re: [m5-users] synchronization primitives in SE mode

2007-06-21 Thread Jiayuan Meng
== FYI. - Original Message - From: "Ali Saidi" <[EMAIL PROTECTED]> To: "M5 users mailing list" Sent: 2007年6月21日 9:11 AM Subject: Re: [m5-users] synchronization primitives in SE mode > I > On Jun 20, 2007, at 7:52 PM, Jiayuan Meng wrote: > >

Re: [m5-users] synchronization primitives in SE mode

2007-06-20 Thread Ali Saidi
I On Jun 20, 2007, at 7:52 PM, Jiayuan Meng wrote: Hi Steve, Also, what happens if you run with AtomicSimpleCPU, and with or without a single level of caches? I manually used the mutex_lock in glibc's sysdeps/mach/alpha/ machine-lock.h, the LL/SC worked fine with both configurations.

Re: [m5-users] synchronization primitives in SE mode

2007-06-20 Thread Jiayuan Meng
Hi Steve, > > Also, what happens if you run with AtomicSimpleCPU, and with or without > a single level of caches? I manually used the mutex_lock in glibc's sysdeps/mach/alpha/machine-lock.h, the LL/SC worked fine with both configurations. (L1 & L2 / L1 only) I am still trying to figure out

Re: [m5-users] synchronization primitives in SE mode

2007-06-17 Thread Jiayuan Meng
ers mailing list" Sent: 2007年6月17日 11:32 AM Subject: Re: [m5-users] synchronization primitives in SE mode If seems like for whatever reason the malloc code is using this header from libc: ./sysdeps/generic/malloc-machine.h as opposed to: ./nptl/sysdeps/pthread/malloc-machine.h The p

Re: [m5-users] synchronization primitives in SE mode

2007-06-16 Thread Ali Saidi
*From:* Ali Saidi <mailto:[EMAIL PROTECTED]> *To:* M5 users mailing list <mailto:m5-users@m5sim.org> *Sent:* 2007年6月16日 2:41 AM *Subject:* Re: [m5-users] synchronization primitives in SE mode The Alpha ISA has a load locked and a store conditional instruction which

Re: [m5-users] synchronization primitives in SE mode

2007-06-16 Thread Jiayuan Meng
>> I'm in trouble now... I wonder how splash2 gets around with this in SE mode? >> >> Thanks again! >> >> Jiayuan >> >> >> - Original Message - >> *From:* Ali Saidi <mailto:[EMAIL PROTECTED]> >> *To

Re: [m5-users] synchronization primitives in SE mode

2007-06-16 Thread Steve Reinhardt
ow splash2 gets around with this in SE mode? Thanks again! Jiayuan - Original Message - *From:* Ali Saidi <mailto:[EMAIL PROTECTED]> *To:* M5 users mailing list <mailto:m5-users@m5sim.org> *Sent:* 2007年6月16日 2:41 AM *Subject:* Re: [m5-users] synchronization

Re: [m5-users] synchronization primitives in SE mode

2007-06-15 Thread Jiayuan Meng
e - From: Ali Saidi To: M5 users mailing list Sent: 2007年6月16日 2:41 AM Subject: Re: [m5-users] synchronization primitives in SE mode The Alpha ISA has a load locked and a store conditional instruction which we support. Again I don't know exactly what you're doing to cr

Re: [m5-users] synchronization primitives in SE mode

2007-06-15 Thread Ali Saidi
The Alpha ISA has a load locked and a store conditional instruction which we support. Again I don't know exactly what you're doing to create your threads, but you need to make sure that their cpu/thread ids are unique. Are you scheduling each thread on it's own cpu or are they moving around

[m5-users] synchronization primitives in SE mode

2007-06-15 Thread Jiayuan Meng
Hey all, By using the --trace-flags=Exec debug tool, I found that there is a race condition in the malloc function in my multithreaded program. However, when looking into the malloc.c in the glibc, it said it is a thread-safe version. I also noticed that in malloc/arena.c, it uses mutex_lock(),