Module: Mesa
Branch: master
Commit: 1866f76f7bc3ec54b4e91eb7d329b2e6f7b6277c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1866f76f7bc3ec54b4e91eb7d329b2e6f7b6277c
Author: Rob Clark <robdcl...@gmail.com>
Date: Sun Apr 1 10:32:36 2018 -0400
freedreno/a5xx: fix page faults on last level
We could alternatively fall back to using "old style" draw's for
mem<->gmem (ie. what <= a4xx do) when height is not aligned to 32,
but that is somewhat more work (and not really something that could
be applied to stable)
Cc: "18.0" <mesa-sta...@lists.freedesktop.org>
Signed-off-by: Rob Clark <robdcl...@gmail.com>
---
src/gallium/drivers/freedreno/a5xx/fd5_resource.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_resource.c
b/src/gallium/drivers/freedreno/a5xx/fd5_resource.c
index 12ee6d76fc..84fa64cec8 100644
--- a/src/gallium/drivers/freedreno/a5xx/fd5_resource.c
+++ b/src/gallium/drivers/freedreno/a5xx/fd5_resource.c
@@ -73,6 +73,16 @@ setup_slices(struct fd_resource *rsc, uint32_t alignment,
enum pipe_format forma
aligned_height = align(aligned_height, heightalign);
} else {
pitchalign = 64;
+
+ /* The blits used for mem<->gmem work at a granularity
of
+ * 32x32, which can cause faults due to over-fetch on
the
+ * last level. The simple solution is to over-allocate
a
+ * bit the last level to ensure any over-fetch is
harmless.
+ * The pitch is already sufficiently aligned, but height
+ * may not be:
+ */
+ if (level == prsc->last_level)
+ aligned_height = align(aligned_height, 32);
}
if (layout == UTIL_FORMAT_LAYOUT_ASTC)
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