Module: Mesa
Branch: master
Commit: e6a9bd97b97a303463db3eeae38fed61c43c44b1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e6a9bd97b97a303463db3eeae38fed61c43c44b1
Author: Ian Romanick <ian.d.roman...@intel.com>
Date: Thu Jun 14 15:26:58 2018 -0700
i965/vec4: Don't register coalesce into source of VS_OPCODE_UNPACK_FLAGS_SIMD4X2
This prevents regressions in a bunch of clipping and interpolation tests
caused by the next patch (i965/vec4: Optimize OR with 0 into a MOV).
Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
---
src/intel/compiler/brw_vec4.cpp | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/src/intel/compiler/brw_vec4.cpp b/src/intel/compiler/brw_vec4.cpp
index 4464a91398..e67d780255 100644
--- a/src/intel/compiler/brw_vec4.cpp
+++ b/src/intel/compiler/brw_vec4.cpp
@@ -1285,6 +1285,15 @@ vec4_visitor::opt_register_coalesce()
}
}
+ /* VS_OPCODE_UNPACK_FLAGS_SIMD4X2 generates a bunch of mov(1)
+ * instructions, and this optimization pass is not capable of
+ * handling that. Bail on these instructions and hope that some
+ * later optimization pass can do the right thing after they are
+ * expanded.
+ */
+ if (scan_inst->opcode == VS_OPCODE_UNPACK_FLAGS_SIMD4X2)
+ break;
+
/* This doesn't handle saturation on the instruction we
* want to coalesce away if the register types do not match.
* But if scan_inst is a non type-converting 'mov', we can fix
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