Mesa (master): glsl: Take 'double' as reserved after GLSL ES 1.0
Module: Mesa Branch: master Commit: 67f7a16b598513d25319e482359a4c4c6fc1271d URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=67f7a16b598513d25319e482359a4c4c6fc1271d Author: zhaowei yuan Date: Tue Jun 5 05:33:59 2018 +0800 glsl: Take 'double' as reserved after GLSL ES 1.0 GLSL ES 1.0.17 specifies that "double" is a keyword reserved Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106823 Signed-off-by: zhaowei yuan Reviewed-by: Ian Romanick Reviewed-by: Kenneth Graunke --- src/compiler/glsl/glsl_lexer.ll | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/compiler/glsl/glsl_lexer.ll b/src/compiler/glsl/glsl_lexer.ll index b7cf10018d..de6dc645cf 100644 --- a/src/compiler/glsl/glsl_lexer.ll +++ b/src/compiler/glsl/glsl_lexer.ll @@ -600,7 +600,7 @@ externalKEYWORD(110, 100, 0, 0, EXTERNAL); interface KEYWORD(110, 100, 0, 0, INTERFACE); long KEYWORD(110, 100, 0, 0, LONG_TOK); short KEYWORD(110, 100, 0, 0, SHORT_TOK); -double TYPE_WITH_ALT(130, 300, 130, 300, yyextra->ARB_gpu_shader_fp64_enable, glsl_type::double_type); +double TYPE_WITH_ALT(130, 100, 130, 300, yyextra->ARB_gpu_shader_fp64_enable, glsl_type::double_type); half KEYWORD(110, 100, 0, 0, HALF); fixed KEYWORD(110, 100, 0, 0, FIXED_TOK); unsigned KEYWORD(110, 100, 0, 0, UNSIGNED); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel/blorp: Emit VF cache invalidates for 48-bit bugs with softpin.
Module: Mesa
Branch: master
Commit: 74259b98aab010d3062c5903770dc3067665b59e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=74259b98aab010d3062c5903770dc3067665b59e
Author: Kenneth Graunke
Date: Thu May 31 16:39:16 2018 -0700
intel/blorp: Emit VF cache invalidates for 48-bit bugs with softpin.
commit 92f01fc5f914fd500497d0c3aed75f3ac8dc054d made i965 start emitting
VF cache invalidates when the high bits of vertex buffers change. But
we were not tracking vertex buffers emitted by BLORP. This was papered
over by a mistake where I emitted VF cache invalidates all the time,
which Chris fixed in commit 3ac5fbadfd8644d30fce9ff267cb811ad157996a.
This patch adds a new hook which allows the driver to track addresses
and request a VF cache invalidate as appropriate.
v2: Make the driver do the PIPE_CONTROL so it can apply workarounds
(caught by Jason Ekstrand). Rebase on anv bug fix.
v3: Don't screw up the boolean (caught by Jason Ekstrand).
Fixes: 92f01fc5f914 ("i965: Emit VF cache invalidates for 48-bit addressing
bugs with softpin.")
Reviewed-by: Jason Ekstrand
---
src/intel/blorp/blorp_genX_exec.h | 17 -
src/intel/vulkan/genX_blorp_exec.c | 10 ++
src/mesa/drivers/dri/i965/genX_blorp_exec.c | 29 +
3 files changed, 51 insertions(+), 5 deletions(-)
diff --git a/src/intel/blorp/blorp_genX_exec.h
b/src/intel/blorp/blorp_genX_exec.h
index bcaef4f367..4800c7dcaa 100644
--- a/src/intel/blorp/blorp_genX_exec.h
+++ b/src/intel/blorp/blorp_genX_exec.h
@@ -59,6 +59,10 @@ blorp_alloc_dynamic_state(struct blorp_batch *batch,
static void *
blorp_alloc_vertex_buffer(struct blorp_batch *batch, uint32_t size,
struct blorp_address *addr);
+static void
+blorp_vf_invalidate_for_vb_48b_transitions(struct blorp_batch *batch,
+ const struct blorp_address *addrs,
+ unsigned num_vbs);
#if GEN_GEN >= 8
static struct blorp_address
@@ -334,19 +338,22 @@ blorp_emit_vertex_buffers(struct blorp_batch *batch,
uint32_t num_vbs = 2;
memset(vb, 0, sizeof(vb));
- struct blorp_address addr;
+ struct blorp_address addrs[2] = {};
uint32_t size;
- blorp_emit_vertex_data(batch, params, , );
- blorp_fill_vertex_buffer_state(batch, vb, 0, addr, size, 3 * sizeof(float));
+ blorp_emit_vertex_data(batch, params, [0], );
+ blorp_fill_vertex_buffer_state(batch, vb, 0, addrs[0], size,
+ 3 * sizeof(float));
- blorp_emit_input_varying_data(batch, params, , );
- blorp_fill_vertex_buffer_state(batch, vb, 1, addr, size, 0);
+ blorp_emit_input_varying_data(batch, params, [1], );
+ blorp_fill_vertex_buffer_state(batch, vb, 1, addrs[1], size, 0);
const unsigned num_dwords = 1 + num_vbs * GENX(VERTEX_BUFFER_STATE_length);
uint32_t *dw = blorp_emitn(batch, GENX(3DSTATE_VERTEX_BUFFERS), num_dwords);
if (!dw)
return;
+ blorp_vf_invalidate_for_vb_48b_transitions(batch, addrs, num_vbs);
+
for (unsigned i = 0; i < num_vbs; i++) {
GENX(VERTEX_BUFFER_STATE_pack)(batch, dw, [i]);
dw += GENX(VERTEX_BUFFER_STATE_length);
diff --git a/src/intel/vulkan/genX_blorp_exec.c
b/src/intel/vulkan/genX_blorp_exec.c
index ecca3928de..2035017ce0 100644
--- a/src/intel/vulkan/genX_blorp_exec.c
+++ b/src/intel/vulkan/genX_blorp_exec.c
@@ -158,6 +158,16 @@ blorp_alloc_vertex_buffer(struct blorp_batch *batch,
uint32_t size,
return vb_state.map;
}
+static void
+blorp_vf_invalidate_for_vb_48b_transitions(struct blorp_batch *batch,
+ const struct blorp_address *addrs,
+ unsigned num_vbs)
+{
+ /* anv forces all vertex buffers into the low 4GB so there are never any
+* transitions that require a VF invalidation.
+*/
+}
+
#if GEN_GEN >= 8
static struct blorp_address
blorp_get_workaround_page(struct blorp_batch *batch)
diff --git a/src/mesa/drivers/dri/i965/genX_blorp_exec.c
b/src/mesa/drivers/dri/i965/genX_blorp_exec.c
index 808bff0db8..34bfcad03e 100644
--- a/src/mesa/drivers/dri/i965/genX_blorp_exec.c
+++ b/src/mesa/drivers/dri/i965/genX_blorp_exec.c
@@ -189,6 +189,35 @@ blorp_alloc_vertex_buffer(struct blorp_batch *batch,
uint32_t size,
return data;
}
+/**
+ * See vf_invalidate_for_vb_48b_transitions in genX_state_upload.c.
+ */
+static void
+blorp_vf_invalidate_for_vb_48b_transitions(struct blorp_batch *batch,
+ const struct blorp_address *addrs,
+ unsigned num_vbs)
+{
+#if GEN_GEN >= 8
+ struct brw_context *brw = batch->driver_batch;
+ bool need_invalidate = false;
+
+ for (unsigned i = 0; i < num_vbs; i++) {
+ struct brw_bo *bo = addrs[i].buffer;
+ uint16_t high_bits =
+ bo && (bo->kflags & EXEC_OBJECT_PINNED) ? bo->gtt_offset >> 32u : 0;
+
+
Mesa (master): i965: Allocate VMA in userspace for full-PPGTT systems.
Module: Mesa
Branch: master
Commit: a363bb2cd0e2a141f2c60be005009703bffcbe4e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a363bb2cd0e2a141f2c60be005009703bffcbe4e
Author: Kenneth Graunke
Date: Tue Apr 10 01:18:25 2018 -0700
i965: Allocate VMA in userspace for full-PPGTT systems.
This patch enables soft-pinning of all buffers, allowing us to skip
relocation processing entirely. All systems with full PPGTT and > 4GB
of VMA should gain these benefits. This should be most Gen8+.
Unfortunately, this excludes a few systems:
- Cherryview (only has 32-bit addressing, despite 48-bit pointers)
- Broadwell with a 32-bit kernel
- Anybody running pre-4.5 kernel.
We may enable it for Cherryview in the future, but it would require
some tweaks to the memory zone.
Reviewed-by: Jordan Justen
---
src/mesa/drivers/dri/i965/brw_bufmgr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.c
b/src/mesa/drivers/dri/i965/brw_bufmgr.c
index 121e952b9e..b5e3eb6bff 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.c
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.c
@@ -1724,7 +1724,7 @@ brw_bufmgr_init(struct gen_device_info *devinfo, int fd)
bufmgr->initial_kflags |= EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
/* Allocate VMA in userspace if we have softpin and full PPGTT. */
- if (false && gem_param(fd, I915_PARAM_HAS_EXEC_SOFTPIN) > 0 &&
+ if (gem_param(fd, I915_PARAM_HAS_EXEC_SOFTPIN) > 0 &&
gem_param(fd, I915_PARAM_HAS_ALIASING_PPGTT) > 1) {
bufmgr->initial_kflags |= EXEC_OBJECT_PINNED;
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Mesa (master): i965: Require softpin support for Cannonlake and later.
Module: Mesa
Branch: master
Commit: 3ea2d791f3e72859a755e6e50a5330fc41a4bd2f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3ea2d791f3e72859a755e6e50a5330fc41a4bd2f
Author: Kenneth Graunke
Date: Tue Apr 10 01:27:56 2018 -0700
i965: Require softpin support for Cannonlake and later.
This isn't strictly necessary, but anyone running Cannonlake will
already have Kernel 4.5 or later, so there's no reason to support
the relocation model on Gen10+.
This will let us avoid dealing with them for new features.
Reviewed-by: Scott D Phillips
Reviewed-by: Jordan Justen
---
src/mesa/drivers/dri/i965/brw_bufmgr.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.c
b/src/mesa/drivers/dri/i965/brw_bufmgr.c
index b5e3eb6bff..7ac3bcad3d 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.c
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.c
@@ -1732,6 +1732,16 @@ brw_bufmgr_init(struct gen_device_info *devinfo, int fd)
4096, _4GB);
util_vma_heap_init(>vma_allocator[BRW_MEMZONE_OTHER],
1 * _4GB, gtt_size - 1 * _4GB);
+ } else if (devinfo->gen >= 10) {
+ /* Softpin landed in 4.5, but GVT used an aliasing PPGTT until
+ * kernel commit 6b3816d69628becb7ff35978aa0751798b4a940a in
+ * 4.14. Gen10+ GVT hasn't landed yet, so it's not actually a
+ * problem - but extending this requirement back to earlier gens
+ * might actually mean requiring 4.14.
+ */
+ fprintf(stderr, "i965 requires softpin (Kernel 4.5) on Gen10+.");
+ free(bufmgr);
+ return NULL;
}
}
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Mesa (master): nir: add opt_if_loop_terminator()
Module: Mesa
Branch: master
Commit: 2a74296f24ba15b14602286a680ca5f344a71059
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2a74296f24ba15b14602286a680ca5f344a71059
Author: Timothy Arceri
Date: Fri Jun 1 15:37:28 2018 +1000
nir: add opt_if_loop_terminator()
This pass detects potential loop terminators and moves intructions
from the non breaking branch after the if-statement.
This enables both the new opt_if_simplification() pass and loop
unrolling to potentially progress further.
Unexpectedly this change speed up shader-db run times by ~3%
Ivy Bridge shader-db results (all changes in dolphin/ubershaders):
total instructions in shared programs: 9995662 -> 9995338 (-0.00%)
instructions in affected programs: 87845 -> 87521 (-0.37%)
helped: 27
HURT: 0
total cycles in shared programs: 230931495 -> 230925015 (-0.00%)
cycles in affected programs: 56391385 -> 56384905 (-0.01%)
helped: 27
HURT: 0
Reviewed-by: Ian Romanick
---
src/compiler/nir/nir_opt_if.c | 68 +++
1 file changed, 68 insertions(+)
diff --git a/src/compiler/nir/nir_opt_if.c b/src/compiler/nir/nir_opt_if.c
index b03657a424..863ca630fb 100644
--- a/src/compiler/nir/nir_opt_if.c
+++ b/src/compiler/nir/nir_opt_if.c
@@ -24,6 +24,7 @@
#include "nir.h"
#include "nir/nir_builder.h"
#include "nir_control_flow.h"
+#include "nir_loop_analyze.h"
/**
* This optimization detects if statements at the tops of loops where the
@@ -283,6 +284,72 @@ opt_if_simplification(nir_builder *b, nir_if *nif)
return true;
}
+/**
+ * This optimization simplifies potential loop terminators which then allows
+ * other passes such as opt_if_simplification() and loop unrolling to progress
+ * further:
+ *
+ * if (cond) {
+ *... then block instructions ...
+ * } else {
+ * ...
+ *break;
+ * }
+ *
+ * into:
+ *
+ * if (cond) {
+ * } else {
+ * ...
+ *break;
+ * }
+ * ... then block instructions ...
+ */
+static bool
+opt_if_loop_terminator(nir_if *nif)
+{
+ nir_block *break_blk = NULL;
+ nir_block *continue_from_blk = NULL;
+ bool continue_from_then = true;
+
+ nir_block *last_then = nir_if_last_then_block(nif);
+ nir_block *last_else = nir_if_last_else_block(nif);
+
+ if (nir_block_ends_in_break(last_then)) {
+ break_blk = last_then;
+ continue_from_blk = last_else;
+ continue_from_then = false;
+ } else if (nir_block_ends_in_break(last_else)) {
+ break_blk = last_else;
+ continue_from_blk = last_then;
+ }
+
+ /* Continue if the if-statement contained no jumps at all */
+ if (!break_blk)
+ return false;
+
+ /* If the continue from block is empty then return as there is nothing to
+* move.
+*/
+ nir_block *first_continue_from_blk = continue_from_then ?
+ nir_if_first_then_block(nif) :
+ nir_if_first_else_block(nif);
+ if (is_block_empty(first_continue_from_blk))
+ return false;
+
+ if (!nir_is_trivial_loop_if(nif, break_blk))
+ return false;
+
+ /* Finally, move the continue from branch after the if-statement. */
+ nir_cf_list tmp;
+ nir_cf_extract(, nir_before_block(first_continue_from_blk),
+nir_after_block(continue_from_blk));
+ nir_cf_reinsert(, nir_after_cf_node(>cf_node));
+ nir_cf_delete();
+
+ return true;
+}
+
static bool
opt_if_cf_list(nir_builder *b, struct exec_list *cf_list)
{
@@ -296,6 +363,7 @@ opt_if_cf_list(nir_builder *b, struct exec_list *cf_list)
nir_if *nif = nir_cf_node_as_if(cf_node);
progress |= opt_if_cf_list(b, >then_list);
progress |= opt_if_cf_list(b, >else_list);
+ progress |= opt_if_loop_terminator(nif);
progress |= opt_if_simplification(b, nif);
break;
}
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Mesa (master): radv: fix Coverity no effect control flow issue
Module: Mesa
Branch: master
Commit: 186988e28f9fe31ad4d08626586d5167051a14e7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=186988e28f9fe31ad4d08626586d5167051a14e7
Author: Timothy Arceri
Date: Thu Jun 7 09:49:37 2018 +1000
radv: fix Coverity no effect control flow issue
swizzle is unsigned so "desc->swizzle[c] < 0" is never true.
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_formats.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/amd/vulkan/radv_formats.c b/src/amd/vulkan/radv_formats.c
index 50ec904d51..958f2a2c82 100644
--- a/src/amd/vulkan/radv_formats.c
+++ b/src/amd/vulkan/radv_formats.c
@@ -921,7 +921,7 @@ bool radv_format_pack_clear_color(VkFormat format,
uint64_t clear_val = 0;
for (unsigned c = 0; c < 4; ++c) {
- if (desc->swizzle[c] < 0 || desc->swizzle[c] >= 4)
+ if (desc->swizzle[c] >= 4)
continue;
const struct vk_format_channel_description *channel =
>channel[desc->swizzle[c]];
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Mesa (master): nir: move ends_in_break() helper to nir_loop_analyze.h
Module: Mesa
Branch: master
Commit: 1098bc5e854a1253e050fa30d16eda6ca676d4b3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1098bc5e854a1253e050fa30d16eda6ca676d4b3
Author: Timothy Arceri
Date: Fri Jun 1 15:37:27 2018 +1000
nir: move ends_in_break() helper to nir_loop_analyze.h
We will use the helper while simplifying potential loop terminators
in the following patch.
Reviewed-by: Ian Romanick
---
src/compiler/nir/nir_loop_analyze.c | 15 ++-
src/compiler/nir/nir_loop_analyze.h | 11 +++
2 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/src/compiler/nir/nir_loop_analyze.c
b/src/compiler/nir/nir_loop_analyze.c
index 84da035052..d5281a5faa 100644
--- a/src/compiler/nir/nir_loop_analyze.c
+++ b/src/compiler/nir/nir_loop_analyze.c
@@ -290,17 +290,6 @@ initialize_ssa_def(nir_ssa_def *def, void *void_state)
return true;
}
-static inline bool
-ends_in_break(nir_block *block)
-{
- if (exec_list_is_empty(>instr_list))
- return false;
-
- nir_instr *instr = nir_block_last_instr(block);
- return instr->type == nir_instr_type_jump &&
- nir_instr_as_jump(instr)->type == nir_jump_break;
-}
-
static bool
find_loop_terminators(loop_info_state *state)
{
@@ -315,11 +304,11 @@ find_loop_terminators(loop_info_state *state)
nir_block *last_then = nir_if_last_then_block(nif);
nir_block *last_else = nir_if_last_else_block(nif);
- if (ends_in_break(last_then)) {
+ if (nir_block_ends_in_break(last_then)) {
break_blk = last_then;
continue_from_blk = last_else;
continue_from_then = false;
- } else if (ends_in_break(last_else)) {
+ } else if (nir_block_ends_in_break(last_else)) {
break_blk = last_else;
continue_from_blk = last_then;
}
diff --git a/src/compiler/nir/nir_loop_analyze.h
b/src/compiler/nir/nir_loop_analyze.h
index 18c2305171..7b4ed66ee5 100644
--- a/src/compiler/nir/nir_loop_analyze.h
+++ b/src/compiler/nir/nir_loop_analyze.h
@@ -92,4 +92,15 @@ nir_is_trivial_loop_if(nir_if *nif, nir_block *break_block)
return true;
}
+static inline bool
+nir_block_ends_in_break(nir_block *block)
+{
+ if (exec_list_is_empty(>instr_list))
+ return false;
+
+ nir_instr *instr = nir_block_last_instr(block);
+ return instr->type == nir_instr_type_jump &&
+ nir_instr_as_jump(instr)->type == nir_jump_break;
+}
+
#endif /* NIR_LOOP_ANALYZE_H */
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Mesa (master): egl: rewire the build systems to use libwayland-egl
Module: Mesa
Branch: master
Commit: 1db4ec05462914096b1f243e9b2af7e71cf38622
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1db4ec05462914096b1f243e9b2af7e71cf38622
Author: Eric Engestrom
Date: Tue May 29 15:41:28 2018 +0100
egl: rewire the build systems to use libwayland-egl
Cc: Emil Velikov
Cc: Daniel Stone
Reviewed-by: Matt Turner
Signed-off-by: Eric Engestrom
---
configure.ac | 6 --
meson.build| 3 +++
src/Makefile.am| 5 -
src/egl/Makefile.am| 3 ++-
src/egl/drivers/dri2/platform_wayland.c| 7 +++
src/egl/meson.build| 10 ++
src/gallium/state_trackers/omx/tizonia/Makefile.am | 2 +-
7 files changed, 15 insertions(+), 21 deletions(-)
diff --git a/configure.ac b/configure.ac
index 600127af8f..875c47fcd4 100644
--- a/configure.ac
+++ b/configure.ac
@@ -90,6 +90,7 @@ LIBOMXIL_TIZONIA_REQUIRED=0.10.0
LIBVA_REQUIRED=0.39.0
VDPAU_REQUIRED=1.1
WAYLAND_REQUIRED=1.11
+WAYLAND_EGL_REQUIRED=1.15
WAYLAND_PROTOCOLS_REQUIRED=1.8
XCB_REQUIRED=1.9.3
XCBDRI2_REQUIRED=1.8
@@ -1808,6 +1809,9 @@ for plat in $platforms; do
PKG_CHECK_MODULES([WAYLAND_CLIENT], [wayland-client >=
$WAYLAND_REQUIRED])
PKG_CHECK_MODULES([WAYLAND_SERVER], [wayland-server >=
$WAYLAND_REQUIRED])
PKG_CHECK_MODULES([WAYLAND_PROTOCOLS], [wayland-protocols >=
$WAYLAND_PROTOCOLS_REQUIRED])
+if test "x$enable_egl" = xyes; then
+ PKG_CHECK_MODULES([WAYLAND_EGL], [wayland-egl >=
$WAYLAND_EGL_REQUIRED])
+fi
WAYLAND_PROTOCOLS_DATADIR=`$PKG_CONFIG --variable=pkgdatadir
wayland-protocols`
PKG_CHECK_MODULES([WAYLAND_SCANNER], [wayland-scanner],
@@ -3022,8 +3026,6 @@ AC_CONFIG_FILES([Makefile
src/egl/Makefile
src/egl/main/egl.pc
src/egl/wayland/wayland-drm/Makefile
- src/egl/wayland/wayland-egl/Makefile
- src/egl/wayland/wayland-egl/wayland-egl.pc
src/gallium/Makefile
src/gallium/auxiliary/Makefile
src/gallium/auxiliary/pipe-loader/Makefile
diff --git a/meson.build b/meson.build
index 1d1b2a979b..4d4ca5d557 100644
--- a/meson.build
+++ b/meson.build
@@ -1201,6 +1201,9 @@ if with_platform_wayland
dep_wl_protocols = dependency('wayland-protocols', version : '>= 1.8')
dep_wayland_client = dependency('wayland-client', version : '>=1.11')
dep_wayland_server = dependency('wayland-server', version : '>=1.11')
+ if with_egl
+dep_wayland_egl = dependency('wayland-egl', version : '>=1.15')
+ endif
wayland_dmabuf_xml = join_paths(
dep_wl_protocols.get_pkgconfig_variable('pkgdatadir'), 'unstable',
'linux-dmabuf', 'linux-dmabuf-unstable-v1.xml'
diff --git a/src/Makefile.am b/src/Makefile.am
index fd5ae44550..9bb3bce3c0 100644
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -95,11 +95,6 @@ if HAVE_GBM
SUBDIRS += gbm
endif
-## Optionally required by EGL
-if HAVE_PLATFORM_WAYLAND
-SUBDIRS += egl/wayland/wayland-egl
-endif
-
if HAVE_EGL
SUBDIRS += egl
endif
diff --git a/src/egl/Makefile.am b/src/egl/Makefile.am
index 086a4a1e63..be3547d968 100644
--- a/src/egl/Makefile.am
+++ b/src/egl/Makefile.am
@@ -84,6 +84,8 @@ drivers/dri2/egl_dri2.lo:
drivers/dri2/linux-dmabuf-unstable-v1-client-protocol.
AM_CFLAGS += $(WAYLAND_CLIENT_CFLAGS)
libEGL_common_la_LIBADD += $(WAYLAND_CLIENT_LIBS)
libEGL_common_la_LIBADD += $(LIBDRM_LIBS)
+AM_CFLAGS += $(WAYLAND_EGL_CFLAGS)
+libEGL_common_la_LIBADD += $(WAYLAND_EGL_LIBS)
AM_CFLAGS += $(WAYLAND_SERVER_CFLAGS)
libEGL_common_la_LIBADD +=
$(top_builddir)/src/egl/wayland/wayland-drm/libwayland-drm.la
libEGL_common_la_LIBADD += $(WAYLAND_SERVER_LIBS)
@@ -114,7 +116,6 @@ AM_CFLAGS += \
-I$(top_builddir)/src/egl/drivers/dri2 \
-I$(top_srcdir)/src/egl/drivers/dri2 \
-I$(top_srcdir)/src/gbm/backends/dri \
- -I$(top_srcdir)/src/egl/wayland/wayland-egl \
-I$(top_builddir)/src/egl/wayland/wayland-drm \
-I$(top_srcdir)/src/egl/wayland/wayland-drm \
-DDEFAULT_DRIVER_DIR=\"$(DRI_DRIVER_SEARCH_DIR)\" \
diff --git a/src/egl/drivers/dri2/platform_wayland.c
b/src/egl/drivers/dri2/platform_wayland.c
index 63da21cdf5..11026f9fbf 100644
--- a/src/egl/drivers/dri2/platform_wayland.c
+++ b/src/egl/drivers/dri2/platform_wayland.c
@@ -45,12 +45,11 @@
#include "util/u_vector.h"
#include "eglglobals.h"
+#include
#include
#include "wayland-drm-client-protocol.h"
#include "linux-dmabuf-unstable-v1-client-protocol.h"
-#include "wayland/wayland-egl/wayland-egl-backend.h"
-
#ifndef DRM_FORMAT_MOD_INVALID
#define DRM_FORMAT_MOD_INVALID ((1ULL << 56) - 1)
#endif
@@ -298,7 +297,7 @@ dri2_wl_create_window_surface(_EGLDriver *drv, _EGLDisplay
*disp,
dri2_surf->wl_queue);
dri2_surf->wl_win
Mesa (master): docs: add note about moving to libwayland-egl in 18.2.0
Module: Mesa Branch: master Commit: 735b104707382b6f14f5d49b456c80f5852240af URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=735b104707382b6f14f5d49b456c80f5852240af Author: Eric Engestrom Date: Tue May 29 15:41:30 2018 +0100 docs: add note about moving to libwayland-egl in 18.2.0 Cc: Emil Velikov Cc: Daniel Stone Cc: Andres Gomez Cc: Dylan Baker Reviewed-by: Matt Turner Signed-off-by: Eric Engestrom --- docs/relnotes/18.2.0.html | 8 1 file changed, 8 insertions(+) diff --git a/docs/relnotes/18.2.0.html b/docs/relnotes/18.2.0.html index a3f44a29dc..0db37b620d 100644 --- a/docs/relnotes/18.2.0.html +++ b/docs/relnotes/18.2.0.html @@ -30,6 +30,13 @@ Some drivers don't support all the features required in OpenGL 4.5. OpenGL Compatibility contexts may report a lower version depending on each driver. + +libwayland-egl is now distributed by libwayland (since 1.15, +https://lists.freedesktop.org/archives/wayland-devel/2018-April/037767.html;>see announcement), +and has been removed from Mesa in this release. Make sure you're using +an up-to-date version of libwayland to keep the functionality. + + SHA256 checksums @@ -57,6 +64,7 @@ Note: some of the new features are only available with certain drivers. Removed GL_EXT_polygon_offset applications should use glPolygonOffset instead. +Removed libwayland-egl, now part of Wayland ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): nir: Add lowering for bitfieldInsert without using bfi.
Module: Mesa
Branch: master
Commit: 74618ccbcab6d785152c2840525d5bef08ed0696
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=74618ccbcab6d785152c2840525d5bef08ed0696
Author: Eric Anholt
Date: Wed May 2 14:13:23 2018 -0700
nir: Add lowering for bitfieldInsert without using bfi.
If you don't have HW to do bfi, then lowering bitfieldInsert to bfi makes
things harder than keeping the "bits" argument around.
This still uses bfm, but I've added the obvious lowering of bfm if you
need it.
Reviewed-by: Matt Turner
Reviewed-by: Ian Romanick
---
src/compiler/nir/nir.h| 5 +
src/compiler/nir/nir_opt_algebraic.py | 14 ++
2 files changed, 19 insertions(+)
diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index 5a1f79515a..6c0276fcc7 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -1904,7 +1904,12 @@ typedef struct nir_shader_compiler_options {
bool lower_fmod32;
bool lower_fmod64;
bool lower_bitfield_extract;
+ /** Lowers bitfield_insert to bfi/bfm */
bool lower_bitfield_insert;
+ /** Lowers bitfield_insert to bfm, compares, and shifts. */
+ bool lower_bitfield_insert_to_shifts;
+ /** Lowers bfm to shifts and subtracts. */
+ bool lower_bfm;
bool lower_uadd_carry;
bool lower_usub_borrow;
/** lowers fneg and ineg to fsub and isub. */
diff --git a/src/compiler/nir/nir_opt_algebraic.py
b/src/compiler/nir/nir_opt_algebraic.py
index fdfb0250b0..878d13ded5 100644
--- a/src/compiler/nir/nir_opt_algebraic.py
+++ b/src/compiler/nir/nir_opt_algebraic.py
@@ -515,6 +515,20 @@ optimizations = [
('bfi', ('bfm', 'bits', 'offset'), 'insert', 'base')),
'options->lower_bitfield_insert'),
+ # Alternative lowering that doesn't rely on bfi.
+ (('bitfield_insert', 'base', 'insert', 'offset', 'bits'),
+('bcsel', ('ilt', 31, 'bits'),
+ 'insert',
+ ('ior',
+ ('iand', 'base', ('inot', ('bfm', 'bits', 'offset'))),
+ ('iand', ('ishl', 'insert', 'offset'), ('bfm', 'bits', 'offset',
+'options->lower_bitfield_insert_to_shifts'),
+
+ # bfm lowering -- note that the NIR opcode is undefined if either arg is 32.
+ (('bfm', 'bits', 'offset'),
+('ishl', ('isub', ('ishl', 1, 'bits'), 1), 'offset'),
+'options->lower_bfm'),
+
(('ibitfield_extract', 'value', 'offset', 'bits'),
('bcsel', ('ilt', 31, 'bits'), 'value',
('ibfe', 'value', 'offset', 'bits')),
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Mesa (master): nir: Look into uniform structs for samplers when counting num_textures.
Module: Mesa
Branch: master
Commit: 833c4046007f22ce1da0e1c2b89e8f1892f8d38e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=833c4046007f22ce1da0e1c2b89e8f1892f8d38e
Author: Eric Anholt
Date: Fri Mar 30 16:04:34 2018 -0700
nir: Look into uniform structs for samplers when counting num_textures.
mesa/st decides whether to update samplers after a program change based on
whether num_textures is nonzero. By not counting samplers in a uniform
struct, we would segfault in
KHR-GLES3.shaders.struct.uniform.sampler_vertex if it was run in the same
context after a non-vertex-shader-uniform testcase (as is the case during
a full conformance run).
v2: Implement using two separate pure functions instead of updating
pointers.
Reviewed-by: Jason Ekstrand
---
src/compiler/nir/nir_gather_info.c | 56 ++
1 file changed, 44 insertions(+), 12 deletions(-)
diff --git a/src/compiler/nir/nir_gather_info.c
b/src/compiler/nir/nir_gather_info.c
index dba9f199ec..3534b6949e 100644
--- a/src/compiler/nir/nir_gather_info.c
+++ b/src/compiler/nir/nir_gather_info.c
@@ -352,24 +352,56 @@ gather_info_block(nir_block *block, nir_shader *shader)
}
}
+static unsigned
+glsl_type_get_sampler_count(const struct glsl_type *type)
+{
+ if (glsl_type_is_array(type)) {
+ return (glsl_get_aoa_size(type) *
+ glsl_type_get_sampler_count(glsl_without_array(type)));
+ }
+
+ if (glsl_type_is_struct(type)) {
+ unsigned count = 0;
+ for (int i = 0; i < glsl_get_length(type); i++)
+ count += glsl_type_get_sampler_count(glsl_get_struct_field(type, i));
+ return count;
+ }
+
+ if (glsl_type_is_sampler(type))
+ return 1;
+
+ return 0;
+}
+
+static unsigned
+glsl_type_get_image_count(const struct glsl_type *type)
+{
+ if (glsl_type_is_array(type)) {
+ return (glsl_get_aoa_size(type) *
+ glsl_type_get_image_count(glsl_without_array(type)));
+ }
+
+ if (glsl_type_is_struct(type)) {
+ unsigned count = 0;
+ for (int i = 0; i < glsl_get_length(type); i++)
+ count += glsl_type_get_image_count(glsl_get_struct_field(type, i));
+ return count;
+ }
+
+ if (glsl_type_is_image(type))
+ return 1;
+
+ return 0;
+}
+
void
nir_shader_gather_info(nir_shader *shader, nir_function_impl *entrypoint)
{
shader->info.num_textures = 0;
shader->info.num_images = 0;
nir_foreach_variable(var, >uniforms) {
- const struct glsl_type *type = var->type;
- unsigned count = 1;
- if (glsl_type_is_array(type)) {
- count = glsl_get_aoa_size(type);
- type = glsl_without_array(type);
- }
-
- if (glsl_type_is_image(type)) {
- shader->info.num_images += count;
- } else if (glsl_type_is_sampler(type)) {
- shader->info.num_textures += count;
- }
+ shader->info.num_textures += glsl_type_get_sampler_count(var->type);
+ shader->info.num_images += glsl_type_get_image_count(var->type);
}
shader->info.inputs_read = 0;
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Mesa (master): nir: Add lowering from ibitfield_extract/ubitfield_extract to shifts.
Module: Mesa
Branch: master
Commit: af88acf4c4e2e14161872752fb9fb4683f9c8845
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=af88acf4c4e2e14161872752fb9fb4683f9c8845
Author: Eric Anholt
Date: Wed May 2 13:02:21 2018 -0700
nir: Add lowering from ibitfield_extract/ubitfield_extract to shifts.
V3D doesn't have opcodes for ibfe/ubfe, so we need to lower similarly to
glsl/lower_instructions.cpp.
Reviewed-by: Matt Turner
Reviewed-by: Ian Romanick
---
src/compiler/nir/nir.h| 3 +++
src/compiler/nir/nir_opt_algebraic.py | 16
2 files changed, 19 insertions(+)
diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index 6c0276fcc7..519c019887 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -1903,7 +1903,10 @@ typedef struct nir_shader_compiler_options {
bool lower_fsqrt;
bool lower_fmod32;
bool lower_fmod64;
+ /** Lowers ibitfield_extract/ubitfield_extract to ibfe/ubfe. */
bool lower_bitfield_extract;
+ /** Lowers ibitfield_extract/ubitfield_extract to bfm, compares, shifts. */
+ bool lower_bitfield_extract_to_shifts;
/** Lowers bitfield_insert to bfi/bfm */
bool lower_bitfield_insert;
/** Lowers bitfield_insert to bfm, compares, and shifts. */
diff --git a/src/compiler/nir/nir_opt_algebraic.py
b/src/compiler/nir/nir_opt_algebraic.py
index 878d13ded5..eaa8b14164 100644
--- a/src/compiler/nir/nir_opt_algebraic.py
+++ b/src/compiler/nir/nir_opt_algebraic.py
@@ -539,6 +539,22 @@ optimizations = [
('ubfe', 'value', 'offset', 'bits')),
'options->lower_bitfield_extract'),
+ (('ibitfield_extract', 'value', 'offset', 'bits'),
+('bcsel', ('ieq', 0, 'bits'),
+ 0,
+ ('ishr',
+ ('ishl', 'value', ('isub', ('isub', 32, 'bits'), 'offset')),
+ ('isub', 32, 'bits'))),
+'options->lower_bitfield_extract_to_shifts'),
+
+ (('ubitfield_extract', 'value', 'offset', 'bits'),
+('iand',
+ ('ushr', 'value', 'offset'),
+ ('bcsel', ('ieq', 'bits', 32),
+ 0x,
+ ('bfm', 'bits', 0))),
+'options->lower_bitfield_extract_to_shifts'),
+
(('extract_i8', a, 'b@32'),
('ishr', ('ishl', a, ('imul', ('isub', 3, b), 8)), 24),
'options->lower_extract_byte'),
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Mesa (master): nir: Add lowering for nir_op_bit_count.
Module: Mesa
Branch: master
Commit: 73953b071365ca64db353023fff78a06b20503a3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=73953b071365ca64db353023fff78a06b20503a3
Author: Eric Anholt
Date: Tue May 8 13:04:37 2018 -0700
nir: Add lowering for nir_op_bit_count.
This is basically the same as the GLSL lowering path.
v2: Fix typo in the link
Reviewed-by: Matt Turner
Reviewed-by: Ian Romanick
---
src/compiler/nir/nir.h | 2 ++
src/compiler/nir/nir_lower_alu.c | 36
2 files changed, 38 insertions(+)
diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index 06154aa990..bb477742dc 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -1913,6 +1913,8 @@ typedef struct nir_shader_compiler_options {
bool lower_bitfield_insert_to_shifts;
/** Lowers bitfield_reverse to shifts. */
bool lower_bitfield_reverse;
+ /** Lowers bit_count to shifts. */
+ bool lower_bit_count;
/** Lowers bfm to shifts and subtracts. */
bool lower_bfm;
/** Lowers ifind_msb to compare and ufind_msb */
diff --git a/src/compiler/nir/nir_lower_alu.c b/src/compiler/nir/nir_lower_alu.c
index ff977f0169..8d1a1d3746 100644
--- a/src/compiler/nir/nir_lower_alu.c
+++ b/src/compiler/nir/nir_lower_alu.c
@@ -94,6 +94,42 @@ lower_alu_instr(nir_alu_instr *instr, nir_builder *b)
}
break;
+ case nir_op_bit_count:
+ if (b->shader->options->lower_bit_count) {
+ /* For more details, see:
+ *
+ *
http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
+ */
+ nir_ssa_def *c1 = nir_imm_int(b, 1);
+ nir_ssa_def *c2 = nir_imm_int(b, 2);
+ nir_ssa_def *c4 = nir_imm_int(b, 4);
+ nir_ssa_def *c24 = nir_imm_int(b, 24);
+ nir_ssa_def *c = nir_imm_int(b, 0x);
+ nir_ssa_def *c = nir_imm_int(b, 0x);
+ nir_ssa_def *c0f0f0f0f = nir_imm_int(b, 0x0f0f0f0f);
+ nir_ssa_def *c01010101 = nir_imm_int(b, 0x01010101);
+
+ lowered = nir_ssa_for_alu_src(b, instr, 0);
+
+ lowered = nir_isub(b, lowered,
+nir_iand(b, nir_ushr(b, lowered, c1), c));
+
+ lowered = nir_iadd(b,
+nir_iand(b, lowered, c),
+nir_iand(b, nir_ushr(b, lowered, c2), c));
+
+ lowered = nir_ushr(b,
+nir_imul(b,
+ nir_iand(b,
+ nir_iadd(b,
+ lowered,
+ nir_ushr(b, lowered,
c4)),
+ c0f0f0f0f),
+ c01010101),
+c24);
+ }
+ break;
+
case nir_op_imul_high:
case nir_op_umul_high:
if (b->shader->options->lower_mul_high) {
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Mesa (master): nir: Add lowering for ifind_msb to ufind_msb.
Module: Mesa
Branch: master
Commit: d4c7c3c225b7c34669498c15c2d3186cf6a4647e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d4c7c3c225b7c34669498c15c2d3186cf6a4647e
Author: Eric Anholt
Date: Fri May 4 13:33:47 2018 -0700
nir: Add lowering for ifind_msb to ufind_msb.
ufind_msb is easily expressed in terms of clz, and we can reduce ifind_msb
to that.
Reviewed-by: Matt Turner
Reviewed-by: Ian Romanick
---
src/compiler/nir/nir.h| 2 ++
src/compiler/nir/nir_opt_algebraic.py | 4
2 files changed, 6 insertions(+)
diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index 519c019887..9fca61f007 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -1913,6 +1913,8 @@ typedef struct nir_shader_compiler_options {
bool lower_bitfield_insert_to_shifts;
/** Lowers bfm to shifts and subtracts. */
bool lower_bfm;
+ /** Lowers ifind_msb to compare and ufind_msb */
+ bool lower_ifind_msb;
bool lower_uadd_carry;
bool lower_usub_borrow;
/** lowers fneg and ineg to fsub and isub. */
diff --git a/src/compiler/nir/nir_opt_algebraic.py
b/src/compiler/nir/nir_opt_algebraic.py
index eaa8b14164..f6685977f3 100644
--- a/src/compiler/nir/nir_opt_algebraic.py
+++ b/src/compiler/nir/nir_opt_algebraic.py
@@ -555,6 +555,10 @@ optimizations = [
('bfm', 'bits', 0))),
'options->lower_bitfield_extract_to_shifts'),
+ (('ifind_msb', 'value'),
+('ufind_msb', ('bcsel', ('ilt', 'value', 0), ('inot', 'value'), 'value')),
+'options->lower_ifind_msb'),
+
(('extract_i8', a, 'b@32'),
('ishr', ('ishl', a, ('imul', ('isub', 3, b), 8)), 24),
'options->lower_extract_byte'),
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Mesa (master): nir: Add lowering for find_lsb.
Module: Mesa
Branch: master
Commit: 6a0db5f08ffac7d43a5b937982262f357a21f95b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6a0db5f08ffac7d43a5b937982262f357a21f95b
Author: Eric Anholt
Date: Fri May 4 14:02:55 2018 -0700
nir: Add lowering for find_lsb.
There is a fairly simple relation to turn this into ufind_msb.
Reviewed-by: Matt Turner
Reviewed-by: Ian Romanick
---
src/compiler/nir/nir.h| 2 ++
src/compiler/nir/nir_opt_algebraic.py | 4
2 files changed, 6 insertions(+)
diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index 9fca61f007..b9426f8eb4 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -1915,6 +1915,8 @@ typedef struct nir_shader_compiler_options {
bool lower_bfm;
/** Lowers ifind_msb to compare and ufind_msb */
bool lower_ifind_msb;
+ /** Lowers find_lsb to ufind_msb and logic ops */
+ bool lower_find_lsb;
bool lower_uadd_carry;
bool lower_usub_borrow;
/** lowers fneg and ineg to fsub and isub. */
diff --git a/src/compiler/nir/nir_opt_algebraic.py
b/src/compiler/nir/nir_opt_algebraic.py
index f6685977f3..db907df854 100644
--- a/src/compiler/nir/nir_opt_algebraic.py
+++ b/src/compiler/nir/nir_opt_algebraic.py
@@ -559,6 +559,10 @@ optimizations = [
('ufind_msb', ('bcsel', ('ilt', 'value', 0), ('inot', 'value'), 'value')),
'options->lower_ifind_msb'),
+ (('find_lsb', 'value'),
+('ufind_msb', ('iand', 'value', ('ineg', 'value'))),
+'options->lower_find_lsb'),
+
(('extract_i8', a, 'b@32'),
('ishr', ('ishl', a, ('imul', ('isub', 3, b), 8)), 24),
'options->lower_extract_byte'),
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Mesa (master): v3d: Enable the new NIR bitfield operation lowering paths.
Module: Mesa
Branch: master
Commit: 9d5860310d57db9b3aabf0c0e562130fb8dcce99
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9d5860310d57db9b3aabf0c0e562130fb8dcce99
Author: Eric Anholt
Date: Wed May 2 14:17:07 2018 -0700
v3d: Enable the new NIR bitfield operation lowering paths.
These together get the GLSL 3.00 unorm/snorm pack functions and
MESA_shader_integer operations working.
v2: Fix commit message typo.
Reviewed-by: Matt Turner
Reviewed-by: Ian Romanick
---
src/broadcom/compiler/nir_to_vir.c | 21 +++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/src/broadcom/compiler/nir_to_vir.c
b/src/broadcom/compiler/nir_to_vir.c
index ec8f22321f..0f7e47689d 100644
--- a/src/broadcom/compiler/nir_to_vir.c
+++ b/src/broadcom/compiler/nir_to_vir.c
@@ -755,6 +755,10 @@ ntq_emit_alu(struct v3d_compile *c, nir_alu_instr *instr)
result = vir_NOT(c, src[0]);
break;
+case nir_op_ufind_msb:
+result = vir_SUB(c, vir_uniform_ui(c, 31), vir_CLZ(c, src[0]));
+break;
+
case nir_op_imul:
result = vir_UMUL(c, src[0], src[1]);
break;
@@ -853,6 +857,13 @@ ntq_emit_alu(struct v3d_compile *c, nir_alu_instr *instr)
result = vir_FDY(c, src[0]);
break;
+case nir_op_uadd_carry:
+vir_PF(c, vir_ADD(c, src[0], src[1]), V3D_QPU_PF_PUSHC);
+result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFA,
+vir_uniform_ui(c, ~0),
+vir_uniform_ui(c, 0)));
+break;
+
default:
fprintf(stderr, "unknown NIR ALU inst: ");
nir_print_instr(>instr, stderr);
@@ -1894,8 +1905,11 @@ const nir_shader_compiler_options v3d_nir_options = {
.lower_all_io_to_temps = true,
.lower_extract_byte = true,
.lower_extract_word = true,
-.lower_bitfield_insert = true,
-.lower_bitfield_extract = true,
+.lower_bfm = true,
+.lower_bitfield_insert_to_shifts = true,
+.lower_bitfield_extract_to_shifts = true,
+.lower_bitfield_reverse = true,
+.lower_bit_count = true,
.lower_pack_unorm_2x16 = true,
.lower_pack_snorm_2x16 = true,
.lower_pack_unorm_4x8 = true,
@@ -1903,12 +1917,15 @@ const nir_shader_compiler_options v3d_nir_options = {
.lower_unpack_unorm_4x8 = true,
.lower_unpack_snorm_4x8 = true,
.lower_fdiv = true,
+.lower_find_lsb = true,
.lower_ffma = true,
.lower_flrp32 = true,
.lower_fpow = true,
.lower_fsat = true,
.lower_fsqrt = true,
+.lower_ifind_msb = true,
.lower_ldexp = true,
+.lower_mul_high = true,
.native_integers = true,
};
___
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Mesa (master): nir: Add an ALU lowering pass for mul_high.
Module: Mesa
Branch: master
Commit: 6e1597c2d9f5e14ffaf1c326985ee3203f995044
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6e1597c2d9f5e14ffaf1c326985ee3203f995044
Author: Eric Anholt
Date: Tue May 8 11:24:40 2018 -0700
nir: Add an ALU lowering pass for mul_high.
This is based on the glsl/lower_instructions.cpp implementation, but
should be much more readable.
Reviewed-by: Matt Turner
Reviewed-by: Ian Romanick
---
src/compiler/Makefile.sources | 1 +
src/compiler/nir/meson.build | 1 +
src/compiler/nir/nir.h| 3 +
src/compiler/nir/nir_lower_alu.c | 165 ++
src/mesa/state_tracker/st_glsl_to_nir.cpp | 1 +
5 files changed, 171 insertions(+)
diff --git a/src/compiler/Makefile.sources b/src/compiler/Makefile.sources
index 3daa2c5133..d629c2b8ec 100644
--- a/src/compiler/Makefile.sources
+++ b/src/compiler/Makefile.sources
@@ -214,6 +214,7 @@ NIR_FILES = \
nir/nir_loop_analyze.c \
nir/nir_loop_analyze.h \
nir/nir_lower_alpha_test.c \
+ nir/nir_lower_alu.c \
nir/nir_lower_alu_to_scalar.c \
nir/nir_lower_atomics_to_ssbo.c \
nir/nir_lower_bitmap.c \
diff --git a/src/compiler/nir/meson.build b/src/compiler/nir/meson.build
index 3fec363691..598c68aff9 100644
--- a/src/compiler/nir/meson.build
+++ b/src/compiler/nir/meson.build
@@ -104,6 +104,7 @@ files_libnir = files(
'nir_liveness.c',
'nir_loop_analyze.c',
'nir_loop_analyze.h',
+ 'nir_lower_alu.c',
'nir_lower_alu_to_scalar.c',
'nir_lower_alpha_test.c',
'nir_lower_atomics_to_ssbo.c',
diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index b9426f8eb4..7d01eb23bc 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -1919,6 +1919,8 @@ typedef struct nir_shader_compiler_options {
bool lower_find_lsb;
bool lower_uadd_carry;
bool lower_usub_borrow;
+ /** Lowers imul_high/umul_high to 16-bit multiplies and carry operations. */
+ bool lower_mul_high;
/** lowers fneg and ineg to fsub and isub. */
bool lower_negate;
/** lowers fsub and isub to fadd+fneg and iadd+ineg. */
@@ -2628,6 +2630,7 @@ bool nir_move_vec_src_uses_to_dest(nir_shader *shader);
bool nir_lower_vec_to_movs(nir_shader *shader);
void nir_lower_alpha_test(nir_shader *shader, enum compare_func func,
bool alpha_to_one);
+bool nir_lower_alu(nir_shader *shader);
bool nir_lower_alu_to_scalar(nir_shader *shader);
bool nir_lower_load_const_to_scalar(nir_shader *shader);
bool nir_lower_read_invocation_to_scalar(nir_shader *shader);
diff --git a/src/compiler/nir/nir_lower_alu.c b/src/compiler/nir/nir_lower_alu.c
new file mode 100644
index 00..28ecaf6bad
--- /dev/null
+++ b/src/compiler/nir/nir_lower_alu.c
@@ -0,0 +1,165 @@
+/*
+ * Copyright © 2010 Intel Corporation
+ * Copyright © 2018 Broadcom
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include "nir.h"
+#include "nir_builder.h"
+
+/** nir_lower_alu.c
+ *
+ * NIR's home for miscellaneous ALU operation lowering implementations.
+ *
+ * Most NIR ALU lowering occurs in nir_opt_algebraic.py, since it's generally
+ * easy to write them there. However, if terms appear multiple times in the
+ * lowered code, it can get very verbose and cause a lot of work for CSE, so
+ * it may end up being easier to write out in C code.
+ *
+ * The shader must be in SSA for this pass.
+ */
+
+#define LOWER_MUL_HIGH (1 << 0)
+
+static bool
+lower_alu_instr(nir_alu_instr *instr, nir_builder *b)
+{
+ nir_ssa_def *lowered = NULL;
+
+ assert(instr->dest.dest.is_ssa);
+
+ b->cursor = nir_before_instr(>instr);
+ b->exact = instr->exact;
+
+ switch (instr->op) {
+ case nir_op_imul_high:
+ case nir_op_umul_high:
+ if (b->shader->options->lower_mul_high) {
+ nir_ssa_def *c1 = nir_imm_int(b, 1);
+ nir_ssa_def *c16 =
Mesa (master): v3d: Work around GFXH-1461/GFXH-1689 by using CLEAR_TILE_BUFFERS.
Module: Mesa
Branch: master
Commit: f69473a712147c27fefbe83b9beacb251969fd92
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f69473a712147c27fefbe83b9beacb251969fd92
Author: Eric Anholt
Date: Wed May 2 11:45:07 2018 -0700
v3d: Work around GFXH-1461/GFXH-1689 by using CLEAR_TILE_BUFFERS.
This doesn't seem to have done anything to my test results. However,
given that we've still got a class of GPU hangs, following the workarounds
that the closed driver does so that we get the same command sequences
seems like a good idea.
---
src/gallium/drivers/v3d/v3dx_rcl.c | 27 +--
1 file changed, 17 insertions(+), 10 deletions(-)
diff --git a/src/gallium/drivers/v3d/v3dx_rcl.c
b/src/gallium/drivers/v3d/v3dx_rcl.c
index 5be29aca1f..766f7909c1 100644
--- a/src/gallium/drivers/v3d/v3dx_rcl.c
+++ b/src/gallium/drivers/v3d/v3dx_rcl.c
@@ -130,10 +130,7 @@ store_general(struct v3d_job *job,
store.address = cl_address(rsc->bo, surf->offset);
#if V3D_VERSION >= 40
-store.clear_buffer_being_stored =
-((job->cleared & pipe_bit) &&
- (general_color_clear ||
- !(pipe_bit & PIPE_CLEAR_COLOR_BUFFERS)));
+store.clear_buffer_being_stored = false;
if (separate_stencil)
store.output_image_format = V3D_OUTPUT_IMAGE_FORMAT_S8;
@@ -269,6 +266,7 @@ v3d_rcl_emit_loads(struct v3d_job *job, struct v3d_cl *cl)
static void
v3d_rcl_emit_stores(struct v3d_job *job, struct v3d_cl *cl)
{
+#if V3D_VERSION < 40
MAYBE_UNUSED bool needs_color_clear = job->cleared &
PIPE_CLEAR_COLOR_BUFFERS;
MAYBE_UNUSED bool needs_z_clear = job->cleared & PIPE_CLEAR_DEPTH;
MAYBE_UNUSED bool needs_s_clear = job->cleared & PIPE_CLEAR_STENCIL;
@@ -290,6 +288,9 @@ v3d_rcl_emit_stores(struct v3d_job *job, struct v3d_cl *cl)
bool general_color_clear = (needs_color_clear &&
(job->cleared & PIPE_CLEAR_COLOR_BUFFERS)
==
(job->resolve & PIPE_CLEAR_COLOR_BUFFERS));
+#else
+bool general_color_clear = false;
+#endif
uint32_t stores_pending = job->resolve;
@@ -342,8 +343,8 @@ v3d_rcl_emit_stores(struct v3d_job *job, struct v3d_cl *cl)
}
}
-if (stores_pending) {
#if V3D_VERSION < 40
+if (stores_pending) {
cl_emit(cl,
STORE_MULTI_SAMPLE_RESOLVED_TILE_COLOR_BUFFER_EXTENDED, store) {
store.disable_color_buffer_write =
@@ -362,23 +363,29 @@ v3d_rcl_emit_stores(struct v3d_job *job, struct v3d_cl
*cl)
store.disable_stencil_buffer_clear_on_write =
!needs_s_clear;
};
-#else /* V3D_VERSION >= 40 */
-unreachable("All color buffers should have been stored.");
-#endif /* V3D_VERSION >= 40 */
} else if (needs_color_clear && !general_color_clear) {
/* If we didn't do our color clears in the general packet,
* then emit a packet to clear all the TLB color buffers now.
*/
-#if V3D_VERSION < 40
cl_emit(cl, STORE_TILE_BUFFER_GENERAL, store) {
store.buffer_to_store = NONE;
}
+}
#else /* V3D_VERSION >= 40 */
+assert(!stores_pending);
+
+/* GFXH-1461/GFXH-1689: The per-buffer store command's clear
+ * buffer bit is broken for depth/stencil. In addition, the
+ * clear packet's Z/S bit is broken, but the RTs bit ends up
+ * clearing Z/S.
+ */
+if (job->cleared) {
cl_emit(cl, CLEAR_TILE_BUFFERS, clear) {
+clear.clear_z_stencil_buffer = true;
clear.clear_all_render_targets = true;
}
-#endif /* V3D_VERSION >= 40 */
}
+#endif /* V3D_VERSION >= 40 */
}
static void
___
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Mesa (master): nir: Add lowering for nir_op_bitfield_reverse.
Module: Mesa
Branch: master
Commit: 7afa26d4e39c73502ad75b95605197eb52c8d099
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7afa26d4e39c73502ad75b95605197eb52c8d099
Author: Eric Anholt
Date: Tue May 8 12:47:48 2018 -0700
nir: Add lowering for nir_op_bitfield_reverse.
This is basically the same as the GLSL lowering path.
Reviewed-by: Matt Turner
Reviewed-by: Ian Romanick
---
src/compiler/nir/nir.h | 2 ++
src/compiler/nir/nir_lower_alu.c | 47 +++-
2 files changed, 48 insertions(+), 1 deletion(-)
diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index 7d01eb23bc..06154aa990 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -1911,6 +1911,8 @@ typedef struct nir_shader_compiler_options {
bool lower_bitfield_insert;
/** Lowers bitfield_insert to bfm, compares, and shifts. */
bool lower_bitfield_insert_to_shifts;
+ /** Lowers bitfield_reverse to shifts. */
+ bool lower_bitfield_reverse;
/** Lowers bfm to shifts and subtracts. */
bool lower_bfm;
/** Lowers ifind_msb to compare and ufind_msb */
diff --git a/src/compiler/nir/nir_lower_alu.c b/src/compiler/nir/nir_lower_alu.c
index 28ecaf6bad..ff977f0169 100644
--- a/src/compiler/nir/nir_lower_alu.c
+++ b/src/compiler/nir/nir_lower_alu.c
@@ -50,6 +50,50 @@ lower_alu_instr(nir_alu_instr *instr, nir_builder *b)
b->exact = instr->exact;
switch (instr->op) {
+ case nir_op_bitfield_reverse:
+ if (b->shader->options->lower_bitfield_reverse) {
+ /* For more details, see:
+ *
+ * http://graphics.stanford.edu/~seander/bithacks.html#ReverseParallel
+ */
+ nir_ssa_def *c1 = nir_imm_int(b, 1);
+ nir_ssa_def *c2 = nir_imm_int(b, 2);
+ nir_ssa_def *c4 = nir_imm_int(b, 4);
+ nir_ssa_def *c8 = nir_imm_int(b, 8);
+ nir_ssa_def *c16 = nir_imm_int(b, 16);
+ nir_ssa_def *c = nir_imm_int(b, 0x);
+ nir_ssa_def *c = nir_imm_int(b, 0x);
+ nir_ssa_def *c0f0f0f0f = nir_imm_int(b, 0x0f0f0f0f);
+ nir_ssa_def *c00ff00ff = nir_imm_int(b, 0x00ff00ff);
+
+ lowered = nir_ssa_for_alu_src(b, instr, 0);
+
+ /* Swap odd and even bits. */
+ lowered = nir_ior(b,
+ nir_iand(b, nir_ushr(b, lowered, c1), c),
+ nir_ishl(b, nir_iand(b, lowered, c), c1));
+
+ /* Swap consecutive pairs. */
+ lowered = nir_ior(b,
+ nir_iand(b, nir_ushr(b, lowered, c2), c),
+ nir_ishl(b, nir_iand(b, lowered, c), c2));
+
+ /* Swap nibbles. */
+ lowered = nir_ior(b,
+ nir_iand(b, nir_ushr(b, lowered, c4), c0f0f0f0f),
+ nir_ishl(b, nir_iand(b, lowered, c0f0f0f0f), c4));
+
+ /* Swap bytes. */
+ lowered = nir_ior(b,
+ nir_iand(b, nir_ushr(b, lowered, c8), c00ff00ff),
+ nir_ishl(b, nir_iand(b, lowered, c00ff00ff), c8));
+
+ lowered = nir_ior(b,
+ nir_ushr(b, lowered, c16),
+ nir_ishl(b, lowered, c16));
+ }
+ break;
+
case nir_op_imul_high:
case nir_op_umul_high:
if (b->shader->options->lower_mul_high) {
@@ -136,7 +180,8 @@ nir_lower_alu(nir_shader *shader)
{
bool progress = false;
- if (!shader->options->lower_mul_high)
+ if (!shader->options->lower_bitfield_reverse &&
+ !shader->options->lower_mul_high)
return false;
nir_foreach_function(function, shader) {
___
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Mesa (master): egl: remove wayland-egl now that we're using libwayland-egl
Module: Mesa
Branch: master
Commit: b9361c9df051be632ef7b6481afe5b6c3c5efe4f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b9361c9df051be632ef7b6481afe5b6c3c5efe4f
Author: Eric Engestrom
Date: Tue May 29 15:41:29 2018 +0100
egl: remove wayland-egl now that we're using libwayland-egl
Cc: Emil Velikov
Cc: Daniel Stone
Reviewed-by: Matt Turner
Signed-off-by: Eric Engestrom
---
src/egl/wayland/wayland-egl/Makefile.am| 24 ---
src/egl/wayland/wayland-egl/meson.build| 50 -
.../wayland/wayland-egl/wayland-egl-abi-check.c| 235 -
src/egl/wayland/wayland-egl/wayland-egl-backend.h | 63 --
.../wayland/wayland-egl/wayland-egl-symbols-check | 24 ---
src/egl/wayland/wayland-egl/wayland-egl.c | 109 --
src/egl/wayland/wayland-egl/wayland-egl.pc.in | 11 -
7 files changed, 516 deletions(-)
diff --git a/src/egl/wayland/wayland-egl/Makefile.am
b/src/egl/wayland/wayland-egl/Makefile.am
deleted file mode 100644
index 31dcca9e10..00
--- a/src/egl/wayland/wayland-egl/Makefile.am
+++ /dev/null
@@ -1,24 +0,0 @@
-pkgconfigdir = $(libdir)/pkgconfig
-pkgconfig_DATA = wayland-egl.pc
-
-AM_CFLAGS = $(DEFINES) \
- $(VISIBILITY_CFLAGS) \
- $(WAYLAND_CLIENT_CFLAGS)
-
-lib_LTLIBRARIES = libwayland-egl.la
-noinst_HEADERS = wayland-egl-backend.h
-libwayland_egl_la_SOURCES = wayland-egl.c
-libwayland_egl_la_LDFLAGS = \
- -no-undefined \
- -version-info 1 \
- $(GC_SECTIONS) \
- $(LD_NO_UNDEFINED)
-
-TESTS = wayland-egl-symbols-check \
-wayland-egl-abi-check
-
-EXTRA_DIST = wayland-egl-symbols-check meson.build
-
-check_PROGRAMS = wayland-egl-abi-check
-
-include $(top_srcdir)/install-lib-links.mk
diff --git a/src/egl/wayland/wayland-egl/meson.build
b/src/egl/wayland/wayland-egl/meson.build
deleted file mode 100644
index d0a7521da9..00
--- a/src/egl/wayland/wayland-egl/meson.build
+++ /dev/null
@@ -1,50 +0,0 @@
-# Copyright © 2017 Intel Corporation
-
-# Permission is hereby granted, free of charge, to any person obtaining a copy
-# of this software and associated documentation files (the "Software"), to deal
-# in the Software without restriction, including without limitation the rights
-# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-# copies of the Software, and to permit persons to whom the Software is
-# furnished to do so, subject to the following conditions:
-
-# The above copyright notice and this permission notice shall be included in
-# all copies or substantial portions of the Software.
-
-# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-# SOFTWARE.
-
-
-libwayland_egl = shared_library(
- 'wayland-egl',
- 'wayland-egl.c',
- c_args : [c_vis_args],
- link_args : ld_args_gc_sections,
- dependencies : dep_wayland_client,
- version : '1.0.0',
- install : true,
-)
-
-pkg.generate(
- name : 'wayland-egl',
- description : 'Mesa wayland-egl library',
- libraries : libwayland_egl,
- version : meson.project_version(),
- requires : 'wayland-client',
-)
-
-if with_tests
- test('wayland-egl-symbols-check',
-find_program('wayland-egl-symbols-check'),
-env : env_test,
-args : libwayland_egl
- )
- test(
-'wayland-egl-abi-check',
-executable('wayland-egl-abi-check', 'wayland-egl-abi-check.c')
- )
-endif
diff --git a/src/egl/wayland/wayland-egl/wayland-egl-abi-check.c
b/src/egl/wayland/wayland-egl/wayland-egl-abi-check.c
deleted file mode 100644
index 62c51a2260..00
--- a/src/egl/wayland/wayland-egl/wayland-egl-abi-check.c
+++ /dev/null
@@ -1,235 +0,0 @@
-/*
- * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE
Mesa (master): intel/blorp: Don't vertex fetch directly from clear values
Module: Mesa
Branch: master
Commit: 44c614843c8785be57af06cc56208ad1497d05bc
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=44c614843c8785be57af06cc56208ad1497d05bc
Author: Jason Ekstrand
Date: Mon Jun 4 17:27:53 2018 -0700
intel/blorp: Don't vertex fetch directly from clear values
On gen8+, we have to VF cache flush whenever a vertex binding aliases a
previous binding at the same index modulo 4GiB. We deal with this in
Vulkan by ensuring that vertex buffers and the dynamic state (from which
BLORP pulls its vertex buffers) are in the same 4GiB region of the
address space. That doesn't work if we're reading clear colors with the
VF unit. In order to work around this we switch to using MI commands to
copy the clear value into the vertex buffer we allocate for the normal
constant data.
Cc: mesa-sta...@lists.freedesktop.org
Reviewed-by: Kenneth Graunke
---
src/intel/blorp/blorp_genX_exec.h | 85 +++
1 file changed, 41 insertions(+), 44 deletions(-)
diff --git a/src/intel/blorp/blorp_genX_exec.h
b/src/intel/blorp/blorp_genX_exec.h
index 446743b591..bcaef4f367 100644
--- a/src/intel/blorp/blorp_genX_exec.h
+++ b/src/intel/blorp/blorp_genX_exec.h
@@ -200,6 +200,14 @@ emit_urb_config(struct blorp_batch *batch,
blorp_emit_urb_config(batch, vs_entry_size, sf_entry_size);
}
+#if GEN_GEN >= 7
+static void
+blorp_emit_memcpy(struct blorp_batch *batch,
+ struct blorp_address dst,
+ struct blorp_address src,
+ uint32_t size);
+#endif
+
static void
blorp_emit_vertex_data(struct blorp_batch *batch,
const struct blorp_params *params,
@@ -260,6 +268,31 @@ blorp_emit_input_varying_data(struct blorp_batch *batch,
}
blorp_flush_range(batch, data, *size);
+
+ if (params->dst_clear_color_as_input) {
+#if GEN_GEN >= 7
+ /* In this case, the clear color isn't known statically and instead
+ * comes in through an indirect which we have to copy into the vertex
+ * buffer before we execute the 3DPRIMITIVE. We already copied the
+ * value of params->wm_inputs.clear_color into the vertex buffer in the
+ * loop above. Now we emit code to stomp it from the GPU with the
+ * actual clear color value.
+ */
+ assert(num_varyings == 1);
+
+ /* The clear color is the first thing after the header */
+ struct blorp_address clear_color_input_addr = *addr;
+ clear_color_input_addr.offset += 16;
+
+ const unsigned clear_color_size =
+ GEN_GEN < 10 ? batch->blorp->isl_dev->ss.clear_value_size : 4 * 4;
+ blorp_emit_memcpy(batch, clear_color_input_addr,
+params->dst.clear_color_addr,
+clear_color_size);
+#else
+ unreachable("MCS partial resolve is not a thing on SNB and earlier");
+#endif
+ }
}
static void
@@ -298,6 +331,7 @@ blorp_emit_vertex_buffers(struct blorp_batch *batch,
const struct blorp_params *params)
{
struct GENX(VERTEX_BUFFER_STATE) vb[3];
+ uint32_t num_vbs = 2;
memset(vb, 0, sizeof(vb));
struct blorp_address addr;
@@ -308,15 +342,6 @@ blorp_emit_vertex_buffers(struct blorp_batch *batch,
blorp_emit_input_varying_data(batch, params, , );
blorp_fill_vertex_buffer_state(batch, vb, 1, addr, size, 0);
- uint32_t num_vbs = 2;
- if (params->dst_clear_color_as_input) {
- const unsigned clear_color_size =
- GEN_GEN < 10 ? batch->blorp->isl_dev->ss.clear_value_size : 4 * 4;
- blorp_fill_vertex_buffer_state(batch, vb, num_vbs++,
- params->dst.clear_color_addr,
- clear_color_size, 0);
- }
-
const unsigned num_dwords = 1 + num_vbs * GENX(VERTEX_BUFFER_STATE_length);
uint32_t *dw = blorp_emitn(batch, GENX(3DSTATE_VERTEX_BUFFERS), num_dwords);
if (!dw)
@@ -449,49 +474,21 @@ blorp_emit_vertex_elements(struct blorp_batch *batch,
};
slot++;
- if (params->dst_clear_color_as_input) {
- /* If the caller wants the destination indirect clear color, redirect
- * to vertex buffer 2 where we stored it earlier. The only users of
- * an indirect clear color source have that as their only vertex
- * attribute.
- */
- assert(num_varyings == 1);
+ for (unsigned i = 0; i < num_varyings; ++i) {
ve[slot] = (struct GENX(VERTEX_ELEMENT_STATE)) {
- .VertexBufferIndex = 2,
+ .VertexBufferIndex = 1,
.Valid = true,
- .SourceElementOffset = 0,
- .Component0Control = VFCOMP_STORE_SRC,
-#if GEN_GEN >= 9
.SourceElementFormat = ISL_FORMAT_R32G32B32A32_FLOAT,
+ .SourceElementOffset = 16 + i * 4 * sizeof(float),
+ .Component0Control = VFCOMP_STORE_SRC,
.Component1Control = VFCOMP_STORE_SRC,
.Component2Control = VFCOMP_STORE_SRC,
.Component3Control = VFCOMP_STORE_SRC,
-#else
-
Mesa (master): dri: add missing 16bits formats mapping
Module: Mesa
Branch: master
Commit: b28a2510cc49711803b9ebcdc315c5011e9a282e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b28a2510cc49711803b9ebcdc315c5011e9a282e
Author: Lionel Landwerlin
Date: Wed Jun 6 12:57:18 2018 +0100
dri: add missing 16bits formats mapping
i965 advertises the 16-bit R and RG formats through
eglQueryDmaBufFormatsEXT but falls over when a client tries to use or
asks more information about such a format because
driImageFormatToGLFormat returns MESA_FORMAT_NONE.
Found by Eero Tamminen.
v2: Add G16R16 formats (Lionel)
v3: Fix G16R16 mapping to mesa format (Jason)
Signed-off-by: Lionel Landwerlin
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106642
Reviewed-by: Plamena Manolova (v2)
Reviewed-by: Jason Ekstrand
---
src/mesa/drivers/dri/common/dri_util.c | 16
1 file changed, 16 insertions(+)
diff --git a/src/mesa/drivers/dri/common/dri_util.c
b/src/mesa/drivers/dri/common/dri_util.c
index a591dfcd7d..d257cb644c 100644
--- a/src/mesa/drivers/dri/common/dri_util.c
+++ b/src/mesa/drivers/dri/common/dri_util.c
@@ -936,6 +936,22 @@ static const struct {
.image_format = __DRI_IMAGE_FORMAT_SARGB8,
.mesa_format =MESA_FORMAT_B8G8R8A8_SRGB,
},
+ {
+ .image_format = __DRI_IMAGE_FORMAT_R16,
+ .mesa_format =MESA_FORMAT_R_UNORM16,
+ },
+ {
+ .image_format = __DRI_IMAGE_FORMAT_R16,
+ .mesa_format =MESA_FORMAT_L_UNORM16,
+ },
+ {
+ .image_format = __DRI_IMAGE_FORMAT_GR1616,
+ .mesa_format =MESA_FORMAT_R16G16_UNORM,
+ },
+ {
+ .image_format = __DRI_IMAGE_FORMAT_GR1616,
+ .mesa_format =MESA_FORMAT_L16A16_UNORM,
+ },
};
uint32_t
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