Mesa (master): radv: fix emitting the TCS regs on GFX9
Module: Mesa Branch: master Commit: 5917761e3dddc968d5ccac9b282b7cb8d3da866f URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5917761e3dddc968d5ccac9b282b7cb8d3da866f Author: Samuel Pitoiset Date: Fri Jun 15 17:50:35 2018 +0200 radv: fix emitting the TCS regs on GFX9 The primitive ID is NULL and this generates an invalid select instruction which crashes because one operand is NULL. This fixes crashes in The Long Journey Home, Quantum Break and Just Cause 3 with DXVK. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106756 CC: Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_nir_to_llvm.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c index 5168c9d554..21f2e9d26b 100644 --- a/src/amd/vulkan/radv_nir_to_llvm.c +++ b/src/amd/vulkan/radv_nir_to_llvm.c @@ -3107,7 +3107,6 @@ static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context *ctx) LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count, ctx->ac.i32_0, ""); ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, ""); - ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, ""); ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_rel_ids, ctx->rel_auto_id, ""); ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_patch_id, ctx->abi.vertex_id, ""); } ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): ac: Clear meminfo to avoid valgrind warning.
Module: Mesa
Branch: master
Commit: c4714f698bf1eda6ee77304f8abe0a92be7a55e7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c4714f698bf1eda6ee77304f8abe0a92be7a55e7
Author: Bas Nieuwenhuizen
Date: Fri Jun 15 00:01:43 2018 +0200
ac: Clear meminfo to avoid valgrind warning.
Somehow valgrind misses that the value is initialized by the ioctl.
Reviewed-by: Dave Airlie
Reviewed-by: Samuel Pitoiset
---
src/amd/common/ac_gpu_info.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index e908cc6fa9..e885c0538e 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -235,7 +235,7 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
}
if (info->drm_minor >= 9) {
- struct drm_amdgpu_memory_info meminfo;
+ struct drm_amdgpu_memory_info meminfo = {};
r = amdgpu_query_info(dev, AMDGPU_INFO_MEMORY, sizeof(meminfo),
);
if (r) {
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Mesa (master): appveyor: Consume LLVM 5.0.1.
Module: Mesa Branch: master Commit: d882331f7ab2be567ce6641230e730ec74507222 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d882331f7ab2be567ce6641230e730ec74507222 Author: Jose Fonseca Date: Sat Jun 16 10:02:15 2018 +0100 appveyor: Consume LLVM 5.0.1. https://ci.appveyor.com/project/jrfonseca/mesa/build/47 Reviewed-by: Roland Scheidegger --- appveyor.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/appveyor.yml b/appveyor.yml index bd33e2e955..86440f0d76 100644 --- a/appveyor.yml +++ b/appveyor.yml @@ -35,13 +35,13 @@ clone_depth: 100 cache: - win_flex_bison-2.5.9.zip -- llvm-3.3.1-msvc2015-mtd.7z +- llvm-5.0.1-msvc2015-mtd.7z os: Visual Studio 2015 environment: WINFLEXBISON_ARCHIVE: win_flex_bison-2.5.9.zip - LLVM_ARCHIVE: llvm-3.3.1-msvc2015-mtd.7z + LLVM_ARCHIVE: llvm-5.0.1-msvc2015-mtd.7z install: # Check pip ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel/fs: New shuffle_for_32bit_write and shuffle_from_32bit_read
Module: Mesa
Branch: master
Commit: 22c654941b576785d2e009bf64aa20fea758de58
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=22c654941b576785d2e009bf64aa20fea758de58
Author: Jose Maria Casanova Crespo
Date: Sat Jun 9 11:45:22 2018 +0200
intel/fs: New shuffle_for_32bit_write and shuffle_from_32bit_read
These new shuffle functions deal with the shuffle/unshuffle operations
needed for read/write operations using 32-bit components when the
read/written components have a different bit-size (8, 16, 64-bits).
Shuffle from 32-bit to 32-bit becomes a simple MOV.
shuffle_src_to_dst takes care of doing a shuffle when source type is
smaller than destination type and an unshuffle when source type is
bigger than destination. So this new read/write functions just need
to call shuffle_src_to_dst assuming that writes use a 32-bit
destination and reads use a 32-bit source.
As shuffle_for_32bit_write/from_32bit_read components take components
in unit of source/destination types and shuffle_src_to_dst takes units
of the smallest type component, we adjust components and first_component
parameters.
To enable this new functions it is needed than there is no
source/destination overlap in the case of shuffle_from_32bit_read.
That never happens on shuffle_for_32bit_write as it allocates a new
destination register as it was at shuffle_64bit_data_for_32bit_write.
v2: Reword commit log and add comments to explain why first_component
and components parameters are adjusted. (Jason Ekstrand)
Reviewed-by: Jason Ekstrand
---
src/intel/compiler/brw_fs.h | 11 ++
src/intel/compiler/brw_fs_nir.cpp | 43 +++
2 files changed, 54 insertions(+)
diff --git a/src/intel/compiler/brw_fs.h b/src/intel/compiler/brw_fs.h
index faf5156863..779170ecc9 100644
--- a/src/intel/compiler/brw_fs.h
+++ b/src/intel/compiler/brw_fs.h
@@ -519,6 +519,17 @@ void shuffle_16bit_data_for_32bit_write(const
brw::fs_builder ,
const fs_reg ,
uint32_t components);
+void shuffle_from_32bit_read(const brw::fs_builder ,
+ const fs_reg ,
+ const fs_reg ,
+ uint32_t first_component,
+ uint32_t components);
+
+fs_reg shuffle_for_32bit_write(const brw::fs_builder ,
+ const fs_reg ,
+ uint32_t first_component,
+ uint32_t components);
+
fs_reg setup_imm_df(const brw::fs_builder ,
double v);
diff --git a/src/intel/compiler/brw_fs_nir.cpp
b/src/intel/compiler/brw_fs_nir.cpp
index d91faf135e..9a0de3ae92 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -5463,6 +5463,49 @@ shuffle_src_to_dst(const fs_builder ,
}
}
+void
+shuffle_from_32bit_read(const fs_builder ,
+const fs_reg ,
+const fs_reg ,
+uint32_t first_component,
+uint32_t components)
+{
+ assert(type_sz(src.type) == 4);
+
+ /* This function takes components in units of the destination type while
+* shuffle_src_to_dst takes components in units of the smallest type
+*/
+ if (type_sz(dst.type) > 4) {
+ assert(type_sz(dst.type) == 8);
+ first_component *= 2;
+ components *= 2;
+ }
+
+ shuffle_src_to_dst(bld, dst, src, first_component, components);
+}
+
+fs_reg
+shuffle_for_32bit_write(const fs_builder ,
+const fs_reg ,
+uint32_t first_component,
+uint32_t components)
+{
+ fs_reg dst = bld.vgrf(BRW_REGISTER_TYPE_D,
+ DIV_ROUND_UP (components * type_sz(src.type), 4));
+ /* This function takes components in units of the source type while
+* shuffle_src_to_dst takes components in units of the smallest type
+*/
+ if (type_sz(src.type) > 4) {
+ assert(type_sz(src.type) == 8);
+ first_component *= 2;
+ components *= 2;
+ }
+
+ shuffle_src_to_dst(bld, dst, src, first_component, components);
+
+ return dst;
+}
+
fs_reg
setup_imm_df(const fs_builder , double v)
{
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Mesa (master): intel/fs: shuffle_from_32bit_read at load_per_vertex_input at TCS/TES
Module: Mesa
Branch: master
Commit: 8003ae87f43f92fd74e29cba6c5fcd0739ce95db
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8003ae87f43f92fd74e29cba6c5fcd0739ce95db
Author: Jose Maria Casanova Crespo
Date: Sat Jun 9 11:46:07 2018 +0200
intel/fs: shuffle_from_32bit_read at load_per_vertex_input at TCS/TES
Previously, the shuffle function had a source/destination overlap that
needs to be avoided to use shuffle_from_32bit_read. As we can use for
the shuffle destination the destination of removed MOVs.
This change also avoids the internal MOVs done by the previous shuffle
to deal with possible overlaps.
Reviewed-by: Jason Ekstrand
---
src/intel/compiler/brw_fs_nir.cpp | 22 --
1 file changed, 8 insertions(+), 14 deletions(-)
diff --git a/src/intel/compiler/brw_fs_nir.cpp
b/src/intel/compiler/brw_fs_nir.cpp
index 7fdc9313d1..352d50e74d 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -2665,13 +2665,10 @@ fs_visitor::nir_emit_tcs_intrinsic(const fs_builder
,
* or SSBOs.
*/
if (type_sz(dst.type) == 8) {
-shuffle_32bit_load_result_to_64bit_data(
- bld, dst, retype(dst, BRW_REGISTER_TYPE_F), num_components);
-
-for (unsigned c = 0; c < num_components; c++) {
- bld.MOV(offset(orig_dst, bld, iter * 2 + c),
- offset(dst, bld, c));
-}
+shuffle_from_32bit_read(bld,
+offset(orig_dst, bld, iter * 2),
+retype(dst, BRW_REGISTER_TYPE_D),
+0, num_components);
}
/* Copy the temporary to the destination to deal with writemasking.
@@ -3014,13 +3011,10 @@ fs_visitor::nir_emit_tes_intrinsic(const fs_builder
,
* or SSBOs.
*/
if (type_sz(dest.type) == 8) {
- shuffle_32bit_load_result_to_64bit_data(
- bld, dest, retype(dest, BRW_REGISTER_TYPE_F),
num_components);
-
- for (unsigned c = 0; c < num_components; c++) {
- bld.MOV(offset(orig_dest, bld, iter * 2 + c),
- offset(dest, bld, c));
- }
+ shuffle_from_32bit_read(bld,
+ offset(orig_dest, bld, iter * 2),
+ retype(dest, BRW_REGISTER_TYPE_D),
+ 0, num_components);
}
/* If we are loading double data and we need a second read message
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Mesa (master): intel/fs: Remove old 16-bit shuffle/unshuffle functions
Module: Mesa
Branch: master
Commit: c2297bdf1927bdc1ef77730813930f96be9010d3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c2297bdf1927bdc1ef77730813930f96be9010d3
Author: Jose Maria Casanova Crespo
Date: Sat Jun 9 11:45:54 2018 +0200
intel/fs: Remove old 16-bit shuffle/unshuffle functions
Reviewed-by: Jason Ekstrand
---
src/intel/compiler/brw_fs.h | 11 ---
src/intel/compiler/brw_fs_nir.cpp | 62 ---
2 files changed, 73 deletions(-)
diff --git a/src/intel/compiler/brw_fs.h b/src/intel/compiler/brw_fs.h
index 779170ecc9..d72164ae0b 100644
--- a/src/intel/compiler/brw_fs.h
+++ b/src/intel/compiler/brw_fs.h
@@ -508,17 +508,6 @@ fs_reg shuffle_64bit_data_for_32bit_write(const
brw::fs_builder ,
const fs_reg ,
uint32_t components);
-void shuffle_32bit_load_result_to_16bit_data(const brw::fs_builder ,
- const fs_reg ,
- const fs_reg ,
- uint32_t first_component,
- uint32_t components);
-
-void shuffle_16bit_data_for_32bit_write(const brw::fs_builder ,
-const fs_reg ,
-const fs_reg ,
-uint32_t components);
-
void shuffle_from_32bit_read(const brw::fs_builder ,
const fs_reg ,
const fs_reg ,
diff --git a/src/intel/compiler/brw_fs_nir.cpp
b/src/intel/compiler/brw_fs_nir.cpp
index 96ebb236a4..01c560e59f 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -5263,40 +5263,6 @@ shuffle_32bit_load_result_to_64bit_data(const fs_builder
,
}
}
-void
-shuffle_32bit_load_result_to_16bit_data(const fs_builder ,
-const fs_reg ,
-const fs_reg ,
-uint32_t first_component,
-uint32_t components)
-{
- assert(type_sz(src.type) == 4);
- assert(type_sz(dst.type) == 2);
-
- /* A temporary is used to un-shuffle the 32-bit data of each component in
-* into a valid 16-bit vector. We can't write directly to dst because it
-* can be the same register as src and in that case the first MOV in the
-* loop below would overwrite the data read in the second MOV.
-*/
- fs_reg tmp = retype(bld.vgrf(src.type), dst.type);
-
- for (unsigned i = 0; i < components; i++) {
- const fs_reg component_i =
- subscript(offset(src, bld, (first_component + i) / 2), dst.type,
- (first_component + i) % 2);
-
- bld.MOV(offset(tmp, bld, i % 2), component_i);
-
- if (i % 2) {
- bld.MOV(offset(dst, bld, i -1), offset(tmp, bld, 0));
- bld.MOV(offset(dst, bld, i), offset(tmp, bld, 1));
- }
- }
- if (components % 2) {
- bld.MOV(offset(dst, bld, components - 1), tmp);
- }
-}
-
/**
* This helper does the inverse operation of
* SHUFFLE_32BIT_LOAD_RESULT_TO_64BIT_DATA.
@@ -5329,34 +5295,6 @@ shuffle_64bit_data_for_32bit_write(const fs_builder ,
return dst;
}
-void
-shuffle_16bit_data_for_32bit_write(const fs_builder ,
- const fs_reg ,
- const fs_reg ,
- uint32_t components)
-{
- assert(type_sz(src.type) == 2);
- assert(type_sz(dst.type) == 4);
-
- /* A temporary is used to shuffle the 16-bit data of each component in the
-* 32-bit data vector. We can't write directly to dst because it can be the
-* same register as src and in that case the first MOV in the loop below
-* would overwrite the data read in the second MOV.
-*/
- fs_reg tmp = bld.vgrf(dst.type);
-
- for (unsigned i = 0; i < components; i++) {
- const fs_reg component_i = offset(src, bld, i);
- bld.MOV(subscript(tmp, src.type, i % 2), component_i);
- if (i % 2) {
- bld.MOV(offset(dst, bld, i / 2), tmp);
- }
- }
- if (components % 2) {
- bld.MOV(offset(dst, bld, components / 2), tmp);
- }
-}
-
/*
* This helper takes a source register and un/shuffles it into the destination
* register.
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Mesa (master): intel/fs: Use shuffle_from_32bit_read for 64-bit FS load_input
Module: Mesa
Branch: master
Commit: 71b319a285f4fea50bb11dc477b551ff69d99c3f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=71b319a285f4fea50bb11dc477b551ff69d99c3f
Author: Jose Maria Casanova Crespo
Date: Sat Jun 9 11:46:11 2018 +0200
intel/fs: Use shuffle_from_32bit_read for 64-bit FS load_input
As the previous use of shuffle_32bit_load_result_to_64bit_data
had a source/destination overlap for 64-bit. Now a temporary destination
is used for 64-bit cases to use shuffle_from_32bit_read that doesn't
handle src/dst overlaps.
Reviewed-by: Jason Ekstrand
---
src/intel/compiler/brw_fs_nir.cpp | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/intel/compiler/brw_fs_nir.cpp
b/src/intel/compiler/brw_fs_nir.cpp
index 352d50e74d..e2cd63c4d8 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -3353,6 +3353,7 @@ fs_visitor::nir_emit_fs_intrinsic(const fs_builder ,
unsigned base = nir_intrinsic_base(instr);
unsigned comp = nir_intrinsic_component(instr);
unsigned num_components = instr->num_components;
+ fs_reg orig_dest = dest;
enum brw_reg_type type = dest.type;
/* Special case fields in the VUE header */
@@ -3368,6 +3369,7 @@ fs_visitor::nir_emit_fs_intrinsic(const fs_builder ,
*/
type = BRW_REGISTER_TYPE_F;
num_components *= 2;
+ dest = bld.vgrf(type, num_components);
}
for (unsigned int i = 0; i < num_components; i++) {
@@ -3376,10 +3378,8 @@ fs_visitor::nir_emit_fs_intrinsic(const fs_builder ,
}
if (nir_dest_bit_size(instr->dest) == 64) {
- shuffle_32bit_load_result_to_64bit_data(bld,
- dest,
- retype(dest, type),
- instr->num_components);
+ shuffle_from_32bit_read(bld, orig_dest, dest, 0,
+ instr->num_components);
}
break;
}
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Mesa (master): intel/fs: shuffle_from_32bit_read for 64-bit do_untyped_vector_read
Module: Mesa
Branch: master
Commit: 8b26a2d96d5806d698f827d5521cf75504dc3a85
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8b26a2d96d5806d698f827d5521cf75504dc3a85
Author: Jose Maria Casanova Crespo
Date: Sat Jun 9 11:45:57 2018 +0200
intel/fs: shuffle_from_32bit_read for 64-bit do_untyped_vector_read
do_untyped_vector_read is used at load_ssbo and load_shared.
The previous MOVs are removed because shuffle_from_32bit_read
can handle storing the shuffle results in the expected destination
just using the proper offset.
Reviewed-by: Jason Ekstrand
---
src/intel/compiler/brw_fs_nir.cpp | 12 ++--
1 file changed, 2 insertions(+), 10 deletions(-)
diff --git a/src/intel/compiler/brw_fs_nir.cpp
b/src/intel/compiler/brw_fs_nir.cpp
index 01c560e59f..81c26321ed 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -2434,16 +2434,8 @@ do_untyped_vector_read(const fs_builder ,
BRW_PREDICATE_NONE);
/* Shuffle the 32-bit load result into valid 64-bit data */
- const fs_reg packed_result = bld.vgrf(dest.type, iter_components);
- shuffle_32bit_load_result_to_64bit_data(
-bld, packed_result, read_result, iter_components);
-
- /* Move each component to its destination */
- read_result = retype(read_result, BRW_REGISTER_TYPE_DF);
- for (int c = 0; c < iter_components; c++) {
-bld.MOV(offset(dest, bld, it * 2 + c),
-offset(packed_result, bld, c));
- }
+ shuffle_from_32bit_read(bld, offset(dest, bld, it * 2),
+ read_result, 0, iter_components);
bld.ADD(read_offset, read_offset, brw_imm_ud(16));
}
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Mesa (master): intel/fs: shuffle_32bit_load_result_to_64bit_data is not used anymore
Module: Mesa
Branch: master
Commit: a4d445b93cc7e50699faa922110d35ff5e31bbb5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a4d445b93cc7e50699faa922110d35ff5e31bbb5
Author: Jose Maria Casanova Crespo
Date: Sat Jun 9 11:46:14 2018 +0200
intel/fs: shuffle_32bit_load_result_to_64bit_data is not used anymore
Reviewed-by: Jason Ekstrand
---
src/intel/compiler/brw_fs.h | 5
src/intel/compiler/brw_fs_nir.cpp | 53 ---
2 files changed, 58 deletions(-)
diff --git a/src/intel/compiler/brw_fs.h b/src/intel/compiler/brw_fs.h
index d72164ae0b..1f86f17ccb 100644
--- a/src/intel/compiler/brw_fs.h
+++ b/src/intel/compiler/brw_fs.h
@@ -499,11 +499,6 @@ private:
void *mem_ctx;
};
-void shuffle_32bit_load_result_to_64bit_data(const brw::fs_builder ,
- const fs_reg ,
- const fs_reg ,
- uint32_t components);
-
fs_reg shuffle_64bit_data_for_32bit_write(const brw::fs_builder ,
const fs_reg ,
uint32_t components);
diff --git a/src/intel/compiler/brw_fs_nir.cpp
b/src/intel/compiler/brw_fs_nir.cpp
index e2cd63c4d8..a55d8ef475 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -5192,59 +5192,6 @@ fs_visitor::nir_emit_jump(const fs_builder ,
nir_jump_instr *instr)
}
/**
- * This helper takes the result of a load operation that reads 32-bit elements
- * in this format:
- *
- * x x x x x x x x
- * y y y y y y y y
- * z z z z z z z z
- * w w w w w w w w
- *
- * and shuffles the data to get this:
- *
- * x y x y x y x y
- * x y x y x y x y
- * z w z w z w z w
- * z w z w z w z w
- *
- * Which is exactly what we want if the load is reading 64-bit components
- * like doubles, where x represents the low 32-bit of the x double component
- * and y represents the high 32-bit of the x double component (likewise with
- * z and w for double component y). The parameter @components represents
- * the number of 64-bit components present in @src. This would typically be
- * 2 at most, since we can only fit 2 double elements in the result of a
- * vec4 load.
- *
- * Notice that @dst and @src can be the same register.
- */
-void
-shuffle_32bit_load_result_to_64bit_data(const fs_builder ,
-const fs_reg ,
-const fs_reg ,
-uint32_t components)
-{
- assert(type_sz(src.type) == 4);
- assert(type_sz(dst.type) == 8);
-
- /* A temporary that we will use to shuffle the 32-bit data of each
-* component in the vector into valid 64-bit data. We can't write directly
-* to dst because dst can be (and would usually be) the same as src
-* and in that case the first MOV in the loop below would overwrite the
-* data read in the second MOV.
-*/
- fs_reg tmp = bld.vgrf(dst.type);
-
- for (unsigned i = 0; i < components; i++) {
- const fs_reg component_i = offset(src, bld, 2 * i);
-
- bld.MOV(subscript(tmp, src.type, 0), component_i);
- bld.MOV(subscript(tmp, src.type, 1), offset(component_i, bld, 1));
-
- bld.MOV(offset(dst, bld, i), tmp);
- }
-}
-
-/**
* This helper does the inverse operation of
* SHUFFLE_32BIT_LOAD_RESULT_TO_64BIT_DATA.
*
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Mesa (master): intel/fs: Use shuffle_from_32bit_read at VARYING_PULL_CONSTANT_LOAD
Module: Mesa
Branch: master
Commit: a0891eabca558b53b630ef5674d16c1c2112aaef
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a0891eabca558b53b630ef5674d16c1c2112aaef
Author: Jose Maria Casanova Crespo
Date: Sat Jun 9 11:45:42 2018 +0200
intel/fs: Use shuffle_from_32bit_read at VARYING_PULL_CONSTANT_LOAD
shuffle_from_32bit_read can manage the shuffle/unshuffle needed
for different 8/16/32/64 bit-sizes at VARYING PULL CONSTANT LOAD.
To get the specific component the first_component parameter is used.
In the case of the previous 16-bit shuffle, the shuffle operation was
generating not needed MOVs where its results where never used. This
behaviour passed unnoticed on SIMD16 because dead_code_eliminate
pass removed the generated instructions but for SIMD8 they cound't be
removed because of being partial writes.
Reviewed-by: Jason Ekstrand
---
src/intel/compiler/brw_fs.cpp | 17 ++---
1 file changed, 2 insertions(+), 15 deletions(-)
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index d836b26862..5c95e260aa 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -191,21 +191,8 @@ fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder
,
vec4_result, surf_index, vec4_offset);
inst->size_written = 4 * vec4_result.component_size(inst->exec_size);
- fs_reg dw = offset(vec4_result, bld, (const_offset & 0xf) / 4);
- switch (type_sz(dst.type)) {
- case 2:
- shuffle_32bit_load_result_to_16bit_data(bld, dst, dw, 0, 1);
- bld.MOV(dst, subscript(dw, dst.type, (const_offset / 2) & 1));
- break;
- case 4:
- bld.MOV(dst, retype(dw, dst.type));
- break;
- case 8:
- shuffle_32bit_load_result_to_64bit_data(bld, dst, dw, 1);
- break;
- default:
- unreachable("Unsupported bit_size");
- }
+ shuffle_from_32bit_read(bld, dst, vec4_result,
+ (const_offset & 0xf) / type_sz(dst.type), 1);
}
/**
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Mesa (master): intel/fs: Use shuffle_for_32bit_write for 16-bits store_ssbo
Module: Mesa Branch: master Commit: fd3d8a8f796f9a15796b1c2f680dfac4bddb5c7e URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=fd3d8a8f796f9a15796b1c2f680dfac4bddb5c7e Author: Jose Maria Casanova Crespo Date: Sat Jun 9 11:45:50 2018 +0200 intel/fs: Use shuffle_for_32bit_write for 16-bits store_ssbo Reviewed-by: Jason Ekstrand --- src/intel/compiler/brw_fs_nir.cpp | 7 ++- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 5cad31b32d..96ebb236a4 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -4297,11 +4297,8 @@ fs_visitor::nir_emit_intrinsic(const fs_builder , nir_intrinsic_instr *instr * aligned. Shuffling only one component would be the same as * striding it. */ -fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_D, - DIV_ROUND_UP(num_components, 2)); -shuffle_16bit_data_for_32bit_write(bld, tmp, write_src, - num_components); -write_src = tmp; +write_src = shuffle_for_32bit_write(bld, write_src, 0, +num_components); } fs_reg offset_reg; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel/fs: Use shuffle_from_32bit_read at VS load_input
Module: Mesa
Branch: master
Commit: 5565630f8542544a8be550f0b52751cfa724a84e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5565630f8542544a8be550f0b52751cfa724a84e
Author: Jose Maria Casanova Crespo
Date: Sat Jun 9 11:46:04 2018 +0200
intel/fs: Use shuffle_from_32bit_read at VS load_input
shuffle_from_32bit_read manages 32-bit reads to 32-bit destination
in the same way that the previous loop so now we just call the new
function for all bitsizes, simplifying also the 64-bit load_input.
v2: Add comment about future 16-bit support (Jason Ekstrand)
Reviewed-by: Jason Ekstrand
---
src/intel/compiler/brw_fs_nir.cpp | 15 +--
1 file changed, 5 insertions(+), 10 deletions(-)
diff --git a/src/intel/compiler/brw_fs_nir.cpp
b/src/intel/compiler/brw_fs_nir.cpp
index f45e123cc1..7fdc9313d1 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -2483,16 +2483,11 @@ fs_visitor::nir_emit_vs_intrinsic(const fs_builder ,
if (type_sz(dest.type) == 8)
first_component /= 2;
- for (unsigned j = 0; j < num_components; j++) {
- bld.MOV(offset(dest, bld, j), offset(src, bld, j + first_component));
- }
-
- if (type_sz(dest.type) == 8) {
- shuffle_32bit_load_result_to_64bit_data(bld,
- dest,
- retype(dest,
BRW_REGISTER_TYPE_F),
- instr->num_components);
- }
+ /* For 16-bit support maybe a temporary will be needed to copy from
+ * the ATTR file.
+ */
+ shuffle_from_32bit_read(bld, dest, retype(src, BRW_REGISTER_TYPE_D),
+ first_component, num_components);
break;
}
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Mesa (master): intel/fs: Use new shuffle_32bit_write for all 64-bit storage writes
Module: Mesa
Branch: master
Commit: a4965842d6847ad1b358d9136ba50cb04f29042b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a4965842d6847ad1b358d9136ba50cb04f29042b
Author: Jose Maria Casanova Crespo
Date: Sat Jun 9 11:46:17 2018 +0200
intel/fs: Use new shuffle_32bit_write for all 64-bit storage writes
Reviewed-by: Jason Ekstrand
---
src/intel/compiler/brw_fs_nir.cpp | 13 ++---
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/src/intel/compiler/brw_fs_nir.cpp
b/src/intel/compiler/brw_fs_nir.cpp
index a55d8ef475..d7a0b7d684 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -2842,8 +2842,7 @@ fs_visitor::nir_emit_tcs_intrinsic(const fs_builder ,
* for that.
*/
unsigned channel = iter * 2 + i;
- fs_reg dest = shuffle_64bit_data_for_32bit_write(bld,
- offset(value, bld, channel), 1);
+ fs_reg dest = shuffle_for_32bit_write(bld, value, channel, 1);
srcs[header_regs + (i + first_component) * 2] = dest;
srcs[header_regs + (i + first_component) * 2 + 1] =
@@ -3697,8 +3696,8 @@ fs_visitor::nir_emit_cs_intrinsic(const fs_builder ,
unsigned type_size = 4;
if (nir_src_bit_size(instr->src[0]) == 64) {
type_size = 8;
- val_reg = shuffle_64bit_data_for_32bit_write(bld,
-val_reg, instr->num_components);
+ val_reg = shuffle_for_32bit_write(bld, val_reg, 0,
+ instr->num_components);
}
unsigned type_slots = type_size / 4;
@@ -4239,8 +4238,8 @@ fs_visitor::nir_emit_intrinsic(const fs_builder ,
nir_intrinsic_instr *instr
* iteration handle the rest.
*/
num_components = MIN2(2, num_components);
-write_src = shuffle_64bit_data_for_32bit_write(bld, write_src,
- num_components);
+write_src = shuffle_for_32bit_write(bld, write_src, 0,
+num_components);
} else if (type_size < 4) {
assert(type_size == 2);
/* For 16-bit types we pack two consecutive values into a 32-bit
@@ -4336,7 +4335,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder ,
nir_intrinsic_instr *instr
unsigned num_components = instr->num_components;
unsigned first_component = nir_intrinsic_component(instr);
if (nir_src_bit_size(instr->src[0]) == 64) {
- src = shuffle_64bit_data_for_32bit_write(bld, src, num_components);
+ src = shuffle_for_32bit_write(bld, src, 0, num_components);
num_components *= 2;
}
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Mesa (master): intel/fs: shuffle_64bit_data_for_32bit_write is not used anymore
Module: Mesa
Branch: master
Commit: b8e099e7d5c8a7165b89da81ff9d5efa45139902
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b8e099e7d5c8a7165b89da81ff9d5efa45139902
Author: Jose Maria Casanova Crespo
Date: Sat Jun 9 11:46:34 2018 +0200
intel/fs: shuffle_64bit_data_for_32bit_write is not used anymore
Reviewed-by: Jason Ekstrand
---
src/intel/compiler/brw_fs.h | 4
src/intel/compiler/brw_fs_nir.cpp | 32
2 files changed, 36 deletions(-)
diff --git a/src/intel/compiler/brw_fs.h b/src/intel/compiler/brw_fs.h
index 1f86f17ccb..17b1368d52 100644
--- a/src/intel/compiler/brw_fs.h
+++ b/src/intel/compiler/brw_fs.h
@@ -499,10 +499,6 @@ private:
void *mem_ctx;
};
-fs_reg shuffle_64bit_data_for_32bit_write(const brw::fs_builder ,
- const fs_reg ,
- uint32_t components);
-
void shuffle_from_32bit_read(const brw::fs_builder ,
const fs_reg ,
const fs_reg ,
diff --git a/src/intel/compiler/brw_fs_nir.cpp
b/src/intel/compiler/brw_fs_nir.cpp
index d7a0b7d684..0abb4798e7 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -5190,38 +5190,6 @@ fs_visitor::nir_emit_jump(const fs_builder ,
nir_jump_instr *instr)
}
}
-/**
- * This helper does the inverse operation of
- * SHUFFLE_32BIT_LOAD_RESULT_TO_64BIT_DATA.
- *
- * We need to do this when we are going to use untyped write messsages that
- * operate with 32-bit components in order to arrange our 64-bit data to be
- * in the expected layout.
- *
- * Notice that callers of this function, unlike in the case of the inverse
- * operation, would typically need to call this with dst and src being
- * different registers, since they would otherwise corrupt the original
- * 64-bit data they are about to write. Because of this the function checks
- * that the src and dst regions involved in the operation do not overlap.
- */
-fs_reg
-shuffle_64bit_data_for_32bit_write(const fs_builder ,
- const fs_reg ,
- uint32_t components)
-{
- assert(type_sz(src.type) == 8);
-
- fs_reg dst = bld.vgrf(BRW_REGISTER_TYPE_D, 2 * components);
-
- for (unsigned i = 0; i < components; i++) {
- const fs_reg component_i = offset(src, bld, i);
- bld.MOV(offset(dst, bld, 2 * i), subscript(component_i, dst.type, 0));
- bld.MOV(offset(dst, bld, 2 * i + 1), subscript(component_i, dst.type,
1));
- }
-
- return dst;
-}
-
/*
* This helper takes a source register and un/shuffles it into the destination
* register.
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Mesa (master): intel/fs: Use shuffle_from_32bit_read for 64-bit gs_input_load
Module: Mesa
Branch: master
Commit: 152bffb69bdb13e63a9112ddab78dc86855d9687
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=152bffb69bdb13e63a9112ddab78dc86855d9687
Author: Jose Maria Casanova Crespo
Date: Sat Jun 9 11:46:01 2018 +0200
intel/fs: Use shuffle_from_32bit_read for 64-bit gs_input_load
This implementation avoids two unneeded MOVs for each 64-bit
component. One was done in the old shuffle, to avoid cases of
src/dst overlap but this is not the case. And the removed MOV
was already being being done in the shuffle.
Copy propagation wasn't able to remove them because shuffle
destination values are defined with partial writes because they
have stride == 2.
v2: Reword commit log summary (Jason Ekstrand)
Reviewed-by: Jason Ekstrand
---
src/intel/compiler/brw_fs_nir.cpp | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/src/intel/compiler/brw_fs_nir.cpp
b/src/intel/compiler/brw_fs_nir.cpp
index 81c26321ed..f45e123cc1 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -2305,11 +2305,11 @@ fs_visitor::emit_gs_input_load(const fs_reg ,
}
if (type_sz(dst.type) == 8) {
- shuffle_32bit_load_result_to_64bit_data(
-bld, tmp_dst, retype(tmp_dst, BRW_REGISTER_TYPE_F),
num_components);
-
- for (unsigned c = 0; c < num_components; c++)
-bld.MOV(offset(dst, bld, iter * 2 + c), offset(tmp_dst, bld, c));
+ shuffle_from_32bit_read(bld,
+ offset(dst, bld, iter * 2),
+ retype(tmp_dst, BRW_REGISTER_TYPE_D),
+ 0,
+ num_components);
}
if (num_iterations > 1) {
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Mesa (master): intel/fs: general 8/16/32/64-bit shuffle_src_to_dst function
Module: Mesa
Branch: master
Commit: a5665056e55fbdc9fc493fcaa9787406561fb4b1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a5665056e55fbdc9fc493fcaa9787406561fb4b1
Author: Jose Maria Casanova Crespo
Date: Sat Jun 9 11:45:01 2018 +0200
intel/fs: general 8/16/32/64-bit shuffle_src_to_dst function
This new function takes care of shuffle/unshuffle components of a
particular bit-size in components with a different bit-size.
If source type size is smaller than destination type size the operation
needed is a component shuffle. The opposite case would be an unshuffle.
Component units are measured in terms of the smaller type between
source and destination. As we are un/shuffling the smaller components
from/into a bigger one.
The operation allows to skip first_component number of components from
the source.
Shuffle MOVs are retyped using integer types avoiding problems with
denorms and float types if source and destination bitsize is different.
This allows to simplify uses of shuffle functions that are dealing with
these retypes individually.
Now there is a new restriction so source and destination can not overlap
anymore when calling this shuffle function. Following patches that migrate
to use this new function will take care individually of avoiding source
and destination overlaps.
v2: (Jason Ekstrand)
- Rewrite overlap asserts.
- Manage type_sz(src.type) == type_sz(dst.type) case using MOVs
from source to dest. This works for 64-bit to 64-bits
operation that on Gen7 as it doesn't support Q registers.
- Explain that components units are based in the smallest type.
v3: - Fix unshuffle overlap assert (Jason Ekstrand)
Reviewed-by: Jason Ekstrand
---
src/intel/compiler/brw_fs_nir.cpp | 101 ++
1 file changed, 101 insertions(+)
diff --git a/src/intel/compiler/brw_fs_nir.cpp
b/src/intel/compiler/brw_fs_nir.cpp
index 166da0aa6d..d91faf135e 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -5362,6 +5362,107 @@ shuffle_16bit_data_for_32bit_write(const fs_builder
,
}
}
+/*
+ * This helper takes a source register and un/shuffles it into the destination
+ * register.
+ *
+ * If source type size is smaller than destination type size the operation
+ * needed is a component shuffle. The opposite case would be an unshuffle. If
+ * source/destination type size is equal a shuffle is done that would be
+ * equivalent to a simple MOV.
+ *
+ * For example, if source is a 16-bit type and destination is 32-bit. A 3
+ * components .xyz 16-bit vector on SIMD8 would be.
+ *
+ *|x1|x2|x3|x4|x5|x6|x7|x8|y1|y2|y3|y4|y5|y6|y7|y8|
+ *|z1|z2|z3|z4|z5|z6|z7|z8| | | | | | | | |
+ *
+ * This helper will return the following 2 32-bit components with the 16-bit
+ * values shuffled:
+ *
+ *|x1 y1|x2 y2|x3 y3|x4 y4|x5 y5|x6 y6|x7 y7|x8 y8|
+ *|z1 |z2 |z3 |z4 |z5 |z6 |z7 |z8 |
+ *
+ * For unshuffle, the example would be the opposite, a 64-bit type source
+ * and a 32-bit destination. A 2 component .xy 64-bit vector on SIMD8
+ * would be:
+ *
+ *| x1l x1h | x2l x2h | x3l x3h | x4l x4h |
+ *| x5l x5h | x6l x6h | x7l x7h | x8l x8h |
+ *| y1l y1h | y2l y2h | y3l y3h | y4l y4h |
+ *| y5l y5h | y6l y6h | y7l y7h | y8l y8h |
+ *
+ * The returned result would be the following 4 32-bit components unshuffled:
+ *
+ *| x1l | x2l | x3l | x4l | x5l | x6l | x7l | x8l |
+ *| x1h | x2h | x3h | x4h | x5h | x6h | x7h | x8h |
+ *| y1l | y2l | y3l | y4l | y5l | y6l | y7l | y8l |
+ *| y1h | y2h | y3h | y4h | y5h | y6h | y7h | y8h |
+ *
+ * - Source and destination register must not be overlapped.
+ * - components units are measured in terms of the smaller type between
+ * source and destination because we are un/shuffling the smaller
+ * components from/into the bigger ones.
+ * - first_component parameter allows skipping source components.
+ */
+void
+shuffle_src_to_dst(const fs_builder ,
+ const fs_reg ,
+ const fs_reg ,
+ uint32_t first_component,
+ uint32_t components)
+{
+ if (type_sz(src.type) == type_sz(dst.type)) {
+ assert(!regions_overlap(dst,
+ type_sz(dst.type) * bld.dispatch_width() * components,
+ offset(src, bld, first_component),
+ type_sz(src.type) * bld.dispatch_width() * components));
+ for (unsigned i = 0; i < components; i++) {
+ bld.MOV(retype(offset(dst, bld, i), src.type),
+ offset(src, bld, i + first_component));
+ }
+ } else if (type_sz(src.type) < type_sz(dst.type)) {
+ /* Source is shuffled into destination */
+ unsigned size_ratio = type_sz(dst.type) / type_sz(src.type);
+ assert(!regions_overlap(dst,
+ type_sz(dst.type) * bld.dispatch_width() *
+ DIV_ROUND_UP(components, size_ratio),
+ offset(src, bld, first_component),
+
Mesa (master): intel/fs: Use shuffle_from_32bit_read to read 16-bit SSBO
Module: Mesa
Branch: master
Commit: 20e4732f7de89ebec9dfe50902cb12d508d69f78
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=20e4732f7de89ebec9dfe50902cb12d508d69f78
Author: Jose Maria Casanova Crespo
Date: Sat Jun 9 11:45:47 2018 +0200
intel/fs: Use shuffle_from_32bit_read to read 16-bit SSBO
Using shuffle_from_32bit_read instead of 16-bit shuffle functions
avoids the need of retype. At the same time new function are
ready for 8-bit type SSBO reads.
Reviewed-by: Jason Ekstrand
---
src/intel/compiler/brw_fs_nir.cpp | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/src/intel/compiler/brw_fs_nir.cpp
b/src/intel/compiler/brw_fs_nir.cpp
index 9a0de3ae92..5cad31b32d 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -2372,10 +2372,8 @@ do_untyped_vector_read(const fs_builder ,
1 /* dims */,
num_components_32bit,
BRW_PREDICATE_NONE);
- shuffle_32bit_load_result_to_16bit_data(bld,
- retype(dest, BRW_REGISTER_TYPE_W),
- retype(read_result, BRW_REGISTER_TYPE_D),
- first_component, num_components);
+ shuffle_from_32bit_read(bld, dest, read_result, first_component,
+ num_components);
} else {
fs_reg read_offset = bld.vgrf(BRW_REGISTER_TYPE_UD);
for (unsigned i = 0; i < num_components; i++) {
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