Mesa (main): android: nir: add nir_lower_fragcolor.c to Makefile.sources

2021-05-09 Thread GitLab Mirror 
Module: Mesa
Branch: main
Commit: 2736ae0454d574a1909863d7870fa4f1fe91bd7d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2736ae0454d574a1909863d7870fa4f1fe91bd7d

Author: Mauro Rossi 
Date:   Sat May  8 12:42:10 2021 +0200

android: nir: add nir_lower_fragcolor.c to Makefile.sources

Fixes the following building error:

FAILED: 
out/target/product/x86_64/obj/SHARED_LIBRARIES/gallium_dri_intermediates/LINKED/gallium_dri.so
...
ld.lld: error: undefined symbol: nir_lower_fragcolor
>>> referenced by pan_assemble.c:81 
>>> (external/mesa/src/gallium/drivers/panfrost/pan_assemble.c:81)

Cc: 21.0 21.1 
Fixes: 1fd356302590 ("nir: add lowering pass for fragcolor -> fragdata")
Acked-by: Rob Clark 
Part-of: 

---

 src/compiler/Makefile.sources | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/compiler/Makefile.sources b/src/compiler/Makefile.sources
index d6bfa32c701..cb09d123c22 100644
--- a/src/compiler/Makefile.sources
+++ b/src/compiler/Makefile.sources
@@ -260,6 +260,7 @@ NIR_FILES = \
nir/nir_lower_fb_read.c \
nir/nir_lower_flatshade.c \
nir/nir_lower_flrp.c \
+   nir/nir_lower_fragcolor.c \
nir/nir_lower_fragcoord_wtrans.c \
nir/nir_lower_frexp.c \
nir/nir_lower_global_vars_to_local.c \

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Mesa (staging/21.0): radeonsi: check that surface->alignment is != 0

2021-05-09 Thread GitLab Mirror 
Module: Mesa
Branch: staging/21.0
Commit: 3e3e6cf759aef66dedef5f8ef2a57b51d6d886db
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3e3e6cf759aef66dedef5f8ef2a57b51d6d886db

Author: Pierre-Eric Pelloux-Prayer 
Date:   Fri May  7 09:26:29 2021 +0200

radeonsi: check that surface->alignment is != 0

This is a workaround for issue 4605: alignment should always be
at least 256 but in this specific case it seems to be 0.

Skip the check in this case to "fix" the regression.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4605
Part-of: 

---

 src/amd/common/ac_surface.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index e534c16b69d..f010e76d071 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -2878,7 +2878,7 @@ bool ac_surface_override_offset_stride(const struct 
radeon_info *info, struct ra
   }
}
 
-   if (offset & (surf->alignment - 1) ||
+   if ((surf->alignment && offset & (surf->alignment - 1)) ||
offset >= UINT64_MAX - surf->total_size)
   return false;
 

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Mesa (main): zink: handle in-renderpass clears in fb_clears_apply_internal()

2021-05-09 Thread GitLab Mirror 
Module: Mesa
Branch: main
Commit: 94aeb1041f8c8a80d06bbbecedc5890954da311a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=94aeb1041f8c8a80d06bbbecedc5890954da311a

Author: Mike Blumenkrantz 
Date:   Wed Apr  7 14:02:54 2021 -0400

zink: handle in-renderpass clears in fb_clears_apply_internal()

this isn't used yet, but it may as well be handled in case that changes

Reviewed-by: Dave Airlie 
Part-of: 

---

 src/gallium/drivers/zink/zink_clear.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/zink/zink_clear.c 
b/src/gallium/drivers/zink/zink_clear.c
index 96f5aaf7b91..ff932b2ca78 100644
--- a/src/gallium/drivers/zink/zink_clear.c
+++ b/src/gallium/drivers/zink/zink_clear.c
@@ -492,8 +492,9 @@ fb_clears_apply_internal(struct zink_context *ctx, struct 
pipe_resource *pres, i
 
if (!zink_fb_clear_enabled(ctx, i))
   return;
-   if (zink_resource(pres)->aspect == VK_IMAGE_ASPECT_COLOR_BIT) {
-  assert(!ctx->batch.in_rp);
+   if (ctx->batch.in_rp)
+  zink_clear_framebuffer(ctx, BITFIELD_BIT(i));
+   else if (zink_resource(pres)->aspect == VK_IMAGE_ASPECT_COLOR_BIT) {
   if (zink_fb_clear_needs_explicit(fb_clear) || 
!check_3d_layers(ctx->fb_state.cbufs[i]))
  /* this will automatically trigger all the clears */
  zink_batch_rp(ctx);
@@ -510,7 +511,6 @@ fb_clears_apply_internal(struct zink_context *ctx, struct 
pipe_resource *pres, i
   zink_fb_clear_reset(ctx, i);
   return;
} else {
-  assert(!ctx->batch.in_rp);
   if (zink_fb_clear_needs_explicit(fb_clear) || 
!check_3d_layers(ctx->fb_state.zsbuf))
  /* this will automatically trigger all the clears */
  zink_batch_rp(ctx);

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Mesa (main): zink: break zs clear loop once both bits are set when beginning renderpass

2021-05-09 Thread GitLab Mirror 
Module: Mesa
Branch: main
Commit: 5ac6c70214dc664238cc1fefcd42d5b2f0b3b30d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5ac6c70214dc664238cc1fefcd42d5b2f0b3b30d

Author: Mike Blumenkrantz 
Date:   Thu Apr  8 13:42:46 2021 -0400

zink: break zs clear loop once both bits are set when beginning renderpass

no point in looping this any more than we have to

Reviewed-by: Dave Airlie 
Part-of: 

---

 src/gallium/drivers/zink/zink_context.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/zink/zink_context.c 
b/src/gallium/drivers/zink/zink_context.c
index 6da5d1b3dd0..899761814c0 100644
--- a/src/gallium/drivers/zink/zink_context.c
+++ b/src/gallium/drivers/zink/zink_context.c
@@ -1188,7 +1188,9 @@ zink_begin_render_pass(struct zink_context *ctx, struct 
zink_batch *batch)
  assert(ctx->framebuffer->rp->state.clears);
   }
   if (zink_fb_clear_needs_explicit(fb_clear)) {
- for (int j = !zink_fb_clear_element_needs_explicit(clear); j < 
zink_fb_clear_count(fb_clear); j++)
+ for (int j = !zink_fb_clear_element_needs_explicit(clear);
+  (clear_buffers & PIPE_CLEAR_DEPTHSTENCIL) != 
PIPE_CLEAR_DEPTHSTENCIL && j < zink_fb_clear_count(fb_clear);
+  j++)
 clear_buffers |= zink_fb_clear_element(fb_clear, j)->zs.bits;
   }
}

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Mesa (main): zink: add debug assert to verify that zink_clear_framebuffer() is accurate

2021-05-09 Thread GitLab Mirror 
Module: Mesa
Branch: main
Commit: b0c51cdc9eaef781ce03e3086219fa5b2fd9eac4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b0c51cdc9eaef781ce03e3086219fa5b2fd9eac4

Author: Mike Blumenkrantz 
Date:   Thu Apr  8 13:47:12 2021 -0400

zink: add debug assert to verify that zink_clear_framebuffer() is accurate

this should never be called for buffers that don't have pending clears

Reviewed-by: Dave Airlie 
Part-of: 

---

 src/gallium/drivers/zink/zink_clear.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/src/gallium/drivers/zink/zink_clear.c 
b/src/gallium/drivers/zink/zink_clear.c
index ff932b2ca78..11b048604d7 100644
--- a/src/gallium/drivers/zink/zink_clear.c
+++ b/src/gallium/drivers/zink/zink_clear.c
@@ -252,6 +252,12 @@ zink_clear_framebuffer(struct zink_context *ctx, unsigned 
clear_buffers)
 {
unsigned to_clear = 0;
struct pipe_framebuffer_state *fb_state = >fb_state;
+#ifndef NDEBUG
+   assert(!(clear_buffers & PIPE_CLEAR_DEPTHSTENCIL) || 
zink_fb_clear_enabled(ctx, PIPE_MAX_COLOR_BUFS));
+   for (int i = 0; i < fb_state->nr_cbufs && clear_buffers >= 
PIPE_CLEAR_COLOR0; i++) {
+  assert(!(clear_buffers & (PIPE_CLEAR_COLOR0 << i)) || 
zink_fb_clear_enabled(ctx, i));
+   }
+#endif
while (clear_buffers) {
   struct zink_framebuffer_clear *color_clear = NULL;
   struct zink_framebuffer_clear *zs_clear = NULL;

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Mesa (main): asahi: Implement set_blend_color

2021-05-09 Thread GitLab Mirror 
Module: Mesa
Branch: main
Commit: 30d1223247fc76ac976a47e83a9cf28d3ba42383
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=30d1223247fc76ac976a47e83a9cf28d3ba42383

Author: Alyssa Rosenzweig 
Date:   Tue May  4 22:29:18 2021 -0400

asahi: Implement set_blend_color

Signed-off-by: Alyssa Rosenzweig 
Part-of: 

---

 src/gallium/drivers/asahi/agx_state.c | 6 +-
 src/gallium/drivers/asahi/agx_state.h | 1 +
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/asahi/agx_state.c 
b/src/gallium/drivers/asahi/agx_state.c
index e7cde23ea61..38f5d7b7f40 100644
--- a/src/gallium/drivers/asahi/agx_state.c
+++ b/src/gallium/drivers/asahi/agx_state.c
@@ -43,9 +43,13 @@
 #include "asahi/lib/agx_formats.h"
 
 static void
-agx_set_blend_color(struct pipe_context *ctx,
+agx_set_blend_color(struct pipe_context *pctx,
 const struct pipe_blend_color *state)
 {
+   struct agx_context *ctx = agx_context(pctx);
+
+   if (state)
+  memcpy(>blend_color, state, sizeof(*state));
 }
 
 static void *
diff --git a/src/gallium/drivers/asahi/agx_state.h 
b/src/gallium/drivers/asahi/agx_state.h
index a8d0aebcc10..47eacf36e54 100644
--- a/src/gallium/drivers/asahi/agx_state.h
+++ b/src/gallium/drivers/asahi/agx_state.h
@@ -131,6 +131,7 @@ struct agx_context {
struct agx_rasterizer *rast;
struct agx_zsa zs;
struct agx_blend *blend;
+   struct pipe_blend_color blend_color;
 
uint8_t viewport[AGX_VIEWPORT_LENGTH];
uint8_t render_target[8][AGX_RENDER_TARGET_LENGTH];

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Mesa (main): agx: Condition writeout ops on already being emitted

2021-05-09 Thread GitLab Mirror 
Module: Mesa
Branch: main
Commit: 1b9b2f90464687f57d48395ac3af0a69d4311b5b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1b9b2f90464687f57d48395ac3af0a69d4311b5b

Author: Alyssa Rosenzweig 
Date:   Sun May  9 21:01:34 2021 -0400

agx: Condition writeout ops on already being emitted

There's a lot of r/e waiting here, but will be needed for ld_tile. Match
the Metal blob.

Signed-off-by: Alyssa Rosenzweig 
Part-of: 

---

 src/asahi/compiler/agx_compile.c  | 9 +++--
 src/asahi/compiler/agx_compiler.h | 3 +++
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/src/asahi/compiler/agx_compile.c b/src/asahi/compiler/agx_compile.c
index b344ecce532..f4b6d059524 100644
--- a/src/asahi/compiler/agx_compile.c
+++ b/src/asahi/compiler/agx_compile.c
@@ -172,9 +172,14 @@ agx_emit_fragment_out(agx_builder *b, nir_intrinsic_instr 
*instr)
unsigned rt = (loc - FRAG_RESULT_DATA0);
 
/* TODO: Reverse-engineer interactions with MRT */
-   agx_writeout(b, 0xC200);
-   agx_writeout(b, 0x000C);
+   if (b->shader->did_writeout) {
+  agx_writeout(b, 0x0004);
+   } else {
+  agx_writeout(b, 0xC200);
+  agx_writeout(b, 0x000C);
+   }
 
+   b->shader->did_writeout = true;
return agx_st_tile(b, agx_src_index(>src[0]),
  b->shader->key->fs.tib_formats[rt]);
 }
diff --git a/src/asahi/compiler/agx_compiler.h 
b/src/asahi/compiler/agx_compiler.h
index 030cb26585b..0c45c0e0b60 100644
--- a/src/asahi/compiler/agx_compiler.h
+++ b/src/asahi/compiler/agx_compiler.h
@@ -318,6 +318,9 @@ typedef struct {
/* For creating temporaries */
unsigned alloc;
 
+   /* I don't really understand how writeout ops work yet */
+   bool did_writeout;
+
/* Stats for shader-db */
unsigned loop_count;
unsigned spills;

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Mesa (main): asahi: Garbage collect bind_state

2021-05-09 Thread GitLab Mirror 
Module: Mesa
Branch: main
Commit: 6b7cc1fa8f3591a393eefb88ca4213925e012c80
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6b7cc1fa8f3591a393eefb88ca4213925e012c80

Author: Alyssa Rosenzweig 
Date:   Tue May  4 22:27:46 2021 -0400

asahi: Garbage collect bind_state

>From noop.

Signed-off-by: Alyssa Rosenzweig 
Part-of: 

---

 src/gallium/drivers/asahi/agx_state.c | 5 -
 1 file changed, 5 deletions(-)

diff --git a/src/gallium/drivers/asahi/agx_state.c 
b/src/gallium/drivers/asahi/agx_state.c
index ab54109edb7..e7cde23ea61 100644
--- a/src/gallium/drivers/asahi/agx_state.c
+++ b/src/gallium/drivers/asahi/agx_state.c
@@ -521,11 +521,6 @@ agx_surface_destroy(struct pipe_context *ctx,
FREE(surface);
 }
 
-static void
-agx_bind_state(struct pipe_context *ctx, void *state)
-{
-}
-
 static void
 agx_delete_state(struct pipe_context *ctx, void *state)
 {

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Mesa (main): agx: Rename blend -> st_tile

2021-05-09 Thread GitLab Mirror 
Module: Mesa
Branch: main
Commit: 07fdc0015e2d212404511b269d0a260323ebcbc0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=07fdc0015e2d212404511b269d0a260323ebcbc0

Author: Alyssa Rosenzweig 
Date:   Tue May  4 22:44:54 2021 -0400

agx: Rename blend -> st_tile

For symmetry.

Signed-off-by: Alyssa Rosenzweig 
Part-of: 

---

 src/asahi/compiler/agx_compile.c   | 3 +--
 src/asahi/compiler/agx_opcodes.py  | 4 +++-
 src/asahi/compiler/agx_optimizer.c | 2 +-
 src/asahi/compiler/agx_pack.c  | 2 +-
 4 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/src/asahi/compiler/agx_compile.c b/src/asahi/compiler/agx_compile.c
index 34270b2e15e..a7f4f0f09a3 100644
--- a/src/asahi/compiler/agx_compile.c
+++ b/src/asahi/compiler/agx_compile.c
@@ -176,8 +176,7 @@ agx_emit_fragment_out(agx_builder *b, nir_intrinsic_instr 
*instr)
agx_writeout(b, 0xC200);
agx_writeout(b, 0x000C);
 
-   /* Emit the blend op itself */
-   return agx_blend(b, agx_src_index(>src[0]),
+   return agx_st_tile(b, agx_src_index(>src[0]),
  b->shader->key->fs.tib_formats[rt]);
 }
 
diff --git a/src/asahi/compiler/agx_opcodes.py 
b/src/asahi/compiler/agx_opcodes.py
index d7b0d866807..b2e540bf4c8 100644
--- a/src/asahi/compiler/agx_opcodes.py
+++ b/src/asahi/compiler/agx_opcodes.py
@@ -172,8 +172,10 @@ op("device_load",
 op("wait", (0x38, 0xFF, 2, _), dests = 0,
   can_eliminate = False, imms = [SCOREBOARD])
 
+op("st_tile", (0x09, 0x7F, 8, _), dests = 0, srcs = 1,
+  can_eliminate = False, imms = [FORMAT])
+
 op("bitop", (0x7E, 0x7F, 6, _), srcs = 2, imms = [TRUTH_TABLE])
-op("blend", (0x09, 0x7F, 8, _), dests = 0, srcs = 1, imms = [FORMAT], 
can_eliminate = False)
 op("convert", (0x3E | L, 0x7F | L | (0x3 << 38), 6, _), srcs = 2, imms = 
[ROUND]) 
 op("ld_vary", (0x21, 0x3F, 8, _), srcs = 1, imms = [CHANNELS])
 op("st_vary", None, dests = 0, srcs = 2, can_eliminate = False)
diff --git a/src/asahi/compiler/agx_optimizer.c 
b/src/asahi/compiler/agx_optimizer.c
index ac5e55f358f..0f93b19ecb0 100644
--- a/src/asahi/compiler/agx_optimizer.c
+++ b/src/asahi/compiler/agx_optimizer.c
@@ -169,7 +169,7 @@ agx_optimizer_forward(agx_context *ctx)
  agx_optimizer_fmov(defs, I, info.nr_srcs);
 
   /* Inline immediates if we can. TODO: systematic */
-  if (I->op != AGX_OPCODE_ST_VARY && I->op != AGX_OPCODE_BLEND && I->op != 
AGX_OPCODE_P_EXTRACT && I->op != AGX_OPCODE_P_COMBINE)
+  if (I->op != AGX_OPCODE_ST_VARY && I->op != AGX_OPCODE_ST_TILE && I->op 
!= AGX_OPCODE_P_EXTRACT && I->op != AGX_OPCODE_P_COMBINE)
  agx_optimizer_inline_imm(defs, I, info.nr_srcs, info.is_float);
}
 
diff --git a/src/asahi/compiler/agx_pack.c b/src/asahi/compiler/agx_pack.c
index b5b09e0ced0..953c7af697e 100644
--- a/src/asahi/compiler/agx_pack.c
+++ b/src/asahi/compiler/agx_pack.c
@@ -356,7 +356,7 @@ static void
 agx_pack_instr(struct util_dynarray *emission, agx_instr *I)
 {
switch (I->op) {
-   case AGX_OPCODE_BLEND:
+   case AGX_OPCODE_ST_TILE:
{
   unsigned D = agx_pack_alu_dst(I->src[0]);
   unsigned rt = 0; /* TODO */

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Mesa (main): agx: Assume lower_fragcolor has been called

2021-05-09 Thread GitLab Mirror 
Module: Mesa
Branch: main
Commit: 41d8db33a2251ddd1e9fc84fbbeffa8f6a8fa49b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=41d8db33a2251ddd1e9fc84fbbeffa8f6a8fa49b

Author: Alyssa Rosenzweig 
Date:   Tue May  4 22:55:37 2021 -0400

agx: Assume lower_fragcolor has been called

Signed-off-by: Alyssa Rosenzweig 
Part-of: 

---

 src/asahi/compiler/agx_compile.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/src/asahi/compiler/agx_compile.c b/src/asahi/compiler/agx_compile.c
index a7f4f0f09a3..b344ecce532 100644
--- a/src/asahi/compiler/agx_compile.c
+++ b/src/asahi/compiler/agx_compile.c
@@ -168,9 +168,8 @@ agx_emit_fragment_out(agx_builder *b, nir_intrinsic_instr 
*instr)
 
unsigned loc = var->data.location;
assert(var->data.index == 0 && "todo: dual-source blending");
-   assert((loc == FRAG_RESULT_COLOR || loc == FRAG_RESULT_DATA0) && "todo: 
MRT");
-   unsigned rt = (loc == FRAG_RESULT_COLOR) ? 0 :
- (loc - FRAG_RESULT_DATA0);
+   assert(loc == FRAG_RESULT_DATA0 && "todo: MRT");
+   unsigned rt = (loc - FRAG_RESULT_DATA0);
 
/* TODO: Reverse-engineer interactions with MRT */
agx_writeout(b, 0xC200);

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Mesa (main): agx: Implement load_output

2021-05-09 Thread GitLab Mirror 
Module: Mesa
Branch: main
Commit: d0f566a90d8ca1a116f728525a2ab01d705bff31
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d0f566a90d8ca1a116f728525a2ab01d705bff31

Author: Alyssa Rosenzweig 
Date:   Tue May  4 23:00:55 2021 -0400

agx: Implement load_output

Signed-off-by: Alyssa Rosenzweig 
Part-of: 

---

 src/asahi/compiler/agx_compile.c | 26 ++
 1 file changed, 26 insertions(+)

diff --git a/src/asahi/compiler/agx_compile.c b/src/asahi/compiler/agx_compile.c
index f4b6d059524..b347e6c2129 100644
--- a/src/asahi/compiler/agx_compile.c
+++ b/src/asahi/compiler/agx_compile.c
@@ -184,6 +184,28 @@ agx_emit_fragment_out(agx_builder *b, nir_intrinsic_instr 
*instr)
  b->shader->key->fs.tib_formats[rt]);
 }
 
+static agx_instr *
+agx_emit_load_tile(agx_builder *b, nir_intrinsic_instr *instr)
+{
+   const nir_variable *var =
+  nir_find_variable_with_driver_location(b->shader->nir,
+nir_var_shader_out, nir_intrinsic_base(instr));
+   assert(var);
+
+   unsigned loc = var->data.location;
+   assert(var->data.index == 0 && "todo: dual-source blending");
+   assert(loc == FRAG_RESULT_DATA0 && "todo: MRT");
+   unsigned rt = (loc - FRAG_RESULT_DATA0);
+
+   /* TODO: Reverse-engineer interactions with MRT */
+   agx_writeout(b, 0xC200);
+   agx_writeout(b, 0x0008);
+   b->shader->did_writeout = true;
+
+   return agx_ld_tile_to(b, agx_dest_index(>dest),
+ b->shader->key->fs.tib_formats[rt]);
+}
+
 static enum agx_format
 agx_format_for_bits(unsigned bits)
 {
@@ -280,6 +302,10 @@ agx_emit_intrinsic(agx_builder *b, nir_intrinsic_instr 
*instr)
  else
 unreachable("Unsupported shader stage");
 
+  case nir_intrinsic_load_output:
+ assert(stage == MESA_SHADER_FRAGMENT);
+ return agx_emit_load_tile(b, instr);
+
   case nir_intrinsic_load_ubo:
   case nir_intrinsic_load_kernel_input:
  return agx_emit_load_ubo(b, instr);

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Mesa (main): asahi: Augment Gallium key with blend state

2021-05-09 Thread GitLab Mirror 
Module: Mesa
Branch: main
Commit: f2179ed4f33d66cefe0f607c048cb6d89a7e979a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f2179ed4f33d66cefe0f607c048cb6d89a7e979a

Author: Alyssa Rosenzweig 
Date:   Tue May  4 22:20:39 2021 -0400

asahi: Augment Gallium key with blend state

Signed-off-by: Alyssa Rosenzweig 
Part-of: 

---

 src/gallium/drivers/asahi/agx_state.c | 13 -
 src/gallium/drivers/asahi/agx_state.h |  5 +
 2 files changed, 13 insertions(+), 5 deletions(-)

diff --git a/src/gallium/drivers/asahi/agx_state.c 
b/src/gallium/drivers/asahi/agx_state.c
index d8875e5c87e..4dfdf366862 100644
--- a/src/gallium/drivers/asahi/agx_state.c
+++ b/src/gallium/drivers/asahi/agx_state.c
@@ -606,7 +606,7 @@ agx_create_shader_state(struct pipe_context *ctx,
 
 static bool
 agx_update_shader(struct agx_context *ctx, struct agx_compiled_shader **out,
-  enum pipe_shader_type stage, struct agx_shader_key *key)
+  enum pipe_shader_type stage, struct asahi_shader_key *key)
 {
struct agx_uncompiled_shader *so = ctx->stage[stage].shader;
assert(so != NULL);
@@ -626,7 +626,7 @@ agx_update_shader(struct agx_context *ctx, struct 
agx_compiled_shader **out,
util_dynarray_init(, NULL);
 
nir_shader *nir = nir_shader_clone(NULL, so->nir);
-   agx_compile_shader_nir(nir, key, , >info);
+   agx_compile_shader_nir(nir, >base, , >info);
 
/* TODO: emit this properly */
nir_variable_mode varying_mode = (nir->info.stage == MESA_SHADER_FRAGMENT) ?
@@ -705,8 +705,11 @@ agx_update_vs(struct agx_context *ctx)
   key.vbuf_strides[i] = ctx->vertex_buffers[i].stride / 4; // TODO: 
alignment
}
 
-   return agx_update_shader(ctx, >vs, PIPE_SHADER_VERTEX,
-(struct agx_shader_key *) );
+   struct asahi_shader_key akey = {
+  .base.vs = key
+   };
+
+   return agx_update_shader(ctx, >vs, PIPE_SHADER_VERTEX, );
 }
 
 static bool
@@ -717,7 +720,7 @@ agx_update_fs(struct agx_context *ctx)
};
 
return agx_update_shader(ctx, >fs, PIPE_SHADER_FRAGMENT,
-(struct agx_shader_key *) );
+(struct asahi_shader_key *) );
 }
 
 static void
diff --git a/src/gallium/drivers/asahi/agx_state.h 
b/src/gallium/drivers/asahi/agx_state.h
index 9cd84c139de..0cbabbaf2fc 100644
--- a/src/gallium/drivers/asahi/agx_state.h
+++ b/src/gallium/drivers/asahi/agx_state.h
@@ -107,6 +107,11 @@ struct agx_blend {
};
 };
 
+struct asahi_shader_key {
+   struct agx_shader_key base;
+   struct agx_blend blend;
+};
+
 #define AGX_DIRTY_VERTEX (1 << 0)
 
 struct agx_context {

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Mesa (main): asahi: Call nir_lower_fragcolor

2021-05-09 Thread GitLab Mirror 
Module: Mesa
Branch: main
Commit: bedf1019beb5075b863079ae1d595070750db317
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bedf1019beb5075b863079ae1d595070750db317

Author: Alyssa Rosenzweig 
Date:   Tue May  4 22:55:26 2021 -0400

asahi: Call nir_lower_fragcolor

Signed-off-by: Alyssa Rosenzweig 
Part-of: 

---

 src/gallium/drivers/asahi/agx_state.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/gallium/drivers/asahi/agx_state.c 
b/src/gallium/drivers/asahi/agx_state.c
index 38f5d7b7f40..25cf86df1be 100644
--- a/src/gallium/drivers/asahi/agx_state.c
+++ b/src/gallium/drivers/asahi/agx_state.c
@@ -644,6 +644,9 @@ agx_update_shader(struct agx_context *ctx, struct 
agx_compiled_shader **out,
   NIR_PASS_V(nir, nir_lower_blend, opts);
}
 
+   if (stage == PIPE_SHADER_FRAGMENT)
+  NIR_PASS_V(nir, nir_lower_fragcolor, key->nr_cbufs);
+
agx_compile_shader_nir(nir, >base, , >info);
 
/* TODO: emit this properly */

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Mesa (main): asahi: Pass through "reads tilebuffer?" bit

2021-05-09 Thread GitLab Mirror 
Module: Mesa
Branch: main
Commit: dd64463d5f79af00ccd803ae317bd626928fec45
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=dd64463d5f79af00ccd803ae317bd626928fec45

Author: Alyssa Rosenzweig 
Date:   Sun May  9 21:04:38 2021 -0400

asahi: Pass through "reads tilebuffer?" bit

To be determined if there's more to this, but it's the only bit I see
varying with Metal when blending is enabled.

Signed-off-by: Alyssa Rosenzweig 
Part-of: 

---

 src/asahi/compiler/agx_compile.h  |  3 +++
 src/gallium/drivers/asahi/agx_state.c | 10 +++---
 2 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/src/asahi/compiler/agx_compile.h b/src/asahi/compiler/agx_compile.h
index f00434f573e..484d96e6fb9 100644
--- a/src/asahi/compiler/agx_compile.h
+++ b/src/asahi/compiler/agx_compile.h
@@ -80,6 +80,9 @@ struct agx_push {
 struct agx_shader_info {
unsigned push_ranges;
struct agx_push push[AGX_MAX_PUSH_RANGES];
+
+   /* Does the shader read the tilebuffer? */
+   bool reads_tib;
 };
 
 #define AGX_MAX_RTS (8)
diff --git a/src/gallium/drivers/asahi/agx_state.c 
b/src/gallium/drivers/asahi/agx_state.c
index 53698202de6..a59ce975be1 100644
--- a/src/gallium/drivers/asahi/agx_state.c
+++ b/src/gallium/drivers/asahi/agx_state.c
@@ -1034,16 +1034,18 @@ demo_rasterizer(struct agx_context *ctx, struct 
agx_pool *pool)
 }
 
 static uint64_t
-demo_unk11(struct agx_pool *pool, bool prim_lines)
+demo_unk11(struct agx_pool *pool, bool prim_lines, bool reads_tib)
 {
 #define UNK11_FILL_MODE_LINES_1 (1 << 26)
 
 #define UNK11_FILL_MODE_LINES_2 (0x5004 << 16)
 #define UNK11_LINES (0x1000)
 
+#define UNK11_READS_TIB (0x2000)
+
uint32_t unk[] = {
   0x24a,
-  0x200 | (prim_lines ? UNK11_FILL_MODE_LINES_1 : 0),
+  0x200 | (prim_lines ? UNK11_FILL_MODE_LINES_1 : 0) | (reads_tib ? 
UNK11_READS_TIB : 0),
   0x7e0 | (prim_lines ? UNK11_LINES : 0),
   0x7e0 | (prim_lines ? UNK11_LINES : 0),
 
@@ -1105,12 +1107,14 @@ agx_encode_state(struct agx_context *ctx, uint8_t *out,
struct agx_ptr zero = agx_pool_alloc_aligned(pool, 16, 256);
memset(zero.cpu, 0, 16);
 
+   bool reads_tib = ctx->fs->info.reads_tib;
+
agx_push_record(, 0, zero.gpu);
agx_push_record(, 5, demo_unk8(ctx->fs, pool));
agx_push_record(, 5, demo_launch_fragment(pool, pipeline_fragment, 
varyings, ctx->fs->varying_count + 1));
agx_push_record(, 4, demo_linkage(ctx->vs, pool));
agx_push_record(, 7, demo_rasterizer(ctx, pool));
-   agx_push_record(, 5, demo_unk11(pool, is_lines));
+   agx_push_record(, 5, demo_unk11(pool, is_lines, reads_tib));
agx_push_record(, 10, agx_pool_upload(pool, ctx->viewport, 
sizeof(ctx->viewport)));
agx_push_record(, 3, demo_unk12(pool));
agx_push_record(, 2, agx_pool_upload(pool, ctx->rast->cull, 
sizeof(ctx->rast->cull)));

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Mesa (main): asahi: Call nir_lower_blend with selected key

2021-05-09 Thread GitLab Mirror 
Module: Mesa
Branch: main
Commit: 91b9839bf70a11963e7ed278f8313dee37f9049c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=91b9839bf70a11963e7ed278f8313dee37f9049c

Author: Alyssa Rosenzweig 
Date:   Sun May  9 20:57:54 2021 -0400

asahi: Call nir_lower_blend with selected key

Also need to key to pipe formats.

Signed-off-by: Alyssa Rosenzweig 
Part-of: 

---

 src/gallium/drivers/asahi/agx_state.c | 36 ---
 src/gallium/drivers/asahi/agx_state.h |  4 +++-
 2 files changed, 36 insertions(+), 4 deletions(-)

diff --git a/src/gallium/drivers/asahi/agx_state.c 
b/src/gallium/drivers/asahi/agx_state.c
index 4dfdf366862..ab54109edb7 100644
--- a/src/gallium/drivers/asahi/agx_state.c
+++ b/src/gallium/drivers/asahi/agx_state.c
@@ -626,6 +626,25 @@ agx_update_shader(struct agx_context *ctx, struct 
agx_compiled_shader **out,
util_dynarray_init(, NULL);
 
nir_shader *nir = nir_shader_clone(NULL, so->nir);
+
+   if (key->blend.blend_enable) {
+  nir_lower_blend_options opts = {
+ .format = { key->rt_formats[0] },
+ .scalar_blend_const = true
+  };
+
+  memcpy(opts.rt, key->blend.rt, sizeof(opts.rt));
+  NIR_PASS_V(nir, nir_lower_blend, opts);
+   } else if (key->blend.logicop_enable) {
+  nir_lower_blend_options opts = {
+ .format = { key->rt_formats[0] },
+ .logicop_enable = true,
+ .logicop_func = key->blend.logicop_func,
+  };
+
+  NIR_PASS_V(nir, nir_lower_blend, opts);
+   }
+
agx_compile_shader_nir(nir, >base, , >info);
 
/* TODO: emit this properly */
@@ -715,12 +734,23 @@ agx_update_vs(struct agx_context *ctx)
 static bool
 agx_update_fs(struct agx_context *ctx)
 {
-   struct agx_fs_shader_key key = {
+   struct agx_fs_shader_key base_key = {
   .tib_formats = { AGX_FORMAT_U8NORM }
};
 
-   return agx_update_shader(ctx, >fs, PIPE_SHADER_FRAGMENT,
-(struct asahi_shader_key *) );
+   struct asahi_shader_key key = {
+  .base.fs = base_key,
+  .nr_cbufs = ctx->batch->nr_cbufs,
+   };
+
+   for (unsigned i = 0; i < key.nr_cbufs; ++i) {
+  key.rt_formats[i] = ctx->batch->cbufs[i] ?
+ ctx->batch->cbufs[i]->format : PIPE_FORMAT_NONE;
+   }
+
+   memcpy(, ctx->blend, sizeof(key.blend));
+
+   return agx_update_shader(ctx, >fs, PIPE_SHADER_FRAGMENT, );
 }
 
 static void
diff --git a/src/gallium/drivers/asahi/agx_state.h 
b/src/gallium/drivers/asahi/agx_state.h
index 0cbabbaf2fc..a8d0aebcc10 100644
--- a/src/gallium/drivers/asahi/agx_state.h
+++ b/src/gallium/drivers/asahi/agx_state.h
@@ -99,7 +99,7 @@ struct agx_zsa {
 };
 
 struct agx_blend {
-   bool logicop_enable;
+   bool logicop_enable, blend_enable;
 
union {
   nir_lower_blend_rt rt[8];
@@ -110,6 +110,8 @@ struct agx_blend {
 struct asahi_shader_key {
struct agx_shader_key base;
struct agx_blend blend;
+   unsigned nr_cbufs;
+   enum pipe_format rt_formats[PIPE_MAX_COLOR_BUFS];
 };
 
 #define AGX_DIRTY_VERTEX (1 << 0)

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Mesa (main): asahi: Fix shader key hash function

2021-05-09 Thread GitLab Mirror 
Module: Mesa
Branch: main
Commit: e2332dea0584fdce4b116e02a2033c4f4745ec86
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e2332dea0584fdce4b116e02a2033c4f4745ec86

Author: Alyssa Rosenzweig 
Date:   Sun May  9 20:56:27 2021 -0400

asahi: Fix shader key hash function

Fixes: 080b05e29e1 ("asahi: Add Gallium driver")
Signed-off-by: Alyssa Rosenzweig 
Part-of: 

---

 src/gallium/drivers/asahi/agx_state.c | 17 +
 1 file changed, 13 insertions(+), 4 deletions(-)

diff --git a/src/gallium/drivers/asahi/agx_state.c 
b/src/gallium/drivers/asahi/agx_state.c
index 25cf86df1be..53698202de6 100644
--- a/src/gallium/drivers/asahi/agx_state.c
+++ b/src/gallium/drivers/asahi/agx_state.c
@@ -585,6 +585,16 @@ agx_bind_vertex_elements_state(struct pipe_context *pctx, 
void *cso)
ctx->dirty |= AGX_DIRTY_VERTEX;
 }
 
+static uint32_t asahi_shader_key_hash(const void *key)
+{
+   return _mesa_hash_data(key, sizeof(struct asahi_shader_key));
+}
+
+static bool asahi_shader_key_equal(const void *a, const void *b)
+{
+   return memcmp(a, b, sizeof(struct asahi_shader_key)) == 0;
+}
+
 static void *
 agx_create_shader_state(struct pipe_context *ctx,
 const struct pipe_shader_state *cso)
@@ -598,8 +608,7 @@ agx_create_shader_state(struct pipe_context *ctx,
assert(cso->type == PIPE_SHADER_IR_NIR);
so->nir = cso->ir.nir;
 
-   so->variants = _mesa_hash_table_create(NULL,
-  _mesa_hash_pointer, 
_mesa_key_pointer_equal);
+   so->variants = _mesa_hash_table_create(NULL, asahi_shader_key_hash, 
asahi_shader_key_equal);
return so;
 }
 
@@ -610,7 +619,7 @@ agx_update_shader(struct agx_context *ctx, struct 
agx_compiled_shader **out,
struct agx_uncompiled_shader *so = ctx->stage[stage].shader;
assert(so != NULL);
 
-   struct hash_entry *he = _mesa_hash_table_search(so->variants, );
+   struct hash_entry *he = _mesa_hash_table_search(so->variants, key);
 
if (he) {
   if ((*out) == he->data)
@@ -706,7 +715,7 @@ agx_update_shader(struct agx_context *ctx, struct 
agx_compiled_shader **out,
ralloc_free(nir);
util_dynarray_fini();
 
-   he = _mesa_hash_table_insert(so->variants, , compiled);
+   he = _mesa_hash_table_insert(so->variants, key, compiled);
*out = he->data;
return true;
 }

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Mesa (main): agx: Return agx_instr* from emit_intrinsic

2021-05-09 Thread GitLab Mirror 
Module: Mesa
Branch: main
Commit: 5fd489a6bdbd1df0cde1496e22178d92d6bfa4c4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5fd489a6bdbd1df0cde1496e22178d92d6bfa4c4

Author: Alyssa Rosenzweig 
Date:   Tue May  4 22:42:07 2021 -0400

agx: Return agx_instr* from emit_intrinsic

Aesthetically useful.

Signed-off-by: Alyssa Rosenzweig 
Part-of: 

---

 src/asahi/compiler/agx_compile.c | 42 +++-
 1 file changed, 20 insertions(+), 22 deletions(-)

diff --git a/src/asahi/compiler/agx_compile.c b/src/asahi/compiler/agx_compile.c
index f1631ae0e2b..dd9b6320d48 100644
--- a/src/asahi/compiler/agx_compile.c
+++ b/src/asahi/compiler/agx_compile.c
@@ -63,7 +63,7 @@ agx_emit_load_const(agx_builder *b, nir_load_const_instr 
*instr)
 }
 
 /* AGX appears to lack support for vertex attributes. Lower to global loads. */
-static void
+static agx_instr *
 agx_emit_load_attr(agx_builder *b, nir_intrinsic_instr *instr)
 {
nir_src *offset_src = nir_get_io_offset_src(instr);
@@ -109,9 +109,11 @@ agx_emit_load_attr(agx_builder *b, nir_intrinsic_instr 
*instr)
  channels[i] = agx_null();
   agx_p_combine_to(b, real_dest, channels[0], channels[1], channels[2], 
channels[3]);
}
+
+   return NULL;
 }
 
-static void
+static agx_instr *
 agx_emit_load_vary(agx_builder *b, nir_intrinsic_instr *instr)
 {
unsigned components = instr->num_components;
@@ -135,11 +137,11 @@ agx_emit_load_vary(agx_builder *b, nir_intrinsic_instr 
*instr)
unsigned imm_index = (4 * nir_intrinsic_base(instr)) + 
nir_src_as_uint(*offset);
imm_index += 1;
 
-   agx_ld_vary_to(b, agx_dest_index(>dest),
+   return agx_ld_vary_to(b, agx_dest_index(>dest),
  agx_immediate(imm_index), components);
 }
 
-static void
+static agx_instr *
 agx_emit_store_vary(agx_builder *b, nir_intrinsic_instr *instr)
 {
nir_src *offset = nir_get_io_offset_src(instr);
@@ -151,12 +153,12 @@ agx_emit_store_vary(agx_builder *b, nir_intrinsic_instr 
*instr)
/* nir_lower_io_to_scalar */
assert(nir_intrinsic_write_mask(instr) == 0x1);
 
-   agx_st_vary(b,
+   return agx_st_vary(b,
agx_immediate(imm_index),
agx_src_index(>src[0]));
 }
 
-static void
+static agx_instr *
 agx_emit_fragment_out(agx_builder *b, nir_intrinsic_instr *instr)
 {
const nir_variable *var =
@@ -175,7 +177,7 @@ agx_emit_fragment_out(agx_builder *b, nir_intrinsic_instr 
*instr)
agx_writeout(b, 0x000C);
 
/* Emit the blend op itself */
-   agx_blend(b, agx_src_index(>src[0]),
+   return agx_blend(b, agx_src_index(>src[0]),
  b->shader->key->fs.tib_formats[rt]);
 }
 
@@ -190,7 +192,7 @@ agx_format_for_bits(unsigned bits)
}
 }
 
-static void
+static agx_instr *
 agx_emit_load_ubo(agx_builder *b, nir_intrinsic_instr *instr)
 {
bool kernel_input = (instr->intrinsic == nir_intrinsic_load_kernel_input);
@@ -231,10 +233,10 @@ agx_emit_load_ubo(agx_builder *b, nir_intrinsic_instr 
*instr)
   agx_format_for_bits(nir_dest_bit_size(instr->dest)),
   BITFIELD_MASK(instr->num_components), 0);
 
-   agx_wait(b, 0);
+   return agx_wait(b, 0);
 }
 
-static void
+static agx_instr *
 agx_emit_intrinsic(agx_builder *b, nir_intrinsic_instr *instr)
 {
   agx_index dst = nir_intrinsic_infos[instr->intrinsic].has_dest ?
@@ -248,38 +250,34 @@ agx_emit_intrinsic(agx_builder *b, nir_intrinsic_instr 
*instr)
   case nir_intrinsic_load_barycentric_at_sample:
   case nir_intrinsic_load_barycentric_at_offset:
  /* handled later via load_vary */
- break;
+ return NULL;
   case nir_intrinsic_load_interpolated_input:
   case nir_intrinsic_load_input:
  if (stage == MESA_SHADER_FRAGMENT)
-agx_emit_load_vary(b, instr);
+return agx_emit_load_vary(b, instr);
  else if (stage == MESA_SHADER_VERTEX)
-agx_emit_load_attr(b, instr);
+return agx_emit_load_attr(b, instr);
  else
 unreachable("Unsupported shader stage");
- break;
 
   case nir_intrinsic_store_output:
  if (stage == MESA_SHADER_FRAGMENT)
-agx_emit_fragment_out(b, instr);
+return agx_emit_fragment_out(b, instr);
  else if (stage == MESA_SHADER_VERTEX)
-agx_emit_store_vary(b, instr);
+return agx_emit_store_vary(b, instr);
  else
 unreachable("Unsupported shader stage");
- break;
 
   case nir_intrinsic_load_ubo:
   case nir_intrinsic_load_kernel_input:
- agx_emit_load_ubo(b, instr);
- break;
+ return agx_emit_load_ubo(b, instr);
 
   case nir_intrinsic_load_vertex_id:
- agx_mov_to(b, dst, agx_abs(agx_register(10, AGX_SIZE_32))); /* TODO: RA */
- break;
+ return agx_mov_to(b, dst, agx_abs(agx_register(10, AGX_SIZE_32))); /* 
TODO: RA */
 
   default:
fprintf(stderr, "Unhandled intrinsic %s\n", 
nir_intrinsic_infos[instr->intrinsic].name);
-   assert(0);
+   unreachable("Unhandled

Mesa (main): asahi: Translate blend CSO to lower_blend options

2021-05-09 Thread GitLab Mirror 
Module: Mesa
Branch: main
Commit: 77f1f12000ec1ed3d461404b30af9a6d14b96afa
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=77f1f12000ec1ed3d461404b30af9a6d14b96afa

Author: Alyssa Rosenzweig 
Date:   Tue May  4 22:20:50 2021 -0400

asahi: Translate blend CSO to lower_blend options

We'll just stick this in the key.

Signed-off-by: Alyssa Rosenzweig 
Part-of: 

---

 src/gallium/drivers/asahi/agx_state.c | 59 +--
 src/gallium/drivers/asahi/agx_state.h | 11 +++
 2 files changed, 68 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/asahi/agx_state.c 
b/src/gallium/drivers/asahi/agx_state.c
index 16751f6b126..d8875e5c87e 100644
--- a/src/gallium/drivers/asahi/agx_state.c
+++ b/src/gallium/drivers/asahi/agx_state.c
@@ -34,6 +34,7 @@
 #include "gallium/auxiliary/util/u_draw.h"
 #include "gallium/auxiliary/util/u_helpers.h"
 #include "gallium/auxiliary/util/u_viewport.h"
+#include "gallium/auxiliary/util/u_blend.h"
 #include "gallium/auxiliary/tgsi/tgsi_from_mesa.h"
 #include "compiler/nir/nir.h"
 #include "asahi/compiler/agx_compile.h"
@@ -51,7 +52,61 @@ static void *
 agx_create_blend_state(struct pipe_context *ctx,
const struct pipe_blend_state *state)
 {
-   return MALLOC(1);
+   struct agx_blend *so = CALLOC_STRUCT(agx_blend);
+
+   assert(!state->alpha_to_coverage);
+   assert(!state->alpha_to_coverage_dither);
+   assert(!state->alpha_to_one);
+   assert(!state->advanced_blend_func);
+
+   if (state->logicop_enable) {
+  so->logicop_enable = true;
+  so->logicop_func = state->logicop_func;
+  return so;
+   }
+
+   for (unsigned i = 0; i < PIPE_MAX_COLOR_BUFS; ++i) {
+  unsigned rti = state->independent_blend_enable ? i : 0;
+  struct pipe_rt_blend_state rt = state->rt[rti];
+
+  if (!rt.blend_enable) {
+ static const nir_lower_blend_channel replace = {
+.func = BLEND_FUNC_ADD,
+.src_factor = BLEND_FACTOR_ZERO,
+.invert_src_factor = true,
+.dst_factor = BLEND_FACTOR_ZERO,
+.invert_dst_factor = false,
+ };
+
+ so->rt[i].rgb = replace;
+ so->rt[i].alpha = replace;
+  } else {
+ so->rt[i].rgb.func = util_blend_func_to_shader(rt.rgb_func);
+ so->rt[i].rgb.src_factor = 
util_blend_factor_to_shader(rt.rgb_src_factor);
+ so->rt[i].rgb.invert_src_factor = 
util_blend_factor_is_inverted(rt.rgb_src_factor);
+ so->rt[i].rgb.dst_factor = 
util_blend_factor_to_shader(rt.rgb_dst_factor);
+ so->rt[i].rgb.invert_dst_factor = 
util_blend_factor_is_inverted(rt.rgb_dst_factor);
+
+ so->rt[i].alpha.func = util_blend_func_to_shader(rt.alpha_func);
+ so->rt[i].alpha.src_factor = 
util_blend_factor_to_shader(rt.alpha_src_factor);
+ so->rt[i].alpha.invert_src_factor = 
util_blend_factor_is_inverted(rt.alpha_src_factor);
+ so->rt[i].alpha.dst_factor = 
util_blend_factor_to_shader(rt.alpha_dst_factor);
+ so->rt[i].alpha.invert_dst_factor = 
util_blend_factor_is_inverted(rt.alpha_dst_factor);
+
+so->blend_enable = true;
+  }
+
+  so->rt[i].colormask = rt.colormask;
+   }
+
+   return so;
+}
+
+static void
+agx_bind_blend_state(struct pipe_context *pctx, void *cso)
+{
+   struct agx_context *ctx = agx_context(pctx);
+   ctx->blend = cso;
 }
 
 static void *
@@ -1150,7 +1205,7 @@ agx_init_state_functions(struct pipe_context *ctx)
ctx->create_surface = agx_create_surface;
ctx->create_vertex_elements_state = agx_create_vertex_elements;
ctx->create_vs_state = agx_create_shader_state;
-   ctx->bind_blend_state = agx_bind_state;
+   ctx->bind_blend_state = agx_bind_blend_state;
ctx->bind_depth_stencil_alpha_state = agx_bind_zsa_state;
ctx->bind_sampler_states = agx_bind_sampler_states;
ctx->bind_fs_state = agx_bind_shader_state;
diff --git a/src/gallium/drivers/asahi/agx_state.h 
b/src/gallium/drivers/asahi/agx_state.h
index 9d860f41c21..9cd84c139de 100644
--- a/src/gallium/drivers/asahi/agx_state.h
+++ b/src/gallium/drivers/asahi/agx_state.h
@@ -32,6 +32,7 @@
 #include "asahi/lib/agx_device.h"
 #include "asahi/lib/pool.h"
 #include "asahi/compiler/agx_compile.h"
+#include "compiler/nir/nir_lower_blend.h"
 #include "util/hash_table.h"
 #include "util/bitset.h"
 
@@ -97,6 +98,15 @@ struct agx_zsa {
bool disable_z_write;
 };
 
+struct agx_blend {
+   bool logicop_enable;
+
+   union {
+  nir_lower_blend_rt rt[8];
+  unsigned logicop_func;
+   };
+};
+
 #define AGX_DIRTY_VERTEX (1 << 0)
 
 struct agx_context {
@@ -113,6 +123,7 @@ struct agx_context {
struct agx_attribute *attributes;
struct agx_rasterizer *rast;
struct agx_zsa zs;
+   struct agx_blend *blend;
 
uint8_t viewport[AGX_VIEWPORT_LENGTH];
uint8_t render_target[8][AGX_RENDER_TARGET_LENGTH];

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Mesa (main): agx: Set reads_tib appropriately

2021-05-09 Thread GitLab Mirror 
Module: Mesa
Branch: main
Commit: 15b557319400424579dcb62c70ed8c72882b44bd
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=15b557319400424579dcb62c70ed8c72882b44bd

Author: Alyssa Rosenzweig 
Date:   Sun May  9 21:05:07 2021 -0400

agx: Set reads_tib appropriately

Signed-off-by: Alyssa Rosenzweig 
Part-of: 

---

 src/asahi/compiler/agx_compile.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/asahi/compiler/agx_compile.c b/src/asahi/compiler/agx_compile.c
index b347e6c2129..5f0ca1f72b6 100644
--- a/src/asahi/compiler/agx_compile.c
+++ b/src/asahi/compiler/agx_compile.c
@@ -201,6 +201,7 @@ agx_emit_load_tile(agx_builder *b, nir_intrinsic_instr 
*instr)
agx_writeout(b, 0xC200);
agx_writeout(b, 0x0008);
b->shader->did_writeout = true;
+   b->shader->out->reads_tib = true;
 
return agx_ld_tile_to(b, agx_dest_index(>dest),
  b->shader->key->fs.tib_formats[rt]);

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Mesa (main): agx: Add ld_tile opcode

2021-05-09 Thread GitLab Mirror 
Module: Mesa
Branch: main
Commit: 1164c992cffd50f97bcef737942f72481e28522e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1164c992cffd50f97bcef737942f72481e28522e

Author: Alyssa Rosenzweig 
Date:   Tue May  4 22:50:25 2021 -0400

agx: Add ld_tile opcode

Variant of st_tile.

Signed-off-by: Alyssa Rosenzweig 
Part-of: 

---

 src/asahi/compiler/agx_opcodes.py  | 4 
 src/asahi/compiler/agx_pack.c  | 6 +-
 src/asahi/compiler/agx_register_allocate.c | 2 +-
 3 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/src/asahi/compiler/agx_opcodes.py 
b/src/asahi/compiler/agx_opcodes.py
index b2e540bf4c8..b33c473f1ef 100644
--- a/src/asahi/compiler/agx_opcodes.py
+++ b/src/asahi/compiler/agx_opcodes.py
@@ -172,6 +172,10 @@ op("device_load",
 op("wait", (0x38, 0xFF, 2, _), dests = 0,
   can_eliminate = False, imms = [SCOREBOARD])
 
+# Essentially same encoding
+op("ld_tile", (0x49, 0x7F, 8, _), dests = 1, srcs = 0,
+  can_eliminate = False, imms = [FORMAT])
+
 op("st_tile", (0x09, 0x7F, 8, _), dests = 0, srcs = 1,
   can_eliminate = False, imms = [FORMAT])
 
diff --git a/src/asahi/compiler/agx_pack.c b/src/asahi/compiler/agx_pack.c
index 953c7af697e..cdf31224812 100644
--- a/src/asahi/compiler/agx_pack.c
+++ b/src/asahi/compiler/agx_pack.c
@@ -356,18 +356,22 @@ static void
 agx_pack_instr(struct util_dynarray *emission, agx_instr *I)
 {
switch (I->op) {
+   case AGX_OPCODE_LD_TILE:
case AGX_OPCODE_ST_TILE:
{
-  unsigned D = agx_pack_alu_dst(I->src[0]);
+  bool load = (I->op == AGX_OPCODE_LD_TILE);
+  unsigned D = agx_pack_alu_dst(load ? I->dest[0] : I->src[0]);
   unsigned rt = 0; /* TODO */
   unsigned mask = I->mask ?: 0xF;
   assert(mask < 0x10);
 
   uint64_t raw =
  0x09 |
+ (load ? (1 << 6) : 0) |
  ((uint64_t) (D & BITFIELD_MASK(8)) << 7) |
  ((uint64_t) (I->format) << 24) |
  ((uint64_t) (rt) << 32) |
+ (load ? (1ull << 35) : 0) |
  ((uint64_t) (mask) << 36) |
  ((uint64_t) 0x0380FC << 40) |
  (((uint64_t) (D >> 8)) << 60);
diff --git a/src/asahi/compiler/agx_register_allocate.c 
b/src/asahi/compiler/agx_register_allocate.c
index 5e4760328d9..6f9b90e0194 100644
--- a/src/asahi/compiler/agx_register_allocate.c
+++ b/src/asahi/compiler/agx_register_allocate.c
@@ -90,7 +90,7 @@ agx_ra(agx_context *ctx)
 unsigned size = ins->dest[d].size == AGX_SIZE_32 ? 2 : 1;
 if (size == 2 && usage & 1) usage++;
 unsigned v = usage;
-unsigned comps = (ins->op == AGX_OPCODE_LD_VARY || ins->op == 
AGX_OPCODE_DEVICE_LOAD || ins->op == AGX_OPCODE_TEXTURE_SAMPLE) ? 4 : 1; // 
todo systematic
+unsigned comps = (ins->op == AGX_OPCODE_LD_VARY || ins->op == 
AGX_OPCODE_DEVICE_LOAD || ins->op == AGX_OPCODE_TEXTURE_SAMPLE || ins->op == 
AGX_OPCODE_LD_TILE) ? 4 : 1; // todo systematic
 usage += comps * size;
 alloc[ins->dest[d].value] = v;
 ins->dest[d] = agx_replace_index(ins->dest[d], agx_register(v, 
ins->dest[d].size));

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Mesa (main): agx: Implement blend constant color sysvals

2021-05-09 Thread GitLab Mirror 
Module: Mesa
Branch: main
Commit: 06fe6651b3172eb56495a4cc863905d119c0fe76
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=06fe6651b3172eb56495a4cc863905d119c0fe76

Author: Alyssa Rosenzweig 
Date:   Tue May  4 22:37:15 2021 -0400

agx: Implement blend constant color sysvals

Signed-off-by: Alyssa Rosenzweig 
Part-of: 

---

 src/asahi/compiler/agx_compile.c | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/src/asahi/compiler/agx_compile.c b/src/asahi/compiler/agx_compile.c
index dd9b6320d48..34270b2e15e 100644
--- a/src/asahi/compiler/agx_compile.c
+++ b/src/asahi/compiler/agx_compile.c
@@ -236,6 +236,15 @@ agx_emit_load_ubo(agx_builder *b, nir_intrinsic_instr 
*instr)
return agx_wait(b, 0);
 }
 
+static agx_instr *
+agx_blend_const(agx_builder *b, agx_index dst, unsigned comp)
+{
+ agx_index val = agx_indexed_sysval(b->shader,
+   AGX_PUSH_BLEND_CONST, AGX_SIZE_32, comp * 2, 4 * 2);
+
+ return agx_mov_to(b, dst, val);
+}
+
 static agx_instr *
 agx_emit_intrinsic(agx_builder *b, nir_intrinsic_instr *instr)
 {
@@ -275,6 +284,11 @@ agx_emit_intrinsic(agx_builder *b, nir_intrinsic_instr 
*instr)
   case nir_intrinsic_load_vertex_id:
  return agx_mov_to(b, dst, agx_abs(agx_register(10, AGX_SIZE_32))); /* 
TODO: RA */
 
+  case nir_intrinsic_load_blend_const_color_r_float: return agx_blend_const(b, 
dst, 0);
+  case nir_intrinsic_load_blend_const_color_g_float: return agx_blend_const(b, 
dst, 1);
+  case nir_intrinsic_load_blend_const_color_b_float: return agx_blend_const(b, 
dst, 2);
+  case nir_intrinsic_load_blend_const_color_a_float: return agx_blend_const(b, 
dst, 3);
+
   default:
fprintf(stderr, "Unhandled intrinsic %s\n", 
nir_intrinsic_infos[instr->intrinsic].name);
unreachable("Unhandled intrinsic");

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Mesa (main): asahi: Add blend constant system value

2021-05-09 Thread GitLab Mirror 
Module: Mesa
Branch: main
Commit: d76ab2b5d67b1b157d9112c94cf6128d228fa4b5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d76ab2b5d67b1b157d9112c94cf6128d228fa4b5

Author: Alyssa Rosenzweig 
Date:   Tue May  4 22:33:35 2021 -0400

asahi: Add blend constant system value

Signed-off-by: Alyssa Rosenzweig 
Part-of: 

---

 src/asahi/compiler/agx_compile.h | 3 +++
 src/gallium/drivers/asahi/agx_uniforms.c | 6 ++
 2 files changed, 9 insertions(+)

diff --git a/src/asahi/compiler/agx_compile.h b/src/asahi/compiler/agx_compile.h
index 4b2670cfddd..f00434f573e 100644
--- a/src/asahi/compiler/agx_compile.h
+++ b/src/asahi/compiler/agx_compile.h
@@ -43,6 +43,9 @@ enum agx_push_type {
/* Push the content of a UBO */
AGX_PUSH_UBO_DATA = 7,
 
+   /* RGBA blend constant (FP32) */
+   AGX_PUSH_BLEND_CONST = 8,
+
/* Keep last */
AGX_PUSH_NUM_TYPES
 };
diff --git a/src/gallium/drivers/asahi/agx_uniforms.c 
b/src/gallium/drivers/asahi/agx_uniforms.c
index 936e976d0a8..7ef9ddfd413 100644
--- a/src/gallium/drivers/asahi/agx_uniforms.c
+++ b/src/gallium/drivers/asahi/agx_uniforms.c
@@ -84,6 +84,12 @@ agx_push_location_direct(struct agx_context *ctx, struct 
agx_push push,
   return ptr.gpu;
}
 
+   case AGX_PUSH_BLEND_CONST:
+   {
+  return agx_pool_upload_aligned(>pool, >blend_color,
+sizeof(ctx->blend_color), 8);
+   }
+
default:
   unreachable("todo: push more");
}

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Mesa (main): zink: make ZINK_INLINE_UNIFORMS more standardized in function

2021-05-09 Thread GitLab Mirror 
Module: Mesa
Branch: main
Commit: 0c2453bb59015c9cdd444d69d605c6bd28d78b50
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0c2453bb59015c9cdd444d69d605c6bd28d78b50

Author: Mike Blumenkrantz 
Date:   Tue Dec 29 13:30:24 2020 -0500

zink: make ZINK_INLINE_UNIFORMS more standardized in function

Reviewed-by: Joshua Ashton 
Part-of: 

---

 src/gallium/drivers/zink/zink_screen.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/drivers/zink/zink_screen.c 
b/src/gallium/drivers/zink/zink_screen.c
index b4bda46600d..27495265b8c 100644
--- a/src/gallium/drivers/zink/zink_screen.c
+++ b/src/gallium/drivers/zink/zink_screen.c
@@ -1624,7 +1624,7 @@ zink_internal_create_screen(const struct 
pipe_screen_config *config)
   screen->driconf.dual_color_blend_by_location = 
driQueryOptionb(config->options, "dual_color_blend_by_location");
   //screen->driconf.inline_uniforms = driQueryOptionb(config->options, 
"radeonsi_inline_uniforms");
 #endif
-   screen->driconf.inline_uniforms = !!getenv("ZINK_INLINE_UNIFORMS");
+   screen->driconf.inline_uniforms = 
debug_get_bool_option("ZINK_INLINE_UNIFORMS", false);
 
screen->total_video_mem = get_video_mem(screen);
if (!os_get_total_physical_memory(>total_mem))

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Mesa (main): zink: simplify samplerview surface creation

2021-05-09 Thread GitLab Mirror 
Module: Mesa
Branch: main
Commit: 3c1ecb93d32373c032024c60cff0b86126ab8ee0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3c1ecb93d32373c032024c60cff0b86126ab8ee0

Author: Mike Blumenkrantz 
Date:   Fri Apr  2 14:49:56 2021 -0400

zink: simplify samplerview surface creation

instead of manually creating the ivci, there's already a util function for
that which will handle everything

also only set layer info if there are multiple layers

Reviewed-by: Dave Airlie 
Part-of: 

---

 src/gallium/drivers/zink/zink_context.c | 43 +++--
 1 file changed, 9 insertions(+), 34 deletions(-)

diff --git a/src/gallium/drivers/zink/zink_context.c 
b/src/gallium/drivers/zink/zink_context.c
index 41b0872e4b8..45b98cabc31 100644
--- a/src/gallium/drivers/zink/zink_context.c
+++ b/src/gallium/drivers/zink/zink_context.c
@@ -404,23 +404,6 @@ zink_delete_sampler_state(struct pipe_context *pctx,
FREE(sampler);
 }
 
-static VkImageViewType
-image_view_type(enum pipe_texture_target target)
-{
-   switch (target) {
-   case PIPE_TEXTURE_1D: return VK_IMAGE_VIEW_TYPE_1D;
-   case PIPE_TEXTURE_1D_ARRAY: return VK_IMAGE_VIEW_TYPE_1D_ARRAY;
-   case PIPE_TEXTURE_2D: return VK_IMAGE_VIEW_TYPE_2D;
-   case PIPE_TEXTURE_2D_ARRAY: return VK_IMAGE_VIEW_TYPE_2D_ARRAY;
-   case PIPE_TEXTURE_CUBE: return VK_IMAGE_VIEW_TYPE_CUBE;
-   case PIPE_TEXTURE_CUBE_ARRAY: return VK_IMAGE_VIEW_TYPE_CUBE_ARRAY;
-   case PIPE_TEXTURE_3D: return VK_IMAGE_VIEW_TYPE_3D;
-   case PIPE_TEXTURE_RECT: return VK_IMAGE_VIEW_TYPE_2D;
-   default:
-  unreachable("unexpected target");
-   }
-}
-
 static VkComponentSwizzle
 component_mapping(enum pipe_swizzle swizzle)
 {
@@ -542,13 +525,17 @@ zink_create_sampler_view(struct pipe_context *pctx, 
struct pipe_resource *pres,
sampler_view->base.context = pctx;
 
if (state->target != PIPE_BUFFER) {
-  VkImageViewCreateInfo ivci = {};
-  ivci.sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO;
-  ivci.image = res->obj->image;
-  ivci.viewType = image_view_type(state->target);
+  VkImageViewCreateInfo ivci;
+
+  struct pipe_surface templ = {};
+  templ.u.tex.level = state->u.tex.first_level;
+  templ.format = state->format;
+  templ.u.tex.first_layer = state->u.tex.first_layer;
+  templ.u.tex.last_layer = state->u.tex.last_layer;
 
+  ivci = create_ivci(screen, res, , state->target);
+  ivci.subresourceRange.levelCount = state->u.tex.last_level - 
state->u.tex.first_level + 1;
   ivci.subresourceRange.aspectMask = 
sampler_aspect_from_format(state->format);
-  ivci.format = zink_get_format(screen, state->format);
   /* samplers for stencil aspects of packed formats need to always use 
stencil swizzle */
   if (ivci.subresourceRange.aspectMask & (VK_IMAGE_ASPECT_DEPTH_BIT | 
VK_IMAGE_ASPECT_STENCIL_BIT)) {
  ivci.components.r = 
component_mapping(clamp_zs_swizzle(sampler_view->base.swizzle_r));
@@ -573,18 +560,6 @@ zink_create_sampler_view(struct pipe_context *pctx, struct 
pipe_resource *pres,
   }
   assert(ivci.format);
 
-  ivci.subresourceRange.baseMipLevel = state->u.tex.first_level;
-  ivci.subresourceRange.levelCount = 1;
-  ivci.subresourceRange.baseArrayLayer = state->u.tex.first_layer;
-  ivci.subresourceRange.levelCount = state->u.tex.last_level - 
state->u.tex.first_level + 1;
-  ivci.subresourceRange.layerCount = state->u.tex.last_layer - 
state->u.tex.first_layer + 1;
-  ivci.viewType = zink_surface_clamp_viewtype(ivci.viewType, 
state->u.tex.first_layer, state->u.tex.last_layer, pres->array_size);
-
-  struct pipe_surface templ = {};
-  templ.u.tex.level = state->u.tex.first_level;
-  templ.format = state->format;
-  templ.u.tex.first_layer = state->u.tex.first_layer;
-  templ.u.tex.last_layer = state->u.tex.last_layer;
   sampler_view->image_view = (struct 
zink_surface*)zink_get_surface(zink_context(pctx), pres, , );
   err = !sampler_view->image_view;
} else {

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Mesa (main): zink: only set layer info for samplerviews if there are multiple layers

2021-05-09 Thread GitLab Mirror 
Module: Mesa
Branch: main
Commit: b715aaa5f1eb86e5d8af244b54979b2bdd1fd7f2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b715aaa5f1eb86e5d8af244b54979b2bdd1fd7f2

Author: Mike Blumenkrantz 
Date:   Fri Apr  2 14:51:17 2021 -0400

zink: only set layer info for samplerviews if there are multiple layers

fixes a bunch of validation errors

Reviewed-by: Dave Airlie 
Part-of: 

---

 src/gallium/drivers/zink/zink_context.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/zink/zink_context.c 
b/src/gallium/drivers/zink/zink_context.c
index 45b98cabc31..6da5d1b3dd0 100644
--- a/src/gallium/drivers/zink/zink_context.c
+++ b/src/gallium/drivers/zink/zink_context.c
@@ -530,8 +530,10 @@ zink_create_sampler_view(struct pipe_context *pctx, struct 
pipe_resource *pres,
   struct pipe_surface templ = {};
   templ.u.tex.level = state->u.tex.first_level;
   templ.format = state->format;
-  templ.u.tex.first_layer = state->u.tex.first_layer;
-  templ.u.tex.last_layer = state->u.tex.last_layer;
+  if (state->target != PIPE_TEXTURE_3D) {
+ templ.u.tex.first_layer = state->u.tex.first_layer;
+ templ.u.tex.last_layer = state->u.tex.last_layer;
+  }
 
   ivci = create_ivci(screen, res, , state->target);
   ivci.subresourceRange.levelCount = state->u.tex.last_level - 
state->u.tex.first_level + 1;

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Mesa (main): zink: add a target param to create_ivci()

2021-05-09 Thread GitLab Mirror 
Module: Mesa
Branch: main
Commit: b243b1d963657cdf7b27435bc0342f08080c391e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b243b1d963657cdf7b27435bc0342f08080c391e

Author: Mike Blumenkrantz 
Date:   Sat Apr  3 10:57:33 2021 -0400

zink: add a target param to create_ivci()

allow creating views of different types than the base resource

Reviewed-by: Dave Airlie 
Part-of: 

---

 src/gallium/drivers/zink/zink_surface.c | 9 +
 src/gallium/drivers/zink/zink_surface.h | 3 ++-
 2 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/src/gallium/drivers/zink/zink_surface.c 
b/src/gallium/drivers/zink/zink_surface.c
index 4cae6fd11ec..e61ccb2f3dd 100644
--- a/src/gallium/drivers/zink/zink_surface.c
+++ b/src/gallium/drivers/zink/zink_surface.c
@@ -34,13 +34,14 @@
 VkImageViewCreateInfo
 create_ivci(struct zink_screen *screen,
 struct zink_resource *res,
-const struct pipe_surface *templ)
+const struct pipe_surface *templ,
+enum pipe_texture_target target)
 {
VkImageViewCreateInfo ivci = {};
ivci.sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO;
ivci.image = res->obj->image;
 
-   switch (res->base.b.target) {
+   switch (target) {
case PIPE_TEXTURE_1D:
   ivci.viewType = VK_IMAGE_VIEW_TYPE_1D;
   break;
@@ -175,7 +176,7 @@ zink_create_surface(struct pipe_context *pctx,
 {
 
VkImageViewCreateInfo ivci = create_ivci(zink_screen(pctx->screen),
-zink_resource(pres), templ);
+zink_resource(pres), templ, 
pres->target);
if (pres->target == PIPE_TEXTURE_3D)
   ivci.viewType = VK_IMAGE_VIEW_TYPE_2D;
 
@@ -248,7 +249,7 @@ zink_rebind_surface(struct zink_context *ctx, struct 
pipe_surface **psurface)
if (surface->simage_view)
   return false;
VkImageViewCreateInfo ivci = create_ivci(screen,
-
zink_resource((*psurface)->texture), (*psurface));
+
zink_resource((*psurface)->texture), (*psurface), 
surface->base.texture->target);
uint32_t hash = hash_ivci();
 
simple_mtx_lock(>surface_mtx);
diff --git a/src/gallium/drivers/zink/zink_surface.h 
b/src/gallium/drivers/zink/zink_surface.h
index c8931ca32fe..4f29509835e 100644
--- a/src/gallium/drivers/zink/zink_surface.h
+++ b/src/gallium/drivers/zink/zink_surface.h
@@ -69,7 +69,8 @@ zink_context_surface_init(struct pipe_context *context);
 VkImageViewCreateInfo
 create_ivci(struct zink_screen *screen,
 struct zink_resource *res,
-const struct pipe_surface *templ);
+const struct pipe_surface *templ,
+enum pipe_texture_target target);
 
 struct pipe_surface *
 zink_get_surface(struct zink_context *ctx,

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Mesa (main): zink: clamp 3D surface viewtype to 2D only in the create_surface hook

2021-05-09 Thread GitLab Mirror 
Module: Mesa
Branch: main
Commit: 438f0b31e2780c1b3cf62559ec12efea7f8c25b0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=438f0b31e2780c1b3cf62559ec12efea7f8c25b0

Author: Mike Blumenkrantz 
Date:   Fri Apr  2 14:53:31 2021 -0400

zink: clamp 3D surface viewtype to 2D only in the create_surface hook

this is only applicable to things that go through the hook, not for internal
surfaces

Reviewed-by: Dave Airlie 
Part-of: 

---

 src/gallium/drivers/zink/zink_surface.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/zink/zink_surface.c 
b/src/gallium/drivers/zink/zink_surface.c
index 568645f4508..4cae6fd11ec 100644
--- a/src/gallium/drivers/zink/zink_surface.c
+++ b/src/gallium/drivers/zink/zink_surface.c
@@ -67,7 +67,7 @@ create_ivci(struct zink_screen *screen,
   break;
 
case PIPE_TEXTURE_3D:
-  ivci.viewType = VK_IMAGE_VIEW_TYPE_2D;
+  ivci.viewType = VK_IMAGE_VIEW_TYPE_3D;
   break;
 
default:
@@ -176,6 +176,8 @@ zink_create_surface(struct pipe_context *pctx,
 
VkImageViewCreateInfo ivci = create_ivci(zink_screen(pctx->screen),
 zink_resource(pres), templ);
+   if (pres->target == PIPE_TEXTURE_3D)
+  ivci.viewType = VK_IMAGE_VIEW_TYPE_2D;
 
return zink_get_surface(zink_context(pctx), pres, templ, );
 }

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Mesa (main): zink: remove compute cruft from resource mapping

2021-05-09 Thread GitLab Mirror 
Module: Mesa
Branch: main
Commit: 9e5d927d22203e0dc22aa9b9381e6a9b64500048
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9e5d927d22203e0dc22aa9b9381e6a9b64500048

Author: Mike Blumenkrantz 
Date:   Mon Apr 19 16:34:56 2021 -0400

zink: remove compute cruft from resource mapping

this used to sync the compute batch, now it does nothing

Reviewed-by: Dave Airlie 
Part-of: 

---

 src/gallium/drivers/zink/zink_resource.c | 17 +++--
 1 file changed, 3 insertions(+), 14 deletions(-)

diff --git a/src/gallium/drivers/zink/zink_resource.c 
b/src/gallium/drivers/zink/zink_resource.c
index 7817003befc..80908a2b195 100644
--- a/src/gallium/drivers/zink/zink_resource.c
+++ b/src/gallium/drivers/zink/zink_resource.c
@@ -83,14 +83,6 @@ get_resource_usage(struct zink_resource *res)
return batch_uses;
 }
 
-static void
-resource_sync_reads(struct zink_context *ctx, struct zink_resource *res)
-{
-   uint32_t reads = p_atomic_read(>obj->reads.usage);
-   assert(reads);
-   zink_wait_on_batch(ctx, reads);
-}
-
 static void
 resource_sync_writes_from_batch_usage(struct zink_context *ctx, struct 
zink_resource *res)
 {
@@ -1043,14 +1035,11 @@ zink_transfer_map(struct pipe_context *pctx,
  base = map_resource(screen, res);
  if (!base)
 return NULL;
- /* special case compute reads since they aren't handled by 
zink_fence_wait() */
- if (zink_resource_has_usage(res, ZINK_RESOURCE_ACCESS_READ))
-resource_sync_reads(ctx, res);
  if (zink_resource_has_usage(res, ZINK_RESOURCE_ACCESS_RW)) {
-if (usage & PIPE_MAP_READ)
-   resource_sync_writes_from_batch_usage(ctx, res);
-else
+if (usage & PIPE_MAP_WRITE)
zink_fence_wait(pctx);
+else
+   resource_sync_writes_from_batch_usage(ctx, res);
  }
  VkImageSubresource isr = {
 res->aspect,

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Mesa (main): zink: break out draw dispatch into separate functions

2021-05-09 Thread GitLab Mirror 
Module: Mesa
Branch: main
Commit: 4ebae25e17fc8eef20b80abf33c93843f1d45f56
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4ebae25e17fc8eef20b80abf33c93843f1d45f56

Author: Mike Blumenkrantz 
Date:   Mon Jan 18 16:00:19 2021 -0500

zink: break out draw dispatch into separate functions

this is much easier to read and is going to greatly simplify the eventual
multidraw implementation which will be dropped in

also it allows moving conditionals outside of loops to very slightly improve
drawoverhead performance (with multidraw)

Reviewed-by: Dave Airlie 
Part-of: 

---

 src/gallium/drivers/zink/zink_draw.c | 116 ---
 1 file changed, 93 insertions(+), 23 deletions(-)

diff --git a/src/gallium/drivers/zink/zink_draw.c 
b/src/gallium/drivers/zink/zink_draw.c
index 59682a9f23b..26f261cc91d 100644
--- a/src/gallium/drivers/zink/zink_draw.c
+++ b/src/gallium/drivers/zink/zink_draw.c
@@ -268,14 +268,89 @@ restart_supported(enum pipe_prim_type mode)
 return mode == PIPE_PRIM_LINE_STRIP || mode == PIPE_PRIM_TRIANGLE_STRIP || 
mode == PIPE_PRIM_TRIANGLE_FAN;
 }
 
-static void
+ALWAYS_INLINE static void
 update_drawid(struct zink_context *ctx, unsigned draw_id)
 {
-   struct zink_batch *batch = >batch;
-   if (ctx->drawid_broken) {
-  vkCmdPushConstants(batch->state->cmdbuf, ctx->curr_program->base.layout, 
VK_SHADER_STAGE_VERTEX_BIT,
- offsetof(struct zink_gfx_push_constant, draw_id), 
sizeof(unsigned),
- _id);
+   vkCmdPushConstants(ctx->batch.state->cmdbuf, 
ctx->curr_program->base.layout, VK_SHADER_STAGE_VERTEX_BIT,
+  offsetof(struct zink_gfx_push_constant, draw_id), 
sizeof(unsigned),
+  _id);
+}
+
+ALWAYS_INLINE static void
+draw_indexed_need_index_buffer_unref(struct zink_context *ctx,
+ const struct pipe_draw_info *dinfo,
+ const struct pipe_draw_start_count_bias *draws,
+ unsigned num_draws,
+ unsigned draw_id,
+ bool needs_drawid)
+{
+   VkCommandBuffer cmdbuf = ctx->batch.state->cmdbuf;
+   if (dinfo->increment_draw_id && needs_drawid) {
+  for (unsigned i = 0; i < num_draws; i++) {
+ update_drawid(ctx, draw_id);
+ vkCmdDrawIndexed(cmdbuf,
+draws[i].count, dinfo->instance_count,
+0, draws[i].index_bias, dinfo->start_instance);
+ draw_id++;
+  }
+   } else {
+  if (needs_drawid)
+ update_drawid(ctx, draw_id);
+  for (unsigned i = 0; i < num_draws; i++)
+ vkCmdDrawIndexed(cmdbuf,
+draws[i].count, dinfo->instance_count,
+0, draws[i].index_bias, dinfo->start_instance);
+
+   }
+}
+
+ALWAYS_INLINE static void
+draw_indexed(struct zink_context *ctx,
+ const struct pipe_draw_info *dinfo,
+ const struct pipe_draw_start_count_bias *draws,
+ unsigned num_draws,
+ unsigned draw_id,
+ bool needs_drawid)
+{
+   VkCommandBuffer cmdbuf = ctx->batch.state->cmdbuf;
+   if (dinfo->increment_draw_id && needs_drawid) {
+  for (unsigned i = 0; i < num_draws; i++) {
+ update_drawid(ctx, draw_id);
+ vkCmdDrawIndexed(cmdbuf,
+draws[i].count, dinfo->instance_count,
+draws[i].start, draws[i].index_bias, dinfo->start_instance);
+ draw_id++;
+  }
+   } else {
+  if (needs_drawid)
+ update_drawid(ctx, draw_id);
+  for (unsigned i = 0; i < num_draws; i++)
+ vkCmdDrawIndexed(cmdbuf,
+draws[i].count, dinfo->instance_count,
+draws[i].start, draws[i].index_bias, dinfo->start_instance);
+   }
+}
+
+ALWAYS_INLINE static void
+draw(struct zink_context *ctx,
+ const struct pipe_draw_info *dinfo,
+ const struct pipe_draw_start_count_bias *draws,
+ unsigned num_draws,
+ unsigned draw_id,
+ bool needs_drawid)
+{
+   VkCommandBuffer cmdbuf = ctx->batch.state->cmdbuf;
+   if (dinfo->increment_draw_id && needs_drawid) {
+  for (unsigned i = 0; i < num_draws; i++) {
+ update_drawid(ctx, draw_id);
+ vkCmdDraw(cmdbuf, draws[i].count, dinfo->instance_count, 
draws[i].start, dinfo->start_instance);
+ draw_id++;
+  }
+   } else {
+  if (needs_drawid)
+ update_drawid(ctx, draw_id);
+  for (unsigned i = 0; i < num_draws; i++)
+ vkCmdDraw(cmdbuf, draws[i].count, dinfo->instance_count, 
draws[i].start, dinfo->start_instance);
}
 }
 
@@ -551,6 +626,7 @@ zink_draw_vbo(struct pipe_context *pctx,
}
 
unsigned draw_id = drawid_offset;
+   bool needs_drawid = ctx->drawid_broken;
if (dinfo->index_size > 0) {
   VkIndexType index_type;
   unsigned index_size = dinfo->index_size;
@@ -576,7 +652,8 @@ zink_draw_vbo(struct pipe_context *pctx,
   zink_batch_reference_resource_rw(batch, res, false);
   if (dindirect && dindirect->buffer) {

Mesa (main): zink: fix texture barriers for real this time

2021-05-09 Thread GitLab Mirror 
Module: Mesa
Branch: main
Commit: 25ab2347f8f70b582e9a24a9981f04aff54e131c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=25ab2347f8f70b582e9a24a9981f04aff54e131c

Author: Mike Blumenkrantz 
Date:   Thu Apr  8 12:38:06 2021 -0400

zink: fix texture barriers for real this time

according to spec, this is supposed to handle fragment shader fetch
from previous draw output, not color output readback from previous
color output write

Reviewed-by: Dave Airlie 
Part-of: 

---

 src/gallium/drivers/zink/zink_context.c | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/gallium/drivers/zink/zink_context.c 
b/src/gallium/drivers/zink/zink_context.c
index 899761814c0..5b4b7dadbb9 100644
--- a/src/gallium/drivers/zink/zink_context.c
+++ b/src/gallium/drivers/zink/zink_context.c
@@ -1947,11 +1947,11 @@ zink_texture_barrier(struct pipe_context *pctx, 
unsigned flags)
   dmb.sType = VK_STRUCTURE_TYPE_MEMORY_BARRIER;
   dmb.pNext = NULL;
   dmb.srcAccessMask = VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT;
-  dmb.dstAccessMask = VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT;
+  dmb.dstAccessMask = VK_ACCESS_SHADER_READ_BIT;
   vkCmdPipelineBarrier(
  ctx->batch.state->cmdbuf,
  VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT | 
VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT,
- VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT | 
VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT,
+ VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT,
  0,
  1, ,
  0, NULL,
@@ -1959,17 +1959,17 @@ zink_texture_barrier(struct pipe_context *pctx, 
unsigned flags)
   );
} else {
   bmb.srcAccessMask |= VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT;
-  bmb.dstAccessMask |= VK_ACCESS_COLOR_ATTACHMENT_READ_BIT;
+  bmb.dstAccessMask |= VK_ACCESS_SHADER_READ_BIT;
}
if (ctx->framebuffer->state.num_attachments > 1) {
   bmb.srcAccessMask |= VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT;
-  bmb.dstAccessMask |= VK_ACCESS_COLOR_ATTACHMENT_READ_BIT;
+  bmb.dstAccessMask |= VK_ACCESS_SHADER_READ_BIT;
}
if (bmb.srcAccessMask)
   vkCmdPipelineBarrier(
  ctx->batch.state->cmdbuf,
  VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT,
- VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT,
+ VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT,
  0,
  1, ,
  0, NULL,

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Mesa (main): zink: rework memory_barrier hook again (third time's the charm)

2021-05-09 Thread GitLab Mirror 
Module: Mesa
Branch: main
Commit: 564519dc84c527a4f6e952a5f0374008d26c5ec0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=564519dc84c527a4f6e952a5f0374008d26c5ec0

Author: Mike Blumenkrantz 
Date:   Wed Apr  7 11:00:06 2021 -0400

zink: rework memory_barrier hook again (third time's the charm)

this improves granularity for the barriers and is more in line with the
spec for glMemoryBarrier

Reviewed-by: Dave Airlie 
Part-of: 

---

 src/gallium/drivers/zink/zink_context.c | 47 +++--
 1 file changed, 22 insertions(+), 25 deletions(-)

diff --git a/src/gallium/drivers/zink/zink_context.c 
b/src/gallium/drivers/zink/zink_context.c
index 5b4b7dadbb9..6b180d932fb 100644
--- a/src/gallium/drivers/zink/zink_context.c
+++ b/src/gallium/drivers/zink/zink_context.c
@@ -1978,14 +1978,14 @@ zink_texture_barrier(struct pipe_context *pctx, 
unsigned flags)
 }
 
 static inline void
-mem_barrier(struct zink_batch *batch, VkPipelineStageFlags stage, 
VkAccessFlags src, VkAccessFlags dst)
+mem_barrier(struct zink_batch *batch, VkPipelineStageFlags src_stage, 
VkPipelineStageFlags dst_stage, VkAccessFlags src, VkAccessFlags dst)
 {
VkMemoryBarrier mb;
mb.sType = VK_STRUCTURE_TYPE_MEMORY_BARRIER;
mb.pNext = NULL;
mb.srcAccessMask = src;
mb.dstAccessMask = dst;
-   vkCmdPipelineBarrier(batch->state->cmdbuf, stage, stage, 0, 1, , 0, 
NULL, 0, NULL);
+   vkCmdPipelineBarrier(batch->state->cmdbuf, src_stage, dst_stage, 0, 1, , 
0, NULL, 0, NULL);
 }
 
 static void
@@ -2010,47 +2010,44 @@ zink_memory_barrier(struct pipe_context *pctx, unsigned 
flags)
   /* TODO: this should flush all persistent buffers in use as I think */
}
 
-   if (flags & (PIPE_BARRIER_SHADER_BUFFER | PIPE_BARRIER_TEXTURE |
-PIPE_BARRIER_IMAGE | PIPE_BARRIER_GLOBAL_BUFFER))
-  mem_barrier(batch, all_flags, VK_ACCESS_SHADER_READ_BIT | 
VK_ACCESS_SHADER_WRITE_BIT,
-VK_ACCESS_SHADER_READ_BIT | 
VK_ACCESS_SHADER_WRITE_BIT);
+   if (flags & (PIPE_BARRIER_TEXTURE | PIPE_BARRIER_SHADER_BUFFER | 
PIPE_BARRIER_IMAGE))
+  mem_barrier(batch, all_flags, all_flags, VK_ACCESS_SHADER_WRITE_BIT, 
VK_ACCESS_SHADER_READ_BIT);
 
-   if (flags & (PIPE_BARRIER_QUERY_BUFFER | PIPE_BARRIER_IMAGE))
-  mem_barrier(batch, VK_PIPELINE_STAGE_TRANSFER_BIT,
-  VK_ACCESS_TRANSFER_READ_BIT | VK_ACCESS_TRANSFER_WRITE_BIT,
-  VK_ACCESS_TRANSFER_READ_BIT | VK_ACCESS_TRANSFER_WRITE_BIT);
+   if (flags & PIPE_BARRIER_QUERY_BUFFER)
+  mem_barrier(batch, all_flags, VK_PIPELINE_STAGE_TRANSFER_BIT,
+  VK_ACCESS_SHADER_WRITE_BIT, VK_ACCESS_TRANSFER_WRITE_BIT | 
VK_ACCESS_TRANSFER_READ_BIT);
 
if (flags & PIPE_BARRIER_VERTEX_BUFFER)
-  mem_barrier(batch, VK_PIPELINE_STAGE_VERTEX_INPUT_BIT,
-  VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT,
+  mem_barrier(batch, all_flags, VK_PIPELINE_STAGE_VERTEX_INPUT_BIT,
+  VK_ACCESS_SHADER_WRITE_BIT,
   VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT);
 
if (flags & PIPE_BARRIER_INDEX_BUFFER)
-  mem_barrier(batch, VK_PIPELINE_STAGE_VERTEX_INPUT_BIT,
-  VK_ACCESS_INDEX_READ_BIT,
+  mem_barrier(batch, all_flags, VK_PIPELINE_STAGE_VERTEX_INPUT_BIT,
+  VK_ACCESS_SHADER_WRITE_BIT,
   VK_ACCESS_INDEX_READ_BIT);
 
-   if (flags & (PIPE_BARRIER_CONSTANT_BUFFER | PIPE_BARRIER_IMAGE))
-  mem_barrier(batch, all_flags,
-  VK_ACCESS_UNIFORM_READ_BIT,
+   if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
+  mem_barrier(batch, all_flags, all_flags,
+  VK_ACCESS_SHADER_WRITE_BIT,
   VK_ACCESS_UNIFORM_READ_BIT);
 
if (flags & PIPE_BARRIER_INDIRECT_BUFFER)
-  mem_barrier(batch, VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT,
-  VK_ACCESS_INDIRECT_COMMAND_READ_BIT,
+  mem_barrier(batch, all_flags, VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT,
+  VK_ACCESS_SHADER_WRITE_BIT,
   VK_ACCESS_INDIRECT_COMMAND_READ_BIT);
 
if (flags & PIPE_BARRIER_FRAMEBUFFER) {
-  mem_barrier(batch, VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT,
-  VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT,
-  VK_ACCESS_COLOR_ATTACHMENT_READ_BIT);
-  mem_barrier(batch, VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT,
+  mem_barrier(batch, all_flags, 
VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT,
+  VK_ACCESS_SHADER_WRITE_BIT,
+  VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT | 
VK_ACCESS_COLOR_ATTACHMENT_READ_BIT);
+  mem_barrier(batch, all_flags, VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT,
   VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT,
   VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT);
}
if (flags & PIPE_BARRIER_STREAMOUT_BUFFER)
-  mem_barrier(batch, VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |