Mesa (master): intel: Refactor intel_map_renderbuffer()
Module: Mesa
Branch: master
Commit: f911cac7a7a8ebcad711587200c7f66ab61d1ccf
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f911cac7a7a8ebcad711587200c7f66ab61d1ccf
Author: Chad Versace chad.vers...@linux.intel.com
Date: Tue Nov 8 18:17:33 2011 -0800
intel: Refactor intel_map_renderbuffer()
The function already implements 3 cases (map through GTT, blit to
a temporary, and detile stencil buffer to temporary), and a 4th will be
added soon: scatter/gather for depthstencil buffers using separate
stencil. For sanity's sake, this factors each case out into its own
function.
Reviewed-by: Eric Anholt e...@anholt.net
Signed-off-by: Chad Versace chad.vers...@linux.intel.com
---
src/mesa/drivers/dri/intel/intel_fbo.c | 390 +---
1 files changed, 256 insertions(+), 134 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c
b/src/mesa/drivers/dri/intel/intel_fbo.c
index 123dafe..f24f976 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.c
+++ b/src/mesa/drivers/dri/intel/intel_fbo.c
@@ -85,25 +85,25 @@ intel_delete_renderbuffer(struct gl_renderbuffer *rb)
free(irb);
}
+/**
+ * \brief Map a renderbuffer through the GTT.
+ *
+ * \see intel_map_renderbuffer()
+ */
static void
-intel_map_renderbuffer(struct gl_context *ctx,
- struct gl_renderbuffer *rb,
- GLuint x, GLuint y, GLuint w, GLuint h,
- GLbitfield mode,
- GLubyte **out_map,
- GLint *out_stride)
+intel_map_renderbuffer_gtt(struct gl_context *ctx,
+ struct gl_renderbuffer *rb,
+ GLuint x, GLuint y, GLuint w, GLuint h,
+ GLbitfield mode,
+ GLubyte **out_map,
+ GLint *out_stride)
{
struct intel_context *intel = intel_context(ctx);
struct intel_renderbuffer *irb = intel_renderbuffer(rb);
GLubyte *map;
int stride, flip_stride;
- /* We sometimes get called with this by our intel_span.c usage. */
- if (!irb-region) {
- *out_map = NULL;
- *out_stride = 0;
- return;
- }
+ assert(irb-region);
irb-map_mode = mode;
irb-map_x = x;
@@ -113,100 +113,6 @@ intel_map_renderbuffer(struct gl_context *ctx,
stride = irb-region-pitch * irb-region-cpp;
- if (rb-Format == MESA_FORMAT_S8) {
- GLuint pix_x, pix_y;
- uint8_t *tiled_s8_map, *untiled_s8_map;
-
- /* Flip the Y axis for the default framebuffer. */
- int y_flip = (rb-Name == 0) ? -1 : 1;
- int y_bias = (rb-Name == 0) ? (2 * irb-region-height - 1) : 0;
-
- /* Perform W-tile deswizzling for stencil buffers into a temporary. */
- stride = w;
- irb-map_buffer = malloc(stride * h);
- untiled_s8_map = irb-map_buffer;
-
- tiled_s8_map = intel_region_map(intel, irb-region, mode);
-
- for (pix_y = 0; pix_y h; pix_y++) {
-for (pix_x = 0; pix_x w; pix_x++) {
- GLuint flipped_y = y_flip * (y + pix_y) + y_bias;
- intptr_t offset = intel_offset_S8(irb-region-pitch,
- x + pix_x,
- flipped_y);
-
- untiled_s8_map[pix_y * stride + pix_x] = tiled_s8_map[offset];
-}
- }
- *out_map = untiled_s8_map;
- *out_stride = stride;
-
- DBG(%s: rb %d (%s) s8 detiled mapped: (%d, %d) (%dx%d) - %p/%d\n,
- __FUNCTION__, rb-Name, _mesa_get_format_name(rb-Format),
- x, y, w, h, *out_map, *out_stride);
-
- return;
- } else if (intel-gen = 6
- !(mode GL_MAP_WRITE_BIT)
- irb-region-tiling == I915_TILING_X) {
- int dst_stride = ALIGN(w * irb-region-cpp, 4);
- int src_x, src_y;
-
- /* On gen6+, we have LLC sharing, which means we can get high-performance
- * access to linear-mapped buffers. So, blit out a tiled buffer (if
- * possible, which it isn't really for Y tiling) to a temporary BO and
- * return a map of that.
- */
-
- if (rb-Name) {
-src_x = x + irb-draw_x;
-src_y = y + irb-draw_y;
- } else {
-src_x = x;
-src_y = irb-region-height - y - h;
- }
-
- irb-map_bo = drm_intel_bo_alloc(intel-bufmgr, MapRenderbuffer() temp,
- dst_stride * h, 4096);
-
- /* We don't do the flip in the blit, because it's always so tricky to get
- * right.
- */
- if (irb-map_bo
- intelEmitCopyBlit(intel,
- irb-region-cpp,
- irb-region-pitch, irb-region-bo,
- 0, irb-region-tiling,
- dst_stride / irb-region-cpp, irb-map_bo,
- 0, I915_TILING_NONE,
- src_x, src_y,
- 0, 0,
- w, h,
- GL_COPY
Mesa (master): intel: Fix intel_unmap_renderbuffer_s8()
Module: Mesa Branch: master Commit: 87d6b359745b6b2c94d1c852ce27e2879d4bec56 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=87d6b359745b6b2c94d1c852ce27e2879d4bec56 Author: Chad Versace chad.vers...@linux.intel.com Date: Thu Nov 10 11:04:17 2011 -0800 intel: Fix intel_unmap_renderbuffer_s8() When gathering the temporary buffer's pixles into the gem buffer, we had the two buffers juxtaposed. Oops. Fixes the following Piglit tests on gen7: general/GL_SELECT - alpha-test enabled general/GL_SELECT - depth-test enabled general/GL_SELECT - no test function general/GL_SELECT - scissor-test enabled general/GL_SELECT - stencil-test enabled Fixes SIGABRT in Piglit tests EXT_framebuffer_object/fbo-stencil-* on gen7. Reviewed-by: Eric Anholt e...@anholt.net Signed-off-by: Chad Versace chad.vers...@linux.intel.com --- src/mesa/drivers/dri/intel/intel_fbo.c |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c b/src/mesa/drivers/dri/intel/intel_fbo.c index f24f976..8bda7ff 100644 --- a/src/mesa/drivers/dri/intel/intel_fbo.c +++ b/src/mesa/drivers/dri/intel/intel_fbo.c @@ -349,8 +349,8 @@ intel_unmap_renderbuffer_s8(struct gl_context *ctx, /* The temporary buffer was written to, so we must copy its pixels into * the real buffer. */ - uint8_t *tiled_s8_map = irb-map_buffer; - uint8_t *untiled_s8_map = irb-region-bo-virtual; + uint8_t *untiled_s8_map = irb-map_buffer; + uint8_t *tiled_s8_map = irb-region-bo-virtual; /* Flip the Y axis for the default framebuffer. */ int y_flip = (rb-Name == 0) ? -1 : 1; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel: Fix software detiling of system stencil buffers
Module: Mesa
Branch: master
Commit: 5365ba19db8e9d714604bb63f037800ba2ff2f4d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5365ba19db8e9d714604bb63f037800ba2ff2f4d
Author: Chad Versace chad.vers...@linux.intel.com
Date: Thu Nov 10 18:39:25 2011 -0800
intel: Fix software detiling of system stencil buffers
If a window system stencil buffer had a region with odd height, then the
calculated y offset needed for software detiling was off by one. The bug
existed in intel_{map,unmap}_renderbuffer_s8() and in the intel_span.c
accessors.
Fixes the following Piglit tests on gen7:
general/depthstencil-default_fb-readpixels-24_8
general/depthstencil-default_fb-readpixels-FLOAT-and-USHORT
Fixes SIGABRT in the following Piglit tests on gen7:
general/depthstencil-default_fb-blit
general/depthstencil-default_fb-copypixels
general/depthstencil-default_fb-drawpixels-24_8
general/depthstencil-default_fb-drawpixels-FLOAT-and-USHORT
Reviewed-by: Eric Anholt e...@anholt.net
Signed-off-by: Chad Versace chad.vers...@linux.intel.com
---
src/mesa/drivers/dri/intel/intel_fbo.c |6 --
src/mesa/drivers/dri/intel/intel_span.c |4 ++--
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c
b/src/mesa/drivers/dri/intel/intel_fbo.c
index 8bda7ff..2a78edf 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.c
+++ b/src/mesa/drivers/dri/intel/intel_fbo.c
@@ -267,8 +267,9 @@ intel_map_renderbuffer_s8(struct gl_context *ctx,
irb-map_h = h;
/* Flip the Y axis for the default framebuffer. */
+ int region_h = irb-region-height;
int y_flip = (rb-Name == 0) ? -1 : 1;
- int y_bias = (rb-Name == 0) ? (2 * irb-region-height - 1) : 0;
+ int y_bias = (rb-Name == 0) ? (region_h * 2 + region_h % 2 - 1) : 0;
irb-map_buffer = malloc(w * h);
untiled_s8_map = irb-map_buffer;
@@ -353,8 +354,9 @@ intel_unmap_renderbuffer_s8(struct gl_context *ctx,
uint8_t *tiled_s8_map = irb-region-bo-virtual;
/* Flip the Y axis for the default framebuffer. */
+ int region_h = irb-region-height;
int y_flip = (rb-Name == 0) ? -1 : 1;
- int y_bias = (rb-Name == 0) ? (2 * irb-region-height - 1) : 0;
+ int y_bias = (rb-Name == 0) ? (region_h * 2 + region_h % 2 - 1) : 0;
for (uint32_t pix_y = 0; pix_y irb-map_h; pix_y++) {
for (uint32_t pix_x = 0; pix_x irb-map_w; pix_x++) {
diff --git a/src/mesa/drivers/dri/intel/intel_span.c
b/src/mesa/drivers/dri/intel/intel_span.c
index 478aec8..271d2e1 100644
--- a/src/mesa/drivers/dri/intel/intel_span.c
+++ b/src/mesa/drivers/dri/intel/intel_span.c
@@ -141,10 +141,10 @@ intel_set_span_functions(struct intel_context *intel,
struct intel_renderbuffer *irb = intel_renderbuffer(rb);\
uint8_t *buf = irb-region-bo-virtual;\
unsigned stride = irb-region-pitch; \
- unsigned height = 2 * irb-region-height; \
+ unsigned height = irb-region-height; \
bool flip = rb-Name == 0; \
int y_scale = flip ? -1 : 1;
\
- int y_bias = flip ? (height - 1) : 0; \
+ int y_bias = flip ? (height * 2 + height % 2 - 1) : 0; \
#undef Y_FLIP
#define Y_FLIP(y) (y_scale * (y) + y_bias)
___
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Mesa (master): intel: Fix intel_map_renderbuffer() for depthstencil buffers with separate stencil
Module: Mesa
Branch: master
Commit: cc502aa9419a6fb127b264dbb131c786281cb8c7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cc502aa9419a6fb127b264dbb131c786281cb8c7
Author: Chad Versace chad.vers...@linux.intel.com
Date: Sun Nov 13 17:36:30 2011 -0800
intel: Fix intel_map_renderbuffer() for depthstencil buffers with separate
stencil
For a depthstencil buffer with separate stencil,
intel_renderbuffer::region is null. (The regions are kept in hidden depth
and stencil buffers). Since the region is null, intel_map_renderbuffer()
assumed there was no data and returned a null map pointer, which in turn
was dereferenced (!) by MapRenderbuffer's caller.
This patch fixes intel_map_renderbuffer() to map the hidden depth buffer
through the GTT and return that as the mapped pointer. Also, the stencil
bits are scattered and gathered when needed.
Fixes the following Piglit tests on gen7:
fbo/fbo-readpixels-depth-formats
hiz/hiz-depth-read-fbo-d24s8
hiz/hiz-stencil-read-fbo-d24s8
EXT_packed_depth_stencil/fbo-clear-formats
EXT_packed_depth_stencil/fbo-depth-GL_DEPTH24_STENCIL8-blit
EXT_packed_depth_stencil/fbo-depth-GL_DEPTH24_STENCIL8-drawpixels
EXT_packed_depth_stencil/fbo-depth-GL_DEPTH24_STENCIL8-readpixels
EXT_packed_depth_stencil/fbo-depthstencil-GL_DEPTH24_STENCIL8-readpixels-24_8
EXT_packed_depth_stencil/fbo-depthstencil-GL_DEPTH24_STENCIL8-readpixels-FLOAT-and-USHORT
EXT_packed_depth_stencil/fbo-stencil-GL_DEPTH24_STENCIL8-readpixels
Reviewed-by: Eric Anholt e...@anholt.net
Signed-off-by: Chad Versace chad.vers...@linux.intel.com
---
src/mesa/drivers/dri/intel/intel_fbo.c | 150 +++-
1 files changed, 149 insertions(+), 1 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c
b/src/mesa/drivers/dri/intel/intel_fbo.c
index 2a78edf..dbd5163 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.c
+++ b/src/mesa/drivers/dri/intel/intel_fbo.c
@@ -294,6 +294,91 @@ intel_map_renderbuffer_s8(struct gl_context *ctx,
}
/**
+ * \brief Map a depthstencil buffer with separate stencil.
+ *
+ * A depthstencil renderbuffer, if using separate stencil, consists of a depth
+ * renderbuffer and a hidden stencil renderbuffer. This function maps the
+ * depth buffer, whose format is MESA_FORMAT_X8_Z24, through the GTT and
+ * returns that as the mapped pointer. The caller need not be aware of the
+ * hidden stencil buffer and may safely assume that the mapped pointer points
+ * to a MESA_FORMAT_S8_Z24 buffer
+ *
+ * The consistency between the depth buffer's S8 bits and the hidden stencil
+ * buffer is managed within intel_map_renderbuffer() and
+ * intel_unmap_renderbuffer() by scattering or gathering the stencil bits
+ * according to the map mode.
+ *
+ * \see intel_map_renderbuffer()
+ * \see intel_unmap_renderbuffer_separate_s8z24()
+ */
+static void
+intel_map_renderbuffer_separate_s8z24(struct gl_context *ctx,
+ struct gl_renderbuffer *rb,
+ GLuint x, GLuint y, GLuint w, GLuint h,
+ GLbitfield mode,
+ GLubyte **out_map,
+ GLint *out_stride)
+{
+ struct intel_context *intel = intel_context(ctx);
+ struct intel_renderbuffer *irb = intel_renderbuffer(rb);
+
+ GLbitfield adjusted_mode;
+
+ uint8_t *s8z24_map;
+ int32_t s8z24_stride;
+
+ assert(rb-Name != 0);
+ assert(rb-Format == MESA_FORMAT_S8_Z24);
+ assert(irb-wrapped_depth != NULL);
+ assert(irb-wrapped_stencil != NULL);
+
+ irb-map_mode = mode;
+ irb-map_x = x;
+ irb-map_y = y;
+ irb-map_w = w;
+ irb-map_h = h;
+
+ if (mode GL_MAP_READ_BIT) {
+ /* Since the caller may read the stencil bits, we must copy the stencil
+ * buffer's contents into the depth buffer. This necessitates that the
+ * depth buffer be mapped in write mode.
+ */
+ adjusted_mode = mode | GL_MAP_WRITE_BIT;
+ } else {
+ adjusted_mode = mode;
+ }
+
+ intel_map_renderbuffer_gtt(ctx, irb-wrapped_depth,
+ x, y, w, h, adjusted_mode,
+ s8z24_map, s8z24_stride);
+
+ if (mode GL_MAP_READ_BIT) {
+ struct intel_renderbuffer *s8_irb;
+ uint8_t *s8_map;
+
+ s8_irb = intel_renderbuffer(irb-wrapped_stencil);
+ s8_map = intel_region_map(intel, s8_irb-region, GL_MAP_READ_BIT);
+
+ for (uint32_t pix_y = 0; pix_y h; ++pix_y) {
+for (uint32_t pix_x = 0; pix_x w; ++pix_x) {
+ ptrdiff_t s8_offset = intel_offset_S8(s8_irb-region-pitch,
+ x + pix_x,
+ y + pix_y);
+ ptrdiff_t s8z24_offset = pix_y * s8z24_stride
+ + pix_x * 4
+ + 3;
+ s8z24_map[s8z24_offset] = s8_map[s8_offset
Mesa (master): intel: Simplify stencil detiling arithmetic
Module: Mesa
Branch: master
Commit: dc4c3a31c64aae2c3d76ccbd5bf54d04a1d5d041
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=dc4c3a31c64aae2c3d76ccbd5bf54d04a1d5d041
Author: Chad Versace chad.vers...@linux.intel.com
Date: Tue Nov 15 07:10:18 2011 -0800
intel: Simplify stencil detiling arithmetic
When calculating the y offset needed for detiling window system stencil
buffers, replace the term
region-height * 2 + region-height % 2 - 1
with
rb-Height - 1 .
The two terms are incidentally equivalent due to some out-of-date,
incorrect code in the Intel DRI2 glue for DDX. (See
intel_process_dri2_buffer_with_separate_stencil(), line ``buffer_height /=
2;``).
Note: This is a candidate for the 7.11 branch (only the intel_span.c hunk).
Signed-off-by: Chad Versace chad.vers...@linux.intel.com
---
src/mesa/drivers/dri/intel/intel_fbo.c |6 ++
src/mesa/drivers/dri/intel/intel_span.c |3 +--
2 files changed, 3 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c
b/src/mesa/drivers/dri/intel/intel_fbo.c
index dbd5163..a724f1d 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.c
+++ b/src/mesa/drivers/dri/intel/intel_fbo.c
@@ -267,9 +267,8 @@ intel_map_renderbuffer_s8(struct gl_context *ctx,
irb-map_h = h;
/* Flip the Y axis for the default framebuffer. */
- int region_h = irb-region-height;
int y_flip = (rb-Name == 0) ? -1 : 1;
- int y_bias = (rb-Name == 0) ? (region_h * 2 + region_h % 2 - 1) : 0;
+ int y_bias = (rb-Name == 0) ? (rb-Height - 1) : 0;
irb-map_buffer = malloc(w * h);
untiled_s8_map = irb-map_buffer;
@@ -442,9 +441,8 @@ intel_unmap_renderbuffer_s8(struct gl_context *ctx,
uint8_t *tiled_s8_map = irb-region-bo-virtual;
/* Flip the Y axis for the default framebuffer. */
- int region_h = irb-region-height;
int y_flip = (rb-Name == 0) ? -1 : 1;
- int y_bias = (rb-Name == 0) ? (region_h * 2 + region_h % 2 - 1) : 0;
+ int y_bias = (rb-Name == 0) ? (rb-Height - 1) : 0;
for (uint32_t pix_y = 0; pix_y irb-map_h; pix_y++) {
for (uint32_t pix_x = 0; pix_x irb-map_w; pix_x++) {
diff --git a/src/mesa/drivers/dri/intel/intel_span.c
b/src/mesa/drivers/dri/intel/intel_span.c
index 271d2e1..31f2828 100644
--- a/src/mesa/drivers/dri/intel/intel_span.c
+++ b/src/mesa/drivers/dri/intel/intel_span.c
@@ -141,10 +141,9 @@ intel_set_span_functions(struct intel_context *intel,
struct intel_renderbuffer *irb = intel_renderbuffer(rb);\
uint8_t *buf = irb-region-bo-virtual;\
unsigned stride = irb-region-pitch; \
- unsigned height = irb-region-height; \
bool flip = rb-Name == 0; \
int y_scale = flip ? -1 : 1;
\
- int y_bias = flip ? (height * 2 + height % 2 - 1) : 0; \
+ int y_bias = flip ? (rb-Height - 1) : 0; \
#undef Y_FLIP
#define Y_FLIP(y) (y_scale * (y) + y_bias)
___
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Mesa (master): intel: Fix region dimensions for stencil buffers received from DDX
Module: Mesa
Branch: master
Commit: 50b33560784dde428fbb5dfe7d428255874c496c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=50b33560784dde428fbb5dfe7d428255874c496c
Author: Chad Versace chad.vers...@linux.intel.com
Date: Tue Nov 15 07:21:25 2011 -0800
intel: Fix region dimensions for stencil buffers received from DDX
I changed the dimensions of the stencil buffer's region, as allocated by
the DDX, at xf86-video-intel commit
commit 3e55f3e88b40471706d5cd45c4df4010f8675c75
dri: Do not tile stencil buffer
But I forgot to make the analogous update to the Intel DRI2 glue in Mesa.
This patch makes that update.
Surprisingly, the mismatch did not cause any bugs. But the mismatch, if
left unfixed, *would* create bugs in the next commit.
Note: This is a candidate for the 7.11 branch.
Signed-off-by: Chad Versace chad.vers...@linux.intel.com
---
src/mesa/drivers/dri/intel/intel_context.c | 31 ++-
1 files changed, 16 insertions(+), 15 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_context.c
b/src/mesa/drivers/dri/intel/intel_context.c
index d00d5d4..d89b388 100644
--- a/src/mesa/drivers/dri/intel/intel_context.c
+++ b/src/mesa/drivers/dri/intel/intel_context.c
@@ -1353,27 +1353,28 @@ intel_process_dri2_buffer_with_separate_stencil(struct
intel_context *intel,
buffer-cpp, buffer-pitch);
}
- /*
-* The stencil buffer has quirky pitch requirements. From Section
-* 2.11.5.6.2.1 3DSTATE_STENCIL_BUFFER, field Surface Pitch:
-*The pitch must be set to 2x the value computed based on width, as
-*the stencil buffer is stored with two rows interleaved.
-* If we neglect to double the pitch, then drm_intel_gem_bo_map_gtt()
-* maps the memory incorrectly.
-*
-* To satisfy the pitch requirement, the X driver hackishly allocated
-* the gem buffer with bpp doubled and height halved. So buffer-cpp is
-* correct, but drawable-height is not.
-*/
- int buffer_height = drawable-h;
+ int buffer_width;
+ int buffer_height;
if (buffer-attachment == __DRI_BUFFER_STENCIL) {
- buffer_height /= 2;
+ /* The stencil buffer has quirky pitch requirements. From Section
+ * 2.11.5.6.2.1 3DSTATE_STENCIL_BUFFER, field Surface Pitch:
+ *The pitch must be set to 2x the value computed based on width, as
+ *the stencil buffer is stored with two rows interleaved.
+ *
+ * To satisfy the pitch requirement, the X driver allocated the region
+ * with the following dimensions.
+ */
+ buffer_width = ALIGN(drawable-w, 64);
+ buffer_height = ALIGN(ALIGN(drawable-h, 2) / 2, 64);
+ } else {
+ buffer_width = drawable-w;
+ buffer_height = drawable-h;
}
struct intel_region *region =
intel_region_alloc_for_handle(intel-intelScreen,
buffer-cpp,
- drawable-w,
+ buffer_width,
buffer_height,
buffer-pitch / buffer-cpp,
buffer-name,
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Mesa (master): intel: Fix separate stencil in builtin DRI2 backend
Module: Mesa
Branch: master
Commit: 79653c12d6da4d89aaa73e4e8260a84d91f93593
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=79653c12d6da4d89aaa73e4e8260a84d91f93593
Author: Chad Versace chad.vers...@linux.intel.com
Date: Tue Nov 15 07:08:49 2011 -0800
intel: Fix separate stencil in builtin DRI2 backend
intelAllocateBuffer() was oblivious to separate stencil buffers. This
patch fixes it to allocate a non-tiled stencil buffer with special pitch,
just as the DDX does.
Without this, any app that attempted to create an EGL surface with stencil
bits would crash. Of course, this affected only environments that used the
builtin DRI2 backend, such as Android and Wayland.
Fixes GLBenchmark2.1 on Android on gen7.
Note: This is a candidate for the 7.11 branch.
Tested-by: Louie Tsaie louie.t...@intel.com
Signed-off-by: Chad Versace chad.vers...@linux.intel.com
---
src/mesa/drivers/dri/intel/intel_screen.c | 89 ++---
1 files changed, 80 insertions(+), 9 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_screen.c
b/src/mesa/drivers/dri/intel/intel_screen.c
index ae55700..5a73030 100644
--- a/src/mesa/drivers/dri/intel/intel_screen.c
+++ b/src/mesa/drivers/dri/intel/intel_screen.c
@@ -796,6 +796,54 @@ struct intel_buffer {
struct intel_region *region;
};
+/**
+ * \brief Get tiling format for a DRI buffer.
+ *
+ * \param attachment is the buffer's attachmet point, such as
+ *__DRI_BUFFER_DEPTH.
+ * \param out_tiling is the returned tiling format for buffer.
+ * \return false if attachment is unrecognized or is incompatible with screen.
+ */
+static bool
+intel_get_dri_buffer_tiling(struct intel_screen *screen,
+uint32_t attachment,
+uint32_t *out_tiling)
+{
+ if (screen-gen 4) {
+ *out_tiling = I915_TILING_X;
+ return true;
+ }
+
+ switch (attachment) {
+ case __DRI_BUFFER_DEPTH:
+ case __DRI_BUFFER_DEPTH_STENCIL:
+ case __DRI_BUFFER_HIZ:
+ *out_tiling = I915_TILING_Y;
+ return true;
+ case __DRI_BUFFER_ACCUM:
+ case __DRI_BUFFER_FRONT_LEFT:
+ case __DRI_BUFFER_FRONT_RIGHT:
+ case __DRI_BUFFER_BACK_LEFT:
+ case __DRI_BUFFER_BACK_RIGHT:
+ case __DRI_BUFFER_FAKE_FRONT_LEFT:
+ case __DRI_BUFFER_FAKE_FRONT_RIGHT:
+ *out_tiling = I915_TILING_X;
+ return true;
+ case __DRI_BUFFER_STENCIL:
+ /* The stencil buffer is W tiled. However, we request from the kernel
+ * a non-tiled buffer because the GTT is incapable of W fencing.
+ */
+ *out_tiling = I915_TILING_NONE;
+ return true;
+ default:
+ if(unlikely(INTEL_DEBUG DEBUG_DRI)) {
+fprintf(stderr, error: %s: unrecognized DRI buffer attachment 0x%x\n,
+__FUNCTION__, attachment);
+ }
+ return false;
+ }
+}
+
static __DRIbuffer *
intelAllocateBuffer(__DRIscreen *screen,
unsigned attachment, unsigned format,
@@ -803,22 +851,45 @@ intelAllocateBuffer(__DRIscreen *screen,
{
struct intel_buffer *intelBuffer;
struct intel_screen *intelScreen = screen-driverPrivate;
+
uint32_t tiling;
+ uint32_t region_width;
+ uint32_t region_height;
+ uint32_t region_cpp;
+
+ bool ok = true;
+
+ ok = intel_get_dri_buffer_tiling(intelScreen, attachment, tiling);
+ if (!ok)
+ return NULL;
intelBuffer = CALLOC(sizeof *intelBuffer);
if (intelBuffer == NULL)
return NULL;
- if ((attachment == __DRI_BUFFER_DEPTH ||
- attachment == __DRI_BUFFER_STENCIL ||
- attachment == __DRI_BUFFER_DEPTH_STENCIL)
- intelScreen-gen = 4)
- tiling = I915_TILING_Y;
- else
- tiling = I915_TILING_X;
+ if (attachment == __DRI_BUFFER_STENCIL) {
+ /* The stencil buffer has quirky pitch requirements. From Vol 2a,
+ * 11.5.6.2.1 3DSTATE_STENCIL_BUFFER, field Surface Pitch:
+ *The pitch must be set to 2x the value computed based on width, as
+ *the stencil buffer is stored with two rows interleaved.
+ * To accomplish this, we resort to the nasty hack of doubling the
+ * region's cpp and halving its height.
+ */
+ region_width = ALIGN(width, 64);
+ region_height = ALIGN(ALIGN(height, 2) / 2, 64);
+ region_cpp = format / 4;
+ } else {
+ region_width = width;
+ region_height = height;
+ region_cpp = format / 8;
+ }
- intelBuffer-region = intel_region_alloc(intelScreen, tiling,
- format / 8, width, height, true);
+ intelBuffer-region = intel_region_alloc(intelScreen,
+tiling,
+region_cpp,
+region_width,
+region_height,
+true);
if (intelBuffer-region == NULL) {
FREE(intelBuffer
Mesa (master): 42 new commits
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4ce635c871d00e442efb2b265562685d7edd44ae Merge: 1f3c5eae5c4be582e50c2d4d7950424d86059c45 e5411d8fdc6a7dda18d82746b84197ef83ee0a13 Author: Chad Versace chad.vers...@linux.intel.com Date: Tue Nov 22 10:52:29 2011 -0800 Merge branch 'hiz' of ssh://people.freedesktop.org/~chadversary/mesa URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e5411d8fdc6a7dda18d82746b84197ef83ee0a13 Author: Chad Versace chad.vers...@linux.intel.com Date: Thu Nov 17 08:53:39 2011 -0800 i965/gen6: Enable HiZ by default Regresses one Piglit test: bugs/fdo10370. I'm not enabling HiZ for gen7 yet because it causes a mysterious performance regression. Reviewed-by: Eric Anholt e...@anholt.net Signed-off-by: Chad Versace chad.vers...@linux.intel.com URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b18875d441ca4b7b1a4098659fb4298a4bf265f6 Author: Chad Versace chad.vers...@linux.intel.com Date: Thu Nov 17 08:50:05 2011 -0800 intel: Use separate stencil whenever possible For depthstencil renderbuffers, we were using separate stencil only if the hardware required it. Since the performance gains from HiZ is so high, we should always use separate stencil if the hardware supports it. Reviewed-by: Eric Anholt e...@anholt.net Signed-off-by: Chad Versace chad.vers...@linux.intel.com URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e7e81714f3ecf67a975d35e74bdb7fd15d924e4d Author: Kenneth Graunke kenn...@whitecape.org Date: Mon Nov 7 15:58:43 2011 -0800 i965: Implement the actual tables for texture alignment units [v2] I implemented functions for horizontal/vertical alignment units separately because I find it easier to read that way...especially with all the corner-cases. [chad] Corrected the vertical alignment calculation by checking for depthstencil formats. v2: - Fix typos in intel_horizontal_texture_alignment_unit(): s/height/width/ and s/VALIGN/HALIGN. - Remove special case for compressed formats in intel_get_texture_alignment unit(). Compressed formats are already handled in the halign and valign functions. - Replace check ``_mesa_is_depth_format(...) || _mesa_is_depthstencil_format(...)`` with explcitit checks against GL_DEPTH_COMPONENT and GL_DEPTH_STENCIL. Reviewed-by: Eric Anholt e...@anholt.net Signed-off-by: Kenneth Graunke kenn...@whitecape.org Signed-off-by: Chad Versace chad.vers...@linux.intel.com URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=dd0e46c4102976b7d317104ecd1bb565ac34613a Author: Chad Versace chad.vers...@linux.intel.com Date: Thu Nov 17 09:09:56 2011 -0800 i965/gen6: Set vertical alignment in SURFACE_STATE batch Reviewed-by: Eric Anholt e...@anholt.net Signed-off-by: Chad Versace chad.vers...@linux.intel.com URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=017c13d55b5b086774d6afea2ca754482c624c6a Author: Chad Versace chad.vers...@linux.intel.com Date: Thu Nov 17 08:30:30 2011 -0800 intel: Store miptree alignment units in the miptree This allows us to replace all the calls to intel_get_texture_alignment_unit() with a single call at miptree creation. Reviewed-by: Eric Anholt e...@anholt.net Reviewed-by: Kenneth Graunke kenn...@whitecape.org Signed-off-by: Chad Versace chad.vers...@linux.intel.com URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=293e9a7ccfeb64efd54464658518e4ded054a13c Author: Chad Versace chad.vers...@linux.intel.com Date: Tue Nov 15 22:51:35 2011 -0800 intel: Enable HiZ for texture renderbuffers When a depth texture is first attached to framebuffer, allocate a HiZ miptree for it. Reviewed-by: Eric Anholt e...@anholt.net Signed-off-by: Chad Versace chad.vers...@linux.intel.com URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b264698d30d3c789bbe1fc64fd72c731f342877a Author: Chad Versace chad.vers...@linux.intel.com Date: Tue Nov 15 18:25:39 2011 -0800 intel: Resolve buffers in intel_map_renderbuffer() Reviewed-by: Eric Anholt e...@anholt.net Signed-off-by: Chad Versace chad.vers...@linux.intel.com URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d2e35a5460c5c4b3951c0aaca4fdb867b20478bb Author: Chad Versace chad.vers...@linux.intel.com Date: Tue Nov 15 18:21:12 2011 -0800 intel: Resolve buffers in intel_map_texture_image() Reviewed-by: Eric Anholt e...@anholt.net Signed-off-by: Chad Versace chad.vers...@linux.intel.com URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3d760664e6349c72624aa6d54d40df0233995c8e Author: Chad Versace chad.vers...@linux.intel.com Date: Tue Nov 15 18:21:09 2011 -0800 intel: Mark needed resolves when first enabling HiZ on a miptree Reviewed-by: Eric Anholt e...@anholt.net Signed
Mesa (master): i965/gen6: Fix GPU hang when using stencil buffer without depth
Module: Mesa Branch: master Commit: f99d5af03b0f97d7a1b7076b2142069770879471 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f99d5af03b0f97d7a1b7076b2142069770879471 Author: Chad Versace chad.vers...@linux.intel.com Date: Wed Nov 23 10:06:46 2011 -0800 i965/gen6: Fix GPU hang when using stencil buffer without depth Enable the bit 3DSTATE_DEPTH_BUFFER.Tiled_Surface. From the Sandybridge PRM, Volume 2, Part 1, Section 7.5.5.1.1 3DSTATE_DEPTH_BUFFER, Bit 1.27 Tiled Surface: [DevGT+]: This field must be set to TRUE. Fixes GPU hangs on the following Piglit tests: hiz-stencil-test-fbo-d0-s8 hiz-stencil-read-fbo-d0-s8 Reviewed-by: Kenneth Graunke kenn...@whitecape.org Signed-off-by: Chad Versace chad.vers...@linux.intel.com --- src/mesa/drivers/dri/i965/brw_misc_state.c |5 + 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c index 17da460..cb1405c 100644 --- a/src/mesa/drivers/dri/i965/brw_misc_state.c +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c @@ -278,6 +278,10 @@ static void emit_depthbuffer(struct brw_context *brw) * * [DevGT]: This field must be set to the same value (enabled or * disabled) as Hierarchical Depth Buffer Enable + * + * The tiled bit must be set. From the Sandybridge PRM, Volume 2, Part 1, + * Section 7.5.5.1.1 3DSTATE_DEPTH_BUFFER, Bit 1.27 Tiled Surface: + * [DevGT+]: This field must be set to TRUE. */ struct intel_region *region = stencil_irb-mt-region; @@ -290,6 +294,7 @@ static void emit_depthbuffer(struct brw_context *brw) (1 21) | /* separate stencil enable */ (1 22) | /* hiz enable */ (BRW_TILEWALK_YMAJOR 26) | + (1 27) | /* tiled surface */ (BRW_SURFACE_2D 29)); OUT_BATCH(0); OUT_BATCH(((region-width - 1) 6) | ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): swrast: Fix some static analysis warnings
Module: Mesa Branch: master Commit: 03bbcd447cbaa28b52465ae1045013f1aff420c2 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=03bbcd447cbaa28b52465ae1045013f1aff420c2 Author: Chad Versace chad.vers...@linux.intel.com Date: Mon Nov 28 11:45:03 2011 -0800 swrast: Fix some static analysis warnings To each switch statement in s_texfilter.c, add a break statement to the default case. Eliminates the Eclipse static analysis warning: No break at the end of this case. Reviewed-by: Brian Paul bri...@vmware.com Signed-off-by: Chad Versace chad.vers...@linux.intel.com --- src/mesa/swrast/s_texfilter.c |9 + 1 files changed, 9 insertions(+), 0 deletions(-) diff --git a/src/mesa/swrast/s_texfilter.c b/src/mesa/swrast/s_texfilter.c index 5662625..fb172f3 100644 --- a/src/mesa/swrast/s_texfilter.c +++ b/src/mesa/swrast/s_texfilter.c @@ -273,6 +273,7 @@ linear_texel_locations(GLenum wrapMode, default: _mesa_problem(NULL, Bad wrap mode); u = 0.0F; + break; } *weight = FRAC(u); } @@ -471,6 +472,7 @@ clamp_rect_coord_linear(GLenum wrapMode, GLfloat coord, GLint max, _mesa_problem(NULL, bad wrapMode in clamp_rect_coord_linear); i0 = i1 = 0; fcol = 0.0F; + break; } *i0out = i0; *i1out = i1; @@ -533,6 +535,7 @@ nearest_texcoord(const struct gl_texture_object *texObj, break; default: *i = *j = *k = 0; + break; } } @@ -589,6 +592,7 @@ linear_texcoord(const struct gl_texture_object *texObj, default: *slice = 0; + break; } } @@ -787,6 +791,7 @@ get_border_color(const struct gl_texture_object *tObj, break; default: COPY_4V(rgba, tObj-Sampler.BorderColor.f); + break; } } @@ -1537,6 +1542,7 @@ sample_lambda_2d(struct gl_context *ctx, break; default: _mesa_problem(ctx, Bad mag filter in sample_lambda_2d); + break; } } } @@ -2528,6 +2534,7 @@ sample_lambda_cube(struct gl_context *ctx, break; default: _mesa_problem(ctx, Bad min filter in sample_lambda_cube); + break; } } @@ -2545,6 +2552,7 @@ sample_lambda_cube(struct gl_context *ctx, break; default: _mesa_problem(ctx, Bad mag filter in sample_lambda_cube); + break; } } } @@ -3473,6 +3481,7 @@ sample_depth_texture( struct gl_context *ctx, break; default: _mesa_problem(ctx, Bad depth texture mode); +break; } } } ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): meta: Disable GL_TEXTURE_EXTERNAL_OES in meta_begin()
Module: Mesa Branch: master Commit: 7e5ffd9be2da66c076e84ae4bc854cca5665620c URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7e5ffd9be2da66c076e84ae4bc854cca5665620c Author: Chad Versace chad.vers...@linux.intel.com Date: Wed Dec 21 18:34:18 2011 -0800 meta: Disable GL_TEXTURE_EXTERNAL_OES in meta_begin() If the meta flag MESA_META_TEXTURE is present, then disable the texture target GL_TEXTURE_EXTERNAL_OES. Reviewed-by: Brian Paul bri...@vmware.com Signed-off-by: Chad Versace chad.vers...@linux.intel.com --- src/mesa/drivers/common/meta.c |2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/src/mesa/drivers/common/meta.c b/src/mesa/drivers/common/meta.c index e622673..5098680 100644 --- a/src/mesa/drivers/common/meta.c +++ b/src/mesa/drivers/common/meta.c @@ -588,6 +588,8 @@ _mesa_meta_begin(struct gl_context *ctx, GLbitfield state) _mesa_set_enable(ctx, GL_TEXTURE_CUBE_MAP, GL_FALSE); if (ctx-Extensions.NV_texture_rectangle) _mesa_set_enable(ctx, GL_TEXTURE_RECTANGLE, GL_FALSE); +if (ctx-Extensions.OES_EGL_image_external) + _mesa_set_enable(ctx, GL_TEXTURE_EXTERNAL_OES, GL_FALSE); _mesa_set_enable(ctx, GL_TEXTURE_GEN_S, GL_FALSE); _mesa_set_enable(ctx, GL_TEXTURE_GEN_T, GL_FALSE); _mesa_set_enable(ctx, GL_TEXTURE_GEN_R, GL_FALSE); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Create mock implementation of GL_OES_EGL_image_external
Module: Mesa
Branch: master
Commit: 7420c9dab4aaf87e6b840410226c296c4668a48f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7420c9dab4aaf87e6b840410226c296c4668a48f
Author: Chad Versace chad.vers...@linux.intel.com
Date: Wed Dec 21 18:34:19 2011 -0800
i965: Create mock implementation of GL_OES_EGL_image_external
In Android IceCreamSandwich, SurfaceFlinger requires GL_OES_image_external
for basic compositing tasks. Without the extension, SurfaceFlinger fails
to start.
Despite the incompleteness of the extension's implementation introduced by
this patch, it is good enough to enable SurfaceFlinger and to unblock the
people who need to begin testing Mesa on IceCreamSandwich.
To enable the extension, set the environment variable
MESA_EXTENSION_OVERRIDE=+GL_OES_EGL_image_external. Ideally, Android
should set this in init.rc.
WARNING: This implementation of GL_OES_EGL_image_external is not complete.
Some of it is even incorrect. When we begin to really implement
GL_OES_EGL_image_external, much of the patch will need reverting.
Reviewed-by: Eric Anholt e...@anholt.net
Signed-off-by: Chad Versace chad.vers...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_wm_emit.c |2 ++
src/mesa/drivers/dri/i965/brw_wm_pass1.c |1 +
src/mesa/drivers/dri/i965/brw_wm_surface_state.c |1 +
src/mesa/drivers/dri/intel/intel_tex_image.c |2 ++
4 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_wm_emit.c
b/src/mesa/drivers/dri/i965/brw_wm_emit.c
index 80ed1ff..270e321 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_emit.c
@@ -1078,6 +1078,7 @@ void emit_tex(struct brw_wm_compile *c,
case TEXTURE_2D_INDEX:
case TEXTURE_1D_ARRAY_INDEX:
case TEXTURE_RECT_INDEX:
+ case TEXTURE_EXTERNAL_INDEX:
emit = WRITEMASK_XY;
nr_texcoords = 2;
break;
@@ -1212,6 +1213,7 @@ void emit_txb(struct brw_wm_compile *c,
break;
case TEXTURE_2D_INDEX:
case TEXTURE_RECT_INDEX:
+ case TEXTURE_EXTERNAL_INDEX:
brw_MOV(p, brw_message_reg(2 + 0 * mrf_per_channel), arg[0]);
brw_MOV(p, brw_message_reg(2 + 1 * mrf_per_channel), arg[1]);
brw_MOV(p, brw_message_reg(2 + 2 * mrf_per_channel), brw_imm_f(0));
diff --git a/src/mesa/drivers/dri/i965/brw_wm_pass1.c
b/src/mesa/drivers/dri/i965/brw_wm_pass1.c
index ee7a627..e96e9ed 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_pass1.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_pass1.c
@@ -94,6 +94,7 @@ static GLuint get_texcoord_mask( GLuint tex_idx )
return WRITEMASK_X;
case TEXTURE_2D_INDEX:
case TEXTURE_1D_ARRAY_INDEX:
+ case TEXTURE_EXTERNAL_INDEX:
return WRITEMASK_XY;
case TEXTURE_3D_INDEX:
case TEXTURE_2D_ARRAY_INDEX:
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index e908430..dedf594 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -58,6 +58,7 @@ translate_tex_target(GLenum target)
case GL_TEXTURE_2D:
case GL_TEXTURE_2D_ARRAY_EXT:
+ case GL_TEXTURE_EXTERNAL_OES:
return BRW_SURFACE_2D;
case GL_TEXTURE_3D:
diff --git a/src/mesa/drivers/dri/intel/intel_tex_image.c
b/src/mesa/drivers/dri/intel/intel_tex_image.c
index dd0c6d3..107d314 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_image.c
+++ b/src/mesa/drivers/dri/intel/intel_tex_image.c
@@ -84,6 +84,8 @@ intel_miptree_create_for_teximage(struct intel_context *intel,
intelImage-base.Base.Level == firstLevel
(intel-gen 4 || firstLevel == 0)) {
lastLevel = firstLevel;
+ } else if (intelObj-base.Target == GL_TEXTURE_EXTERNAL_OES) {
+lastLevel = firstLevel;
} else {
lastLevel = firstLevel + _mesa_logbase2(MAX2(MAX2(width, height),
depth));
}
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Mesa (master): intel: Fix memory leak in intel_miptree_create()
Module: Mesa
Branch: master
Commit: 747f0307626ef5bcf2f889ab66bcc95ab8eda2c8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=747f0307626ef5bcf2f889ab66bcc95ab8eda2c8
Author: Chad Versace chad.vers...@linux.intel.com
Date: Tue Dec 27 10:10:05 2011 -0800
intel: Fix memory leak in intel_miptree_create()
On failure, intel_miptree_create() needs to *release* the miptree, not
just free it, so that the stencil_mt gets released too.
Reviewed-by: Eric Anholt e...@anholt.net
Signed-off-by: Chad Versace chad.vers...@linux.intel.com
---
src/mesa/drivers/dri/intel/intel_mipmap_tree.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
index 9576489..60cc694 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
@@ -204,7 +204,7 @@ intel_miptree_create(struct intel_context *intel,
* pitch == 0 || height == 0 indicates the null texture
*/
if (!mt || !mt-total_width || !mt-total_height) {
- free(mt);
+ intel_miptree_release(mt);
return NULL;
}
@@ -216,7 +216,7 @@ intel_miptree_create(struct intel_context *intel,
expect_accelerated_upload);
if (!mt-region) {
- free(mt);
+ intel_miptree_release(mt);
return NULL;
}
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Mesa (master): i965: Fix misnamed GEN7_WM_DEPTH_RESOLVE
Module: Mesa
Branch: master
Commit: b755f5894ce211dcb8ec881ba9cd9856383c3c79
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b755f5894ce211dcb8ec881ba9cd9856383c3c79
Author: Chad Versace chad.vers...@linux.intel.com
Date: Wed Dec 21 17:49:07 2011 -0800
i965: Fix misnamed GEN7_WM_DEPTH_RESOLVE
It was named GEN6_WM_DEPTH_RESOLVE. Luckily, this caused no conflict,
because the value is identical for gen6 and gen7.
Reviewed-by: Eric Anholt e...@anholt.net
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
Signed-off-by: Chad Versace chad.vers...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_defines.h |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
b/src/mesa/drivers/dri/i965/brw_defines.h
index f7bb05a..4d90a99 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1345,7 +1345,7 @@ enum brw_wm_barycentric_interp_mode {
# define GEN7_WM_STATISTICS_ENABLE (1 31)
# define GEN7_WM_DEPTH_CLEAR (1 30)
# define GEN7_WM_DISPATCH_ENABLE (1 29)
-# define GEN6_WM_DEPTH_RESOLVE (1 28)
+# define GEN7_WM_DEPTH_RESOLVE (1 28)
# define GEN7_WM_HIERARCHICAL_DEPTH_RESOLVE(1 27)
# define GEN7_WM_KILL_ENABLE (1 25)
# define GEN7_WM_PSCDEPTH_OFF (0 23)
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Mesa (master): i965: Replace references to stencil region size with buffer size
Module: Mesa
Branch: master
Commit: bebc91f0f3a1f2d19d36a7f1a4f7c992ace064e9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bebc91f0f3a1f2d19d36a7f1a4f7c992ace064e9
Author: Chad Versace chad.vers...@linux.intel.com
Date: Wed Dec 21 16:58:38 2011 -0800
i965: Replace references to stencil region size with buffer size
It is unwise to use a stencil region's size to determine its
renderbuffer's size, because at region creation we fudge the width and
height to accomodate interleaved rows. (See the comment for MESA_FORMAT_S8
in intel_miptree_create()). Most users of stencil_region-{width,height}
should be converted to use stencil_rb-{Width,Height}.
We have already done the replacement in several locations. This patch
continues the replacement in {brw,gen7}_emit_depthbuffer(). To make those
functions look consistent, I've also done the equivalent replacement for
the depth buffer.
Acked-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Eric Anholt e...@anholt.net
Signed-off-by: Chad Versace chad.vers...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_misc_state.c |8
src/mesa/drivers/dri/i965/gen7_misc_state.c |6 --
2 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c
b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 1c0c52b..726d8d8 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -343,8 +343,8 @@ static void emit_depthbuffer(struct brw_context *brw)
(1 27) | /* tiled surface */
(BRW_SURFACE_2D 29));
OUT_BATCH(0);
- OUT_BATCH(((region-width - 1) 6) |
-(2 * region-height - 1) 19);
+ OUT_BATCH(((stencil_irb-Base.Width - 1) 6) |
+(stencil_irb-Base.Height - 1) 19);
OUT_BATCH(0);
OUT_BATCH(0);
@@ -378,8 +378,8 @@ static void emit_depthbuffer(struct brw_context *brw)
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
offset);
OUT_BATCH((BRW_SURFACE_MIPMAPLAYOUT_BELOW 1) |
- ((region-width - 1) 6) |
- ((region-height - 1) 19));
+ ((depth_irb-Base.Width - 1) 6) |
+ ((depth_irb-Base.Height - 1) 19));
OUT_BATCH(0);
if (intel-is_g4x || intel-gen = 5)
diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c
b/src/mesa/drivers/dri/i965/gen7_misc_state.c
index 89a4e71..9c93046 100644
--- a/src/mesa/drivers/dri/i965/gen7_misc_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c
@@ -71,7 +71,8 @@ static void emit_depthbuffer(struct brw_context *brw)
/* 3DSTATE_STENCIL_BUFFER inherits surface type and dimensions. */
dw1 |= (BRW_SURFACE_2D 29);
-dw3 = ((region-width - 1) 4) | ((2 * region-height - 1) 18);
+dw3 = ((srb-Base.Width - 1) 4) |
+ ((srb-Base.Height - 1) 18);
}
BEGIN_BATCH(7);
@@ -103,7 +104,8 @@ static void emit_depthbuffer(struct brw_context *brw)
OUT_RELOC(region-bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
offset);
- OUT_BATCH(((region-width - 1) 4) | ((region-height - 1) 18));
+ OUT_BATCH(((drb-Base.Width - 1) 4) |
+((drb-Base.Height - 1) 18));
OUT_BATCH(0);
OUT_BATCH(tile_x | (tile_y 16));
OUT_BATCH(0);
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Mesa (master): i965/gen7: Enable HiZ
Module: Mesa
Branch: master
Commit: 06ad9adcb031b97af2ce9cd22b919b8befcec43b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=06ad9adcb031b97af2ce9cd22b919b8befcec43b
Author: Chad Versace chad.vers...@linux.intel.com
Date: Wed Dec 21 17:09:58 2011 -0800
i965/gen7: Enable HiZ
This patch modifies all batches needed for HiZ. The batch length for
3DSTATE_HIER_DEPTH_BUFFER is also corrected from 4 to 3.
Performance +6.7% on Citybench.
num-frames: 400
resolution: 1918x1031
avg-hiz-off: 127.90 fps
avg-hiz-on: 136.50 fps
kernel: git://people.freedesktop.org/~anholt/linux.git
branch=gen7-reset-sol sha=23360e4
Reviewed-by: Eric Anholt e...@anholt.net
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
Signed-off-by: Chad Versace chad.vers...@linux.intel.com
---
src/mesa/drivers/dri/i965/gen7_clip_state.c | 20 -
src/mesa/drivers/dri/i965/gen7_misc_state.c | 31 ---
src/mesa/drivers/dri/i965/gen7_sf_state.c | 18 +--
src/mesa/drivers/dri/i965/gen7_wm_state.c | 18 +++
src/mesa/drivers/dri/intel/intel_screen.c |2 +-
5 files changed, 76 insertions(+), 13 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen7_clip_state.c
b/src/mesa/drivers/dri/i965/gen7_clip_state.c
index c32cd98..9be3ce9 100644
--- a/src/mesa/drivers/dri/i965/gen7_clip_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_clip_state.c
@@ -39,6 +39,23 @@ upload_clip_state(struct brw_context *brw)
/* BRW_NEW_FRAGMENT_PROGRAM */
const struct gl_fragment_program *fprog = brw-fragment_program;
+ if (brw-hiz.op) {
+ /* HiZ operations emit a rectangle primitive, which requires clipping to
+ * be disabled. From page 10 of the Sandy Bridge PRM Volume 2 Part 1
+ * Section 1.3 3D Primitives Overview:
+ *RECTLIST:
+ *Either the CLIP unit should be DISABLED, or the CLIP unit's Clip
+ *Mode should be set to a value other than CLIPMODE_NORMAL.
+ */
+ BEGIN_BATCH(4);
+ OUT_BATCH(_3DSTATE_CLIP 16 | (4 - 2));
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ ADVANCE_BATCH();
+ return;
+ }
+
/* _NEW_BUFFERS */
bool render_to_fbo = brw-intel.ctx.DrawBuffer-Name != 0;
@@ -116,7 +133,8 @@ const struct brw_tracked_state gen7_clip_state = {
_NEW_LIGHT |
_NEW_TRANSFORM),
.brw = (BRW_NEW_CONTEXT |
-BRW_NEW_FRAGMENT_PROGRAM),
+BRW_NEW_FRAGMENT_PROGRAM |
+BRW_NEW_HIZ),
.cache = 0
},
.emit = upload_clip_state,
diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c
b/src/mesa/drivers/dri/i965/gen7_misc_state.c
index 9c93046..f287485 100644
--- a/src/mesa/drivers/dri/i965/gen7_misc_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c
@@ -38,11 +38,16 @@ static void emit_depthbuffer(struct brw_context *brw)
/* _NEW_BUFFERS */
struct intel_renderbuffer *drb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
struct intel_renderbuffer *srb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
- struct intel_mipmap_tree *depth_mt = NULL, *stencil_mt = NULL;
+ struct intel_mipmap_tree *depth_mt = NULL,
+ *stencil_mt = NULL,
+ *hiz_mt = NULL;
if (drb)
depth_mt = drb-mt;
+ if (depth_mt)
+ hiz_mt = depth_mt-hiz_mt;
+
if (srb) {
stencil_mt = srb-mt;
if (stencil_mt-stencil_mt)
@@ -97,7 +102,7 @@ static void emit_depthbuffer(struct brw_context *brw)
OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER 16 | (7 - 2));
OUT_BATCH(((region-pitch * region-cpp) - 1) |
(brw_depthbuffer_format(brw) 18) |
- (0 22) /* no HiZ buffer */ |
+ ((hiz_mt ? 1 : 0) 22) | /* hiz enable */
((stencil_mt != NULL ctx-Stencil.WriteMask != 0) 27) |
((ctx-Depth.Mask != 0) 28) |
(BRW_SURFACE_2D 29));
@@ -112,12 +117,22 @@ static void emit_depthbuffer(struct brw_context *brw)
ADVANCE_BATCH();
}
- BEGIN_BATCH(4);
- OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER 16 | (4 - 2));
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- ADVANCE_BATCH();
+ if (hiz_mt == NULL) {
+ BEGIN_BATCH(5);
+ OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER 16 | (3 - 2));
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ ADVANCE_BATCH();
+ } else {
+ BEGIN_BATCH(5);
+ OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER 16 | (3 - 2));
+ OUT_BATCH(hiz_mt-region-pitch * hiz_mt-region-cpp - 1);
+ OUT_RELOC(hiz_mt-region-bo,
+I915_GEM_DOMAIN_RENDER,
+I915_GEM_DOMAIN_RENDER,
+0);
+ ADVANCE_BATCH();
+ }
if (stencil_mt == NULL) {
BEGIN_BATCH(3);
diff --git a/src/mesa/drivers/dri/i965/gen7_sf_state.c
b/src/mesa/drivers/dri/i965/gen7_sf_state.c
index c4cacf0..7691cb2 100644
--- a/src/mesa/drivers/dri/i965/gen7_sf_state.c
+++ b/src
Mesa (master): i965/gen7: Fix batch length for 3DSTATE_HIER_DEPTH_BUFFER
Module: Mesa
Branch: master
Commit: f7cbd80028247b83ca6835a3f68b8d5bd28b6f70
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f7cbd80028247b83ca6835a3f68b8d5bd28b6f70
Author: Chad Versace chad.vers...@linux.intel.com
Date: Tue Jan 10 16:31:39 2012 -0800
i965/gen7: Fix batch length for 3DSTATE_HIER_DEPTH_BUFFER
Change from 5 to 3.
Signed-off-by: Chad Versace chad.vers...@linux.intel.com
---
src/mesa/drivers/dri/i965/gen7_misc_state.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c
b/src/mesa/drivers/dri/i965/gen7_misc_state.c
index f287485..d7a3dae 100644
--- a/src/mesa/drivers/dri/i965/gen7_misc_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c
@@ -118,13 +118,13 @@ static void emit_depthbuffer(struct brw_context *brw)
}
if (hiz_mt == NULL) {
- BEGIN_BATCH(5);
+ BEGIN_BATCH(3);
OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER 16 | (3 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
ADVANCE_BATCH();
} else {
- BEGIN_BATCH(5);
+ BEGIN_BATCH(3);
OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER 16 | (3 - 2));
OUT_BATCH(hiz_mt-region-pitch * hiz_mt-region-cpp - 1);
OUT_RELOC(hiz_mt-region-bo,
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Mesa (master): gen6_hiz: Don't bind GL_DRAW_FRAMEBUFFER on GLES
Module: Mesa
Branch: master
Commit: 9462b8447864c754252cd2580c9e1e4d36d5cc63
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9462b8447864c754252cd2580c9e1e4d36d5cc63
Author: Neil Roberts n...@linux.intel.com
Date: Wed Nov 30 22:29:21 2011 +
gen6_hiz: Don't bind GL_DRAW_FRAMEBUFFER on GLES
When using Mesa with a GLES API, calling _mesa_FramebufferRenderbuffer
with GL_DRAW_FRAMEBUFFER will report a 'user error' because
get_framebuffer_target validates that this enum from the framebuffer
blit extension is only used on GL. To work around it this patch makes
it use the GL_FRAMEBUFFER enum instead in that case.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=43418
Note: This is a candidate for the 8.0 branch.
Signed-off-by: Chad Versace chad.vers...@linux.intel.com
---
src/mesa/drivers/dri/i965/gen6_hiz.c | 34 +-
1 files changed, 29 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen6_hiz.c
b/src/mesa/drivers/dri/i965/gen6_hiz.c
index e282511..92b1d61 100644
--- a/src/mesa/drivers/dri/i965/gen6_hiz.c
+++ b/src/mesa/drivers/dri/i965/gen6_hiz.c
@@ -109,6 +109,24 @@ static const uint32_t gen6_hiz_meta_save =
MESA_META_SELECT_FEEDBACK;
+static void
+gen6_hiz_get_framebuffer_enum(struct gl_context *ctx,
+ GLenum *bind_enum,
+ GLenum *get_enum)
+{
+ /* If the blit framebuffer extension isn't supported then Mesa will
+ report an error if we try to bind GL_DRAW_FRAMEBUFFER. However in
+ that case it should be safe to just save and restore
+ GL_FRAMEBUFFER instead. */
+ if (ctx-Extensions.EXT_framebuffer_blit ctx-API == API_OPENGL) {
+ *bind_enum = GL_DRAW_FRAMEBUFFER;
+ *get_enum = GL_DRAW_FRAMEBUFFER_BINDING;
+ } else {
+ *bind_enum = GL_FRAMEBUFFER;
+ *get_enum = GL_FRAMEBUFFER_BINDING;
+ }
+}
+
/**
* Initialize static data needed for HiZ operations.
*/
@@ -117,10 +135,13 @@ gen6_hiz_init(struct brw_context *brw)
{
struct gl_context *ctx = brw-intel.ctx;
struct brw_hiz_state *hiz = brw-hiz;
+ GLenum fb_bind_enum, fb_get_enum;
if (hiz-fbo != 0)
return;
+ gen6_hiz_get_framebuffer_enum(ctx, fb_bind_enum, fb_get_enum);
+
/* Create depthbuffer.
*
* Until glRenderbufferStorage is called, the renderbuffer hash table
@@ -139,8 +160,8 @@ gen6_hiz_init(struct brw_context *brw)
/* Setup FBO. */
_mesa_GenFramebuffersEXT(1, hiz-fbo);
- _mesa_BindFramebufferEXT(GL_DRAW_FRAMEBUFFER, hiz-fbo);
- _mesa_FramebufferRenderbufferEXT(GL_DRAW_FRAMEBUFFER,
+ _mesa_BindFramebufferEXT(fb_bind_enum, hiz-fbo);
+ _mesa_FramebufferRenderbufferEXT(fb_bind_enum,
GL_DEPTH_ATTACHMENT,
GL_RENDERBUFFER,
hiz-depth_rb-Name);
@@ -241,6 +262,7 @@ gen6_resolve_slice(struct intel_context *intel,
struct gl_context *ctx = intel-ctx;
struct brw_context *brw = brw_context(ctx);
struct brw_hiz_state *hiz = brw-hiz;
+ GLenum fb_bind_enum, fb_get_enum;
/* Do not recurse. */
assert(!brw-hiz.op);
@@ -250,11 +272,13 @@ gen6_resolve_slice(struct intel_context *intel,
assert(level = mt-last_level);
assert(layer mt-level[level].depth);
+ gen6_hiz_get_framebuffer_enum(ctx, fb_bind_enum, fb_get_enum);
+
/* Save state. */
GLint save_drawbuffer;
GLint save_renderbuffer;
_mesa_meta_begin(ctx, gen6_hiz_meta_save);
- _mesa_GetIntegerv(GL_DRAW_FRAMEBUFFER_BINDING, save_drawbuffer);
+ _mesa_GetIntegerv(fb_get_enum, save_drawbuffer);
_mesa_GetIntegerv(GL_RENDERBUFFER_BINDING, save_renderbuffer);
/* Initialize context data for HiZ operations. */
@@ -272,7 +296,7 @@ gen6_resolve_slice(struct intel_context *intel,
/* Setup FBO. */
gen6_hiz_setup_depth_buffer(brw, mt, level, layer);
- _mesa_BindFramebufferEXT(GL_DRAW_FRAMEBUFFER, hiz-fbo);
+ _mesa_BindFramebufferEXT(fb_bind_enum, hiz-fbo);
/* A rectangle primitive (3DPRIM_RECTLIST) consists of only three vertices.
@@ -316,7 +340,7 @@ gen6_resolve_slice(struct intel_context *intel,
*/
gen6_hiz_teardown_depth_buffer(hiz-depth_rb);
_mesa_BindRenderbufferEXT(GL_RENDERBUFFER, save_renderbuffer);
- _mesa_BindFramebufferEXT(GL_DRAW_FRAMEBUFFER, save_drawbuffer);
+ _mesa_BindFramebufferEXT(fb_bind_enum, save_drawbuffer);
_mesa_meta_end(ctx);
}
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Mesa (8.0): gen6_hiz: Don't bind GL_DRAW_FRAMEBUFFER on GLES
Module: Mesa
Branch: 8.0
Commit: 399b9799de9980b8ebc0ba46304be207b28b7825
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=399b9799de9980b8ebc0ba46304be207b28b7825
Author: Neil Roberts n...@linux.intel.com
Date: Wed Nov 30 22:29:21 2011 +
gen6_hiz: Don't bind GL_DRAW_FRAMEBUFFER on GLES
When using Mesa with a GLES API, calling _mesa_FramebufferRenderbuffer
with GL_DRAW_FRAMEBUFFER will report a 'user error' because
get_framebuffer_target validates that this enum from the framebuffer
blit extension is only used on GL. To work around it this patch makes
it use the GL_FRAMEBUFFER enum instead in that case.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=43418
Note: This is a candidate for the 8.0 branch.
Signed-off-by: Chad Versace chad.vers...@linux.intel.com
(cherry picked from commit 9462b8447864c754252cd2580c9e1e4d36d5cc63)
---
src/mesa/drivers/dri/i965/gen6_hiz.c | 34 +-
1 files changed, 29 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen6_hiz.c
b/src/mesa/drivers/dri/i965/gen6_hiz.c
index e282511..92b1d61 100644
--- a/src/mesa/drivers/dri/i965/gen6_hiz.c
+++ b/src/mesa/drivers/dri/i965/gen6_hiz.c
@@ -109,6 +109,24 @@ static const uint32_t gen6_hiz_meta_save =
MESA_META_SELECT_FEEDBACK;
+static void
+gen6_hiz_get_framebuffer_enum(struct gl_context *ctx,
+ GLenum *bind_enum,
+ GLenum *get_enum)
+{
+ /* If the blit framebuffer extension isn't supported then Mesa will
+ report an error if we try to bind GL_DRAW_FRAMEBUFFER. However in
+ that case it should be safe to just save and restore
+ GL_FRAMEBUFFER instead. */
+ if (ctx-Extensions.EXT_framebuffer_blit ctx-API == API_OPENGL) {
+ *bind_enum = GL_DRAW_FRAMEBUFFER;
+ *get_enum = GL_DRAW_FRAMEBUFFER_BINDING;
+ } else {
+ *bind_enum = GL_FRAMEBUFFER;
+ *get_enum = GL_FRAMEBUFFER_BINDING;
+ }
+}
+
/**
* Initialize static data needed for HiZ operations.
*/
@@ -117,10 +135,13 @@ gen6_hiz_init(struct brw_context *brw)
{
struct gl_context *ctx = brw-intel.ctx;
struct brw_hiz_state *hiz = brw-hiz;
+ GLenum fb_bind_enum, fb_get_enum;
if (hiz-fbo != 0)
return;
+ gen6_hiz_get_framebuffer_enum(ctx, fb_bind_enum, fb_get_enum);
+
/* Create depthbuffer.
*
* Until glRenderbufferStorage is called, the renderbuffer hash table
@@ -139,8 +160,8 @@ gen6_hiz_init(struct brw_context *brw)
/* Setup FBO. */
_mesa_GenFramebuffersEXT(1, hiz-fbo);
- _mesa_BindFramebufferEXT(GL_DRAW_FRAMEBUFFER, hiz-fbo);
- _mesa_FramebufferRenderbufferEXT(GL_DRAW_FRAMEBUFFER,
+ _mesa_BindFramebufferEXT(fb_bind_enum, hiz-fbo);
+ _mesa_FramebufferRenderbufferEXT(fb_bind_enum,
GL_DEPTH_ATTACHMENT,
GL_RENDERBUFFER,
hiz-depth_rb-Name);
@@ -241,6 +262,7 @@ gen6_resolve_slice(struct intel_context *intel,
struct gl_context *ctx = intel-ctx;
struct brw_context *brw = brw_context(ctx);
struct brw_hiz_state *hiz = brw-hiz;
+ GLenum fb_bind_enum, fb_get_enum;
/* Do not recurse. */
assert(!brw-hiz.op);
@@ -250,11 +272,13 @@ gen6_resolve_slice(struct intel_context *intel,
assert(level = mt-last_level);
assert(layer mt-level[level].depth);
+ gen6_hiz_get_framebuffer_enum(ctx, fb_bind_enum, fb_get_enum);
+
/* Save state. */
GLint save_drawbuffer;
GLint save_renderbuffer;
_mesa_meta_begin(ctx, gen6_hiz_meta_save);
- _mesa_GetIntegerv(GL_DRAW_FRAMEBUFFER_BINDING, save_drawbuffer);
+ _mesa_GetIntegerv(fb_get_enum, save_drawbuffer);
_mesa_GetIntegerv(GL_RENDERBUFFER_BINDING, save_renderbuffer);
/* Initialize context data for HiZ operations. */
@@ -272,7 +296,7 @@ gen6_resolve_slice(struct intel_context *intel,
/* Setup FBO. */
gen6_hiz_setup_depth_buffer(brw, mt, level, layer);
- _mesa_BindFramebufferEXT(GL_DRAW_FRAMEBUFFER, hiz-fbo);
+ _mesa_BindFramebufferEXT(fb_bind_enum, hiz-fbo);
/* A rectangle primitive (3DPRIM_RECTLIST) consists of only three vertices.
@@ -316,7 +340,7 @@ gen6_resolve_slice(struct intel_context *intel,
*/
gen6_hiz_teardown_depth_buffer(hiz-depth_rb);
_mesa_BindRenderbufferEXT(GL_RENDERBUFFER, save_renderbuffer);
- _mesa_BindFramebufferEXT(GL_DRAW_FRAMEBUFFER, save_drawbuffer);
+ _mesa_BindFramebufferEXT(fb_bind_enum, save_drawbuffer);
_mesa_meta_end(ctx);
}
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Mesa (master): i965: Comment gen6_hiz_get_framebuffer_enum()
Module: Mesa
Branch: master
Commit: e13c99a0043854cb286c773faa891a3115cd0a68
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e13c99a0043854cb286c773faa891a3115cd0a68
Author: Chad Versace chad.vers...@linux.intel.com
Date: Fri Jan 13 10:26:01 2012 -0800
i965: Comment gen6_hiz_get_framebuffer_enum()
Make the comments precise. Explain why each branch is needed and correct.
Document the potential pitfall in the true-branch.
Signed-off-by: Chad Versace chad.vers...@linux.intel.com
---
src/mesa/drivers/dri/i965/gen6_hiz.c | 10 ++
1 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen6_hiz.c
b/src/mesa/drivers/dri/i965/gen6_hiz.c
index 92b1d61..4d36729 100644
--- a/src/mesa/drivers/dri/i965/gen6_hiz.c
+++ b/src/mesa/drivers/dri/i965/gen6_hiz.c
@@ -114,14 +114,16 @@ gen6_hiz_get_framebuffer_enum(struct gl_context *ctx,
GLenum *bind_enum,
GLenum *get_enum)
{
- /* If the blit framebuffer extension isn't supported then Mesa will
- report an error if we try to bind GL_DRAW_FRAMEBUFFER. However in
- that case it should be safe to just save and restore
- GL_FRAMEBUFFER instead. */
if (ctx-Extensions.EXT_framebuffer_blit ctx-API == API_OPENGL) {
+ /* Different buffers may be bound to GL_DRAW_FRAMEBUFFER and
+ * GL_READ_FRAMEBUFFER. Take care to not disrupt the read buffer.
+ */
*bind_enum = GL_DRAW_FRAMEBUFFER;
*get_enum = GL_DRAW_FRAMEBUFFER_BINDING;
} else {
+ /* The enums GL_DRAW_FRAMEBUFFER and GL_READ_FRAMEBUFFER do not exist.
+ * The bound framebuffer is both the read and draw buffer.
+ */
*bind_enum = GL_FRAMEBUFFER;
*get_enum = GL_FRAMEBUFFER_BINDING;
}
___
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Mesa (master): i965: Fix gen6, gen7 when used with a non-HiZ capable DDX
Module: Mesa
Branch: master
Commit: 7e08bf08d13228001f6306800b5bd69b89b1bb6f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7e08bf08d13228001f6306800b5bd69b89b1bb6f
Author: Chad Versace chad.vers...@linux.intel.com
Date: Tue Dec 27 10:52:44 2011 -0800
i965: Fix gen6,gen7 when used with a non-HiZ capable DDX
Nothing works if HiZ is enabled and the DDX is incapable of HiZ (that is,
the DDX version is 2.16).
The problem is that the refactoring that eliminated
intel_renderbuffer::stencil_rb broke the recovery path in
intel_verify_dri2_has_hiz(). Specifically, it broke line
intel_context.c:1445, which allocates the region for
DRI_BUFFER_DEPTH_STENCIL. That allocation was creating a separate stencil
miptree, despite the buffer being a packed depthstencil buffer. Havoc
ensued.
This patch introduces a bool flag that prevents allocation of that stencil
miptree.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=44103
Tested-by: Ian Romanick i...@freedesktop.org
Note: This is a candidate for the 8.0 branch.
Signed-off-by: Chad Versace chad.vers...@linux.intel.com
---
src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 17 +
1 files changed, 13 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
index 4e1a502..eae79c1 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
@@ -58,6 +58,11 @@ target_to_target(GLenum target)
}
}
+/**
+ * @param for_region Indicates that the caller is
+ *intel_miptree_create_for_region(). If true, then do not create
+ *\c stencil_mt.
+ */
static struct intel_mipmap_tree *
intel_miptree_create_internal(struct intel_context *intel,
GLenum target,
@@ -66,7 +71,8 @@ intel_miptree_create_internal(struct intel_context *intel,
GLuint last_level,
GLuint width0,
GLuint height0,
- GLuint depth0)
+ GLuint depth0,
+ bool for_region)
{
struct intel_mipmap_tree *mt = calloc(sizeof(*mt), 1);
int compress_byte = 0;
@@ -106,7 +112,8 @@ intel_miptree_create_internal(struct intel_context *intel,
mt-cpp = 2;
}
- if (_mesa_is_depthstencil_format(_mesa_get_format_base_format(format))
+ if (!for_region
+ _mesa_is_depthstencil_format(_mesa_get_format_base_format(format))
(intel-must_use_separate_stencil ||
(intel-has_separate_stencil
intel-vtbl.is_hiz_depth_format(intel, format {
@@ -199,7 +206,8 @@ intel_miptree_create(struct intel_context *intel,
mt = intel_miptree_create_internal(intel, target, format,
first_level, last_level, width0,
- height0, depth0);
+ height0, depth0,
+ false);
/*
* pitch == 0 || height == 0 indicates the null texture
*/
@@ -234,7 +242,8 @@ intel_miptree_create_for_region(struct intel_context *intel,
mt = intel_miptree_create_internal(intel, target, format,
0, 0,
- region-width, region-height, 1);
+ region-width, region-height, 1,
+ true);
if (!mt)
return mt;
___
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Mesa (master): i965/gen5: Fix rendering of depth buffers without stencil [ v2]
Module: Mesa
Branch: master
Commit: a6dd4bf5fcce2520ab199201fdd1ad155457d781
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a6dd4bf5fcce2520ab199201fdd1ad155457d781
Author: Chad Versace chad.vers...@linux.intel.com
Date: Tue Jan 17 15:41:46 2012 -0800
i965/gen5: Fix rendering of depth buffers without stencil [v2]
Fixes the following OGLConform tests on gen5:
depth-stencil(misc.state_on.depth_int)
fbo_db_ARBfp(basic.OnlyDepthBuffDrawBufferRender)
The problem was that, if the depth buffer's Mesa format was X8_Z24, then
we emitted the hardware format D24_UNORM_X8. But, on gen5, D24_UNORM_S8
must be emitted.
This bug was introduced by:
commit d84a180417d1eabd680554970f1eaaa93abcd41e
Author: Eric Anholt e...@anholt.net
i965: Base HW depth format setup based on MESA_FORMAT, not bpp.
v2: Deref 'intel' directly. Move the branch for newer chipset to top.
Quote the PRM. As requested by Ken.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=43408
Note: This is a candidate for the 8.0 branch.
Reported-by: Xunx Fang xunx.f...@intel.com
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
Signed-off-by: Chad Versace chad.vers...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_misc_state.c | 17 +++--
1 files changed, 15 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c
b/src/mesa/drivers/dri/i965/brw_misc_state.c
index b6bca4b..8e59a47 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -223,10 +223,23 @@ brw_depthbuffer_format(struct brw_context *brw)
case MESA_FORMAT_Z32_FLOAT:
return BRW_DEPTHFORMAT_D32_FLOAT;
case MESA_FORMAT_X8_Z24:
- if (intel-gen = 5)
+ if (intel-gen = 6) {
return BRW_DEPTHFORMAT_D24_UNORM_X8_UINT;
- else /* Gen4 doesn't support X8; use S8 instead. */
+ } else {
+/* Use D24_UNORM_S8, not D24_UNORM_X8.
+ *
+ * D24_UNORM_X8 was not introduced until Gen5. (See the Ironlake PRM,
+ * Volume 2, Part 1, Section 8.4.6 Depth/Stencil Buffer State, Bits
+ * 3DSTATE_DEPTH_BUFFER.Surface_Format).
+ *
+ * However, on Gen5, D24_UNORM_X8 may be used only if separate
+ * stencil is enabled, and we never enable it. From the Ironlake PRM,
+ * same section as above, Bit
3DSTATE_DEPTH_BUFFER.Separate_Stencil_Buffer_Enable:
+ * If this field is disabled, the Surface Format of the depth
+ * buffer cannot be D24_UNORM_X8_UINT.
+ */
return BRW_DEPTHFORMAT_D24_UNORM_S8_UINT;
+ }
case MESA_FORMAT_S8_Z24:
return BRW_DEPTHFORMAT_D24_UNORM_S8_UINT;
case MESA_FORMAT_Z32_FLOAT_X24S8:
___
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Mesa (master): mesa: Loosen glBlitFramebuffer restrictions on depthstencil buffers (v2)
Module: Mesa
Branch: master
Commit: f74d8aacbf2f6d140381e272d17c31162a3481b3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f74d8aacbf2f6d140381e272d17c31162a3481b3
Author: Chad Versace chad.vers...@linux.intel.com
Date: Tue Jan 17 12:01:34 2012 -0800
mesa: Loosen glBlitFramebuffer restrictions on depthstencil buffers (v2)
This loosens the format validation in glBlitFramebuffer. When blitting
depth bits, don't require an exact match between the depth formats; only
require that the two formats have the same number of depth bits and the
same depth datatype (float vs uint). Ditto for stencil.
Between S8_Z24 buffers, the EXT_framebuffer_blit spec allows
glBlitFramebuffer to blit the depth and stencil bits separately. So I see
no reason to prevent blitting the depth bits between X8_Z24 and S8_Z24 or
the stencil bits between S8 and S8_Z24. However, we of course don't want
to allow blitting from Z32 to Z32_FLOAT.
Fixes Piglit fbo/fbo-blit-d24s8 on Intel drivers with separate stencil
enabled.
The problem was that, on Intel drivers with separate stencil, the default
framebuffer has separate depth and stencil buffers with formats X8_Z24 and
S8. The test attempts to blit the depth bits from a S8_Z24 buffer into the
default framebuffer.
v2: Check that depth datatypes match.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=44665
Note: This is a candidate for the 8.0 branch.
Reported-by: Xunx Fang xunx.f...@intel.com
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
Signed-off-by: Chad Versace chad.vers...@linux.intel.com
---
src/mesa/main/fbobject.c | 13 ++---
1 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/src/mesa/main/fbobject.c b/src/mesa/main/fbobject.c
index 0524959..2b3ac2e 100644
--- a/src/mesa/main/fbobject.c
+++ b/src/mesa/main/fbobject.c
@@ -2709,9 +2709,13 @@ _mesa_BlitFramebufferEXT(GLint srcX0, GLint srcY0, GLint
srcX1, GLint srcY1,
if ((readRb == NULL) || (drawRb == NULL)) {
mask = ~GL_STENCIL_BUFFER_BIT;
}
- else if (readRb-Format != drawRb-Format) {
+ else if (_mesa_get_format_bits(readRb-Format, GL_STENCIL_BITS) !=
+ _mesa_get_format_bits(drawRb-Format, GL_STENCIL_BITS)) {
+/* There is no need to check the stencil datatype here, because
+ * there is only one: GL_UNSIGNED_INT.
+ */
_mesa_error(ctx, GL_INVALID_OPERATION,
- glBlitFramebufferEXT(stencil buffer format mismatch));
+ glBlitFramebufferEXT(stencil buffer size mismatch));
return;
}
}
@@ -2731,7 +2735,10 @@ _mesa_BlitFramebufferEXT(GLint srcX0, GLint srcY0, GLint
srcX1, GLint srcY1,
if ((readRb == NULL) || (drawRb == NULL)) {
mask = ~GL_DEPTH_BUFFER_BIT;
}
- else if (readRb-Format != drawRb-Format) {
+ else if ((_mesa_get_format_bits(readRb-Format, GL_DEPTH_BITS) !=
+ _mesa_get_format_bits(drawRb-Format, GL_DEPTH_BITS)) ||
+ (_mesa_get_format_datatype(readRb-Format) !=
+ _mesa_get_format_datatype(drawRb-Format))) {
_mesa_error(ctx, GL_INVALID_OPERATION,
glBlitFramebufferEXT(depth buffer format mismatch));
return;
___
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Mesa (master): intel/gen6: Some framebuffers having separate depthstencil should be unsupported
Module: Mesa
Branch: master
Commit: ba5252e590782a77b8a46d9c0ec4691cf8da6298
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ba5252e590782a77b8a46d9c0ec4691cf8da6298
Author: Chad Versace chad.vers...@linux.intel.com
Date: Thu Jan 19 13:08:48 2012 -0800
intel/gen6: Some framebuffers having separate depthstencil should be unsupported
When the framebuffer has separate depth and stencil buffers, and HiZ is
not enabled on the depth buffer, mark the framebuffer as unsupported. This
happens when trying to create a framebuffer with Z16/S8 because we haven't
enabled HiZ on Z16 yet.
Fixes gles2conform test stencil8.
Note: This is a candiate for the 8.0 branch.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=44948
Reviewed-and-tested-by: Ian Romanick ian.d.roman...@intel.com
Reviewed--by: Eric Anholt e...@anholt.net
Signed-off-by: Chad Versace chad.vers...@linux.intel.com
---
src/mesa/drivers/dri/intel/intel_fbo.c |9 +
1 files changed, 9 insertions(+), 0 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c
b/src/mesa/drivers/dri/intel/intel_fbo.c
index c37075c..45a6827 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.c
+++ b/src/mesa/drivers/dri/intel/intel_fbo.c
@@ -804,6 +804,15 @@ intel_validate_framebuffer(struct gl_context *ctx, struct
gl_framebuffer *fb)
fb-_Status = GL_FRAMEBUFFER_UNSUPPORTED_EXT;
if (stencil_mt-format != MESA_FORMAT_S8)
fb-_Status = GL_FRAMEBUFFER_UNSUPPORTED_EXT;
+if (intel-gen 7 depth_mt-hiz_mt == NULL) {
+ /* Before Gen7, separate depth and stencil buffers can be used
+* only if HiZ is enabled. From the Sandybridge PRM, Volume 2,
+* Part 1, Bit 3DSTATE_DEPTH_BUFFER.SeparateStencilBufferEnable:
+* [DevSNB]: This field must be set to the same value (enabled
+* or disabled) as Hierarchical Depth Buffer Enable.
+*/
+ fb-_Status = GL_FRAMEBUFFER_UNSUPPORTED;
+}
}
}
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Mesa (master): swrast: Fix unsigned promotion in pointer arithmetic
Module: Mesa
Branch: master
Commit: aed5c8299fe47b8e1728f8140d069bc89d3fa947
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=aed5c8299fe47b8e1728f8140d069bc89d3fa947
Author: Chad Versace chad.vers...@linux.intel.com
Date: Wed Jan 18 15:56:58 2012 -0800
swrast: Fix unsigned promotion in pointer arithmetic
When rowstride was negatie, unsigned promotion caused a segfault here:
299│if (rb-Format == MESA_FORMAT_S8) {
300│ const GLuint rowStride = rb-RowStride;
301│ for (i = 0; i count; i++) {
302│ if (x[i] = 0 y[i] = 0 x[i] w y[i] h) {
303├stencil[i] = *(map + y[i] * rowStride + x[i]);
304│ }
305│ }
306│}
Fixes segfault in oglconform
separatestencil-neu(NonPolygon.BothFacesBitmapCoreAPI),
though test still fails.
Note: This is a candidate for the stable branches.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=43327
Reviewed-by: Brian Paul bri...@vmware.com
Signed-off-by: Chad Versace chad.vers...@linux.intel.com
---
src/mesa/swrast/s_stencil.c |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/mesa/swrast/s_stencil.c b/src/mesa/swrast/s_stencil.c
index dbcbd2b..fb95ef1 100644
--- a/src/mesa/swrast/s_stencil.c
+++ b/src/mesa/swrast/s_stencil.c
@@ -297,7 +297,7 @@ get_s8_values(struct gl_context *ctx, struct
gl_renderbuffer *rb,
GLuint i;
if (rb-Format == MESA_FORMAT_S8) {
- const GLuint rowStride = rb-RowStride;
+ const GLint rowStride = rb-RowStride;
for (i = 0; i count; i++) {
if (x[i] = 0 y[i] = 0 x[i] w y[i] h) {
stencil[i] = *(map + y[i] * rowStride + x[i]);
@@ -305,8 +305,8 @@ get_s8_values(struct gl_context *ctx, struct
gl_renderbuffer *rb,
}
}
else {
- const GLuint bpp = _mesa_get_format_bytes(rb-Format);
- const GLuint rowStride = rb-RowStride * bpp;
+ const GLint bpp = _mesa_get_format_bytes(rb-Format);
+ const GLint rowStride = rb-RowStride * bpp;
for (i = 0; i count; i++) {
if (x[i] = 0 y[i] = 0 x[i] w y[i] h) {
const GLubyte *src = map + y[i] * rowStride + x[i] * bpp;
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Mesa (master): swrast: Fix fixed-function fragment processing
Module: Mesa
Branch: master
Commit: 1c0f1dd42a50464eeb81de4aad8eecf24b3d6c89
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1c0f1dd42a50464eeb81de4aad8eecf24b3d6c89
Author: Chad Versace chad.vers...@linux.intel.com
Date: Wed Jan 25 19:38:10 2012 -0800
swrast: Fix fixed-function fragment processing
On i965, _mesa_ir_link_shader is never called. As a consequence, the
current fragment program (ctx-FragmentProgram-_Current) exists but is
invalid because it has no instructions. Yet swrast continued to attempt to
use the empty program.
To avoid using the empty program, this patch 1) defines a new function,
_swrast_use_fragment_program, which checks if the current fragment program
exists and differs from the fixed function fragment program, and, when
appropriate, 2) replaces checks of the form
if (ctx-FragmentProgram-_Current == NULL)
with
if (_swrast_use_fragment_program(ctx))
Fixes the following oglconform regressions on i965/gen6:
api-fogcoord(basic.allCases.log)
api-mtexcoord(basic.allCases.log)
api-seccolor(basic.allCases.log)
api-texcoord(basic.allCases.log)
blend-separate(basic.allCases)
colorsum(basic.allCases.log)
The tests were ran with the GLXFBConfig:
visual x bf lv rg d st colorbuffer sr ax dp st accumbuffer ms cav
id dep cl sp sz l ci b ro r g b a F gb bf th cl r g b a ns b eat
0x021 24 tc 0 32 0 r y . 8 8 8 8 . . 0 24 8 0 0 0 0 0 0 None
(Note: I originally believed that the hunk in
_swrast_update_fragment_program was unnecessary. But it is required to fix
blend-separate.)
Note: This is a candidate for the 8.0 branch.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=43327
Reveiwed-by: Eric Anholt e...@anholt.net
Reviewed-by: Ian Romanick i...@freedesktop.org
Signed-off-by: Chad Versace chad.vers...@linux.intel.com
---
src/mesa/swrast/s_aaline.c |2 +-
src/mesa/swrast/s_aalinetemp.h |2 +-
src/mesa/swrast/s_aatriangle.c |2 +-
src/mesa/swrast/s_context.c| 25 ++---
src/mesa/swrast/s_fragprog.c | 12
src/mesa/swrast/s_fragprog.h |2 ++
src/mesa/swrast/s_lines.c |2 +-
src/mesa/swrast/s_span.c | 38 +++---
src/mesa/swrast/s_triangle.c |4 ++--
9 files changed, 45 insertions(+), 44 deletions(-)
diff --git a/src/mesa/swrast/s_aaline.c b/src/mesa/swrast/s_aaline.c
index d4b1805..d36d876 100644
--- a/src/mesa/swrast/s_aaline.c
+++ b/src/mesa/swrast/s_aaline.c
@@ -479,7 +479,7 @@ _swrast_choose_aa_line_function(struct gl_context *ctx)
ASSERT(ctx-Line.SmoothFlag);
if (ctx-Texture._EnabledCoordUnits != 0
- || ctx-FragmentProgram._Current
+ || _swrast_use_fragment_program(ctx)
|| (ctx-Light.Enabled
ctx-Light.Model.ColorControl == GL_SEPARATE_SPECULAR_COLOR)
|| ctx-Fog.ColorSumEnabled
diff --git a/src/mesa/swrast/s_aalinetemp.h b/src/mesa/swrast/s_aalinetemp.h
index 376ef32..ba9f8ab 100644
--- a/src/mesa/swrast/s_aalinetemp.h
+++ b/src/mesa/swrast/s_aalinetemp.h
@@ -67,7 +67,7 @@ NAME(plot)(struct gl_context *ctx, struct LineInfo *line, int
ix, int iy)
ATTRIB_LOOP_BEGIN
GLfloat (*attribArray)[4] = line-span.array-attribs[attr];
if (attr = FRAG_ATTRIB_TEX0 attr FRAG_ATTRIB_VAR0
- !ctx-FragmentProgram._Current) {
+ !_swrast_use_fragment_program(ctx)) {
/* texcoord w/ divide by Q */
const GLuint unit = attr - FRAG_ATTRIB_TEX0;
const GLfloat invQ = solve_plane_recip(fx, fy,
line-attrPlane[attr][3]);
diff --git a/src/mesa/swrast/s_aatriangle.c b/src/mesa/swrast/s_aatriangle.c
index c68fdf6..b59177f 100644
--- a/src/mesa/swrast/s_aatriangle.c
+++ b/src/mesa/swrast/s_aatriangle.c
@@ -299,7 +299,7 @@ _swrast_set_aa_triangle_function(struct gl_context *ctx)
ASSERT(ctx-Polygon.SmoothFlag);
if (ctx-Texture._EnabledCoordUnits != 0
- || ctx-FragmentProgram._Current
+ || _swrast_use_fragment_program(ctx)
|| swrast-_FogEnabled
|| _mesa_need_secondary_color(ctx)) {
SWRAST_CONTEXT(ctx)-Triangle = general_aa_tri;
diff --git a/src/mesa/swrast/s_context.c b/src/mesa/swrast/s_context.c
index 14cb9b1..cc304d7 100644
--- a/src/mesa/swrast/s_context.c
+++ b/src/mesa/swrast/s_context.c
@@ -105,7 +105,7 @@ _swrast_update_rasterflags( struct gl_context *ctx )
}
- if (ctx-FragmentProgram._Current) {
+ if (_swrast_use_fragment_program(ctx)) {
rasterMask |= FRAGPROG_BIT;
}
@@ -170,7 +170,7 @@ _swrast_update_fog_hint( struct gl_context *ctx )
{
SWcontext *swrast = SWRAST_CONTEXT(ctx);
swrast-_PreferPixelFog = (!swrast-AllowVertexFog ||
- ctx-FragmentProgram._Current ||
+ _swrast_use_fragment_program(ctx) ||
(ctx-Hint.Fog == GL_NICEST
Mesa (master): i965: Rewrite the HiZ op
Module: Mesa Branch: master Commit: 7b36c68ba6899c7f30fd56b7ef07a78b027771ac URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7b36c68ba6899c7f30fd56b7ef07a78b027771ac Author: Chad Versace chad.vers...@linux.intel.com Date: Thu Jan 26 11:01:36 2012 -0800 i965: Rewrite the HiZ op The HiZ op was implemented as a meta-op. This patch reimplements it by emitting a special HiZ batch. This fixes several known bugs, and likely a lot of undiscovered ones too. Why the HiZ meta-op needed to die The HiZ op was implemented as a meta-op, which caused lots of trouble. All other meta-ops occur as a result of some GL call (for example, glClear and glGenerateMipmap), but the HiZ meta-op was special. It was called in places that Mesa (in particular, the vbo and swrast modules) did not expect---and were not prepared for---state changes to occur (for example: glDraw; glCallList; within glBegin/End blocks; and within swrast_prepare_render as a result of intel_miptree_map). In an attempt to work around these unexpected state changes, I added two hooks in i965: - A hook for glDraw, located in brw_predraw_resolve_buffers (which is called in the glDraw path). This hook detected if a predraw resolve meta-op had occurred, and would hackishly repropagate some GL state if necessary. This ensured that the meta-op state changes would not intefere with the vbo module's subsequent execution of glDraw. - A hook for glBegin, implemented by brwPrepareExecBegin. This hook resolved all buffers before entering a glBegin/End block, thus preventing an infinitely recurring call to vbo_exec_FlushVertices. The vbo module calls vbo_exec_FlushVertices to flush its vertex queue in response to GL state changes. Unfortunately, these hooks were not sufficient. The meta-op state changes still interacted badly with glPopAttrib (as discovered in bug 44927) and with swrast rendering (as discovered by debugging gen6's swrast fallback for glBitmap). I expect there are more undiscovered bugs. Rather than play whack-a-mole in a minefield, the sane approach is to replace the HiZ meta-op with something safer. How it was killed This patch consists of several logical components: 1. Rewrite the HiZ op by replacing function gen6_resolve_slice with gen6_hiz_exec and gen7_hiz_exec. The new functions do not call a meta-op, but instead manually construct and emit a batch to draw the HiZ op's rectangle primitive. The new functions alter no GL state. 2. Add fields to brw_context::hiz for the new HiZ op. 3. Emit a workaround flush when toggling 3DSTATE_VS.VsFunctionEnable. 4. Kill all dead HiZ code: - the function gen6_resolve_slice - the dirty flag BRW_NEW_HIZ - the dead fields in brw_context::hiz - the state packet manipulation triggered by the now removed brw_context::hiz::op - the meta-op workaround in brw_predraw_resolve_buffers (discussed above) - the meta-op workaround brwPrepareExecBegin (discussed above) Note: This is a candidate for the 8.0 branch. Reviewed-by: Eric Anholt e...@anholt.net Reviewed-by: Kenneth Graunke kenn...@whitecape.org Acked-by: Paul Berry stereotype...@gmail.com Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=43327 Reported-by: xunx.f...@intel.com Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=44927 Reported-by: chao.a.c...@intel.com Signed-off-by: Chad Versace chad.vers...@linux.intel.com --- src/mesa/drivers/dri/i965/Makefile.sources|1 + src/mesa/drivers/dri/i965/brw_context.c | 55 -- src/mesa/drivers/dri/i965/brw_context.h | 40 +- src/mesa/drivers/dri/i965/brw_draw.c | 47 +-- src/mesa/drivers/dri/i965/brw_state_upload.c |1 - src/mesa/drivers/dri/i965/brw_vtbl.c | 14 +- src/mesa/drivers/dri/i965/gen6_clip_state.c | 20 +- src/mesa/drivers/dri/i965/gen6_depthstencil.c |9 +- src/mesa/drivers/dri/i965/gen6_hiz.c | 830 src/mesa/drivers/dri/i965/gen6_hiz.h | 38 ++ src/mesa/drivers/dri/i965/gen6_sf_state.c | 16 +- src/mesa/drivers/dri/i965/gen6_vs_state.c |9 + src/mesa/drivers/dri/i965/gen6_wm_state.c | 20 +- src/mesa/drivers/dri/i965/gen7_clip_state.c | 20 +- src/mesa/drivers/dri/i965/gen7_hiz.c | 463 ++ src/mesa/drivers/dri/i965/gen7_hiz.h | 43 ++ src/mesa/drivers/dri/i965/gen7_sf_state.c | 19 +- src/mesa/drivers/dri/i965/gen7_wm_state.c | 18 - 18 files changed, 1146 insertions(+), 517 deletions(-) Diff: http://cgit.freedesktop.org/mesa/mesa/diff/?id=7b36c68ba6899c7f30fd56b7ef07a78b027771ac ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Remove file i965/junk, accidentally added in 7b36c68
Module: Mesa Branch: master Commit: b44c459cc32d0a4e70e86deae245b3097ac360a1 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b44c459cc32d0a4e70e86deae245b3097ac360a1 Author: Chad Versace chad.vers...@linux.intel.com Date: Wed Feb 8 09:18:46 2012 -0800 i965: Remove file i965/junk, accidentally added in 7b36c68 --- 0 files changed, 0 insertions(+), 0 deletions(-) diff --git a/src/mesa/drivers/dri/i965/junk b/src/mesa/drivers/dri/i965/junk deleted file mode 100644 index e69de29..000 ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): glsl: Fix Android build
Module: Mesa Branch: master Commit: 5497cc428fa7c6670d252d34f4a67c9498ae3895 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5497cc428fa7c6670d252d34f4a67c9498ae3895 Author: Chad Versace chad.vers...@linux.intel.com Date: Wed Feb 8 15:07:33 2012 -0800 glsl: Fix Android build The build was broken by the line below, added in commit 4f82fed4. s_expression.cpp:26: #include limits Mesa's half of the fix is to add 'external/astl/include' to the include path. The other half of the fix requires implementing numeric_limitsfloat::infinity() in astl, for which I have patches submitted upstream for review. Signed-off-by: Chad Versace chad.vers...@linux.intel.com --- src/glsl/Android.mk |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/src/glsl/Android.mk b/src/glsl/Android.mk index 754f3cc..cf793d6 100644 --- a/src/glsl/Android.mk +++ b/src/glsl/Android.mk @@ -39,6 +39,7 @@ LOCAL_SRC_FILES := \ $(LIBGLSL_CXX_FILES) LOCAL_C_INCLUDES := \ + external/astl/include \ $(MESA_TOP)/src/mapi \ $(MESA_TOP)/src/mesa ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (8.0): glsl: Fix Android build
Module: Mesa Branch: 8.0 Commit: 54f7391664d2cffe1f719d11fec1f18db672be5d URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=54f7391664d2cffe1f719d11fec1f18db672be5d Author: Chad Versace chad.vers...@linux.intel.com Date: Wed Feb 8 15:07:33 2012 -0800 glsl: Fix Android build The build was broken by the line below, added in commit 4f82fed4. s_expression.cpp:26: #include limits Mesa's half of the fix is to add 'external/astl/include' to the include path. The other half of the fix requires implementing numeric_limitsfloat::infinity() in astl, for which I have patches submitted upstream for review. Signed-off-by: Chad Versace chad.vers...@linux.intel.com (cherry picked from commit 5497cc428fa7c6670d252d34f4a67c9498ae3895) --- src/glsl/Android.mk |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/src/glsl/Android.mk b/src/glsl/Android.mk index d7d17dd..84a8655 100644 --- a/src/glsl/Android.mk +++ b/src/glsl/Android.mk @@ -39,6 +39,7 @@ LOCAL_SRC_FILES := \ $(LIBGLSL_CXX_SOURCES) LOCAL_C_INCLUDES := \ + external/astl/include \ $(MESA_TOP)/src/mapi \ $(MESA_TOP)/src/mesa ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): glsl: Fix linker bug in cross_validate_globals()
Module: Mesa
Branch: master
Commit: 7528f143dfb77e3e0486006676e990964392aebf
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7528f143dfb77e3e0486006676e990964392aebf
Author: Chad Versace chad.vers...@intel.com
Date: Wed Nov 17 14:34:38 2010 -0800
glsl: Fix linker bug in cross_validate_globals()
Cause linking to fail if a global has mismatching invariant qualifiers.
See https://bugs.freedesktop.org/show_bug.cgi?id=30261
---
src/glsl/linker.cpp |7 +++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/src/glsl/linker.cpp b/src/glsl/linker.cpp
index cde70ad..576b72a 100644
--- a/src/glsl/linker.cpp
+++ b/src/glsl/linker.cpp
@@ -411,6 +411,13 @@ cross_validate_globals(struct gl_shader_program *prog,
existing-constant_value =
var-constant_value-clone(talloc_parent(existing), NULL);
}
+
+ if (existing-invariant != var-invariant) {
+ linker_error_printf(prog, declarations for %s `%s' have
+ mismatching invariant qualifiers\n,
+ mode_string(var), var-name);
+ return false;
+ }
} else
variables.add_variable(var);
}
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Mesa (master): glsl: In ast_to_hir, check sampler array indexing
Module: Mesa
Branch: master
Commit: f0f2ec4d8a50c79c2943ac95eb790fb734d88980
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f0f2ec4d8a50c79c2943ac95eb790fb734d88980
Author: Chad Versace chad.vers...@intel.com
Date: Tue Dec 7 10:35:36 2010 -0800
glsl: In ast_to_hir, check sampler array indexing
Raise error if a sampler array is indexed with a non-constant expression.
From section 4.1.7 of the GLSL 1.30 spec:
Samplers aggregated into arrays within a shader (using square
brackets [ ]) can only be indexed with integral constant
expressions [...].
---
src/glsl/ast_to_hir.cpp | 14 ++
1 files changed, 14 insertions(+), 0 deletions(-)
diff --git a/src/glsl/ast_to_hir.cpp b/src/glsl/ast_to_hir.cpp
index 82b3f2e..1f4972c 100644
--- a/src/glsl/ast_to_hir.cpp
+++ b/src/glsl/ast_to_hir.cpp
@@ -1567,6 +1567,20 @@ ast_expression::hir(exec_list *instructions,
}
}
+ /* From section 4.1.7 of the GLSL 1.30 spec:
+ *Samplers aggregated into arrays within a shader (using square
+ *brackets [ ]) can only be indexed with integral constant
+ *expressions [...].
+ */
+ if (array-type-is_array()
+ array-type-element_type()-is_sampler()
+ const_index == NULL) {
+
+ _mesa_glsl_error(loc, state, sampler arrays can only be indexed
+ with constant expressions);
+ error_emitted = true;
+ }
+
if (error_emitted)
result-type = glsl_type::error_type;
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Mesa (master): glsl: Comment ast_type_qualifier.flags
Module: Mesa
Branch: master
Commit: 4a62a1c366703c5df10fd1d96f46ecb03ce45138
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4a62a1c366703c5df10fd1d96f46ecb03ce45138
Author: Chad Versace chad.vers...@intel.com
Date: Wed Dec 15 15:58:49 2010 -0800
glsl: Comment ast_type_qualifier.flags
---
src/glsl/ast.h |6 +-
1 files changed, 5 insertions(+), 1 deletions(-)
diff --git a/src/glsl/ast.h b/src/glsl/ast.h
index a77b522..cd933cf 100644
--- a/src/glsl/ast.h
+++ b/src/glsl/ast.h
@@ -349,7 +349,11 @@ struct ast_type_qualifier {
* qualifier is used.
*/
unsigned explicit_location:1;
- } q;
+ }
+ /** \brief Set of flags, accessed by name. */
+ q;
+
+ /** \brief Set of flags, accessed as a bitmask. */
unsigned i;
} flags;
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Mesa (master): glsl: Allow redeclaration of gl_Color and its variants in GLSL 1.30
Module: Mesa
Branch: master
Commit: b84e3f570f4b5aba1dd96760e090ae976d0e1cba
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b84e3f570f4b5aba1dd96760e090ae976d0e1cba
Author: Chad Versace chad.vers...@intel.com
Date: Wed Dec 15 16:32:47 2010 -0800
glsl: Allow redeclaration of gl_Color and its variants in GLSL 1.30
Allow redeclaration of the following built-in variables with an
interpolation qualifier in language versions = 1.30:
* gl_FrontColor
* gl_BackColor
* gl_FrontSecondaryColor
* gl_BackSecondaryColor
* gl_Color
* gl_SecondaryColor
See section 4.3.7 of the GLSL 1.30 spec.
---
src/glsl/ast_to_hir.cpp | 21 +
1 files changed, 21 insertions(+), 0 deletions(-)
diff --git a/src/glsl/ast_to_hir.cpp b/src/glsl/ast_to_hir.cpp
index 2baeffc..6770eed 100644
--- a/src/glsl/ast_to_hir.cpp
+++ b/src/glsl/ast_to_hir.cpp
@@ -2344,6 +2344,27 @@ ast_declarator_list::hir(exec_list *instructions,
*/
earlier-origin_upper_left = var-origin_upper_left;
earlier-pixel_center_integer = var-pixel_center_integer;
+
+/* According to section 4.3.7 of the GLSL 1.30 spec,
+ * the following built-in varaibles can be redeclared with an
+ * interpolation qualifier:
+ ** gl_FrontColor
+ ** gl_BackColor
+ ** gl_FrontSecondaryColor
+ ** gl_BackSecondaryColor
+ ** gl_Color
+ ** gl_SecondaryColor
+ */
+} else if (state-language_version = 130
+(strcmp(var-name, gl_FrontColor) == 0
+|| strcmp(var-name, gl_BackColor) == 0
+|| strcmp(var-name, gl_FrontSecondaryColor) == 0
+|| strcmp(var-name, gl_BackSecondaryColor) == 0
+|| strcmp(var-name, gl_Color) == 0
+|| strcmp(var-name, gl_SecondaryColor) == 0)
+earlier-type == var-type
+earlier-mode == var-mode) {
+ earlier-interpolation = var-interpolation;
} else {
YYLTYPE loc = this-get_location();
_mesa_glsl_error(loc, state, `%s' redeclared, decl-identifier);
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Mesa (master): glsl: Check that integer vertex outputs are qualified with flat
Module: Mesa
Branch: master
Commit: 68d06b1454aea30c492c7318ab4e8514df8f38fd
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=68d06b1454aea30c492c7318ab4e8514df8f38fd
Author: Chad Versace chad.vers...@intel.com
Date: Thu Dec 16 11:06:19 2010 -0800
glsl: Check that integer vertex outputs are qualified with flat
Perform this check in ast_declarator_list::hir().
From section 4.3.6 of the GLSL 1.30 spec:
If a vertex output is a signed or unsigned integer or integer
vector, then it must be qualified with the interpolation
qualifier
flat.
---
src/glsl/ast_to_hir.cpp | 19 +++
1 files changed, 19 insertions(+), 0 deletions(-)
diff --git a/src/glsl/ast_to_hir.cpp b/src/glsl/ast_to_hir.cpp
index 6770eed..67202df 100644
--- a/src/glsl/ast_to_hir.cpp
+++ b/src/glsl/ast_to_hir.cpp
@@ -2158,6 +2158,25 @@ ast_declarator_list::hir(exec_list *instructions,
}
}
+ /* Integer vertex outputs must be qualified with 'flat'.
+ *
+ * From section 4.3.6 of the GLSL 1.30 spec:
+ *If a vertex output is a signed or unsigned integer or integer
+ *vector, then it must be qualified with the interpolation qualifier
+ *flat.
+ */
+ if (state-language_version = 130
+ state-target == vertex_shader
+ state-current_function == NULL
+ var-type-is_integer()
+ var-mode == ir_var_out
+ var-interpolation != ir_var_flat) {
+
+ _mesa_glsl_error(loc, state, If a vertex output is an integer,
+ then it must be qualified with 'flat');
+ }
+
+
/* Process the initializer and add its instructions to a temporary
* list. This list will be added to the instruction stream (below) after
* the declaration is added. This is done because in some cases (such as
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Mesa (master): glsl: At link-time, check that globals have matching centroid qualifiers
Module: Mesa
Branch: master
Commit: 61428dd2ab66017f80dc4f3b0793e741d93a6d47
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=61428dd2ab66017f80dc4f3b0793e741d93a6d47
Author: Chad Versace chad.vers...@intel.com
Date: Mon Jan 10 15:29:30 2011 -0800
glsl: At link-time, check that globals have matching centroid qualifiers
Fixes bug 31923: http://bugs.freedesktop.org/show_bug.cgi?id=31923
---
src/glsl/linker.cpp |6 ++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/src/glsl/linker.cpp b/src/glsl/linker.cpp
index d8c42ac..c906d74 100644
--- a/src/glsl/linker.cpp
+++ b/src/glsl/linker.cpp
@@ -422,6 +422,12 @@ cross_validate_globals(struct gl_shader_program *prog,
mode_string(var), var-name);
return false;
}
+if (existing-centroid != var-centroid) {
+ linker_error_printf(prog, declarations for %s `%s' have
+ mismatching centroid qualifiers\n,
+ mode_string(var), var-name);
+ return false;
+}
} else
variables.add_variable(var);
}
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Mesa (master): glcpp: Regenerate glcpp-parse.c
Module: Mesa
Branch: master
Commit: 4e09a786d20ee5a2793e29d1cf336ad5383da22b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4e09a786d20ee5a2793e29d1cf336ad5383da22b
Author: Chad Versace chad.vers...@intel.com
Date: Mon Jan 10 17:09:24 2011 -0800
glcpp: Regenerate glcpp-parse.c
---
src/glsl/glcpp/glcpp-parse.c | 21 +
1 files changed, 21 insertions(+), 0 deletions(-)
diff --git a/src/glsl/glcpp/glcpp-parse.c b/src/glsl/glcpp/glcpp-parse.c
index ab7c30e..55ec165 100644
--- a/src/glsl/glcpp/glcpp-parse.c
+++ b/src/glsl/glcpp/glcpp-parse.c
@@ -3150,10 +3150,31 @@ _token_list_trim_trailing_space (token_list_t *list)
}
int
+_token_list_is_empty_ignoring_space (token_list_t *l)
+{
+ token_node_t *n;
+
+ if (l == NULL)
+ return 1;
+
+ n = l-head;
+ while (n != NULL n-token-type == SPACE)
+ n = n-next;
+
+ return n == NULL;
+}
+
+int
_token_list_equal_ignoring_space (token_list_t *a, token_list_t *b)
{
token_node_t *node_a, *node_b;
+ if (a == NULL || b == NULL) {
+ int a_empty = _token_list_is_empty_ignoring_space(a);
+ int b_empty = _token_list_is_empty_ignoring_space(b);
+ return a_empty == b_empty;
+ }
+
node_a = a-head;
node_b = b-head;
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Mesa (master): glcpp: Fix segfault when validating macro redefinitions
Module: Mesa
Branch: master
Commit: 4fff52f1c973f2f284c142fbb31536a9656767c9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4fff52f1c973f2f284c142fbb31536a9656767c9
Author: Chad Versace chad.vers...@intel.com
Date: Mon Jan 10 16:55:17 2011 -0800
glcpp: Fix segfault when validating macro redefinitions
In _token_list_equal_ignoring_space(token_list_t*, token_list_t*), add
a guard that prevents dereferncing a null token list.
This fixes test src/glsl/glcpp/tests/092-redefine-macro-error-2.c and
Bugzilla #32695.
---
src/glsl/glcpp/glcpp-parse.y | 21 +
1 files changed, 21 insertions(+), 0 deletions(-)
diff --git a/src/glsl/glcpp/glcpp-parse.y b/src/glsl/glcpp/glcpp-parse.y
index 558ad0a..148b0ff 100644
--- a/src/glsl/glcpp/glcpp-parse.y
+++ b/src/glsl/glcpp/glcpp-parse.y
@@ -825,10 +825,31 @@ _token_list_trim_trailing_space (token_list_t *list)
}
int
+_token_list_is_empty_ignoring_space (token_list_t *l)
+{
+ token_node_t *n;
+
+ if (l == NULL)
+ return 1;
+
+ n = l-head;
+ while (n != NULL n-token-type == SPACE)
+ n = n-next;
+
+ return n == NULL;
+}
+
+int
_token_list_equal_ignoring_space (token_list_t *a, token_list_t *b)
{
token_node_t *node_a, *node_b;
+ if (a == NULL || b == NULL) {
+ int a_empty = _token_list_is_empty_ignoring_space(a);
+ int b_empty = _token_list_is_empty_ignoring_space(b);
+ return a_empty == b_empty;
+ }
+
node_a = a-head;
node_b = b-head;
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Mesa (master): mesa: Refactor handling of extension strings
Module: Mesa Branch: master Commit: 9b260c377f5b437b7e03607fefa022459ef758ed URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9b260c377f5b437b7e03607fefa022459ef758ed Author: Chad Versace chad.vers...@intel.com Date: Sun Jan 9 10:53:52 2011 -0800 mesa: Refactor handling of extension strings Place GL, GLES1, and GLES2 extensions in a unified extension table. This allows one to enable, disable, and query the status of GLES1 and GLES2 extensions by name. When tested on Intel Ironlake, this patch did not alter the extension string [as given by glGetString(GL_EXTENSIONS)] for any API. Reviewed-by: Ian Romanick i...@freedesktop.org Reviewed-by: Brian Paul bri...@vmware.com --- src/mesa/main/extensions.c | 893 src/mesa/main/mtypes.h |3 + 2 files changed, 406 insertions(+), 490 deletions(-) Diff: http://cgit.freedesktop.org/mesa/mesa/diff/?id=9b260c377f5b437b7e03607fefa022459ef758ed ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): mesa: Add/remove extensions in extension string
Module: Mesa
Branch: master
Commit: 19418e921af0efce198627d0ce6c92660797d011
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=19418e921af0efce198627d0ce6c92660797d011
Author: Chad Versace chad.vers...@intel.com
Date: Sun Jan 9 21:53:52 2011 -0800
mesa: Add/remove extensions in extension string
Add GL_OES_stencil8 to ES2.
Remove the following:
GL_OES_compressed_paletted_texture : ES1
GL_OES_depth32 : ES1, ES2
GL_OES_stencil1: ES1, ES2
GL_OES_stencil4: ES1, ES2
Mesa advertised these extensions, but did not actually support them.
Reviewed-by: Ian Romanick i...@freedesktop.org
---
src/mesa/main/extensions.c | 10 +-
1 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/src/mesa/main/extensions.c b/src/mesa/main/extensions.c
index ca03c09..851bf9e 100644
--- a/src/mesa/main/extensions.c
+++ b/src/mesa/main/extensions.c
@@ -208,9 +208,9 @@ static const struct extension extension_table[] = {
{ GL_OES_blend_func_separate, o(EXT_blend_func_separate),
ES1 },
{ GL_OES_blend_subtract, o(EXT_blend_subtract),
ES1 },
{ GL_OES_byte_coordinates,o(dummy_true),
ES1 },
- { GL_OES_compressed_paletted_texture, o(dummy_true),
ES1 },
+ { GL_OES_compressed_paletted_texture, o(dummy_false),
DISABLE},
{ GL_OES_depth24, o(ARB_framebuffer_object),
ES1 | ES2 },
- { GL_OES_depth32, o(ARB_framebuffer_object),
ES1 | ES2 },
+ { GL_OES_depth32, o(dummy_false),
DISABLE},
{ GL_OES_depth_texture, o(ARB_depth_texture),
ES2 },
#if FEATURE_OES_draw_texture
{ GL_OES_draw_texture,o(OES_draw_texture),
ES1 | ES2 },
@@ -233,9 +233,9 @@ static const struct extension extension_table[] = {
{ GL_OES_rgb8_rgba8, o(ARB_framebuffer_object),
ES1 | ES2 },
{ GL_OES_single_precision,o(dummy_true),
ES1 },
{ GL_OES_standard_derivatives,o(ARB_fragment_shader),
ES2 },
- { GL_OES_stencil1,o(ARB_framebuffer_object),
ES1 | ES2 },
- { GL_OES_stencil4,o(ARB_framebuffer_object),
ES1 | ES2 },
- { GL_OES_stencil8,o(ARB_framebuffer_object),
ES1 },
+ { GL_OES_stencil1,o(dummy_false),
DISABLE},
+ { GL_OES_stencil4,o(dummy_false),
DISABLE},
+ { GL_OES_stencil8,o(ARB_framebuffer_object),
ES1 | ES2 },
{ GL_OES_stencil_wrap,o(EXT_stencil_wrap),
ES1 },
/* GL_OES_texture_3D is disabled due to missing GLSL support. */
{ GL_OES_texture_3D, o(EXT_texture3D),
DISABLE},
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Mesa (master): mesa: Change dependencies of some OES extension strings
Module: Mesa
Branch: master
Commit: 039150169e99be28d8b172a95a07032a3c862585
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=039150169e99be28d8b172a95a07032a3c862585
Author: Chad Versace chad.vers...@intel.com
Date: Tue Jan 11 14:56:13 2011 -0800
mesa: Change dependencies of some OES extension strings
Change all OES extension strings that depend on ARB_framebuffer_object to
instead depend on EXT_framebuffer_object.
Reviewed-by: Ian Romanick i...@freedesktop.org
---
src/mesa/main/extensions.c | 10 +-
1 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/src/mesa/main/extensions.c b/src/mesa/main/extensions.c
index 851bf9e..fff4c6e 100644
--- a/src/mesa/main/extensions.c
+++ b/src/mesa/main/extensions.c
@@ -209,7 +209,7 @@ static const struct extension extension_table[] = {
{ GL_OES_blend_subtract, o(EXT_blend_subtract),
ES1 },
{ GL_OES_byte_coordinates,o(dummy_true),
ES1 },
{ GL_OES_compressed_paletted_texture, o(dummy_false),
DISABLE},
- { GL_OES_depth24, o(ARB_framebuffer_object),
ES1 | ES2 },
+ { GL_OES_depth24, o(EXT_framebuffer_object),
ES1 | ES2 },
{ GL_OES_depth32, o(dummy_false),
DISABLE},
{ GL_OES_depth_texture, o(ARB_depth_texture),
ES2 },
#if FEATURE_OES_draw_texture
@@ -220,9 +220,9 @@ static const struct extension extension_table[] = {
{ GL_OES_EGL_image, o(OES_EGL_image),
GL | ES1 | ES2 },
#endif
{ GL_OES_element_index_uint, o(EXT_vertex_array),
ES1 | ES2 },
- { GL_OES_fbo_render_mipmap, o(ARB_framebuffer_object),
ES1 | ES2 },
+ { GL_OES_fbo_render_mipmap, o(EXT_framebuffer_object),
ES1 | ES2 },
{ GL_OES_fixed_point, o(dummy_true),
ES1 },
- { GL_OES_framebuffer_object, o(ARB_framebuffer_object),
ES1 },
+ { GL_OES_framebuffer_object, o(EXT_framebuffer_object),
ES1 },
{ GL_OES_mapbuffer,
o(ARB_vertex_buffer_object), ES1 | ES2 },
{ GL_OES_matrix_get, o(dummy_true),
ES1 },
{ GL_OES_packed_depth_stencil,
o(EXT_packed_depth_stencil), ES1 | ES2 },
@@ -230,12 +230,12 @@ static const struct extension extension_table[] = {
{ GL_OES_point_sprite,o(dummy_true),
ES1 },
{ GL_OES_query_matrix,o(dummy_true),
ES1 },
{ GL_OES_read_format, o(OES_read_format),
GL | ES1 },
- { GL_OES_rgb8_rgba8, o(ARB_framebuffer_object),
ES1 | ES2 },
+ { GL_OES_rgb8_rgba8, o(EXT_framebuffer_object),
ES1 | ES2 },
{ GL_OES_single_precision,o(dummy_true),
ES1 },
{ GL_OES_standard_derivatives,o(ARB_fragment_shader),
ES2 },
{ GL_OES_stencil1,o(dummy_false),
DISABLE},
{ GL_OES_stencil4,o(dummy_false),
DISABLE},
- { GL_OES_stencil8,o(ARB_framebuffer_object),
ES1 | ES2 },
+ { GL_OES_stencil8,o(EXT_framebuffer_object),
ES1 | ES2 },
{ GL_OES_stencil_wrap,o(EXT_stencil_wrap),
ES1 },
/* GL_OES_texture_3D is disabled due to missing GLSL support. */
{ GL_OES_texture_3D, o(EXT_texture3D),
DISABLE},
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Mesa (master): mesa: Change OES_point_sprite to depend on ARB_point_sprite
Module: Mesa
Branch: master
Commit: a7b5664c05a7a0bdc999caedf2dea17fee6bb5c8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a7b5664c05a7a0bdc999caedf2dea17fee6bb5c8
Author: Chad Versace chad.vers...@intel.com
Date: Wed Jan 12 15:21:23 2011 -0800
mesa: Change OES_point_sprite to depend on ARB_point_sprite
The extension string in GLES1 contexts always advertised
GL_OES_point_sprite. Now advertisement depends on ARB_point_sprite being
enabled.
Reviewed-by: Ian Romanick i...@freedesktop.org
---
src/mesa/main/extensions.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/src/mesa/main/extensions.c b/src/mesa/main/extensions.c
index fff4c6e..750b12f 100644
--- a/src/mesa/main/extensions.c
+++ b/src/mesa/main/extensions.c
@@ -227,7 +227,7 @@ static const struct extension extension_table[] = {
{ GL_OES_matrix_get, o(dummy_true),
ES1 },
{ GL_OES_packed_depth_stencil,
o(EXT_packed_depth_stencil), ES1 | ES2 },
{ GL_OES_point_size_array,o(dummy_true),
ES1 },
- { GL_OES_point_sprite,o(dummy_true),
ES1 },
+ { GL_OES_point_sprite,o(ARB_point_sprite),
ES1 },
{ GL_OES_query_matrix,o(dummy_true),
ES1 },
{ GL_OES_read_format, o(OES_read_format),
GL | ES1 },
{ GL_OES_rgb8_rgba8, o(EXT_framebuffer_object),
ES1 | ES2 },
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Mesa (master): i965/brw: Emit state for hiz and separate stencil buffers
Module: Mesa
Branch: master
Commit: 2abc8cae87b4cd037ebde68b4b9a1d02254657df
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2abc8cae87b4cd037ebde68b4b9a1d02254657df
Author: Chad Versace c...@chad-versace.us
Date: Mon May 23 13:48:28 2011 -0700
i965/brw: Emit state for hiz and separate stencil buffers
When emitting 3DSTATE_DEPTH_BUFFER, also emit 3DSTATE_HIER_DEPTH_BUFFER if
there is a hiz buffer. Ditto for 3DSTATE_STENCIL_BUFFER and a separate
stencil buffer.
Reviewed-by: Eric Anholt e...@anholt.net
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
Signed-off-by: Chad Versace c...@chad-versace.us
---
src/mesa/drivers/dri/i965/brw_misc_state.c | 114 --
src/mesa/drivers/dri/i965/brw_wm_surface_state.c |2 +
2 files changed, 107 insertions(+), 9 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c
b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 3ec9009..4256234 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -202,6 +202,8 @@ static void prepare_depthbuffer(struct brw_context *brw)
if (drb)
brw_add_validated_bo(brw, drb-region-buffer);
+ if (drb drb-hiz_region)
+ brw_add_validated_bo(brw, drb-hiz_region-buffer);
if (srb)
brw_add_validated_bo(brw, srb-region-buffer);
}
@@ -212,14 +214,28 @@ static void emit_depthbuffer(struct brw_context *brw)
struct gl_context *ctx = intel-ctx;
struct gl_framebuffer *fb = ctx-DrawBuffer;
/* _NEW_BUFFERS */
- struct intel_renderbuffer *irb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
+ struct intel_renderbuffer *depth_irb = intel_get_renderbuffer(fb,
BUFFER_DEPTH);
+ struct intel_renderbuffer *stencil_irb = intel_get_renderbuffer(fb,
BUFFER_STENCIL);
+ struct intel_region *hiz_region = depth_irb ? depth_irb-hiz_region : NULL;
unsigned int len;
- /* If we're combined depth stencil but no depth is attached, look
-* up stencil.
+ /*
+* If depth and stencil buffers are identical, then don't use separate
+* stencil.
*/
- if (!irb)
- irb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
+ if (depth_irb depth_irb == stencil_irb) {
+ stencil_irb = NULL;
+ }
+
+ /*
+* If stencil buffer uses combined depth/stencil format, but no depth buffer
+* is attached, then use stencil buffer as depth buffer.
+*/
+ if (!depth_irb stencil_irb
+stencil_irb-Base.Format == MESA_FORMAT_S8_Z24) {
+ depth_irb = stencil_irb;
+ stencil_irb = NULL;
+ }
if (intel-gen = 6)
len = 7;
@@ -228,7 +244,7 @@ static void emit_depthbuffer(struct brw_context *brw)
else
len = 5;
- if (!irb) {
+ if (!depth_irb !stencil_irb) {
BEGIN_BATCH(len);
OUT_BATCH(_3DSTATE_DEPTH_BUFFER 16 | (len - 2));
OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT 18) |
@@ -244,11 +260,57 @@ static void emit_depthbuffer(struct brw_context *brw)
OUT_BATCH(0);
ADVANCE_BATCH();
+
+ } else if (!depth_irb stencil_irb) {
+ /*
+ * There exists a separate stencil buffer but no depth buffer.
+ *
+ * The stencil buffer inherits most of its fields from
+ * 3DSTATE_DEPTH_BUFFER: namely the tile walk, surface type, width, and
+ * height.
+ *
+ * Since the stencil buffer has quirky pitch requirements, its region
+ * was allocated with half height and double cpp. So we need
+ * a multiplier of 2 to obtain the surface's real height.
+ *
+ * Enable the hiz bit because it and the separate stencil bit must have
+ * the same value. From Section 2.11.5.6.1.1 3DSTATE_DEPTH_BUFFER, Bit
+ * 1.21 Separate Stencil Enable:
+ * [DevIL]: If this field is enabled, Hierarchical Depth Buffer
+ * Enable must also be enabled.
+ *
+ * [DevGT]: This field must be set to the same value (enabled or
+ * disabled) as Hierarchical Depth Buffer Enable
+ */
+ assert(intel-has_separate_stencil);
+ assert(stencil_irb-Base.Format == MESA_FORMAT_S8);
+
+ BEGIN_BATCH(len);
+ OUT_BATCH(_3DSTATE_DEPTH_BUFFER 16 | (len - 2));
+ OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT 18) |
+ (1 21) | /* separate stencil enable */
+ (1 22) | /* hiz enable */
+ (BRW_TILEWALK_YMAJOR 26) |
+ (BRW_SURFACE_2D 29));
+ OUT_BATCH(0);
+ OUT_BATCH(((stencil_irb-region-width - 1) 6) |
+(2 * stencil_irb-region-height - 1) 19);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+
+ if (intel-gen = 6)
+OUT_BATCH(0);
+
+ ADVANCE_BATCH();
+
} else {
- struct intel_region *region = irb-region;
+ struct intel_region *region = depth_irb-region;
unsigned int format;
uint32_t tile_x, tile_y, offset;
+ /* If using separate stencil, hiz must be enabled. */
+ assert(!stencil_irb || hiz_region);
+
switch (region-cpp
Mesa (master): intel: Define span functions for S8 renderbuffers
Module: Mesa
Branch: master
Commit: ff99103c0a8a1b9e76fff80f9753d2124da27da2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ff99103c0a8a1b9e76fff80f9753d2124da27da2
Author: Chad Versace c...@chad-versace.us
Date: Wed Jun 1 11:31:56 2011 -0700
intel: Define span functions for S8 renderbuffers
Since the stencil buffer is interleaved, the generic Mesa renderbuffer
accessors do not suffice. Custom span functions are necessary.
Acked-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Eric Anholt e...@anholt.net
Signed-off-by: Chad Versace c...@chad-versace.us
---
src/mesa/drivers/dri/intel/intel_span.c | 64 +++
1 files changed, 64 insertions(+), 0 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_span.c
b/src/mesa/drivers/dri/intel/intel_span.c
index 5290342..a4a1d6b 100644
--- a/src/mesa/drivers/dri/intel/intel_span.c
+++ b/src/mesa/drivers/dri/intel/intel_span.c
@@ -1,6 +1,7 @@
/**
*
* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
+ * Copyright 2011 Intel Corporation
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -23,9 +24,13 @@
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
+ * Authors:
+ * Chad Versace c...@chad-versace.us
+ *
**/
#include stdbool.h
+#include stdint.h
#include main/glheader.h
#include main/macros.h
#include main/mtypes.h
@@ -112,6 +117,64 @@ intel_set_span_functions(struct intel_context *intel,
#define TAG2(x,y) intel_##x##y##_A8
#include spantmp2.h
+/* - */
+/* s8 stencil span and pixel functions */
+/* - */
+
+/*
+ * HAVE_HW_STENCIL_SPANS determines if stencil buffer read/writes are done with
+ * memcpy or for loops. Since the stencil buffer is interleaved, memcpy won't
+ * work.
+ */
+#define HAVE_HW_STENCIL_SPANS 0
+
+#define LOCAL_STENCIL_VARS \
+ (void) ctx; \
+ int minx = 0; \
+ int miny = 0; \
+ int maxx = rb-Width; \
+ int maxy = rb-Height; \
+ int stride = rb-RowStride; \
+ uint8_t *buf = rb-Data;\
+
+/* Don't flip y. */
+#undef Y_FLIP
+#define Y_FLIP(y) y
+
+/**
+ * \brief Get pointer offset into stencil buffer.
+ *
+ * The stencil buffer interleaves two rows into one. Yay for crazy hardware.
+ * The table below demonstrates how the pointer arithmetic behaves for a buffer
+ * with positive stride (s=stride).
+ *
+ * x| y | byte offset
+ * --
+ * 0| 0 | 0
+ * 0| 0 | 1
+ * 1| 0 | 2
+ * 1| 1 | 3
+ * ... | ... | ...
+ * 0| 2 | s
+ * 0| 3 | s + 1
+ * 1| 2 | s + 2
+ * 1| 3 | s + 3
+ *
+ *
+ */
+static inline intptr_t
+intel_offset_S8(int stride, GLint x, GLint y)
+{
+ return 2 * ((y / 2) * stride + x) + y % 2;
+}
+
+#define WRITE_STENCIL(x, y, src) buf[intel_offset_S8(stride, x, y)] = src;
+#define READ_STENCIL(dest, x, y) dest = buf[intel_offset_S8(stride, x, y)]
+#define TAG(x) intel_##x##_S8
+#include stenciltmp.h
+
+/* - */
+
void
intel_renderbuffer_map(struct intel_context *intel, struct gl_renderbuffer *rb)
{
@@ -332,6 +395,7 @@ static span_init_func
intel_span_init_funcs[MESA_FORMAT_COUNT] =
[MESA_FORMAT_Z16] = _mesa_set_renderbuffer_accessors,
[MESA_FORMAT_X8_Z24] = _mesa_set_renderbuffer_accessors,
[MESA_FORMAT_S8_Z24] = _mesa_set_renderbuffer_accessors,
+ [MESA_FORMAT_S8] = intel_InitStencilPointers_S8,
[MESA_FORMAT_R8] = _mesa_set_renderbuffer_accessors,
[MESA_FORMAT_RG88] = _mesa_set_renderbuffer_accessors,
[MESA_FORMAT_R16] = _mesa_set_renderbuffer_accessors,
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Mesa (master): dri2: Add token for DRI2BufferHiz
Module: Mesa
Branch: master
Commit: 4501a5d6e8d00fd0d87625352ed5ba1a8861f72e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4501a5d6e8d00fd0d87625352ed5ba1a8861f72e
Author: Chad Versace c...@chad-versace.us
Date: Thu May 26 16:50:30 2011 -0700
dri2: Add token for DRI2BufferHiz
CC: Ian Romanick i...@freedesktop.org
CC: Kristian Høgsberg k...@bitplanet.net
Acked-by: Eric Anholt e...@anholt.net
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
Signed-off-by: Chad Versace c...@chad-versace.us
---
include/GL/internal/dri_interface.h |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/include/GL/internal/dri_interface.h
b/include/GL/internal/dri_interface.h
index d791557..f022b44 100644
--- a/include/GL/internal/dri_interface.h
+++ b/include/GL/internal/dri_interface.h
@@ -692,6 +692,7 @@ struct __DRIswrastExtensionRec {
#define __DRI_BUFFER_FAKE_FRONT_LEFT 7
#define __DRI_BUFFER_FAKE_FRONT_RIGHT 8
#define __DRI_BUFFER_DEPTH_STENCIL 9 /** Only available with DRI2 1.1 */
+#define __DRI_BUFFER_HIZ 10
struct __DRIbufferRec {
unsigned int attachment;
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Mesa (master): intel: Define enum intel_dri2_has_hiz
Module: Mesa
Branch: master
Commit: df9f533c67e06713ae1b7f759c3644ca610058fd
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=df9f533c67e06713ae1b7f759c3644ca610058fd
Author: Chad Versace c...@chad-versace.us
Date: Wed Jun 1 14:19:29 2011 -0700
intel: Define enum intel_dri2_has_hiz
... which indicates if the X driver supports DRI2BufferHiz and
DRI2BufferStencil.
I'm placing this in its own commit due to the large comment block.
CC: Ian Romanick i...@freedesktop.org
CC: Kristian Høgsberg k...@bitplanet.net
Acked-by: Eric Anholt e...@anholt.net
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
Signed-off-by: Chad Versace c...@chad-versace.us
---
src/mesa/drivers/dri/intel/intel_screen.h | 56 +
1 files changed, 56 insertions(+), 0 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_screen.h
b/src/mesa/drivers/dri/intel/intel_screen.h
index 4613c98..5d13dfb 100644
--- a/src/mesa/drivers/dri/intel/intel_screen.h
+++ b/src/mesa/drivers/dri/intel/intel_screen.h
@@ -34,6 +34,62 @@
#include i915_drm.h
#include xmlconfig.h
+/**
+ * \brief Does X driver support DRI2BufferHiz and DRI2BufferStencil?
+ *
+ * (Here, X driver referes to the DDX driver, xf86-video-intel).
+ *
+ * The DRI2 protocol does not allow us to query the X driver's version nor
+ * query for a list of buffer formats that the driver supports. So, to
+ * determine if the X driver supports DRI2BufferHiz and DRI2BufferStencil we
+ * must resort to a handshake.
+ *
+ * If the hardware lacks support for separate stencil (and consequently, lacks
+ * support for hiz also), then the X driver's separate stencil and hiz support
+ * is irrelevant and the handshake never occurs.
+ *
+ * Complications
+ * -
+ * The handshake is complicated by a bug in xf86-video-intel 2.15. Even though
+ * that version of the X driver did not supppot requests for DRI2BufferHiz or
+ * DRI2BufferStencil, if requested one it still allocated and returned one.
+ * The returned buffer, however, was incorrectly X tiled.
+ *
+ * How the handshake works
+ * ---
+ * (TODO: To be implemented on a future commit).
+ *
+ * Initially, intel_screen.dri2_has_hiz is set to unknown. The first time the
+ * user requests a depth and stencil buffer, intelCreateBuffers() creates a
+ * framebuffer with separate depth and stencil attachments (with formats
+ * x8_z24 and s8).
+ *
+ * Eventually, intel_update_renderbuffers() makes a DRI2 request for
+ * DRI2BufferStencil and DRI2BufferHiz. If the returned buffers are Y tiled,
+ * then we joyfully set intel_screen.dri2_has_hiz to true and continue as if
+ * nothing happend.
+ *
+ * If the buffers are X tiled, however, the handshake has failed and we must
+ * clean up.
+ *1. Angrily set intel_screen.dri2_has_hiz to false.
+ *2. Discard the framebuffer's depth and stencil attachments.
+ *3. Attach a packed depth/stencil buffer to the framebuffer (with format
+ * s8_z24).
+ *4. Make a DRI2 request for the new buffer, using attachment type
+ * DRI2BufferDepthStencil).
+ *
+ * Future Considerations
+ * -
+ * On a sunny day in the far future, when we are certain that no one has an
+ * xf86-video-intel installed without hiz and separate stencil support, then
+ * this enumerant and the handshake should die.
+ */
+enum intel_dri2_has_hiz {
+ INTEL_DRI2_HAS_HIZ_UNKNOWN,
+ INTEL_DRI2_HAS_HIZ_TRUE,
+ INTEL_DRI2_HAS_HIZ_FALSE,
+};
+
struct intel_screen
{
int deviceID;
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Mesa (master): intel: Add flags to intel_screen for hiz and separate stencil
Module: Mesa
Branch: master
Commit: 6b2bf272ee173bd8ee6c731500861de21fa01b5f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6b2bf272ee173bd8ee6c731500861de21fa01b5f
Author: Chad Versace c...@chad-versace.us
Date: Thu May 26 15:24:48 2011 -0700
intel: Add flags to intel_screen for hiz and separate stencil
Add the fields below to intel_screen. The expression in parens is the
value to which intelInitScreen2() currently sets the field.
GLboolean hw_has_separate_stencil (true iff gen = 7)
GLboolean hw_must_use_separate_stencil (true iff gen = 7)
GLboolean hw_has_hiz (always false)
enum intel_dri2_has_hiz dri2_has_hiz (INTEL_DRI2_HAS_HIZ_UNKNOWN)
The analogous fields in intel_context now inherit their values from
intel_screen.
When hiz and separate stencil become completely implemented for a given
chipset, then the respective fields need to be enabled.
CC: Ian Romanick i...@freedesktop.org
CC: Kristian Høgsberg k...@bitplanet.net
Acked-by: Eric Anholt e...@anholt.net
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
Signed-off-by: Chad Versace c...@chad-versace.us
---
src/mesa/drivers/dri/intel/intel_context.c | 10 +---
src/mesa/drivers/dri/intel/intel_screen.c | 60
src/mesa/drivers/dri/intel/intel_screen.h | 10 +
3 files changed, 73 insertions(+), 7 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_context.c
b/src/mesa/drivers/dri/intel/intel_context.c
index b6a017a..22704a3 100644
--- a/src/mesa/drivers/dri/intel/intel_context.c
+++ b/src/mesa/drivers/dri/intel/intel_context.c
@@ -704,14 +704,9 @@ intelInitContext(struct intel_context *intel,
if (IS_GEN7(intel-intelScreen-deviceID)) {
intel-needs_ff_sync = GL_TRUE;
intel-has_luminance_srgb = GL_TRUE;
- /* FINISHME: Enable intel-has_separate_stencil on Gen7. */
- /* FINISHME: Enable intel-must_use_separate_stencil on Gen7. */
- /* FINISHME: Enable intel-has_hiz on Gen7. */
} else if (IS_GEN6(intel-intelScreen-deviceID)) {
intel-needs_ff_sync = GL_TRUE;
intel-has_luminance_srgb = GL_TRUE;
- /* FINISHME: Enable intel-has_separate_stencil on Gen6. */
- /* FINISHME: Enable intel-has_hiz on Gen6. */
} else if (IS_GEN5(intel-intelScreen-deviceID)) {
intel-needs_ff_sync = GL_TRUE;
intel-has_luminance_srgb = GL_TRUE;
@@ -731,8 +726,9 @@ intelInitContext(struct intel_context *intel,
}
}
- intel_override_hiz(intel);
- intel_override_separate_stencil(intel);
+ intel-has_separate_stencil = intel-intelScreen-hw_has_separate_stencil;
+ intel-must_use_separate_stencil =
intel-intelScreen-hw_must_use_separate_stencil;
+ intel-has_hiz = intel-intelScreen-hw_has_hiz;
memset(ctx-TextureFormatSupported, 0,
sizeof(ctx-TextureFormatSupported));
diff --git a/src/mesa/drivers/dri/intel/intel_screen.c
b/src/mesa/drivers/dri/intel/intel_screen.c
index deca11d..646b960 100644
--- a/src/mesa/drivers/dri/intel/intel_screen.c
+++ b/src/mesa/drivers/dri/intel/intel_screen.c
@@ -507,6 +507,54 @@ intel_init_bufmgr(struct intel_screen *intelScreen)
}
/**
+ * Override intel_screen.hw_has_hiz with environment variable INTEL_HIZ.
+ *
+ * Valid values for INTEL_HIZ are 0 and 1. If an invalid valid value is
+ * encountered, a warning is emitted and INTEL_HIZ is ignored.
+ */
+static void
+intel_override_hiz(struct intel_screen *intel)
+{
+ const char *s = getenv(INTEL_HIZ);
+ if (!s) {
+ return;
+ } else if (!strncmp(0, s, 2)) {
+ intel-hw_has_hiz = false;
+ } else if (!strncmp(1, s, 2)) {
+ intel-hw_has_hiz = true;
+ } else {
+ fprintf(stderr,
+ warning: env variable INTEL_HIZ=\%s\ has invalid value
+ and is ignored, s);
+ }
+}
+
+/**
+ * Override intel_screen.hw_has_separate_stencil with environment variable
+ * INTEL_SEPARATE_STENCIL.
+ *
+ * Valid values for INTEL_SEPARATE_STENCIL are 0 and 1. If an invalid
+ * valid value is encountered, a warning is emitted and INTEL_SEPARATE_STENCIL
+ * is ignored.
+ */
+static void
+intel_override_separate_stencil(struct intel_screen *screen)
+{
+ const char *s = getenv(INTEL_SEPARATE_STENCIL);
+ if (!s) {
+ return;
+ } else if (!strncmp(0, s, 2)) {
+ screen-hw_has_separate_stencil = false;
+ } else if (!strncmp(1, s, 2)) {
+ screen-hw_has_separate_stencil = true;
+ } else {
+ fprintf(stderr,
+ warning: env variable INTEL_SEPARATE_STENCIL=\%s\ has
+ invalid value and is ignored, s);
+ }
+}
+
+/**
* This is the driver specific part of the createNewScreen entry point.
* Called when using DRI2.
*
@@ -570,6 +618,18 @@ __DRIconfig **intelInitScreen2(__DRIscreen *psp)
intelScreen-gen = 2;
}
+ /*
+* FIXME: The hiz and separate stencil fields need updating once the
+* FIXME: features are completely implemented for a given chipset.
+*/
+ intelScreen-hw_has_separate_stencil
Mesa (master): intel/intel_context.c: Remove unused functions
Module: Mesa
Branch: master
Commit: beb8b7da20c862549b96a500226caf3a610342d9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=beb8b7da20c862549b96a500226caf3a610342d9
Author: Chad Versace c...@chad-versace.us
Date: Wed Jun 1 15:14:18 2011 -0700
intel/intel_context.c: Remove unused functions
Remove functions intel_override_hiz() and
intel_override_separate_stencil(). They are now located in intel_screen.c.
CC: Ian Romanick i...@freedesktop.org
CC: Kristian Høgsberg k...@bitplanet.net
Acked-by: Eric Anholt e...@anholt.net
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
Signed-off-by: Chad Versace c...@chad-versace.us
---
src/mesa/drivers/dri/intel/intel_context.c | 48
1 files changed, 0 insertions(+), 48 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_context.c
b/src/mesa/drivers/dri/intel/intel_context.c
index 22704a3..0259891 100644
--- a/src/mesa/drivers/dri/intel/intel_context.c
+++ b/src/mesa/drivers/dri/intel/intel_context.c
@@ -610,54 +610,6 @@ intelInitDriverFunctions(struct dd_function_table
*functions)
intel_init_syncobj_functions(functions);
}
-/**
- * Override intel-has_hiz with environment variable INTEL_HIZ.
- *
- * Valid values for INTEL_HIZ are 0 and 1. If an invalid valid value is
- * encountered, a warning is emitted and INTEL_HIZ is ignored.
- */
-static void
-intel_override_hiz(struct intel_context *intel)
-{
- const char *s = getenv(INTEL_HIZ);
- if (!s) {
- return;
- } else if (!strncmp(0, s, 2)) {
- intel-has_hiz = false;
- } else if (!strncmp(1, s, 2)) {
- intel-has_hiz = true;
- } else {
- _mesa_warning(intel-ctx,
-env variable INTEL_HIZ=\%s\ has invalid value and
-is ignored, s);
- }
-}
-
-/**
- * Override intel-has_separate_stencil with environment variable
- * INTEL_SEPARATE_STENCIL.
- *
- * Valid values for INTEL_SEPARATE_STENCIL are 0 and 1. If an invalid
- * value is encountered, a warning is emitted and INTEL_SEPARATE_STENCIL is
- * ignored.
- */
-static void
-intel_override_separate_stencil(struct intel_context *intel)
-{
- const char *s = getenv(INTEL_SEPARATE_STENCIL);
- if (!s) {
- return;
- } else if (!strncmp(0, s, 2)) {
- intel-has_separate_stencil = false;
- } else if (!strncmp(1, s, 2)) {
- intel-has_separate_stencil = true;
- } else {
- _mesa_warning(intel-ctx,
-env variable INTEL_SEPARATE_STENCIL=\%s\ has invalid
-value and is ignored, s);
- }
-}
-
GLboolean
intelInitContext(struct intel_context *intel,
int api,
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Mesa (master): intel: Add function intel_renderbuffer_set_hiz_region()
Module: Mesa
Branch: master
Commit: 84294fe26ca5860c34e6541f633be4d093ab57f2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=84294fe26ca5860c34e6541f633be4d093ab57f2
Author: Chad Versace c...@chad-versace.us
Date: Tue May 31 14:18:22 2011 -0700
intel: Add function intel_renderbuffer_set_hiz_region()
It's the analog of intel_renderbuffer_set_region(), but for the hiz region
of course.
CC: Ian Romanick i...@freedesktop.org
CC: Kristian Høgsberg k...@bitplanet.net
Acked-by: Eric Anholt e...@anholt.net
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
Signed-off-by: Chad Versace c...@chad-versace.us
---
src/mesa/drivers/dri/intel/intel_fbo.c | 12
src/mesa/drivers/dri/intel/intel_fbo.h |5 +
2 files changed, 17 insertions(+), 0 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c
b/src/mesa/drivers/dri/intel/intel_fbo.c
index 7434e0e..83f622d 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.c
+++ b/src/mesa/drivers/dri/intel/intel_fbo.c
@@ -321,6 +321,18 @@ intel_renderbuffer_set_region(struct intel_context *intel,
}
+void
+intel_renderbuffer_set_hiz_region(struct intel_context *intel,
+ struct intel_renderbuffer *rb,
+ struct intel_region *region)
+{
+ struct intel_region *old = rb-hiz_region;
+ rb-hiz_region = NULL;
+ intel_region_reference(rb-hiz_region, region);
+ intel_region_release(old);
+}
+
+
/**
* Create a new intel_renderbuffer which corresponds to an on-screen window,
* not a user-created renderbuffer.
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.h
b/src/mesa/drivers/dri/intel/intel_fbo.h
index 212dd9a..e9929b0 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.h
+++ b/src/mesa/drivers/dri/intel/intel_fbo.h
@@ -113,6 +113,11 @@ intel_renderbuffer_set_region(struct intel_context *intel,
struct intel_renderbuffer *irb,
struct intel_region *region);
+extern void
+intel_renderbuffer_set_hiz_region(struct intel_context *intel,
+ struct intel_renderbuffer *rb,
+ struct intel_region *region);
+
extern struct intel_renderbuffer *
intel_create_renderbuffer(gl_format format);
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Mesa (master): intel: Refactor intel_update_renderbuffers()
Module: Mesa
Branch: master
Commit: 89d34cfd3e7c96cefc489fbb995124e2dc4a97ec
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=89d34cfd3e7c96cefc489fbb995124e2dc4a97ec
Author: Chad Versace c...@chad-versace.us
Date: Fri Jun 3 16:14:25 2011 -0700
intel: Refactor intel_update_renderbuffers()
Extract the code that queries DRI2 to obtain the DRIdrawable's buffers
into intel_query_dri2_buffers_no_separate_stencil().
Extract the code that assigns the DRI buffer's DRM region to the
corresponding renderbuffer into
intel_process_dri2_buffer_no_separate_stencil().
Rationale
-
The next commit enables intel_update_renderbuffers() to query for separate
stencil and hiz buffers. Without separating the separate-stencil and
no-separate-stencil paths, intel_update_renderbuffers() degenerates into
an impenetrable labyrinth of if-trees.
CC: Ian Romanick i...@freedesktop.org
CC: Kristian Høgsberg k...@bitplanet.net
Acked-by: Eric Anholt e...@anholt.net
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
Signed-off-by: Chad Versace c...@chad-versace.us
---
src/mesa/drivers/dri/intel/intel_context.c | 323 ++--
1 files changed, 212 insertions(+), 111 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_context.c
b/src/mesa/drivers/dri/intel/intel_context.c
index 0259891..3460e67 100644
--- a/src/mesa/drivers/dri/intel/intel_context.c
+++ b/src/mesa/drivers/dri/intel/intel_context.c
@@ -227,18 +227,27 @@ intel_bits_per_pixel(const struct intel_renderbuffer *rb)
return _mesa_get_format_bytes(rb-Base.Format) * 8;
}
+static void
+intel_query_dri2_buffers_no_separate_stencil(struct intel_context *intel,
+__DRIdrawable *drawable,
+__DRIbuffer **buffers,
+int *count);
+
+static void
+intel_process_dri2_buffer_no_separate_stencil(struct intel_context *intel,
+ __DRIdrawable *drawable,
+ __DRIbuffer *buffer,
+ struct intel_renderbuffer *rb,
+ const char *buffer_name);
+
void
intel_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable)
{
struct gl_framebuffer *fb = drawable-driverPrivate;
struct intel_renderbuffer *rb;
- struct intel_region *region, *depth_region;
struct intel_context *intel = context-driverPrivate;
- struct intel_renderbuffer *front_rb, *back_rb, *depth_rb, *stencil_rb;
__DRIbuffer *buffers = NULL;
- __DRIscreen *screen;
int i, count;
- unsigned int attachments[10];
const char *region_name;
/* If we're rendering to the fake front buffer, make sure all the
@@ -260,70 +269,12 @@ intel_update_renderbuffers(__DRIcontext *context,
__DRIdrawable *drawable)
if (unlikely(INTEL_DEBUG DEBUG_DRI))
fprintf(stderr, enter %s, drawable %p\n, __func__, drawable);
- screen = intel-intelScreen-driScrnPriv;
-
- if (screen-dri2.loader
-(screen-dri2.loader-base.version 2)
-(screen-dri2.loader-getBuffersWithFormat != NULL)) {
-
- front_rb = intel_get_renderbuffer(fb, BUFFER_FRONT_LEFT);
- back_rb = intel_get_renderbuffer(fb, BUFFER_BACK_LEFT);
- depth_rb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
- stencil_rb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
-
- i = 0;
- if ((intel-is_front_buffer_rendering ||
- intel-is_front_buffer_reading ||
- !back_rb) front_rb) {
-attachments[i++] = __DRI_BUFFER_FRONT_LEFT;
-attachments[i++] = intel_bits_per_pixel(front_rb);
- }
-
- if (back_rb) {
-attachments[i++] = __DRI_BUFFER_BACK_LEFT;
-attachments[i++] = intel_bits_per_pixel(back_rb);
- }
-
- if ((depth_rb != NULL) (stencil_rb != NULL)) {
-attachments[i++] = __DRI_BUFFER_DEPTH_STENCIL;
-attachments[i++] = intel_bits_per_pixel(depth_rb);
- } else if (depth_rb != NULL) {
-attachments[i++] = __DRI_BUFFER_DEPTH;
-attachments[i++] = intel_bits_per_pixel(depth_rb);
- } else if (stencil_rb != NULL) {
-attachments[i++] = __DRI_BUFFER_STENCIL;
-attachments[i++] = intel_bits_per_pixel(stencil_rb);
- }
-
- buffers =
-(*screen-dri2.loader-getBuffersWithFormat)(drawable,
- drawable-w,
- drawable-h,
- attachments, i / 2,
- count,
- drawable-loaderPrivate);
- } else if (screen-dri2.loader) {
- i = 0;
- if (intel_get_renderbuffer(fb, BUFFER_FRONT_LEFT))
-attachments[i++] = __DRI_BUFFER_FRONT_LEFT;
- if (intel_get_renderbuffer(fb, BUFFER_BACK_LEFT
Mesa (master): intel: Add assertions to intelCreateBuffer()
Module: Mesa
Branch: master
Commit: f4efb7ff4f9cb0f6386e9b53f4dcfd9ef23dc9d1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f4efb7ff4f9cb0f6386e9b53f4dcfd9ef23dc9d1
Author: Chad Versace c...@chad-versace.us
Date: Thu May 26 14:55:54 2011 -0700
intel: Add assertions to intelCreateBuffer()
Assert that the GLX config has an expected depth/stencil bit combination:
one of d24/s8, d16/s0, d0/s0. These are the only depth/stencil
configurations that we advertise.
Remove the check for software stencil, because given the assertions'
constraints the check always fails.
CC: Ian Romanick i...@freedesktop.org
CC: Kristian Høgsberg k...@bitplanet.net
Acked-by: Eric Anholt e...@anholt.net
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
Signed-off-by: Chad Versace c...@chad-versace.us
---
src/mesa/drivers/dri/intel/intel_screen.c | 15 ---
1 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_screen.c
b/src/mesa/drivers/dri/intel/intel_screen.c
index 646b960..21dc8dc 100644
--- a/src/mesa/drivers/dri/intel/intel_screen.c
+++ b/src/mesa/drivers/dri/intel/intel_screen.c
@@ -364,8 +364,6 @@ intelCreateBuffer(__DRIscreen * driScrnPriv,
return GL_FALSE; /* not implemented */
}
else {
- GLboolean swStencil = (mesaVis-stencilBits 0
- mesaVis-depthBits != 24);
gl_format rgbFormat;
struct gl_framebuffer *fb = CALLOC_STRUCT(gl_framebuffer);
@@ -391,6 +389,11 @@ intelCreateBuffer(__DRIscreen * driScrnPriv,
_mesa_add_renderbuffer(fb, BUFFER_BACK_LEFT, rb-Base);
}
+ /*
+ * Assert here that the gl_config has an expected depth/stencil bit
+ * combination: one of d24/s8, d16/s0, d0/s0. (See intelInitScreen2(),
+ * which constructs the advertised configs.)
+ */
if (mesaVis-depthBits == 24) {
assert(mesaVis-stencilBits == 8);
/* combined depth/stencil buffer */
@@ -401,17 +404,23 @@ intelCreateBuffer(__DRIscreen * driScrnPriv,
_mesa_add_renderbuffer(fb, BUFFER_STENCIL, depthStencilRb-Base);
}
else if (mesaVis-depthBits == 16) {
+assert(mesaVis-stencilBits == 0);
/* just 16-bit depth buffer, no hw stencil */
struct intel_renderbuffer *depthRb
= intel_create_renderbuffer(MESA_FORMAT_Z16);
_mesa_add_renderbuffer(fb, BUFFER_DEPTH, depthRb-Base);
}
+ else {
+assert(mesaVis-depthBits == 0);
+assert(mesaVis-stencilBits == 0);
+ }
/* now add any/all software-based renderbuffers we may need */
_mesa_add_soft_renderbuffers(fb,
GL_FALSE, /* never sw color */
GL_FALSE, /* never sw depth */
- swStencil, mesaVis-accumRedBits 0,
+ GL_FALSE, /* never sw stencil */
+ mesaVis-accumRedBits 0,
GL_FALSE, /* never sw alpha */
GL_FALSE /* never sw aux */ );
driDrawPriv-driverPrivate = fb;
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Mesa (master): intel: Request DRI2 buffers for separate stencil and hiz
Module: Mesa
Branch: master
Commit: aea2236af60aee329e6ea73a41f2410d8eacc7b6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=aea2236af60aee329e6ea73a41f2410d8eacc7b6
Author: Chad Versace c...@chad-versace.us
Date: Fri Jun 3 16:33:32 2011 -0700
intel: Request DRI2 buffers for separate stencil and hiz
When it is sensible to do so,
1) intelCreateBuffer() now attaches separate depth and stencil
buffers
to the framebuffer it creates.
2) intel_update_renderbuffers() requests for the framebuffer
a separate stencil buffer (DRI2BufferStencil).
The criteria for sensible is:
- The GLX config has nonzero depth and stencil bits.
- The hardware supports separate stencil.
- The X driver supports separate stencil, or its support has not yet
been determined.
If the hardware supports hiz too, then intel_update_renderbuffers()
also requests DRI2BufferHiz.
If after requesting DRI2BufferStencil we determine that X driver did not
actually support separate stencil, we clean up the mistake and never ask
for DRI2BufferStencil again.
CC: Ian Romanick i...@freedesktop.org
CC: Kristian Høgsberg k...@bitplanet.net
Acked-by: Eric Anholt e...@anholt.net
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
Signed-off-by: Chad Versace c...@chad-versace.us
---
src/mesa/drivers/dri/intel/intel_context.c | 428 +++-
src/mesa/drivers/dri/intel/intel_screen.c | 28 ++-
src/mesa/drivers/dri/intel/intel_screen.h |2 -
3 files changed, 444 insertions(+), 14 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_context.c
b/src/mesa/drivers/dri/intel/intel_context.c
index 3460e67..0c2ba41 100644
--- a/src/mesa/drivers/dri/intel/intel_context.c
+++ b/src/mesa/drivers/dri/intel/intel_context.c
@@ -33,6 +33,7 @@
#include main/framebuffer.h
#include main/imports.h
#include main/points.h
+#include main/renderbuffer.h
#include swrast/swrast.h
#include swrast_setup/swrast_setup.h
@@ -240,6 +241,26 @@ intel_process_dri2_buffer_no_separate_stencil(struct
intel_context *intel,
struct intel_renderbuffer *rb,
const char *buffer_name);
+static void
+intel_query_dri2_buffers_with_separate_stencil(struct intel_context *intel,
+ __DRIdrawable *drawable,
+ __DRIbuffer **buffers,
+ unsigned **attachments,
+ int *count);
+
+static void
+intel_process_dri2_buffer_with_separate_stencil(struct intel_context *intel,
+ __DRIdrawable *drawable,
+ __DRIbuffer *buffer,
+ struct intel_renderbuffer *rb,
+ const char *buffer_name);
+static void
+intel_verify_dri2_has_hiz(struct intel_context *intel,
+ __DRIdrawable *drawable,
+ __DRIbuffer **buffers,
+ unsigned **attachments,
+ int *count);
+
void
intel_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable)
{
@@ -247,9 +268,19 @@ intel_update_renderbuffers(__DRIcontext *context,
__DRIdrawable *drawable)
struct intel_renderbuffer *rb;
struct intel_context *intel = context-driverPrivate;
__DRIbuffer *buffers = NULL;
+ unsigned *attachments = NULL;
int i, count;
const char *region_name;
+ bool try_separate_stencil =
+ intel-has_separate_stencil
+ intel-intelScreen-dri2_has_hiz != INTEL_DRI2_HAS_HIZ_FALSE
+ intel-intelScreen-driScrnPriv-dri2.loader != NULL
+ intel-intelScreen-driScrnPriv-dri2.loader-base.version 2
+ intel-intelScreen-driScrnPriv-dri2.loader-getBuffersWithFormat !=
NULL;
+
+ assert(!intel-must_use_separate_stencil || try_separate_stencil);
+
/* If we're rendering to the fake front buffer, make sure all the
* pending drawing has landed on the real front buffer. Otherwise
* when we eventually get to DRI2GetBuffersWithFormat the stale
@@ -269,12 +300,17 @@ intel_update_renderbuffers(__DRIcontext *context,
__DRIdrawable *drawable)
if (unlikely(INTEL_DEBUG DEBUG_DRI))
fprintf(stderr, enter %s, drawable %p\n, __func__, drawable);
+ if (try_separate_stencil) {
+ intel_query_dri2_buffers_with_separate_stencil(intel, drawable, buffers,
+attachments, count);
+ } else {
+ intel_query_dri2_buffers_no_separate_stencil(intel, drawable, buffers,
+ count);
+ }
+
if (buffers == NULL)
return;
- intel_query_dri2_buffers_no_separate_stencil(intel, drawable, buffers,
- count);
-
drawable-x = 0
Mesa (master): i965/brw: Fix emit_depthbuffer() when packed depth/ stencil texture is attached
Module: Mesa
Branch: master
Commit: 97d230b0bcf8ed001f685ebac314fbd8e1955718
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=97d230b0bcf8ed001f685ebac314fbd8e1955718
Author: Chad Versace c...@chad-versace.us
Date: Fri Jun 10 10:27:54 2011 -0700
i965/brw: Fix emit_depthbuffer() when packed depth/stencil texture is attached
If either depth or stencil buffer has packed depth/stencil format, then do
not use separate stencil.
Before this commit, emit_depthbuffer() incorrectly assumed that the
texture's stencil renderbuffer wrapper was a *separate* stencil buffer,
because the depth and stencil renderbuffer wrappers are distinct for
depth/stencil textures (that is, depth_irb != stencil_irb).
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=38134
Signed-off-by: Chad Versace c...@chad-versace.us
---
src/mesa/drivers/dri/i965/brw_misc_state.c | 16 +---
1 files changed, 5 insertions(+), 11 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c
b/src/mesa/drivers/dri/i965/brw_misc_state.c
index a6de28b..3d0983e 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -220,19 +220,13 @@ static void emit_depthbuffer(struct brw_context *brw)
unsigned int len;
/*
-* If depth and stencil buffers are identical, then don't use separate
-* stencil.
+* If either depth or stencil buffer has packed depth/stencil format,
+* then don't use separate stencil. Emit only a depth buffer.
*/
- if (depth_irb depth_irb == stencil_irb) {
+ if (depth_irb depth_irb-Base.Format == MESA_FORMAT_S8_Z24) {
stencil_irb = NULL;
- }
-
- /*
-* If stencil buffer uses combined depth/stencil format, but no depth buffer
-* is attached, then use stencil buffer as depth buffer.
-*/
- if (!depth_irb stencil_irb
-stencil_irb-Base.Format == MESA_FORMAT_S8_Z24) {
+ } else if (!depth_irb stencil_irb
+ stencil_irb-Base.Format == MESA_FORMAT_S8_Z24) {
depth_irb = stencil_irb;
stencil_irb = NULL;
}
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Mesa (master): i965/gen5,6: Fix hang when emitting hiz buffer without stencil buffer
Module: Mesa
Branch: master
Commit: d105f6684dfbfe596e57ddeb9377e7f9e4e57dcb
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d105f6684dfbfe596e57ddeb9377e7f9e4e57dcb
Author: Chad Versace c...@chad-versace.us
Date: Wed Jun 8 21:51:10 2011 -0700
i965/gen5,6: Fix hang when emitting hiz buffer without stencil buffer
When emitting either a hiz or stencil buffer, the 'separate stencil
enable' and 'hiz enable' bits are set in 3DSTATE_DEPTH_BUFFER. Therefore
we must emit both 3DSTATE_HIER_DEPTH_BUFFER and 3DSTATE_STENCIL_BUFFER.
Even if there is no stencil buffer, 3DSTATE_STENCIL_BUFFER must be
emitted; failure to do so causes a hang on gen5 and a stall on gen6.
This also fixes a silly, obvious segfault that occured when a hiz buffer
xor separate stencil buffer existed.
Fixes the piglit tests below on Gen5 when hiz and separate stencil are
manually enabled:
fbo-alphatest-nocolor
fbo-depth-sample-compare
fbo
hiz-depth-read-fbo-d24-s0
hiz-depth-stencil-test-fbo-d24-s0
hiz-depth-test-fbo-d24-s0
hiz-stencil-read-fbo-d0-s8
hiz-stencil-test-fbo-d0-s8
fbo-missing-attachment-clear
fbo-clear-formats
fbo-depth-*
Changes piglit test result from crash to fail:
hiz-depth-stencil-test-fbo-d0-s8
Signed-off-by: Chad Versace c...@chad-versace.us
---
src/mesa/drivers/dri/i965/brw_misc_state.c | 58 +++-
1 files changed, 40 insertions(+), 18 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c
b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 2b5ec8a..1f3b64f 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -355,26 +355,48 @@ static void emit_depthbuffer(struct brw_context *brw)
ADVANCE_BATCH();
}
- /* Emit hiz buffer. */
if (hiz_region || stencil_irb) {
- BEGIN_BATCH(3);
- OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER 16) | (3 - 2));
- OUT_BATCH(hiz_region-pitch * hiz_region-cpp - 1);
- OUT_RELOC(hiz_region-buffer,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
- 0);
- ADVANCE_BATCH();
- }
+ /*
+ * In the 3DSTATE_DEPTH_BUFFER batch emitted above, the 'separate
+ * stencil enable' and 'hiz enable' bits were set. Therefore we must
+ * emit 3DSTATE_HIER_DEPTH_BUFFER and 3DSTATE_STENCIL_BUFFER. Even if
+ * there is no stencil buffer, 3DSTATE_STENCIL_BUFFER must be emitted;
+ * failure to do so causes hangs on gen5 and a stall on gen6.
+ */
- /* Emit stencil buffer. */
- if (hiz_region || stencil_irb) {
- BEGIN_BATCH(3);
- OUT_BATCH((_3DSTATE_STENCIL_BUFFER 16) | (3 - 2));
- OUT_BATCH(stencil_irb-region-pitch * stencil_irb-region-cpp - 1);
- OUT_RELOC(stencil_irb-region-buffer,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
- 0);
- ADVANCE_BATCH();
+ /* Emit hiz buffer. */
+ if (hiz_region) {
+BEGIN_BATCH(3);
+OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER 16) | (3 - 2));
+OUT_BATCH(hiz_region-pitch * hiz_region-cpp - 1);
+OUT_RELOC(hiz_region-buffer,
+ I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+ 0);
+ADVANCE_BATCH();
+ } else {
+BEGIN_BATCH(3);
+OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER 16) | (3 - 2));
+OUT_BATCH(0);
+OUT_BATCH(0);
+ADVANCE_BATCH();
+ }
+
+ /* Emit stencil buffer. */
+ if (stencil_irb) {
+BEGIN_BATCH(3);
+OUT_BATCH((_3DSTATE_STENCIL_BUFFER 16) | (3 - 2));
+OUT_BATCH(stencil_irb-region-pitch * stencil_irb-region-cpp - 1);
+OUT_RELOC(stencil_irb-region-buffer,
+ I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+ 0);
+ADVANCE_BATCH();
+ } else {
+BEGIN_BATCH(3);
+OUT_BATCH((_3DSTATE_STENCIL_BUFFER 16) | (3 - 2));
+OUT_BATCH(0);
+OUT_BATCH(0);
+ADVANCE_BATCH();
+ }
}
/*
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Mesa (master): intel: Fix typo in intel_offset_S8 comments
Module: Mesa Branch: master Commit: 8875dd58719b978283e89acf04422a4eaf9b021d URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8875dd58719b978283e89acf04422a4eaf9b021d Author: Chad Versace c...@chad-versace.us Date: Tue Jun 14 12:56:49 2011 -0700 intel: Fix typo in intel_offset_S8 comments Signed-off-by: Chad Versace c...@chad-versace.us --- src/mesa/drivers/dri/intel/intel_span.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/mesa/drivers/dri/intel/intel_span.c b/src/mesa/drivers/dri/intel/intel_span.c index 9343f40..fdf687a 100644 --- a/src/mesa/drivers/dri/intel/intel_span.c +++ b/src/mesa/drivers/dri/intel/intel_span.c @@ -148,7 +148,7 @@ intel_set_span_functions(struct intel_context *intel, * x| y | byte offset * -- * 0| 0 | 0 - * 0| 0 | 1 + * 0| 1 | 1 * 1| 0 | 2 * 1| 1 | 3 * ... | ... | ... ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel: Unconditionally enable support for S8_Z24 texture format
Module: Mesa Branch: master Commit: 23ed3b90c7f9056182307f9a69a56f748da331a3 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=23ed3b90c7f9056182307f9a69a56f748da331a3 Author: Chad Versace c...@chad-versace.us Date: Wed Jun 8 19:08:14 2011 -0700 intel: Unconditionally enable support for S8_Z24 texture format Commit b5c847c7ca06823af3b72324056a2e478caca70b erroneously disabled support for S8_Z24 texture format when the context required separate stencil (intel_context.must_use_separate_stencil). But the GL spec requires implementations to support GL_DEPTH24_STENCIL8. So we better find a way to fake it... From page 180 (196 of pdf) of the OpenGL 3.0 spec: In addition, implementations are required to support the following sized internal [texture] formats. [...] - Combined depth+stencil formats: DEPTH32F_STENCIL8 and and DEPTH24_STENCIL8. Reviewed-by: Eric Anholt e...@anholt.net Signed-off-by: Chad Versace c...@chad-versace.us --- src/mesa/drivers/dri/intel/intel_context.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c index 820688e..30d5c5b 100644 --- a/src/mesa/drivers/dri/intel/intel_context.c +++ b/src/mesa/drivers/dri/intel/intel_context.c @@ -663,7 +663,7 @@ intelInitContext(struct intel_context *intel, ctx-TextureFormatSupported[MESA_FORMAT_AL1616] = GL_TRUE; /* Depth and stencil */ - ctx-TextureFormatSupported[MESA_FORMAT_S8_Z24] = !intel-must_use_separate_stencil; + ctx-TextureFormatSupported[MESA_FORMAT_S8_Z24] = GL_TRUE; ctx-TextureFormatSupported[MESA_FORMAT_X8_Z24] = intel-has_separate_stencil; ctx-TextureFormatSupported[MESA_FORMAT_S8] = intel-has_separate_stencil; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel: Unobfuscate intel_alloc_renderbuffer_storage
Module: Mesa
Branch: master
Commit: 36e05c6870fc466053b4f54edd890e19d5ac9dcf
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=36e05c6870fc466053b4f54edd890e19d5ac9dcf
Author: Chad Versace c...@chad-versace.us
Date: Tue Jun 14 17:38:30 2011 -0700
intel: Unobfuscate intel_alloc_renderbuffer_storage
Hiz buffer allocation can only occur if the 'else' branch has been taken,
so move the hiz buffer allocation into the 'else' branch.
Having the hiz buffer allocation dangling outside of the if-tree was just
damn confusing.
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
Signed-off-by: Chad Versace c...@chad-versace.us
---
src/mesa/drivers/dri/intel/intel_fbo.c | 34
1 files changed, 17 insertions(+), 17 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c
b/src/mesa/drivers/dri/intel/intel_fbo.c
index b48eac4..ff09b5d 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.c
+++ b/src/mesa/drivers/dri/intel/intel_fbo.c
@@ -196,26 +196,26 @@ intel_alloc_renderbuffer_storage(struct gl_context * ctx,
struct gl_renderbuffer
width,
height / 2,
GL_TRUE);
+ if (!irb-region)
+ return false;
+
} else {
irb-region = intel_region_alloc(intel-intelScreen, tiling, cpp,
width, height, GL_TRUE);
- }
-
- if (!irb-region)
- return GL_FALSE; /* out of memory? */
-
- ASSERT(irb-region-buffer);
-
- if (intel-vtbl.is_hiz_depth_format(intel, rb-Format)) {
- irb-hiz_region = intel_region_alloc(intel-intelScreen,
- I915_TILING_Y,
- irb-region-cpp,
- irb-region-width,
- irb-region-height,
- GL_TRUE);
- if (!irb-hiz_region) {
- intel_region_release(irb-region);
- return GL_FALSE;
+ if (!irb-region)
+return false;
+
+ if (intel-vtbl.is_hiz_depth_format(intel, rb-Format)) {
+irb-hiz_region = intel_region_alloc(intel-intelScreen,
+ I915_TILING_Y,
+ irb-region-cpp,
+ irb-region-width,
+ irb-region-height,
+ GL_TRUE);
+if (!irb-hiz_region) {
+ intel_region_release(irb-region);
+ return false;
+}
}
}
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Mesa (master): intel: Allocate s8_z24 non-texture renderbuffers when using separate stencil
Module: Mesa
Branch: master
Commit: 3db27d4a4aee9f311a447778ce94007415f2637f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3db27d4a4aee9f311a447778ce94007415f2637f
Author: Chad Versace c...@chad-versace.us
Date: Fri Jun 17 12:12:35 2011 -0700
intel: Allocate s8_z24 non-texture renderbuffers when using separate stencil
Now all infrastructure is in place to support s8_z24 non-texture
renderbuffers for gen7.
Reviewed-by: Eric Anholt e...@anholt.net
Signed-off-by: Chad Versace c...@chad-versace.us
---
src/mesa/drivers/dri/intel/intel_fbo.c | 84 ++-
1 files changed, 81 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c
b/src/mesa/drivers/dri/intel/intel_fbo.c
index ff09b5d..f48703e 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.c
+++ b/src/mesa/drivers/dri/intel/intel_fbo.c
@@ -107,6 +107,12 @@ intel_get_pointer(struct gl_context * ctx, struct
gl_renderbuffer *rb,
}
+static struct gl_renderbuffer*
+intel_create_wrapped_renderbuffer(struct gl_context * ctx,
+ struct gl_renderbuffer *wrapper,
+ gl_format format);
+
+
/**
* Called via glRenderbufferStorageEXT() to set the format and allocate
* storage for a user-created renderbuffer.
@@ -147,6 +153,8 @@ intel_alloc_renderbuffer_storage(struct gl_context * ctx,
struct gl_renderbuffer
break;
}
+ rb-Width = width;
+ rb-Height = height;
rb-_BaseFormat = _mesa_base_fbo_format(ctx, internalFormat);
rb-DataType = intel_mesa_format_to_rb_datatype(rb-Format);
cpp = _mesa_get_format_bytes(rb-Format);
@@ -199,6 +207,38 @@ intel_alloc_renderbuffer_storage(struct gl_context * ctx,
struct gl_renderbuffer
if (!irb-region)
return false;
+ } else if (irb-Base.Format == MESA_FORMAT_S8_Z24
+ intel-must_use_separate_stencil) {
+
+ bool ok = true;
+ struct gl_renderbuffer *depth_rb;
+ struct gl_renderbuffer *stencil_rb;
+
+ depth_rb = intel_create_wrapped_renderbuffer(ctx, rb,
+ MESA_FORMAT_X8_Z24);
+ stencil_rb = intel_create_wrapped_renderbuffer(ctx, rb,
+MESA_FORMAT_S8);
+ ok = depth_rb stencil_rb;
+ ok = ok intel_alloc_renderbuffer_storage(ctx, depth_rb,
+ depth_rb-InternalFormat,
+ width, height);
+ ok = ok intel_alloc_renderbuffer_storage(ctx, stencil_rb,
+ stencil_rb-InternalFormat,
+ width, height);
+
+ if (!ok) {
+if (depth_rb) {
+ intel_delete_renderbuffer(depth_rb);
+}
+if (stencil_rb) {
+ intel_delete_renderbuffer(stencil_rb);
+}
+return false;
+ }
+
+ _mesa_reference_renderbuffer(irb-wrapped_depth, depth_rb);
+ _mesa_reference_renderbuffer(irb-wrapped_stencil, stencil_rb);
+
} else {
irb-region = intel_region_alloc(intel-intelScreen, tiling, cpp,
width, height, GL_TRUE);
@@ -219,9 +259,6 @@ intel_alloc_renderbuffer_storage(struct gl_context * ctx,
struct gl_renderbuffer
}
}
- rb-Width = width;
- rb-Height = height;
-
return GL_TRUE;
}
@@ -372,6 +409,47 @@ intel_create_renderbuffer(gl_format format)
}
+static struct gl_renderbuffer *
+intel_create_wrapped_renderbuffer(struct gl_context * ctx,
+ struct gl_renderbuffer *wrapper,
+ gl_format format)
+{
+ /*
+* The name here is irrelevant, as long as its nonzero, because the
+* renderbuffer never gets entered into Mesa's renderbuffer hash table.
+*/
+ GLuint name = ~0;
+
+ struct intel_renderbuffer *irb = CALLOC_STRUCT(intel_renderbuffer);
+ if (!irb) {
+ _mesa_error(ctx, GL_OUT_OF_MEMORY, creating renderbuffer);
+ return NULL;
+ }
+
+ struct gl_renderbuffer *rb = irb-Base;
+ _mesa_init_renderbuffer(rb, name);
+ rb-ClassID = INTEL_RB_CLASS;
+ rb-_BaseFormat = _mesa_get_format_base_format(format);
+ rb-Format = format;
+ rb-InternalFormat = rb-_BaseFormat;
+ rb-DataType = intel_mesa_format_to_rb_datatype(format);
+ rb-Width = wrapper-Width;
+ rb-Height = wrapper-Height;
+
+ rb-AllocStorage = intel_nop_alloc_storage;
+ rb-Delete = intel_delete_renderbuffer;
+ rb-GetPointer = intel_get_pointer;
+
+ /*
+* A refcount here would cause a cyclic reference. The wrapper references
+* the unwrapper.
+*/
+ rb-Wrapped = wrapper;
+
+ return rb;
+}
+
+
/**
* Create a new renderbuffer object.
* Typically called via glBindRenderbufferEXT().
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Mesa (master): intel: Define functions intel_texture_s8z24_scatter/gather
Module: Mesa
Branch: master
Commit: 01e493980c133ad20f70d627dcc1b1900e3ebf44
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=01e493980c133ad20f70d627dcc1b1900e3ebf44
Author: Chad Versace c...@chad-versace.us
Date: Tue Jun 21 22:58:39 2011 -0700
intel: Define functions intel_texture_s8z24_scatter/gather
... which copy the stencil bits between intel_image-depth_rb and
intel_image-stencil_rb.
Signed-off-by: Chad Versace c...@chad-versace.us
---
src/mesa/drivers/dri/intel/intel_tex_image.c | 70 ++
1 files changed, 70 insertions(+), 0 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_tex_image.c
b/src/mesa/drivers/dri/intel/intel_tex_image.c
index 472a8e1..6065238 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_image.c
+++ b/src/mesa/drivers/dri/intel/intel_tex_image.c
@@ -21,6 +21,7 @@
#include intel_tex.h
#include intel_blit.h
#include intel_fbo.h
+#include intel_span.h
#define FILE_DEBUG_FLAG DEBUG_TEXTURE
@@ -277,6 +278,75 @@ try_pbo_zcopy(struct intel_context *intel,
return GL_TRUE;
}
+/**
+ * \param scatter Scatter if true. Gather if false.
+ *
+ * \see intel_tex_image_x8z24_scatter
+ * \see intel_tex_image_x8z24_gather
+ */
+static void
+intel_tex_image_s8z24_scattergather(struct intel_context *intel,
+ struct intel_texture_image *intel_image,
+ bool scatter)
+{
+ struct gl_context *ctx = intel-ctx;
+ struct gl_renderbuffer *depth_rb = intel_image-depth_rb;
+ struct gl_renderbuffer *stencil_rb = intel_image-stencil_rb;
+
+ int w = intel_image-base.Width;
+ int h = intel_image-base.Height;
+
+ uint32_t depth_row[w];
+ uint8_t stencil_row[w];
+
+ intel_renderbuffer_map(intel, depth_rb);
+ intel_renderbuffer_map(intel, stencil_rb);
+
+ if (scatter) {
+ for (int y = 0; y h; ++y) {
+depth_rb-GetRow(ctx, depth_rb, w, 0, y, depth_row);
+for (int x = 0; x w; ++x) {
+ stencil_row[x] = depth_row[x] 24;
+}
+stencil_rb-PutRow(ctx, stencil_rb, w, 0, y, stencil_row, NULL);
+ }
+ } else { /* gather */
+ for (int y = 0; y h; ++y) {
+depth_rb-GetRow(ctx, depth_rb, w, 0, y, depth_row);
+stencil_rb-GetRow(ctx, stencil_rb, w, 0, y, stencil_row);
+for (int x = 0; x w; ++x) {
+ uint32_t s8_x24 = stencil_row[x] 24;
+ uint32_t x8_z24 = depth_row[x] 0x00ff;
+ depth_row[x] = s8_x24 | x8_z24;
+}
+depth_rb-PutRow(ctx, depth_rb, w, 0, y, depth_row, NULL);
+ }
+ }
+
+ intel_renderbuffer_unmap(intel, depth_rb);
+ intel_renderbuffer_unmap(intel, stencil_rb);
+}
+
+/**
+ * Copy the x8 bits from intel_image-depth_rb to intel_image-stencil_rb.
+ */
+static void
+intel_tex_image_s8z24_scatter(struct intel_context *intel,
+ struct intel_texture_image *intel_image)
+{
+ intel_tex_image_s8z24_scattergather(intel, intel_image, true);
+}
+
+/**
+ * Copy the data in intel_image-stencil_rb to the x8 bits in
+ * intel_image-depth_rb.
+ */
+static void
+intel_tex_image_s8z24_gather(struct intel_context *intel,
+struct intel_texture_image *intel_image)
+{
+ intel_tex_image_s8z24_scattergather(intel, intel_image, false);
+}
static void
intelTexImage(struct gl_context * ctx,
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Mesa (master): intel: Add fields to intel_texture for faking s8z24 with separate stencil
Module: Mesa
Branch: master
Commit: 1a062dfc6f6e872e18f048bb5a61709c36f22870
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1a062dfc6f6e872e18f048bb5a61709c36f22870
Author: Chad Versace c...@chad-versace.us
Date: Tue Jun 21 13:44:57 2011 -0700
intel: Add fields to intel_texture for faking s8z24 with separate stencil
Add the fields depth_rb and stencil_rb, and put hooks in place to
release the renderbuffers in intelFreeTextureImageData and
intelTexImage.
Signed-off-by: Chad Versace c...@chad-versace.us
---
src/mesa/drivers/dri/intel/intel_tex.c |9 +++
src/mesa/drivers/dri/intel/intel_tex_image.c | 13 +--
src/mesa/drivers/dri/intel/intel_tex_obj.h | 30 ++
3 files changed, 40 insertions(+), 12 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_tex.c
b/src/mesa/drivers/dri/intel/intel_tex.c
index 32e1fb7..21c4a1d 100644
--- a/src/mesa/drivers/dri/intel/intel_tex.c
+++ b/src/mesa/drivers/dri/intel/intel_tex.c
@@ -1,4 +1,5 @@
#include swrast/swrast.h
+#include main/renderbuffer.h
#include main/texobj.h
#include main/teximage.h
#include main/mipmap.h
@@ -59,6 +60,14 @@ intelFreeTextureImageData(struct gl_context * ctx, struct
gl_texture_image *texI
_mesa_free_texmemory(texImage-Data);
texImage-Data = NULL;
}
+
+ if (intelImage-depth_rb) {
+ _mesa_reference_renderbuffer(intelImage-depth_rb, NULL);
+ }
+
+ if (intelImage-stencil_rb) {
+ _mesa_reference_renderbuffer(intelImage-stencil_rb, NULL);
+ }
}
/**
diff --git a/src/mesa/drivers/dri/intel/intel_tex_image.c
b/src/mesa/drivers/dri/intel/intel_tex_image.c
index 90d4117..472a8e1 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_image.c
+++ b/src/mesa/drivers/dri/intel/intel_tex_image.c
@@ -314,18 +314,7 @@ intelTexImage(struct gl_context * ctx,
}
}
- /* Release the reference to a potentially orphaned buffer.
-* Release any old malloced memory.
-*/
- if (intelImage-mt) {
- intel_miptree_release(intel, intelImage-mt);
- assert(!texImage-Data);
- }
- else if (texImage-Data) {
- _mesa_free_texmemory(texImage-Data);
- texImage-Data = NULL;
- }
-
+ ctx-Driver.FreeTexImageData(ctx, texImage);
assert(!intelImage-mt);
if (intelObj-mt
diff --git a/src/mesa/drivers/dri/intel/intel_tex_obj.h
b/src/mesa/drivers/dri/intel/intel_tex_obj.h
index e93ef4a..a9ae2ec 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_obj.h
+++ b/src/mesa/drivers/dri/intel/intel_tex_obj.h
@@ -63,6 +63,36 @@ struct intel_texture_image
*/
struct intel_mipmap_tree *mt;
GLboolean used_as_render_target;
+
+ /**
+* \name Renderbuffers for faking packed depth/stencil
+*
+* These renderbuffers are non-null only if the intel_context is using
+* separate stencil and this texture has a packed depth/stencil format. When
+* glFramebufferTexture is called on this image, the resultant renderbuffer
+* wrapper reuses these renderbuffers as its own.
+*
+* \see intel_wrap_texture
+* \see intel_tex_image_s8z24_create_renderbuffers
+* \see intel_tex_image_s8z24_scatter
+* \see intel_tex_image_s8z24_gather
+*
+* \{
+*/
+
+ /**
+* The depth buffer has format X8_Z24. The x8 bits are undefined unless
+* intel_tex_image_s8z24_gather has been immediately called. The depth
buffer
+* resuses the image miptree's region and hiz_region as its own.
+*/
+ struct gl_renderbuffer *depth_rb;
+
+ /**
+* The stencil buffer has format S8 and keeps its data in its own region.
+*/
+ struct gl_renderbuffer *stencil_rb;
+
+ /** \} */
};
static INLINE struct intel_texture_object *
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Mesa (master): intel: Change signature of intel_create_wrapped_renderbuffer
Module: Mesa
Branch: master
Commit: 8869a2623775a4879ac310d7073f184b7d45eed1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8869a2623775a4879ac310d7073f184b7d45eed1
Author: Chad Versace c...@chad-versace.us
Date: Tue Jun 21 14:06:13 2011 -0700
intel: Change signature of intel_create_wrapped_renderbuffer
Redeclare as non-static because
intel_tex_image_s8z24_create_renderbuffers will use it.
Remove the 'wrapper' parameter, because there is no wrapper for
intel_texture_image.depth_rb and stencil_rb.
Signed-off-by: Chad Versace c...@chad-versace.us
---
src/mesa/drivers/dri/intel/intel_fbo.c | 30 --
src/mesa/drivers/dri/intel/intel_fbo.h |4
2 files changed, 12 insertions(+), 22 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c
b/src/mesa/drivers/dri/intel/intel_fbo.c
index f48703e..8dd3696 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.c
+++ b/src/mesa/drivers/dri/intel/intel_fbo.c
@@ -107,12 +107,6 @@ intel_get_pointer(struct gl_context * ctx, struct
gl_renderbuffer *rb,
}
-static struct gl_renderbuffer*
-intel_create_wrapped_renderbuffer(struct gl_context * ctx,
- struct gl_renderbuffer *wrapper,
- gl_format format);
-
-
/**
* Called via glRenderbufferStorageEXT() to set the format and allocate
* storage for a user-created renderbuffer.
@@ -214,9 +208,9 @@ intel_alloc_renderbuffer_storage(struct gl_context * ctx,
struct gl_renderbuffer
struct gl_renderbuffer *depth_rb;
struct gl_renderbuffer *stencil_rb;
- depth_rb = intel_create_wrapped_renderbuffer(ctx, rb,
+ depth_rb = intel_create_wrapped_renderbuffer(ctx, width, height,
MESA_FORMAT_X8_Z24);
- stencil_rb = intel_create_wrapped_renderbuffer(ctx, rb,
+ stencil_rb = intel_create_wrapped_renderbuffer(ctx, width, height,
MESA_FORMAT_S8);
ok = depth_rb stencil_rb;
ok = ok intel_alloc_renderbuffer_storage(ctx, depth_rb,
@@ -236,6 +230,8 @@ intel_alloc_renderbuffer_storage(struct gl_context * ctx,
struct gl_renderbuffer
return false;
}
+ depth_rb-Wrapped = rb;
+ stencil_rb-Wrapped = rb;
_mesa_reference_renderbuffer(irb-wrapped_depth, depth_rb);
_mesa_reference_renderbuffer(irb-wrapped_stencil, stencil_rb);
@@ -409,9 +405,9 @@ intel_create_renderbuffer(gl_format format)
}
-static struct gl_renderbuffer *
+struct gl_renderbuffer*
intel_create_wrapped_renderbuffer(struct gl_context * ctx,
- struct gl_renderbuffer *wrapper,
+ int width, int height,
gl_format format)
{
/*
@@ -433,18 +429,8 @@ intel_create_wrapped_renderbuffer(struct gl_context * ctx,
rb-Format = format;
rb-InternalFormat = rb-_BaseFormat;
rb-DataType = intel_mesa_format_to_rb_datatype(format);
- rb-Width = wrapper-Width;
- rb-Height = wrapper-Height;
-
- rb-AllocStorage = intel_nop_alloc_storage;
- rb-Delete = intel_delete_renderbuffer;
- rb-GetPointer = intel_get_pointer;
-
- /*
-* A refcount here would cause a cyclic reference. The wrapper references
-* the unwrapper.
-*/
- rb-Wrapped = wrapper;
+ rb-Width = width;
+ rb-Height = height;
return rb;
}
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.h
b/src/mesa/drivers/dri/intel/intel_fbo.h
index da0b240..08cf577 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.h
+++ b/src/mesa/drivers/dri/intel/intel_fbo.h
@@ -169,6 +169,10 @@ intel_renderbuffer_set_hiz_region(struct intel_context
*intel,
extern struct intel_renderbuffer *
intel_create_renderbuffer(gl_format format);
+struct gl_renderbuffer*
+intel_create_wrapped_renderbuffer(struct gl_context * ctx,
+ int width, int height,
+ gl_format format);
extern void
intel_fbo_init(struct intel_context *intel);
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Mesa (master): intel: Perform gather on s8z24 texture images during glGetTexImage
Module: Mesa
Branch: master
Commit: 951b75808eeac5fb97183ea8e653512bfa35fdb2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=951b75808eeac5fb97183ea8e653512bfa35fdb2
Author: Chad Versace c...@chad-versace.us
Date: Tue Jun 21 21:42:48 2011 -0700
intel: Perform gather on s8z24 texture images during glGetTexImage
Signed-off-by: Chad Versace c...@chad-versace.us
---
src/mesa/drivers/dri/intel/intel_tex_image.c |8
1 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_tex_image.c
b/src/mesa/drivers/dri/intel/intel_tex_image.c
index 6065238..4a29bc5 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_image.c
+++ b/src/mesa/drivers/dri/intel/intel_tex_image.c
@@ -659,6 +659,14 @@ intel_get_tex_image(struct gl_context * ctx, GLenum
target, GLint level,
assert(intelImage-base.Data);
}
+ if (intelImage-stencil_rb) {
+ /*
+ * The texture has packed depth/stencil format, but uses separate
+ * stencil. The texture's embedded stencil buffer contains the real
+ * stencil data, so copy that into the miptree.
+ */
+ intel_tex_image_s8z24_gather(intel, intelImage);
+ }
if (compressed) {
_mesa_get_compressed_teximage(ctx, target, level, pixels,
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Mesa (master): intel: Declare some functions in intel_fbo.c as non-static
Module: Mesa Branch: master Commit: 5cd4d8551778e1b371397ad4a1144a1c0b9f436f URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5cd4d8551778e1b371397ad4a1144a1c0b9f436f Author: Chad Versace c...@chad-versace.us Date: Wed Jun 22 10:26:26 2011 -0700 intel: Declare some functions in intel_fbo.c as non-static ... because they will be needed by intel_tex_image_s8z24_create_renderbuffers. Redeclared functions are: intel_alloc_renderbuffer_storage intel_renderbuffer_set_draw_offsets Signed-off-by: Chad Versace c...@chad-versace.us --- src/mesa/drivers/dri/intel/intel_fbo.c |4 ++-- src/mesa/drivers/dri/intel/intel_fbo.h | 12 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c b/src/mesa/drivers/dri/intel/intel_fbo.c index 8dd3696..b431f53 100644 --- a/src/mesa/drivers/dri/intel/intel_fbo.c +++ b/src/mesa/drivers/dri/intel/intel_fbo.c @@ -111,7 +111,7 @@ intel_get_pointer(struct gl_context * ctx, struct gl_renderbuffer *rb, * Called via glRenderbufferStorageEXT() to set the format and allocate * storage for a user-created renderbuffer. */ -static GLboolean +GLboolean intel_alloc_renderbuffer_storage(struct gl_context * ctx, struct gl_renderbuffer *rb, GLenum internalFormat, GLuint width, GLuint height) @@ -582,7 +582,7 @@ intel_wrap_texture(struct gl_context * ctx, struct gl_texture_image *texImage) return irb; } -static void +void intel_renderbuffer_set_draw_offset(struct intel_renderbuffer *irb, struct intel_texture_image *intel_image, int zoffset) diff --git a/src/mesa/drivers/dri/intel/intel_fbo.h b/src/mesa/drivers/dri/intel/intel_fbo.h index 08cf577..cbf29c8 100644 --- a/src/mesa/drivers/dri/intel/intel_fbo.h +++ b/src/mesa/drivers/dri/intel/intel_fbo.h @@ -33,6 +33,7 @@ #include intel_screen.h struct intel_context; +struct intel_texture_image; /** * Intel renderbuffer, derived from gl_renderbuffer. @@ -174,6 +175,12 @@ intel_create_wrapped_renderbuffer(struct gl_context * ctx, int width, int height, gl_format format); +GLboolean +intel_alloc_renderbuffer_storage(struct gl_context * ctx, +struct gl_renderbuffer *rb, + GLenum internalFormat, + GLuint width, GLuint height); + extern void intel_fbo_init(struct intel_context *intel); @@ -181,6 +188,11 @@ intel_fbo_init(struct intel_context *intel); extern void intel_flip_renderbuffers(struct gl_framebuffer *fb); +void +intel_renderbuffer_set_draw_offset(struct intel_renderbuffer *irb, + struct intel_texture_image *intel_image, + int zoffset); + uint32_t intel_renderbuffer_tile_offsets(struct intel_renderbuffer *irb, uint32_t *tile_x, ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel: Factor region updates out of intel_update_wrapper
Module: Mesa
Branch: master
Commit: bffae4c9cd7df044cdbeeed1de257d720f1e76ac
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bffae4c9cd7df044cdbeeed1de257d720f1e76ac
Author: Chad Versace c...@chad-versace.us
Date: Wed Jun 22 16:08:49 2011 -0700
intel: Factor region updates out of intel_update_wrapper
... and into new function intel_update_tex_wrapper_regions.
This prevents code duplication in the next commit.
Also add a note explaining that the hiz region is broken for mipmapped
depth textures.
Signed-off-by: Chad Versace c...@chad-versace.us
---
src/mesa/drivers/dri/intel/intel_fbo.c | 18 ++
1 files changed, 18 insertions(+), 0 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c
b/src/mesa/drivers/dri/intel/intel_fbo.c
index b431f53..fcbe451 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.c
+++ b/src/mesa/drivers/dri/intel/intel_fbo.c
@@ -497,6 +497,10 @@ intel_framebuffer_renderbuffer(struct gl_context * ctx,
intel_draw_buffer(ctx, fb);
}
+static bool
+intel_update_tex_wrapper_regions(struct intel_context *intel,
+struct intel_renderbuffer *irb,
+struct intel_texture_image *intel_image);
static GLboolean
intel_update_wrapper(struct gl_context *ctx, struct intel_renderbuffer *irb,
@@ -523,6 +527,20 @@ intel_update_wrapper(struct gl_context *ctx, struct
intel_renderbuffer *irb,
irb-Base.Delete = intel_delete_renderbuffer;
irb-Base.AllocStorage = intel_nop_alloc_storage;
+ return intel_update_tex_wrapper_regions(intel, irb, intel_image);
+}
+
+/**
+ * FIXME: The handling of the hiz region is broken for mipmapped depth textures
+ * FIXME: because intel_finalize_mipmap_tree is unaware of it.
+ */
+static bool
+intel_update_tex_wrapper_regions(struct intel_context *intel,
+struct intel_renderbuffer *irb,
+struct intel_texture_image *intel_image)
+{
+ struct gl_texture_image *texImage = intel_image-base;
+
/* Point the renderbuffer's region to the texture's region. */
if (irb-region != intel_image-mt-region) {
intel_region_release(irb-region);
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Mesa (master): intel: In intel_update_wrapper, support s8z24 textures when using separate stencil
Module: Mesa
Branch: master
Commit: e357ae949465d0304adb704df5d860ee678390e7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e357ae949465d0304adb704df5d860ee678390e7
Author: Chad Versace c...@chad-versace.us
Date: Wed Jun 22 19:44:53 2011 -0700
intel: In intel_update_wrapper, support s8z24 textures when using separate
stencil
Also, in order to coerce intel_update_tex_wrapper_regions() to
allocate the hiz region, alter intel_update_tex_wrapper_regions() to
examine the renderbuffer format instead of the texture image format.
Signed-off-by: Chad Versace c...@chad-versace.us
---
src/mesa/drivers/dri/intel/intel_fbo.c | 41 +++
1 files changed, 35 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c
b/src/mesa/drivers/dri/intel/intel_fbo.c
index fcbe451..e84b5ab 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.c
+++ b/src/mesa/drivers/dri/intel/intel_fbo.c
@@ -527,7 +527,36 @@ intel_update_wrapper(struct gl_context *ctx, struct
intel_renderbuffer *irb,
irb-Base.Delete = intel_delete_renderbuffer;
irb-Base.AllocStorage = intel_nop_alloc_storage;
- return intel_update_tex_wrapper_regions(intel, irb, intel_image);
+ if (intel_image-stencil_rb) {
+ /* The tex image has packed depth/stencil format, but is using separate
+ * stencil. */
+
+ bool ok;
+ struct intel_renderbuffer *depth_irb =
+intel_renderbuffer(intel_image-depth_rb);
+
+ /* Update the hiz region if necessary. */
+ ok = intel_update_tex_wrapper_regions(intel, depth_irb, intel_image);
+ if (!ok) {
+return false;
+ }
+
+ /* The tex image shares its embedded depth and stencil renderbuffers with
+ * the renderbuffer wrapper. */
+ if (irb-wrapped_depth != intel_image-depth_rb) {
+_mesa_reference_renderbuffer(irb-wrapped_depth,
+ intel_image-depth_rb);
+ }
+ if (irb-wrapped_stencil != intel_image-stencil_rb) {
+_mesa_reference_renderbuffer(irb-wrapped_stencil,
+ intel_image-stencil_rb);
+ }
+
+ return true;
+
+ } else {
+ return intel_update_tex_wrapper_regions(intel, irb, intel_image);
+ }
}
/**
@@ -539,7 +568,7 @@ intel_update_tex_wrapper_regions(struct intel_context
*intel,
struct intel_renderbuffer *irb,
struct intel_texture_image *intel_image)
{
- struct gl_texture_image *texImage = intel_image-base;
+ struct gl_renderbuffer *rb = irb-Base;
/* Point the renderbuffer's region to the texture's region. */
if (irb-region != intel_image-mt-region) {
@@ -548,14 +577,14 @@ intel_update_tex_wrapper_regions(struct intel_context
*intel,
}
/* Allocate the texture's hiz region if necessary. */
- if (intel-vtbl.is_hiz_depth_format(intel, texImage-TexFormat)
+ if (intel-vtbl.is_hiz_depth_format(intel, rb-Format)
!intel_image-mt-hiz_region) {
intel_image-mt-hiz_region =
intel_region_alloc(intel-intelScreen,
I915_TILING_Y,
-_mesa_get_format_bytes(texImage-TexFormat),
-texImage-Width,
-texImage-Height,
+_mesa_get_format_bytes(rb-Format),
+rb-Width,
+rb-Height,
GL_TRUE);
if (!intel_image-mt-hiz_region)
return GL_FALSE;
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Mesa (master): intel: Change framebuffer validation criteria
Module: Mesa
Branch: master
Commit: 97f263c229784a55014b32e8b3e420e58f8bc851
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=97f263c229784a55014b32e8b3e420e58f8bc851
Author: Chad Versace c...@chad-versace.us
Date: Wed Jun 22 17:52:22 2011 -0700
intel: Change framebuffer validation criteria
Since all infrastructure is now in place to support packed
depth/stencil renderbuffers when using separate stencil, there is no
need for special cases when separate stencil is enabled.
Signed-off-by: Chad Versace c...@chad-versace.us
---
src/mesa/drivers/dri/intel/intel_fbo.c | 13 +++--
1 files changed, 3 insertions(+), 10 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c
b/src/mesa/drivers/dri/intel/intel_fbo.c
index e84b5ab..90c3909 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.c
+++ b/src/mesa/drivers/dri/intel/intel_fbo.c
@@ -836,16 +836,9 @@ intel_validate_framebuffer(struct gl_context *ctx, struct
gl_framebuffer *fb)
else
depth_stencil_are_same = false;
- bool fb_has_combined_depth_stencil_format =
- (depthRb depthRb-Base.Format == MESA_FORMAT_S8_Z24) ||
- (stencilRb stencilRb-Base.Format == MESA_FORMAT_S8_Z24);
-
- bool fb_has_hiz = intel_framebuffer_has_hiz(fb);
-
- if ((intel-must_use_separate_stencil || fb_has_hiz)
- (depth_stencil_are_same || fb_has_combined_depth_stencil_format)) {
- fb-_Status = GL_FRAMEBUFFER_UNSUPPORTED_EXT;
- } else if (!intel-has_separate_stencil depthRb stencilRb
!depth_stencil_are_same) {
+ if (!intel-has_separate_stencil
+depthRb stencilRb
+!depth_stencil_are_same) {
fb-_Status = GL_FRAMEBUFFER_UNSUPPORTED_EXT;
}
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Mesa (master): intel: Fix workaround for _mesa_update_framebuffer
Module: Mesa
Branch: master
Commit: 6062692cc6cd2a88d854b304d9a85bcf4bab0d11
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6062692cc6cd2a88d854b304d9a85bcf4bab0d11
Author: Chad Versace c...@chad-versace.us
Date: Thu Jun 23 01:20:19 2011 -0700
intel: Fix workaround for _mesa_update_framebuffer
In intel_draw_buffer, there exists a workaround to prevent
_mesa_update_framebuffer from creating a swrast depth wrapper when
using separate stencil. This commit fixes the workaround, which was
incomplete for s8z24 texture renderbuffers.
Fixes fbo-blit-d24s8 on gen5 with separate stencil manually enabled.
Signed-off-by: Chad Versace c...@chad-versace.us
---
src/mesa/drivers/dri/intel/intel_buffers.c |8 +---
1 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_buffers.c
b/src/mesa/drivers/dri/intel/intel_buffers.c
index 33f691b..a52a07c 100644
--- a/src/mesa/drivers/dri/intel/intel_buffers.c
+++ b/src/mesa/drivers/dri/intel/intel_buffers.c
@@ -105,9 +105,9 @@ intel_draw_buffer(struct gl_context * ctx, struct
gl_framebuffer *fb)
/*
* If intel_context is using separate stencil, but the depth attachment
* (gl_framebuffer.Attachment[BUFFER_DEPTH]) has a packed depth/stencil
-* format, then we must install the real depth buffer at
-* gl_framebuffer._DepthBuffer before calling _mesa_update_framebuffer.
-* Otherwise, _mesa_update_framebuffer will create and install a swrast
+* format, then we must install the real depth buffer at fb-_DepthBuffer
+* and set fb-_DepthBuffer-Wrapped before calling
_mesa_update_framebuffer.
+* Otherwise, _mesa_update_framebuffer will create and install a swras
* depth wrapper instead.
*
* Ditto for stencil.
@@ -115,11 +115,13 @@ intel_draw_buffer(struct gl_context * ctx, struct
gl_framebuffer *fb)
irbDepth = intel_get_renderbuffer(fb, BUFFER_DEPTH);
if (irbDepth irbDepth-Base.Format == MESA_FORMAT_X8_Z24) {
_mesa_reference_renderbuffer(fb-_DepthBuffer, irbDepth-Base);
+ irbDepth-Base.Wrapped = fb-Attachment[BUFFER_DEPTH].Renderbuffer;
}
irbStencil = intel_get_renderbuffer(fb, BUFFER_STENCIL);
if (irbStencil irbStencil-Base.Format == MESA_FORMAT_S8) {
_mesa_reference_renderbuffer(fb-_StencilBuffer, irbStencil-Base);
+ irbStencil-Base.Wrapped = fb-Attachment[BUFFER_STENCIL].Renderbuffer;
}
/* Do this here, not core Mesa, since this function is called from
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Mesa (master): intel: Fix stencil buffer to be W tiled
Module: Mesa
Branch: master
Commit: f7dbcba280e4397cadb14f230aa925b4143cdde4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f7dbcba280e4397cadb14f230aa925b4143cdde4
Author: Chad Versace c...@chad-versace.us
Date: Mon Jul 18 00:37:45 2011 -0700
intel: Fix stencil buffer to be W tiled
Until now, the stencil buffer was allocated as a Y tiled buffer, because
in several locations the PRM states that it is. However, it is actually
W tiled. From the PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section
4.5.2.1 W-Major Format:
W-Major Tile Format is used for separate stencil.
The GTT is incapable of W fencing, so we allocate the stencil buffer with
I915_TILING_NONE and decode the tile's layout in software.
This fix touches the following portions of code:
- In intel_allocate_renderbuffer_storage(), allocate the stencil
buffer with I915_TILING_NONE.
- In intel_verify_dri2_has_hiz(), verify that the stencil buffer is
not tiled.
- In the stencil buffer's span functions, the tile's layout must be
decoded in software.
This commit mutually depends on the xf86-video-intel commit
dri: Do not tile stencil buffer
Author: Chad Versace c...@chad-versace.us
Date: Mon Jul 18 00:38:00 2011 -0700
On Gen6 with separate stencil enabled, fixes the following Piglit tests:
bugs/fdo23670-drawpix_stencil
general/stencil-drawpixels
spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX16-copypixels
spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX16-drawpixels
spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX16-readpixels
spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX1-copypixels
spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX1-drawpixels
spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX1-readpixels
spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX4-copypixels
spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX4-drawpixels
spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX4-readpixels
spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX8-copypixels
spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX8-drawpixels
spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX8-readpixels
spec/EXT_packed_depth_stencil/fbo-stencil-GL_DEPTH24_STENCIL8-copypixels
spec/EXT_packed_depth_stencil/fbo-stencil-GL_DEPTH24_STENCIL8-readpixels
spec/EXT_packed_depth_stencil/readpixels-24_8
Note: This is a candidate for the 7.11 branch.
Signed-off-by: Chad Versace c...@chad-versace.us
Reviewed-by: Eric Anholt e...@anholt.net
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
Acked-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/intel/intel_clear.c |6 ++
src/mesa/drivers/dri/intel/intel_context.c |9 ++-
src/mesa/drivers/dri/intel/intel_fbo.c | 12 ++--
src/mesa/drivers/dri/intel/intel_screen.h |9 ++-
src/mesa/drivers/dri/intel/intel_span.c| 88 +---
5 files changed, 93 insertions(+), 31 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_clear.c
b/src/mesa/drivers/dri/intel/intel_clear.c
index dfca03c..5ab9873 100644
--- a/src/mesa/drivers/dri/intel/intel_clear.c
+++ b/src/mesa/drivers/dri/intel/intel_clear.c
@@ -143,6 +143,12 @@ intelClear(struct gl_context *ctx, GLbitfield mask)
*/
tri_mask |= BUFFER_BIT_STENCIL;
}
+else if (intel-has_separate_stencil
+ stencilRegion-tiling == I915_TILING_NONE) {
+ /* The stencil buffer is actually W tiled, which the hardware
+* cannot blit to. */
+ tri_mask |= BUFFER_BIT_STENCIL;
+}
else {
/* clearing all stencil bits, use blitting */
blit_mask |= BUFFER_BIT_STENCIL;
diff --git a/src/mesa/drivers/dri/intel/intel_context.c
b/src/mesa/drivers/dri/intel/intel_context.c
index 2ba1363..fe8be08 100644
--- a/src/mesa/drivers/dri/intel/intel_context.c
+++ b/src/mesa/drivers/dri/intel/intel_context.c
@@ -1439,7 +1439,12 @@ intel_verify_dri2_has_hiz(struct intel_context *intel,
assert(stencil_rb-Base.Format == MESA_FORMAT_S8);
assert(depth_rb depth_rb-Base.Format == MESA_FORMAT_X8_Z24);
- if (stencil_rb-region-tiling == I915_TILING_Y) {
+ if (stencil_rb-region-tiling == I915_TILING_NONE) {
+/*
+ * The stencil buffer is actually W tiled. The region's tiling is
+ * I915_TILING_NONE, however, because the GTT is incapable of W
+ * fencing.
+ */
intel-intelScreen-dri2_has_hiz = INTEL_DRI2_HAS_HIZ_TRUE;
return;
} else {
@@ -1527,7 +1532,7 @@ intel_verify_dri2_has_hiz(struct intel_context *intel,
* Presently, however, no verification or clean up is necessary, and
* execution should not reach here. If the framebuffer still has a hiz
* region, then we have already set dri2_has_hiz to true after
- * confirming
Mesa (7.11): intel: Fix stencil buffer to be W tiled
Module: Mesa
Branch: 7.11
Commit: f5fa4606eab3def54d15f258c8575b2d1b07157d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f5fa4606eab3def54d15f258c8575b2d1b07157d
Author: Chad Versace c...@chad-versace.us
Date: Mon Jul 18 00:37:45 2011 -0700
intel: Fix stencil buffer to be W tiled
Until now, the stencil buffer was allocated as a Y tiled buffer, because
in several locations the PRM states that it is. However, it is actually
W tiled. From the PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section
4.5.2.1 W-Major Format:
W-Major Tile Format is used for separate stencil.
The GTT is incapable of W fencing, so we allocate the stencil buffer with
I915_TILING_NONE and decode the tile's layout in software.
This fix touches the following portions of code:
- In intel_allocate_renderbuffer_storage(), allocate the stencil
buffer with I915_TILING_NONE.
- In intel_verify_dri2_has_hiz(), verify that the stencil buffer is
not tiled.
- In the stencil buffer's span functions, the tile's layout must be
decoded in software.
This commit mutually depends on the xf86-video-intel commit
dri: Do not tile stencil buffer
Author: Chad Versace c...@chad-versace.us
Date: Mon Jul 18 00:38:00 2011 -0700
On Gen6 with separate stencil enabled, fixes the following Piglit tests:
bugs/fdo23670-drawpix_stencil
general/stencil-drawpixels
spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX16-copypixels
spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX16-drawpixels
spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX16-readpixels
spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX1-copypixels
spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX1-drawpixels
spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX1-readpixels
spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX4-copypixels
spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX4-drawpixels
spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX4-readpixels
spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX8-copypixels
spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX8-drawpixels
spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX8-readpixels
spec/EXT_packed_depth_stencil/fbo-stencil-GL_DEPTH24_STENCIL8-copypixels
spec/EXT_packed_depth_stencil/fbo-stencil-GL_DEPTH24_STENCIL8-readpixels
spec/EXT_packed_depth_stencil/readpixels-24_8
Note: This is a candidate for the 7.11 branch.
Signed-off-by: Chad Versace c...@chad-versace.us
Reviewed-by: Eric Anholt e...@anholt.net
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
Acked-by: Kenneth Graunke kenn...@whitecape.org
(cherry picked from commit f7dbcba280e4397cadb14f230aa925b4143cdde4)
---
src/mesa/drivers/dri/intel/intel_clear.c |6 ++
src/mesa/drivers/dri/intel/intel_context.c |9 ++-
src/mesa/drivers/dri/intel/intel_fbo.c | 12 ++--
src/mesa/drivers/dri/intel/intel_screen.h |9 ++-
src/mesa/drivers/dri/intel/intel_span.c| 88 +---
5 files changed, 93 insertions(+), 31 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_clear.c
b/src/mesa/drivers/dri/intel/intel_clear.c
index 5a96232..57e89f9 100644
--- a/src/mesa/drivers/dri/intel/intel_clear.c
+++ b/src/mesa/drivers/dri/intel/intel_clear.c
@@ -144,6 +144,12 @@ intelClear(struct gl_context *ctx, GLbitfield mask)
*/
tri_mask |= BUFFER_BIT_STENCIL;
}
+else if (intel-has_separate_stencil
+ stencilRegion-tiling == I915_TILING_NONE) {
+ /* The stencil buffer is actually W tiled, which the hardware
+* cannot blit to. */
+ tri_mask |= BUFFER_BIT_STENCIL;
+}
else {
/* clearing all stencil bits, use blitting */
blit_mask |= BUFFER_BIT_STENCIL;
diff --git a/src/mesa/drivers/dri/intel/intel_context.c
b/src/mesa/drivers/dri/intel/intel_context.c
index 70aee52..50b966f 100644
--- a/src/mesa/drivers/dri/intel/intel_context.c
+++ b/src/mesa/drivers/dri/intel/intel_context.c
@@ -1442,7 +1442,12 @@ intel_verify_dri2_has_hiz(struct intel_context *intel,
assert(stencil_rb-Base.Format == MESA_FORMAT_S8);
assert(depth_rb depth_rb-Base.Format == MESA_FORMAT_X8_Z24);
- if (stencil_rb-region-tiling == I915_TILING_Y) {
+ if (stencil_rb-region-tiling == I915_TILING_NONE) {
+/*
+ * The stencil buffer is actually W tiled. The region's tiling is
+ * I915_TILING_NONE, however, because the GTT is incapable of W
+ * fencing.
+ */
intel-intelScreen-dri2_has_hiz = INTEL_DRI2_HAS_HIZ_TRUE;
return;
} else {
@@ -1532,7 +1537,7 @@ intel_verify_dri2_has_hiz(struct intel_context *intel,
* Presently, however, no verification or clean up is necessary, and
* execution should not reach here. If the framebuffer still has a hiz
* region
Mesa (master): glsl: Add method glsl_type::can_implicitly_convert_to()
Module: Mesa
Branch: master
Commit: 200e4972c1579e8dfaa6f11eee2a7e54baad4852
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=200e4972c1579e8dfaa6f11eee2a7e54baad4852
Author: Chad Versace c...@chad-versace.us
Date: Wed Jul 27 12:21:27 2011 -0700
glsl: Add method glsl_type::can_implicitly_convert_to()
This method checks if a source type is identical to or can be implicitly
converted to a target type according to the GLSL 1.20 spec, Section 4.1.10
Implicit Conversions.
The following commits use the method for a bugfix:
glsl: Fix implicit conversions in non-constructor function calls
glsl: Fix implicit conversions in array constructors
Note: This is a candidate for the 7.10 and 7.11 branches.
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
Signed-off-by: Chad Versace c...@chad-versace.us
---
src/glsl/glsl_types.cpp | 16
src/glsl/glsl_types.h | 35 +++
2 files changed, 51 insertions(+), 0 deletions(-)
diff --git a/src/glsl/glsl_types.cpp b/src/glsl/glsl_types.cpp
index a5e21bb..c94aec0 100644
--- a/src/glsl/glsl_types.cpp
+++ b/src/glsl/glsl_types.cpp
@@ -523,3 +523,19 @@ glsl_type::component_slots() const
return 0;
}
}
+
+bool
+glsl_type::can_implicitly_convert_to(const glsl_type *desired) const
+{
+ if (this == desired)
+ return true;
+
+ /* There is no conversion among matrix types. */
+ if (this-matrix_columns 1 || desired-matrix_columns 1)
+ return false;
+
+ /* int and uint can be converted to float. */
+ return desired-is_float()
+ this-is_integer()
+ this-vector_elements == desired-vector_elements;
+}
diff --git a/src/glsl/glsl_types.h b/src/glsl/glsl_types.h
index 87f57e7..0486966 100644
--- a/src/glsl/glsl_types.h
+++ b/src/glsl/glsl_types.h
@@ -224,6 +224,41 @@ struct glsl_type {
*/
unsigned component_slots() const;
+ /**
+* \brief Can this type be implicitly converted to another?
+*
+* \return True if the types are identical or if this type can be converted
+* to \c desired according to Section 4.1.10 of the GLSL spec.
+*
+* \verbatim
+* From page 25 (31 of the pdf) of the GLSL 1.50 spec, Section 4.1.10
+* Implicit Conversions:
+*
+* In some situations, an expression and its type will be implicitly
+* converted to a different type. The following table shows all allowed
+* implicit conversions:
+*
+* Type of expression | Can be implicitly converted to
+* --
+* int float
+* uint
+*
+* ivec2vec2
+* uvec2
+*
+* ivec3vec3
+* uvec3
+*
+* ivec4vec4
+* uvec4
+*
+* There are no implicit array or structure conversions. For example,
+* an array of int cannot be implicitly converted to an array of float.
+* There are no implicit conversions between signed and unsigned
+* integers.
+* \endverbatim
+*/
+ bool can_implicitly_convert_to(const glsl_type *desired) const;
/**
* Query whether or not a type is a scalar (non-vector and non-matrix).
___
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Mesa (master): glsl: Remove ir_function.cpp:type_compare()
Module: Mesa
Branch: master
Commit: 6efe1a849586e46028c1eb763175904166ec7076
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6efe1a849586e46028c1eb763175904166ec7076
Author: Chad Versace c...@chad-versace.us
Date: Wed Jul 27 12:32:10 2011 -0700
glsl: Remove ir_function.cpp:type_compare()
The function is no longer used and has been replaced by
glsl_type::can_implicitly_convert_to().
Note: This is a candidate for the 7.10 and 7.11 branches.
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
Signed-off-by: Chad Versace c...@chad-versace.us
---
src/glsl/ir_function.cpp | 61 --
1 files changed, 0 insertions(+), 61 deletions(-)
diff --git a/src/glsl/ir_function.cpp b/src/glsl/ir_function.cpp
index eca0079..dd63e30 100644
--- a/src/glsl/ir_function.cpp
+++ b/src/glsl/ir_function.cpp
@@ -24,67 +24,6 @@
#include glsl_types.h
#include ir.h
-int
-type_compare(const glsl_type *a, const glsl_type *b)
-{
- /* If the types are the same, they trivially match.
-*/
- if (a == b)
- return 0;
-
- switch (a-base_type) {
- case GLSL_TYPE_UINT:
- case GLSL_TYPE_INT:
- case GLSL_TYPE_BOOL:
- /* There is no implicit conversion to or from integer types or bool.
- */
- if ((a-is_integer() != b-is_integer())
- || (a-is_boolean() != b-is_boolean()))
-return -1;
-
- /* FALLTHROUGH */
-
- case GLSL_TYPE_FLOAT:
- if ((a-vector_elements != b-vector_elements)
- || (a-matrix_columns != b-matrix_columns))
-return -1;
-
- return 1;
-
- case GLSL_TYPE_SAMPLER:
- case GLSL_TYPE_STRUCT:
- /* Samplers and structures must match exactly.
- */
- return -1;
-
- case GLSL_TYPE_ARRAY:
- if ((b-base_type != GLSL_TYPE_ARRAY)
- || (a-length != b-length))
-return -1;
-
- /* From GLSL 1.50 spec, page 27 (page 33 of the PDF):
- *There are no implicit array or structure conversions.
- *
- * If the comparison of the array element types detects that a conversion
- * would be required, the array types do not match.
- */
- return (type_compare(a-fields.array, b-fields.array) == 0) ? 0 : -1;
-
- case GLSL_TYPE_VOID:
- case GLSL_TYPE_ERROR:
- default:
- /* These are all error conditions. It is invalid for a parameter to
- * a function to be declared as error, void, or a function.
- */
- return -1;
- }
-
- /* This point should be unreachable.
-*/
- assert(0);
-}
-
-
/**
* \brief Check if two parameter lists match.
*
___
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Mesa (master): glsl: Fix implicit conversions in non-constructor function calls
Module: Mesa
Branch: master
Commit: 8b3627fd7b52723102f070957d87f98073e92d7c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8b3627fd7b52723102f070957d87f98073e92d7c
Author: Chad Versace c...@chad-versace.us
Date: Wed Jul 27 12:31:10 2011 -0700
glsl: Fix implicit conversions in non-constructor function calls
Context
---
In ast_function_expression::hir(), parameter_lists_match() checks if the
function call's actual parameter list matches the signature's parameter
list, where the match may require implicit conversion of some arguments.
To check if an implicit conversion exists between individual arguments,
type_compare() is used.
Problems
type_compare() allowed the following illegal implicit conversions:
bool - float
bvecN - vecN
int - uint
ivecN - uvecN
uint - int
uvecN - ivecN
Change
--
type_compare() is buggy, so replace it with
glsl_type::can_be_implicitly_converted_to().
This comprises a rewrite of parameter_lists_match().
Fixes piglit:spec/glsl-1.20/compiler/built-in-functions/outerProduct-bvec*.vert
Note: This is a candidate for the 7.10 and 7.11 branches.
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
Signed-off-by: Chad Versace c...@chad-versace.us
---
src/glsl/ir_function.cpp | 46 +-
1 files changed, 29 insertions(+), 17 deletions(-)
diff --git a/src/glsl/ir_function.cpp b/src/glsl/ir_function.cpp
index 0f2f1a0..eca0079 100644
--- a/src/glsl/ir_function.cpp
+++ b/src/glsl/ir_function.cpp
@@ -85,12 +85,25 @@ type_compare(const glsl_type *a, const glsl_type *b)
}
+/**
+ * \brief Check if two parameter lists match.
+ *
+ * \param list_a Parameters of the function definition.
+ * \param list_b Actual parameters passed to the function.
+ * \return If an exact match, return 0.
+ * If an inexact match requiring implicit conversion, return 1.
+ * If not a match, return -1.
+ * \see matching_signature()
+ */
static int
parameter_lists_match(const exec_list *list_a, const exec_list *list_b)
{
const exec_node *node_a = list_a-head;
const exec_node *node_b = list_b-head;
- int total_score = 0;
+
+ /* This is set to true if there is an inexact match requiring an implicit
+* conversion. */
+ bool inexact_match = false;
for (/* empty */
; !node_a-is_tail_sentinel()
@@ -106,12 +119,11 @@ parameter_lists_match(const exec_list *list_a, const
exec_list *list_b)
const ir_variable *const param = (ir_variable *) node_a;
const ir_instruction *const actual = (ir_instruction *) node_b;
- /* Determine whether or not the types match. If the types are an
- * exact match, the match score is zero. If the types don't match
- * but the actual parameter can be coerced to the type of the declared
- * parameter, the match score is one.
- */
- int score;
+ if (param-type == actual-type)
+continue;
+
+ /* Try to find an implicit conversion from actual to param. */
+ inexact_match = true;
switch ((enum ir_variable_mode)(param-mode)) {
case ir_var_auto:
case ir_var_uniform:
@@ -125,11 +137,13 @@ parameter_lists_match(const exec_list *list_a, const
exec_list *list_b)
case ir_var_const_in:
case ir_var_in:
-score = type_compare(param-type, actual-type);
+if (!actual-type-can_implicitly_convert_to(param-type))
+ return -1;
break;
case ir_var_out:
-score = type_compare(actual-type, param-type);
+if (!param-type-can_implicitly_convert_to(actual-type))
+ return -1;
break;
case ir_var_inout:
@@ -137,17 +151,12 @@ parameter_lists_match(const exec_list *list_a, const
exec_list *list_b)
* there is int - float but no float - int), inout parameters must
* be exact matches.
*/
-score = (type_compare(actual-type, param-type) == 0) ? 0 : -1;
-break;
+return -1;
default:
assert(false);
- }
-
- if (score 0)
return -1;
-
- total_score += score;
+ }
}
/* If all of the parameters from the other parameter list have been
@@ -157,7 +166,10 @@ parameter_lists_match(const exec_list *list_a, const
exec_list *list_b)
if (!node_b-is_tail_sentinel())
return -1;
- return total_score;
+ if (inexact_match)
+ return 1;
+ else
+ return 0;
}
___
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Mesa (master): glsl: Fix conversions in array constructors
Module: Mesa
Branch: master
Commit: a5ab9398e34287ed8cbb010d0758790e6692530c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a5ab9398e34287ed8cbb010d0758790e6692530c
Author: Chad Versace c...@chad-versace.us
Date: Wed Jul 27 13:00:02 2011 -0700
glsl: Fix conversions in array constructors
Array constructors obey narrower conversion rules than other constructors
[1] --- they use the implicit conversion rules [2] instead of the scalar
constructor conversions [3]. But process_array_constructor() was
incorrectly applying the broader rules.
[1] GLSL 1.50 spec, Section 5.4.4 Array Constructors, page 52 (58 of pdf)
[2] GLSL 1.50 spec, Section 4.1.10 Implicit Conversions, page 25 (31 of pdf)
[3] GLSL 1.50 spec, Section 5.4.1 Conversion, page 48 (54 of pdf)
To fix this, first check (with glsl_type::can_be_implicitly_converted_to)
if an implicit conversion is legal before performing the conversion.
Fixes:
piglit:spec/glsl-1.20/compiler/structure-and-array-operations/array-ctor-implicit-conversion-bool-float.vert
piglit:spec/glsl-1.20/compiler/structure-and-array-operations/array-ctor-implicit-conversion-bvec*-vec*.vert
Note: This is a candidate for the 7.10 and 7.11 branches.
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
Signed-off-by: Chad Versace c...@chad-versace.us
---
src/glsl/ast_function.cpp | 12 ++--
1 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/src/glsl/ast_function.cpp b/src/glsl/ast_function.cpp
index bdb73f4..8bcf48d 100644
--- a/src/glsl/ast_function.cpp
+++ b/src/glsl/ast_function.cpp
@@ -442,13 +442,21 @@ process_array_constructor(exec_list *instructions,
ir_rvalue *ir = (ir_rvalue *) n;
ir_rvalue *result = ir;
- /* Apply implicit conversions (not the scalar constructor rules!) */
+ /* Apply implicit conversions (not the scalar constructor rules!). See
+ * the spec quote above. */
if (constructor_type-element_type()-is_float()) {
const glsl_type *desired_type =
glsl_type::get_instance(GLSL_TYPE_FLOAT,
ir-type-vector_elements,
ir-type-matrix_columns);
-result = convert_component(ir, desired_type);
+if (result-type-can_implicitly_convert_to(desired_type)) {
+ /* Even though convert_component() implements the constructor
+* conversion rules (not the implicit conversion rules), its safe
+* to use it here because we already checked that the implicit
+* conversion is legal.
+*/
+ result = convert_component(ir, desired_type);
+}
}
if (result-type != constructor_type-element_type()) {
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Mesa (master): glsl: Clarify ir_function::matching_sigature()
Module: Mesa
Branch: master
Commit: 5081d31a0ed753e7e23c5ed51f572d38aef66bfe
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5081d31a0ed753e7e23c5ed51f572d38aef66bfe
Author: Chad Versace c...@chad-versace.us
Date: Wed Jul 27 12:37:51 2011 -0700
glsl: Clarify ir_function::matching_sigature()
The function used a variable named 'score', which was an outright lie.
A signature matches or it doesn't; there is no fuzzy scoring.
Change the return type of parameter_lists_match() to an enum, and
let ir_function::matching_sigature() switch on that enum.
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
Signed-off-by: Chad Versace c...@chad-versace.us
---
src/glsl/ir_function.cpp | 53 -
1 files changed, 33 insertions(+), 20 deletions(-)
diff --git a/src/glsl/ir_function.cpp b/src/glsl/ir_function.cpp
index dd63e30..6cfc32c 100644
--- a/src/glsl/ir_function.cpp
+++ b/src/glsl/ir_function.cpp
@@ -24,17 +24,28 @@
#include glsl_types.h
#include ir.h
+typedef enum {
+ PARAMETER_LIST_NO_MATCH,
+ PARAMETER_LIST_EXACT_MATCH,
+ PARAMETER_LIST_INEXACT_MATCH, /* Match requires implicit conversion. */
+} parameter_list_match_t;
+
/**
* \brief Check if two parameter lists match.
*
* \param list_a Parameters of the function definition.
* \param list_b Actual parameters passed to the function.
- * \return If an exact match, return 0.
- * If an inexact match requiring implicit conversion, return 1.
- * If not a match, return -1.
* \see matching_signature()
*/
-static int
+
+/**
+ * \brief Check if two parameter lists match.
+ *
+ * \param list_a Parameters of the function definition.
+ * \param list_b Actual parameters passed to the function.
+ * \see matching_signature()
+ */
+static parameter_list_match_t
parameter_lists_match(const exec_list *list_a, const exec_list *list_b)
{
const exec_node *node_a = list_a-head;
@@ -52,7 +63,7 @@ parameter_lists_match(const exec_list *list_a, const
exec_list *list_b)
* do not match.
*/
if (node_b-is_tail_sentinel())
-return -1;
+return PARAMETER_LIST_NO_MATCH;
const ir_variable *const param = (ir_variable *) node_a;
@@ -72,17 +83,17 @@ parameter_lists_match(const exec_list *list_a, const
exec_list *list_b)
* as uniform.
*/
assert(0);
-return -1;
+return PARAMETER_LIST_NO_MATCH;
case ir_var_const_in:
case ir_var_in:
if (!actual-type-can_implicitly_convert_to(param-type))
- return -1;
+ return PARAMETER_LIST_NO_MATCH;
break;
case ir_var_out:
if (!param-type-can_implicitly_convert_to(actual-type))
- return -1;
+ return PARAMETER_LIST_NO_MATCH;
break;
case ir_var_inout:
@@ -90,11 +101,11 @@ parameter_lists_match(const exec_list *list_a, const
exec_list *list_b)
* there is int - float but no float - int), inout parameters must
* be exact matches.
*/
-return -1;
+return PARAMETER_LIST_NO_MATCH;
default:
assert(false);
-return -1;
+return PARAMETER_LIST_NO_MATCH;
}
}
@@ -103,12 +114,12 @@ parameter_lists_match(const exec_list *list_a, const
exec_list *list_b)
* match.
*/
if (!node_b-is_tail_sentinel())
- return -1;
+ return PARAMETER_LIST_NO_MATCH;
if (inexact_match)
- return 1;
+ return PARAMETER_LIST_INEXACT_MATCH;
else
- return 0;
+ return PARAMETER_LIST_EXACT_MATCH;
}
@@ -132,18 +143,20 @@ ir_function::matching_signature(const exec_list
*actual_parameters)
ir_function_signature *const sig =
(ir_function_signature *) iter.get();
- const int score = parameter_lists_match( sig-parameters,
- actual_parameters);
-
- /* If we found an exact match, simply return it */
- if (score == 0)
+ switch (parameter_lists_match( sig-parameters, actual_parameters)) {
+ case PARAMETER_LIST_EXACT_MATCH:
return sig;
-
- if (score 0) {
+ case PARAMETER_LIST_INEXACT_MATCH:
if (match == NULL)
match = sig;
else
multiple_inexact_matches = true;
+continue;
+ case PARAMETER_LIST_NO_MATCH:
+continue;
+ default:
+assert(false);
+return NULL;
}
}
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Mesa (master): glsl: Remove duplicate comment
Module: Mesa
Branch: master
Commit: 5541920e0ac4ea8383c7f896daba24a304aafec6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5541920e0ac4ea8383c7f896daba24a304aafec6
Author: Chad Versace c...@chad-versace.us
Date: Mon Aug 1 09:36:08 2011 -0700
glsl: Remove duplicate comment
Remove duplicate doxgen comment for
ir_function.cpp:parameter_lists_match().
Signed-off-by: Chad Versace c...@chad-versace.us
---
src/glsl/ir_function.cpp |8
1 files changed, 0 insertions(+), 8 deletions(-)
diff --git a/src/glsl/ir_function.cpp b/src/glsl/ir_function.cpp
index 6cfc32c..2a4de5b 100644
--- a/src/glsl/ir_function.cpp
+++ b/src/glsl/ir_function.cpp
@@ -37,14 +37,6 @@ typedef enum {
* \param list_b Actual parameters passed to the function.
* \see matching_signature()
*/
-
-/**
- * \brief Check if two parameter lists match.
- *
- * \param list_a Parameters of the function definition.
- * \param list_b Actual parameters passed to the function.
- * \see matching_signature()
- */
static parameter_list_match_t
parameter_lists_match(const exec_list *list_a, const exec_list *list_b)
{
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Mesa (master): x86-64: Fix compile error with clang
Module: Mesa Branch: master Commit: 9cd64ec35acd54cbe0be4d03236d2c5a9d4be6fe URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9cd64ec35acd54cbe0be4d03236d2c5a9d4be6fe Author: Chad Versace c...@chad-versace.us Date: Wed Aug 10 15:46:14 2011 -0700 x86-64: Fix compile error with clang Remove the 'f' suffix from a float literal. - .float 0.0f+1.0 + .float 1.0 This fixes the following compile error with clang: error: unexpected token in directive .float 0.0f+1.0 ^ Note: This is a candidate for the stable branches. Reviewed-by: Ben Widawsky b...@bwidawsk.net Signed-off-by: Chad Versace c...@chad-versace.us --- src/mesa/x86-64/xform4.S |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/mesa/x86-64/xform4.S b/src/mesa/x86-64/xform4.S index 6141e43..5abd5a2 100644 --- a/src/mesa/x86-64/xform4.S +++ b/src/mesa/x86-64/xform4.S @@ -118,7 +118,7 @@ p4_constants: .byte 0x00, 0x00, 0x00, 0x00 .byte 0x00, 0x00, 0x00, 0x00 .byte 0x00, 0x00, 0x00, 0x00 -.float 0f+1.0 +.float 1.0 .text .align 16 ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): mesa: Remove use of fpu_control.h
Module: Mesa
Branch: master
Commit: eb0ff1a1c0f1978d867c748bf2525f717a56bfce
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=eb0ff1a1c0f1978d867c748bf2525f717a56bfce
Author: Chad Versace c...@chad-versace.us
Date: Mon Aug 15 10:58:25 2011 -0700
mesa: Remove use of fpu_control.h
Remove the inclusion of fpu_control.h from compiler.h. Since Bionic lacks
fpu_control.h, this fixes the Android build.
Also remove the sole use of the fpu_control bits, which was in debug.c.
Those were brianp's debug bits, and he approved of their removal.
Reviewed-by: Eric Anholt e...@anholt.net
Signed-off-by: Chad Versace c...@chad-versace.us
---
src/mesa/main/compiler.h |3 ---
src/mesa/main/debug.c| 11 ---
2 files changed, 0 insertions(+), 14 deletions(-)
diff --git a/src/mesa/main/compiler.h b/src/mesa/main/compiler.h
index ee7d0b2..8ed1c6f 100644
--- a/src/mesa/main/compiler.h
+++ b/src/mesa/main/compiler.h
@@ -45,9 +45,6 @@
#include stdlib.h
#include stdio.h
#include string.h
-#if defined(__linux__) defined(__i386__)
-#include fpu_control.h
-#endif
#include float.h
#include stdarg.h
diff --git a/src/mesa/main/debug.c b/src/mesa/main/debug.c
index e7f6be9..b1fc096 100644
--- a/src/mesa/main/debug.c
+++ b/src/mesa/main/debug.c
@@ -192,17 +192,6 @@ static void add_debug_flags( const char *debug )
if (strstr(debug, flush))
MESA_DEBUG_FLAGS |= DEBUG_ALWAYS_FLUSH;
-#if defined(_FPU_GETCW) defined(_FPU_SETCW)
- if (strstr(debug, fpexceptions)) {
- /* raise FP exceptions */
- fpu_control_t mask;
- _FPU_GETCW(mask);
- mask = ~(_FPU_MASK_IM | _FPU_MASK_DM | _FPU_MASK_ZM
-| _FPU_MASK_OM | _FPU_MASK_UM);
- _FPU_SETCW(mask);
- }
-#endif
-
#else
(void) debug;
#endif
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Mesa (master): mesa: Fix Android build by #ifdef'ing out locale support
Module: Mesa
Branch: master
Commit: bd064a49f119d126623c0e85702801e4cee62187
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bd064a49f119d126623c0e85702801e4cee62187
Author: Chad Versace c...@chad-versace.us
Date: Mon Aug 15 13:26:21 2011 -0700
mesa: Fix Android build by #ifdef'ing out locale support
Bionic does not support locales. This commit #ifdef's out the locale usage
in _mesa_strtof().
Signed-off-by: Chad Versace c...@chad-versace.us
---
src/mesa/main/imports.c |3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/src/mesa/main/imports.c b/src/mesa/main/imports.c
index 0a572ec..8f09719 100644
--- a/src/mesa/main/imports.c
+++ b/src/mesa/main/imports.c
@@ -753,7 +753,8 @@ _mesa_strdup( const char *s )
float
_mesa_strtof( const char *s, char **end )
{
-#if defined(_GNU_SOURCE) !defined(__CYGWIN__) !defined(__FreeBSD__)
+#if defined(_GNU_SOURCE) !defined(__CYGWIN__) !defined(__FreeBSD__) \
+!defined(ANDROID)
static locale_t loc = NULL;
if (!loc) {
loc = newlocale(LC_CTYPE_MASK, C, NULL);
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Mesa (master): mesa: Add Android to list of platforms that define fpclassify()
Module: Mesa Branch: master Commit: 3c9f172fe801a8e954a40affc38942b628b81bda URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3c9f172fe801a8e954a40affc38942b628b81bda Author: Chad Versace c...@chad-versace.us Date: Mon Aug 15 13:29:15 2011 -0700 mesa: Add Android to list of platforms that define fpclassify() This is a fix for the Android build. Signed-off-by: Chad Versace c...@chad-versace.us --- src/mesa/main/querymatrix.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/mesa/main/querymatrix.c b/src/mesa/main/querymatrix.c index 944ad43..eaedf7c 100644 --- a/src/mesa/main/querymatrix.c +++ b/src/mesa/main/querymatrix.c @@ -73,7 +73,7 @@ fpclassify(double x) #elif defined(__APPLE__) || defined(__CYGWIN__) || defined(__FreeBSD__) || \ defined(__OpenBSD__) || defined(__NetBSD__) || defined(__DragonFly__) || \ (defined(__sun) defined(__C99FEATURES__)) || defined(__MINGW32__) || \ - (defined(__sun) defined(__GNUC__)) + (defined(__sun) defined(__GNUC__)) || defined(ANDROID) /* fpclassify is available. */ ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): mesa: Declare _mesa_meta_begin()/end() as public
Module: Mesa
Branch: master
Commit: f23c3ebeccc5c591b79c10cbdb693270ef27a2f5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f23c3ebeccc5c591b79c10cbdb693270ef27a2f5
Author: Chad Versace c...@chad-versace.us
Date: Fri Aug 12 16:50:27 2011 -0700
mesa: Declare _mesa_meta_begin()/end() as public
Declare _mesa_meta_begin()/end() in meta.h so that drivers can write
custom meta-ops (such as HiZ resolves for i965).
This necessitates moving the the META_* macros into meta.h. To prevent
naming collisions, this commit renames each macro to be MESA_META_*.
Reviewed-by: Brian Paul bri...@vmware.com
Signed-off-by: Chad Versace c...@chad-versace.us
---
src/mesa/drivers/common/meta.c | 256 ++--
src/mesa/drivers/common/meta.h | 33 +
2 files changed, 147 insertions(+), 142 deletions(-)
diff --git a/src/mesa/drivers/common/meta.c b/src/mesa/drivers/common/meta.c
index f9b4755..e37b78a 100644
--- a/src/mesa/drivers/common/meta.c
+++ b/src/mesa/drivers/common/meta.c
@@ -73,64 +73,36 @@
/** Return offset in bytes of the field within a vertex struct */
#define OFFSET(FIELD) ((void *) offsetof(struct vertex, FIELD))
-
-/**
- * Flags passed to _mesa_meta_begin().
- */
-/*@{*/
-#define META_ALL ~0x0
-#define META_ALPHA_TEST0x1
-#define META_BLEND 0x2 /** includes logicop */
-#define META_COLOR_MASK0x4
-#define META_DEPTH_TEST0x8
-#define META_FOG 0x10
-#define META_PIXEL_STORE 0x20
-#define META_PIXEL_TRANSFER 0x40
-#define META_RASTERIZATION0x80
-#define META_SCISSOR 0x100
-#define META_SHADER 0x200
-#define META_STENCIL_TEST0x400
-#define META_TRANSFORM 0x800 /** modelview/projection matrix state */
-#define META_TEXTURE0x1000
-#define META_VERTEX 0x2000
-#define META_VIEWPORT 0x4000
-#define META_CLAMP_FRAGMENT_COLOR 0x8000
-#define META_CLAMP_VERTEX_COLOR 0x1
-#define META_CONDITIONAL_RENDER 0x2
-#define META_CLIP 0x4
-/*@}*/
-
-
/**
* State which we may save/restore across meta ops.
* XXX this may be incomplete...
*/
struct save_state
{
- GLbitfield SavedState; /** bitmask of META_* flags */
+ GLbitfield SavedState; /** bitmask of MESA_META_* flags */
- /** META_ALPHA_TEST */
+ /** MESA_META_ALPHA_TEST */
GLboolean AlphaEnabled;
GLenum AlphaFunc;
GLclampf AlphaRef;
- /** META_BLEND */
+ /** MESA_META_BLEND */
GLbitfield BlendEnabled;
GLboolean ColorLogicOpEnabled;
- /** META_COLOR_MASK */
+ /** MESA_META_COLOR_MASK */
GLubyte ColorMask[MAX_DRAW_BUFFERS][4];
- /** META_DEPTH_TEST */
+ /** MESA_META_DEPTH_TEST */
struct gl_depthbuffer_attrib Depth;
- /** META_FOG */
+ /** MESA_META_FOG */
GLboolean Fog;
- /** META_PIXEL_STORE */
+ /** MESA_META_PIXEL_STORE */
struct gl_pixelstore_attrib Pack, Unpack;
- /** META_PIXEL_TRANSFER */
+ /** MESA_META_PIXEL_TRANSFER */
GLfloat RedBias, RedScale;
GLfloat GreenBias, GreenScale;
GLfloat BlueBias, BlueScale;
@@ -138,17 +110,17 @@ struct save_state
GLfloat DepthBias, DepthScale;
GLboolean MapColorFlag;
- /** META_RASTERIZATION */
+ /** MESA_META_RASTERIZATION */
GLenum FrontPolygonMode, BackPolygonMode;
GLboolean PolygonOffset;
GLboolean PolygonSmooth;
GLboolean PolygonStipple;
GLboolean PolygonCull;
- /** META_SCISSOR */
+ /** MESA_META_SCISSOR */
struct gl_scissor_attrib Scissor;
- /** META_SHADER */
+ /** MESA_META_SHADER */
GLboolean VertexProgramEnabled;
struct gl_vertex_program *VertexProgram;
GLboolean FragmentProgramEnabled;
@@ -158,19 +130,19 @@ struct save_state
struct gl_shader_program *FragmentShader;
struct gl_shader_program *ActiveShader;
- /** META_STENCIL_TEST */
+ /** MESA_META_STENCIL_TEST */
struct gl_stencil_attrib Stencil;
- /** META_TRANSFORM */
+ /** MESA_META_TRANSFORM */
GLenum MatrixMode;
GLfloat ModelviewMatrix[16];
GLfloat ProjectionMatrix[16];
GLfloat TextureMatrix[16];
- /** META_CLIP */
+ /** MESA_META_CLIP */
GLbitfield ClipPlanesEnabled;
- /** META_TEXTURE */
+ /** MESA_META_TEXTURE */
GLuint ActiveUnit;
GLuint ClientActiveUnit;
/** for unit[0] only */
@@ -180,21 +152,21 @@ struct save_state
GLbitfield TexGenEnabled[MAX_TEXTURE_UNITS];
GLuint EnvMode; /* unit[0] only */
- /** META_VERTEX */
+ /** MESA_META_VERTEX */
struct gl_array_object *ArrayObj;
struct gl_buffer_object *ArrayBufferObj;
- /** META_VIEWPORT */
+ /** MESA_META_VIEWPORT */
GLint ViewportX, ViewportY, ViewportW, ViewportH;
GLclampd DepthNear, DepthFar;
- /** META_CLAMP_FRAGMENT_COLOR */
+ /** MESA_META_CLAMP_FRAGMENT_COLOR */
GLenum ClampFragmentColor;
- /** META_CLAMP_VERTEX_COLOR */
+ /** MESA_META_CLAMP_VERTEX_COLOR */
GLenum ClampVertexColor;
- /** META_CONDITIONAL_RENDER
Mesa (master): intel: Abort when DRI2 separate stencil handshake fails
Module: Mesa
Branch: master
Commit: 69595283b64d1f01b33022c38468376ad8596ea7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=69595283b64d1f01b33022c38468376ad8596ea7
Author: Chad Versace c...@chad-versace.us
Date: Wed Aug 17 17:35:07 2011 -0700
intel: Abort when DRI2 separate stencil handshake fails
When intel_context requires separate stencil but the DRI2 separate stencil
handshake fails, then abort and emit an error instructing the user to
upgrade the DDX to 2.16.0.
CC: Eric Anholt e...@anholt.net
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
Signed-off-by: Chad Versace c...@chad-versace.us
---
src/mesa/drivers/dri/intel/intel_context.c |7 +++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_context.c
b/src/mesa/drivers/dri/intel/intel_context.c
index fe8be08..14342ef 100644
--- a/src/mesa/drivers/dri/intel/intel_context.c
+++ b/src/mesa/drivers/dri/intel/intel_context.c
@@ -1454,6 +1454,13 @@ intel_verify_dri2_has_hiz(struct intel_context *intel,
* a combined depth/stencil buffer. Discard the hiz buffer too.
*/
intel-intelScreen-dri2_has_hiz = INTEL_DRI2_HAS_HIZ_FALSE;
+if (intel-must_use_separate_stencil) {
+ _mesa_problem(intel-ctx,
+ intel_context requires separate stencil, but the
+ DRIscreen does not support it. You may need to
+ upgrade the Intel X driver to 2.16.0);
+ abort();
+}
/* 1. Discard depth and stencil renderbuffers. */
_mesa_remove_renderbuffer(fb, BUFFER_DEPTH);
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Mesa (master): i965: Factor our source lists into Makefile.sources
Module: Mesa Branch: master Commit: f55a9a481ff8778ee423895230d8221294296300 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f55a9a481ff8778ee423895230d8221294296300 Author: Chad Versace c...@chad-versace.us Date: Fri Aug 26 15:52:16 2011 -0700 i965: Factor our source lists into Makefile.sources In preparation for porting i965 to Android, factor its source lists into a shared makefile. This prevents duplication of source lists, and hence prevents the Android from breaking as often. Acked-by: Chia-I Wu o...@lunarg.com Signed-off-by: Chad Versace c...@chad-versace.us --- src/mesa/drivers/dri/i965/Makefile | 138 ++- src/mesa/drivers/dri/i965/Makefile.sources | 125 + 2 files changed, 136 insertions(+), 127 deletions(-) diff --git a/src/mesa/drivers/dri/i965/Makefile b/src/mesa/drivers/dri/i965/Makefile index d9c885d..57af7a6 100644 --- a/src/mesa/drivers/dri/i965/Makefile +++ b/src/mesa/drivers/dri/i965/Makefile @@ -1,138 +1,22 @@ - TOP = ../../../../.. +MESA_TOP := $(TOP) + +# Import variables i965_*. +include Makefile.sources + include $(TOP)/configs/current LIBNAME = i965_dri.so include ../Makefile.defines -DRIVER_SOURCES = \ - intel_batchbuffer.c \ - intel_blit.c \ - intel_buffer_objects.c \ - intel_buffers.c \ - intel_clear.c \ - intel_context.c \ - intel_decode.c \ - intel_extensions.c \ - intel_extensions_es2.c \ - intel_fbo.c \ - intel_mipmap_tree.c \ - intel_regions.c \ - intel_screen.c \ - intel_span.c \ - intel_pixel.c \ - intel_pixel_bitmap.c \ - intel_pixel_copy.c \ - intel_pixel_draw.c \ - intel_pixel_read.c \ - intel_state.c \ - intel_syncobj.c \ - intel_tex.c \ - intel_tex_copy.c \ - intel_tex_format.c \ - intel_tex_image.c \ - intel_tex_layout.c \ - intel_tex_subimage.c \ - intel_tex_validate.c \ - brw_cc.c \ - brw_clip.c \ - brw_clip_line.c \ - brw_clip_point.c \ - brw_clip_state.c \ - brw_clip_tri.c \ - brw_clip_unfilled.c \ - brw_clip_util.c \ - brw_context.c \ - brw_curbe.c \ - brw_disasm.c \ - brw_draw.c \ - brw_draw_upload.c \ - brw_eu.c \ - brw_eu_debug.c \ - brw_eu_emit.c \ - brw_eu_util.c \ - brw_fallback.c \ - brw_gs.c \ - brw_gs_emit.c \ - brw_gs_state.c \ - brw_misc_state.c \ - brw_optimize.c \ - brw_program.c \ - brw_queryobj.c \ - brw_sf.c \ - brw_sf_emit.c \ - brw_sf_state.c \ - brw_state_batch.c \ - brw_state_cache.c \ - brw_state_dump.c \ - brw_state_upload.c \ - brw_tex.c \ - brw_tex_layout.c \ - brw_urb.c \ - brw_util.c \ - brw_vs.c \ - brw_vs_constval.c \ - brw_vs_emit.c \ - brw_vs_state.c \ - brw_vs_surface_state.c \ - brw_vtbl.c \ - brw_wm.c \ - brw_wm_debug.c \ - brw_wm_emit.c \ - brw_wm_fp.c \ - brw_wm_iz.c \ - brw_wm_pass0.c \ - brw_wm_pass1.c \ - brw_wm_pass2.c \ - brw_wm_sampler_state.c \ - brw_wm_state.c \ - brw_wm_surface_state.c \ - gen6_cc.c \ - gen6_clip_state.c \ - gen6_depthstencil.c \ - gen6_gs_state.c \ - gen6_sampler_state.c \ - gen6_scissor_state.c \ - gen6_sf_state.c \ - gen6_urb.c \ - gen6_viewport_state.c \ - gen6_vs_state.c \ - gen6_wm_state.c \ - gen7_cc_state.c \ - gen7_clip_state.c \ - gen7_disable.c \ - gen7_misc_state.c \ - gen7_sampler_state.c \ - gen7_sf_state.c \ - gen7_urb.c \ - gen7_viewport_state.c \ - gen7_vs_state.c \ - gen7_wm_state.c \ - gen7_wm_surface_state.c \ - -C_SOURCES = \ - $(COMMON_SOURCES) \ - $(DRIVER_SOURCES) - -CXX_SOURCES = \ - brw_cubemap_normalize.cpp \ - brw_fs.cpp \ - brw_fs_emit.cpp \ - brw_fs_visitor.cpp \ - brw_fs_channel_expressions.cpp \ - brw_fs_reg_allocate.cpp \ - brw_fs_schedule_instructions.cpp \ - brw_fs_vector_splitting.cpp \ - brw_shader.cpp \ - brw_vec4.cpp \ - brw_vec4_emit.cpp \ - brw_vec4_reg_allocate.cpp \ - brw_vec4_visitor.cpp - -ASM_SOURCES = +C_SOURCES := \ + $(i965_C_SOURCES) \ + $(COMMON_SOURCES) -DRIVER_DEFINES = -I../intel +CXX_SOURCES := $(i965_CXX_SOURCES) +ASM_SOURCES := $(i965_ASM_SOURCES) +DRIVER_DEFINES := $(addprefix -I, $(i965_INCLUDES)) INCLUDES += $(INTEL_CFLAGS) DRI_LIB_DEPS += $(INTEL_LIBS) diff --git a/src/mesa/drivers/dri/i965/Makefile.sources b/src/mesa/drivers/dri/i965/Makefile.sources new file mode 100644 index 000..e9bd707 --- /dev/null +++ b/src/mesa/drivers/dri/i965/Makefile.sources @@ -0,0 +1,125 @@ +i965_INCLUDES := \ + $(MESA_TOP)/src \ + $(MESA_TOP
Mesa (master): make: Remove duplicate defintion of COMMON_SOURCES in Radeon makefiles
Module: Mesa
Branch: master
Commit: 08701b6c952e2c65a06f26305633eb699dabe748
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=08701b6c952e2c65a06f26305633eb699dabe748
Author: Chad Versace c...@chad-versace.us
Date: Sun Aug 28 07:58:28 2011 -0700
make: Remove duplicate defintion of COMMON_SOURCES in Radeon makefiles
Remove defintion of COMMON_SOURCES from {r300,r660}/Makefile. The
defintion is a duplicate of that found in
src/mesa/drivers/dri/Makefile.defines.
Reviewed-by: Ian Romanick i...@freedesktop.org
Signed-off-by: Chad Versace c...@chad-versace.us
---
src/mesa/drivers/dri/r300/Makefile |9 -
src/mesa/drivers/dri/r600/Makefile |9 -
2 files changed, 0 insertions(+), 18 deletions(-)
diff --git a/src/mesa/drivers/dri/r300/Makefile
b/src/mesa/drivers/dri/r300/Makefile
index 9f23a84..a0a00e0 100644
--- a/src/mesa/drivers/dri/r300/Makefile
+++ b/src/mesa/drivers/dri/r300/Makefile
@@ -11,15 +11,6 @@ ifeq ($(RADEON_LDFLAGS),)
CS_SOURCES = radeon_cs_space_drm.c radeon_bo.c radeon_cs.c
endif
-COMMON_SOURCES = \
- ../../common/driverfuncs.c \
- ../common/drirenderbuffer.c \
- ../common/utils.c \
- ../common/texmem.c \
- ../common/vblank.c \
- ../common/xmlconfig.c \
- ../common/dri_util.c
-
RADEON_COMMON_SOURCES = \
radeon_bo_legacy.c \
radeon_buffer_objects.c \
diff --git a/src/mesa/drivers/dri/r600/Makefile
b/src/mesa/drivers/dri/r600/Makefile
index bec0b5a..2adc352 100644
--- a/src/mesa/drivers/dri/r600/Makefile
+++ b/src/mesa/drivers/dri/r600/Makefile
@@ -11,15 +11,6 @@ ifeq ($(RADEON_LDFLAGS),)
CS_SOURCES = radeon_cs_space_drm.c radeon_bo.c radeon_cs.c
endif
-COMMON_SOURCES = \
- ../../common/driverfuncs.c \
- ../common/drirenderbuffer.c \
- ../common/utils.c \
- ../common/texmem.c \
- ../common/vblank.c \
- ../common/xmlconfig.c \
- ../common/dri_util.c
-
RADEON_COMMON_SOURCES = \
radeon_bo_legacy.c \
radeon_common_context.c \
___
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Mesa (master): make: Remove duplicate occurence of driverfuncs.c
Module: Mesa Branch: master Commit: e4a6ebdd87cbff4d6c23db2a8d220ce212093620 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e4a6ebdd87cbff4d6c23db2a8d220ce212093620 Author: Chad Versace c...@chad-versace.us Date: Thu Aug 25 20:32:13 2011 -0700 make: Remove duplicate occurence of driverfuncs.c driverfuncs.o is already contained in libmesa.a, so remove it from the following source lists: src/mesa/drivers/dri/Makefiles.defines:COMMON_SOURCES. src/mesa/drivers/dri/swrast/Makefile:SWRAST_COMMON_SOURCES Reviewed-by: Ian Romanick i...@freedesktop.org Signed-off-by: Chad Versace c...@chad-versace.us --- src/mesa/drivers/dri/Makefile.defines |1 - src/mesa/drivers/dri/swrast/Makefile |1 - 2 files changed, 0 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/Makefile.defines b/src/mesa/drivers/dri/Makefile.defines index 19b6de8..90ae551 100644 --- a/src/mesa/drivers/dri/Makefile.defines +++ b/src/mesa/drivers/dri/Makefile.defines @@ -7,7 +7,6 @@ COMMON_GALLIUM_SOURCES = \ ../common/xmlconfig.c COMMON_SOURCES = $(COMMON_GALLIUM_SOURCES) \ -../../common/driverfuncs.c \ ../common/texmem.c \ ../common/drirenderbuffer.c diff --git a/src/mesa/drivers/dri/swrast/Makefile b/src/mesa/drivers/dri/swrast/Makefile index 4cb99fd..509fa28 100644 --- a/src/mesa/drivers/dri/swrast/Makefile +++ b/src/mesa/drivers/dri/swrast/Makefile @@ -20,7 +20,6 @@ C_SOURCES = \ ASM_SOURCES = SWRAST_COMMON_SOURCES = \ - ../../common/driverfuncs.c \ ../common/utils.c \ ../common/drisw_util.c ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): make: Factor out source lists from drivers/dri/ common into Makefile.sources
Module: Mesa Branch: master Commit: 16f442e9d58cc50a40d1f85e90a13a909fc9cab1 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=16f442e9d58cc50a40d1f85e90a13a909fc9cab1 Author: Chad Versace c...@chad-versace.us Date: Thu Aug 25 17:55:42 2011 -0700 make: Factor out source lists from drivers/dri/common into Makefile.sources In order that the Autoconf and Android build can share the same source lists, move the lists from src/mesa/drivers/dri/Makefile.defines into src/mesa/drivers/dri/common/Makefile.sources I would like for Android to just reuse Makefile.defines, but the file is unsuitable for reuse. Reviewed-by: Chia-I Wu o...@lunarg.com Reviewed-by: Ian Romanick ian.d.roman...@intel.com Signed-off: Chad Versace c...@chad-versace.us --- src/mesa/drivers/dri/Makefile.defines| 20 +++- src/mesa/drivers/dri/common/Makefile.sources | 19 +++ 2 files changed, 26 insertions(+), 13 deletions(-) diff --git a/src/mesa/drivers/dri/Makefile.defines b/src/mesa/drivers/dri/Makefile.defines index 90ae551..6ff8df5 100644 --- a/src/mesa/drivers/dri/Makefile.defines +++ b/src/mesa/drivers/dri/Makefile.defines @@ -1,14 +1,13 @@ # -*-makefile-*- +# Import mesa_dri_common_* +include ../common/Makefile.sources + COMMON_GALLIUM_SOURCES = \ -../common/utils.c \ -../common/vblank.c \ -../common/dri_util.c \ -../common/xmlconfig.c + $(addprefix ../common/, $(mesa_dri_common_gallium_SOURCES)) -COMMON_SOURCES = $(COMMON_GALLIUM_SOURCES) \ -../common/texmem.c \ -../common/drirenderbuffer.c +COMMON_SOURCES = \ + $(addprefix ../common/, $(mesa_dri_common_SOURCES)) INCLUDES = $(SHARED_INCLUDES) $(EXPAT_INCLUDES) @@ -20,13 +19,8 @@ OBJECTS = $(C_SOURCES:.c=.o) \ ### Include directories SHARED_INCLUDES = \ -I. \ - -I$(TOP)/src/mesa/drivers/dri/common \ -Iserver \ - -I$(TOP)/include \ - -I$(TOP)/src/mapi \ - -I$(TOP)/src/mesa \ - -I$(TOP)/src/egl/main \ - -I$(TOP)/src/egl/drivers/dri \ + $(addprefix -I$(TOP)/, $(mesa_dri_common_INCLUDES)) \ $(LIBDRM_CFLAGS) INCLUDES += $(API_DEFINES) diff --git a/src/mesa/drivers/dri/common/Makefile.sources b/src/mesa/drivers/dri/common/Makefile.sources new file mode 100644 index 000..3432dda --- /dev/null +++ b/src/mesa/drivers/dri/common/Makefile.sources @@ -0,0 +1,19 @@ +mesa_dri_common_gallium_SOURCES := \ + utils.c \ + vblank.c \ + dri_util.c \ + xmlconfig.c + +mesa_dri_common_SOURCES := \ + $(mesa_dri_common_gallium_SOURCES) \ +texmem.c \ +drirenderbuffer.c + +# Paths are relative to MESA_TOP. +mesa_dri_common_INCLUDES := \ + include \ + src/egl/drivers/dri \ + src/egl/main \ + src/mapi \ + src/mesa \ + src/mesa/drivers/dri/common ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): mesa: Build libmesa_dricore.a for Android
Module: Mesa Branch: master Commit: 3758173149325a16d2044be01a70ad3b4fa7260d URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3758173149325a16d2044be01a70ad3b4fa7260d Author: Chad Versace c...@chad-versace.us Date: Fri Aug 26 13:29:20 2011 -0700 mesa: Build libmesa_dricore.a for Android libmesa_dricore.a is analogous to the libmesa.a built by the Autoconf build. Reviewed-by: Chia-I Wu o...@lunarg.com Signed-off-by: Chad Versace c...@chad-versace.us --- src/mesa/Android.mk | 29 + 1 files changed, 29 insertions(+), 0 deletions(-) diff --git a/src/mesa/Android.mk b/src/mesa/Android.mk index 67808d4..5f0f4af 100644 --- a/src/mesa/Android.mk +++ b/src/mesa/Android.mk @@ -83,6 +83,35 @@ include $(BUILD_STATIC_LIBRARY) endif # MESA_BUILD_GALLIUM # --- +# Build libmesa_dricore for DRI modules +# --- + +ifeq ($(strip $(MESA_BUILD_CLASSIC)),true) + +include $(CLEAR_VARS) + +LOCAL_MODULE := libmesa_dricore +LOCAL_MODULE_CLASS := STATIC_LIBRARIES + +LOCAL_CFLAGS := \ + $(common_CFLAGS) \ + -DFEATURE_GL=1 + +LOCAL_C_INCLUDES := \ + $(common_C_INCLUDES) + +LOCAL_SRC_FILES := \ +$(MESA_SOURCES) \ +$(MESA_CXX_SOURCES) \ +$(common_ASM) + +include $(LOCAL_PATH)/Android.gen.mk +include $(MESA_COMMON_MK) +include $(BUILD_STATIC_LIBRARY) + +endif # MESA_BUILD_CLASSIC + +# --- # Build libmesa_glsl_utils # # It is used to avoid circular dependency between core mesa and glsl. ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): make: Document imported variables
Module: Mesa Branch: master Commit: 05049e709efc1658ddd21047fba6081cbbdca6fe URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=05049e709efc1658ddd21047fba6081cbbdca6fe Author: Chad Versace c...@chad-versace.us Date: Fri Aug 26 15:48:29 2011 -0700 make: Document imported variables In src/mesa/Android.mk, it is non-trivial to determine which variables are imported by `include sources.mak`. So document them. Reviewed-by: Chia-I Wu o...@lunarg.com Signed-off-by: Chad Versace c...@chad-versace.us --- src/mesa/Android.mk |6 ++ 1 files changed, 6 insertions(+), 0 deletions(-) diff --git a/src/mesa/Android.mk b/src/mesa/Android.mk index 5f0f4af..f21ba3a 100644 --- a/src/mesa/Android.mk +++ b/src/mesa/Android.mk @@ -25,6 +25,12 @@ LOCAL_PATH := $(call my-dir) +# Import the following variables: +# MESA_CXX_SOURCES +# MESA_GALLIUM_CXX_SOURCES +# MESA_GALLIUM_SOURCES +# MESA_SOURCES +# X86_SOURCES include $(LOCAL_PATH)/sources.mak common_CFLAGS := \ ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): dri: Build libmesa_dri_common for Android
Module: Mesa Branch: master Commit: 34349d4431831e8e0ccfb8c149d2178630b780dd URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=34349d4431831e8e0ccfb8c149d2178630b780dd Author: Chad Versace c...@chad-versace.us Date: Fri Aug 26 16:00:33 2011 -0700 dri: Build libmesa_dri_common for Android libmesa_dri_common is a static library that contains the sources in src/mesa/drivers/dri/common. Each DRI driver should link to it. Reviewed-by: Chia-I Wu o...@lunarg.com Signed-off-by: Chad Versace c...@chad-versace.us --- Android.mk |4 ++- src/mesa/drivers/dri/Android.mk| 27 + src/mesa/drivers/dri/common/Android.mk | 41 3 files changed, 71 insertions(+), 1 deletions(-) diff --git a/Android.mk b/Android.mk index bc4b74e..2ad83a0 100644 --- a/Android.mk +++ b/Android.mk @@ -78,7 +78,9 @@ SUBDIRS := \ src/egl/main ifeq ($(strip $(MESA_BUILD_CLASSIC)),true) -SUBDIRS += src/egl/drivers/dri2 +SUBDIRS += \ + src/egl/drivers/dri2 \ + src/mesa/drivers/dri endif ifeq ($(strip $(MESA_BUILD_GALLIUM)),true) diff --git a/src/mesa/drivers/dri/Android.mk b/src/mesa/drivers/dri/Android.mk new file mode 100644 index 000..05b02cb --- /dev/null +++ b/src/mesa/drivers/dri/Android.mk @@ -0,0 +1,27 @@ +# +# Copyright (C) 2011 Intel Corporation +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the Software), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included +# in all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. +# + +LOCAL_PATH := $(call my-dir) + +SUBDIRS := common + +include $(foreach d, $(SUBDIRS), $(LOCAL_PATH)/$(d)/Android.mk) diff --git a/src/mesa/drivers/dri/common/Android.mk b/src/mesa/drivers/dri/common/Android.mk new file mode 100644 index 000..76464a1 --- /dev/null +++ b/src/mesa/drivers/dri/common/Android.mk @@ -0,0 +1,41 @@ +# +# Mesa 3-D graphics library +# +# Copyright (C) 2011 Intel Corporation +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the Software), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included +# in all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. +# + +# +# Build libmesa_dri_common +# + +LOCAL_PATH := $(call my-dir) +include $(CLEAR_VARS) + +include $(LOCAL_PATH)/Makefile.sources + +LOCAL_MODULE := libmesa_dri_common +LOCAL_MODULE_CLASS := STATIC_LIBRARIES + +LOCAL_C_INCLUDES := $(MESA_DRI_C_INCLUDES) +LOCAL_SRC_FILES := $(mesa_dri_common_SOURCES) + +include $(MESA_COMMON_MK) +include $(BUILD_STATIC_LIBRARY) ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Fix Android build by removing relative includes
Module: Mesa
Branch: master
Commit: 2f0edc60f4bd2ae5999a6afa656e3bb3f181bf0f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2f0edc60f4bd2ae5999a6afa656e3bb3f181bf0f
Author: Chad Versace c...@chad-versace.us
Date: Fri Aug 26 13:58:41 2011 -0700
i965: Fix Android build by removing relative includes
Replace each occurence of
#include ../glsl/*.h
with
#include glsl/*.h
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
Signed-off-by: Chad Versace c...@chad-versace.us
---
src/mesa/drivers/dri/i965/brw_clip.c |2 +-
src/mesa/drivers/dri/i965/brw_context.c|2 +-
.../drivers/dri/i965/brw_cubemap_normalize.cpp |4 ++--
src/mesa/drivers/dri/i965/brw_eu.c |2 +-
src/mesa/drivers/dri/i965/brw_eu_emit.c|2 +-
src/mesa/drivers/dri/i965/brw_fs.cpp |4 ++--
src/mesa/drivers/dri/i965/brw_fs.h |4 ++--
.../dri/i965/brw_fs_channel_expressions.cpp|6 +++---
src/mesa/drivers/dri/i965/brw_fs_emit.cpp |2 +-
src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp |6 +++---
.../dri/i965/brw_fs_schedule_instructions.cpp |6 +++---
.../drivers/dri/i965/brw_fs_vector_splitting.cpp | 10 +-
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp |6 +++---
src/mesa/drivers/dri/i965/brw_gs.c |2 +-
src/mesa/drivers/dri/i965/brw_program.c|2 +-
src/mesa/drivers/dri/i965/brw_sf.c |2 +-
src/mesa/drivers/dri/i965/brw_shader.cpp |4 ++--
src/mesa/drivers/dri/i965/brw_state_batch.c|2 +-
src/mesa/drivers/dri/i965/brw_vec4.h |2 +-
src/mesa/drivers/dri/i965/brw_vec4_emit.cpp|2 +-
.../drivers/dri/i965/brw_vec4_reg_allocate.cpp |2 +-
src/mesa/drivers/dri/i965/brw_vs.c |2 +-
src/mesa/drivers/dri/i965/brw_vtbl.c |2 +-
src/mesa/drivers/dri/i965/brw_wm.c |2 +-
24 files changed, 40 insertions(+), 40 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_clip.c
b/src/mesa/drivers/dri/i965/brw_clip.c
index d82206b..b49c9f4 100644
--- a/src/mesa/drivers/dri/i965/brw_clip.c
+++ b/src/mesa/drivers/dri/i965/brw_clip.c
@@ -42,7 +42,7 @@
#include brw_state.h
#include brw_clip.h
-#include ../glsl/ralloc.h
+#include glsl/ralloc.h
#define FRONT_UNFILLED_BIT 0x1
#define BACK_UNFILLED_BIT 0x2
diff --git a/src/mesa/drivers/dri/i965/brw_context.c
b/src/mesa/drivers/dri/i965/brw_context.c
index e00e248..898ad8a 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -40,7 +40,7 @@
#include brw_state.h
#include intel_span.h
#include tnl/t_pipeline.h
-#include ../glsl/ralloc.h
+#include glsl/ralloc.h
/***
* Mesa's Driver Functions
diff --git a/src/mesa/drivers/dri/i965/brw_cubemap_normalize.cpp
b/src/mesa/drivers/dri/i965/brw_cubemap_normalize.cpp
index 8574169..ff9485c 100644
--- a/src/mesa/drivers/dri/i965/brw_cubemap_normalize.cpp
+++ b/src/mesa/drivers/dri/i965/brw_cubemap_normalize.cpp
@@ -30,8 +30,8 @@
* \author Eric Anholt e...@anholt.net
*/
-#include ../glsl/glsl_types.h
-#include ../glsl/ir.h
+#include glsl/glsl_types.h
+#include glsl/ir.h
class brw_cubemap_normalize_visitor : public ir_hierarchical_visitor {
public:
diff --git a/src/mesa/drivers/dri/i965/brw_eu.c
b/src/mesa/drivers/dri/i965/brw_eu.c
index c1f2520..0e04af9 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.c
+++ b/src/mesa/drivers/dri/i965/brw_eu.c
@@ -34,7 +34,7 @@
#include brw_defines.h
#include brw_eu.h
-#include ../glsl/ralloc.h
+#include glsl/ralloc.h
/* Returns the corresponding conditional mod for swapping src0 and
* src1 in e.g. CMP.
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c
b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index c5013de..e8d0998 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -34,7 +34,7 @@
#include brw_defines.h
#include brw_eu.h
-#include ../glsl/ralloc.h
+#include glsl/ralloc.h
/***
* Internal helper for constructing instructions
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 0b0445e..8b85f3b 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -46,8 +46,8 @@ extern C {
}
#include brw_shader.h
#include brw_fs.h
-#include ../glsl/glsl_types.h
-#include ../glsl/ir_print_visitor.h
+#include glsl/glsl_types.h
+#include glsl/ir_print_visitor.h
#define MAX_INSTRUCTION (1 30)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
b/src/mesa/drivers/dri/i965/brw_fs.h
index a06949e..f3d8fbf 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -44,8 +44,8 @@ extern C {
#include brw_eu.h
#include brw_wm.h
}
-#include
Mesa (master): i965: Build i965_dri.so for Android
Module: Mesa Branch: master Commit: 1995d1e2070f8cda9e2ce489c694e0949749c8cb URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1995d1e2070f8cda9e2ce489c694e0949749c8cb Author: Chad Versace c...@chad-versace.us Date: Fri Aug 26 15:35:47 2011 -0700 i965: Build i965_dri.so for Android Compile tested only. Reviewed-by: Chia-I Wu o...@lunarg.com Signed-off-by: Chad Versace c...@chad-versace.us --- Android.mk |4 +- src/mesa/drivers/dri/Android.mk | 35 +++ src/mesa/drivers/dri/i965/Android.mk | 61 ++ 3 files changed, 98 insertions(+), 2 deletions(-) diff --git a/Android.mk b/Android.mk index 2ad83a0..7c7c55a 100644 --- a/Android.mk +++ b/Android.mk @@ -23,7 +23,7 @@ # BOARD_GPU_DRIVERS should be defined. The valid values are # -# classic drivers: +# classic drivers: i965 # gallium drivers: swrast i915g nouveau r300g r600g vmwgfx # # The main target is libGLES_mesa. For each classic driver enabled, a DRI @@ -36,7 +36,7 @@ MESA_PYTHON2 := python DRM_TOP := external/drm DRM_GRALLOC_TOP := hardware/drm_gralloc -classic_drivers := +classic_drivers := i965 gallium_drivers := swrast i915g nouveau r300g r600g vmwgfx MESA_GPU_DRIVERS := $(strip $(BOARD_GPU_DRIVERS)) diff --git a/src/mesa/drivers/dri/Android.mk b/src/mesa/drivers/dri/Android.mk index 05b02cb..b8ccd0c 100644 --- a/src/mesa/drivers/dri/Android.mk +++ b/src/mesa/drivers/dri/Android.mk @@ -22,6 +22,41 @@ LOCAL_PATH := $(call my-dir) +# Import mesa_dri_common_INCLUDES. +include $(LOCAL_PATH)/common/Makefile.sources + +#--- +# Variables common to all DRI drivers + +MESA_DRI_MODULE_PATH := $(TARGET_OUT_SHARED_LIBRARIES)/dri +MESA_DRI_MODULE_UNSTRIPPED_PATH := $(TARGET_OUT_SHARED_LIBRARIES_UNSTRIPPED)/dri + +MESA_DRI_C_INCLUDES := \ + $(addprefix $(MESA_TOP)/, $(mesa_dri_common_INCLUDES)) \ + $(DRM_TOP) \ + $(DRM_TOP)/include/drm \ + external/expat/lib + +MESA_DRI_WHOLE_STATIC_LIBRARIES := \ + libmesa_glsl \ + libmesa_dri_common \ + libmesa_dricore + +MESA_DRI_SHARED_LIBRARIES := \ + libcutils \ + libdl \ + libdrm \ + libexpat \ + libglapi \ + liblog + +#--- +# Build drivers and libmesa_dri_common + SUBDIRS := common +ifneq ($(filter i965, $(MESA_GPU_DRIVERS)),) + SUBDIRS += i965 +endif + include $(foreach d, $(SUBDIRS), $(LOCAL_PATH)/$(d)/Android.mk) diff --git a/src/mesa/drivers/dri/i965/Android.mk b/src/mesa/drivers/dri/i965/Android.mk new file mode 100644 index 000..2a289dd --- /dev/null +++ b/src/mesa/drivers/dri/i965/Android.mk @@ -0,0 +1,61 @@ +# +# Copyright (C) 2011 Intel Corporation +# Copyright (C) 2010-2011 Chia-I Wu olva...@gmail.com +# Copyright (C) 2010-2011 LunarG +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the Software), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included +# in all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. +# + +LOCAL_PATH := $(call my-dir) +include $(CLEAR_VARS) + +LOCAL_MODULE := i965_dri +LOCAL_MODULE_PATH := $(MESA_DRI_MODULE_PATH) +LOCAL_UNSTRIPPED_PATH := $(MESA_DRI_MODULE_UNSTRIPPED_PATH) + +# Import variables i965_*. +include $(LOCAL_PATH)/Makefile.sources + +# Overriding LOCAL_CC below is an ugly workaround. We cannot place -std=c99 +# in LOCAL_C_FLAGS because Android appends LOCAL_C_FLAGS to LOCAL_CPP_FLAGS. +LOCAL_CC := $(CC) -std=c99 + +LOCAL_C_FLAGS := \ + $(MESA_DRI_C_FLAGS) \ + -DI965 + +LOCAL_C_INCLUDES := \ + $(i965_INCLUDES) \ + $(MESA_DRI_C_INCLUDES) \ + $(DRM_TOP)/intel + +LOCAL_SRC_FILES := \ + $(i965_C_SOURCES) \ + $(i965_CXX_SOURCES) \ + $(i965_ASM_SOURCES) + +LOCAL_WHOLE_STATIC_LIBRARIES := \ + $(MESA_DRI_WHOLE_STATIC_LIBRARIES) + +LOCAL_SHARED_LIBRARIES := \ + $(MESA_DRI_SHARED_LIBRARIES) \ + libdrm_intel + +include $(MESA_COMMON_MK) +include $(BUILD_SHARED_LIBRARY) ___ mesa-commit mailing
Mesa (master): mesa: Add missing includes to meta.h
Module: Mesa
Branch: master
Commit: deff7fff494a04314fe9ad859029f0436bcc9e9f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=deff7fff494a04314fe9ad859029f0436bcc9e9f
Author: Chad Versace c...@chad-versace.us
Date: Thu Sep 22 11:04:40 2011 -0700
mesa: Add missing includes to meta.h
Include mtypes.h.
Signed-off-by: Chad Versace c...@chad-versace.us
---
src/mesa/drivers/common/meta.h |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/src/mesa/drivers/common/meta.h b/src/mesa/drivers/common/meta.h
index 9d634ae..3c91792 100644
--- a/src/mesa/drivers/common/meta.h
+++ b/src/mesa/drivers/common/meta.h
@@ -26,6 +26,8 @@
#ifndef META_H
#define META_H
+#include main/mtypes.h
+
/**
* \name Flags for meta operations
* \{
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Mesa (master): glsl: Fix Android build
Module: Mesa Branch: master Commit: 06ae4a62b1b3c668a5b50661df25d87f8c2679ef URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=06ae4a62b1b3c668a5b50661df25d87f8c2679ef Author: Chad Versace c...@chad-versace.us Date: Sat Sep 24 19:35:35 2011 -0700 glsl: Fix Android build Add lower_clip_distance.cpp to list of source files. Signed-off-by: Chad Versace c...@chad-versace.us --- src/glsl/Android.mk |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/src/glsl/Android.mk b/src/glsl/Android.mk index d0b3ff3..9bf4ff7 100644 --- a/src/glsl/Android.mk +++ b/src/glsl/Android.mk @@ -70,6 +70,7 @@ CXX_SOURCES = \ loop_analysis.cpp \ loop_controls.cpp \ loop_unroll.cpp \ + lower_clip_distance.cpp \ lower_discard.cpp \ lower_if_to_cond_assign.cpp \ lower_instructions.cpp \ ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): mesa: Allow override of GL version with environment variable
Module: Mesa
Branch: master
Commit: 0527c11d7aa42bd74f4527d7299e3c18f37c4c44
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0527c11d7aa42bd74f4527d7299e3c18f37c4c44
Author: Chad Versace c...@chad-versace.us
Date: Mon Sep 26 11:48:46 2011 -0700
mesa: Allow override of GL version with environment variable
It is necessary to manually set the GL version to 3.0 in order to run
Piglit tests that use glGetUniform*().
This patch allows one to override the version of the OpenGL context by
setting the environment variable MESA_GL_VERSION_OVERRIDE.
Reviewed-by: Brian Paul bri...@vmware.com
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
Signed-off-by: Chad Versace c...@chad-versace.us
---
docs/envvars.html |4
src/mesa/main/version.c | 25 +
2 files changed, 29 insertions(+), 0 deletions(-)
diff --git a/docs/envvars.html b/docs/envvars.html
index 986d2f8..6402ec5 100644
--- a/docs/envvars.html
+++ b/docs/envvars.html
@@ -58,6 +58,10 @@ copied into a fixed-size buffer without truncating.
If the extension string is too long, the buffer overrun can cause the game
to crash.
This is a work-around for that.
+liMESA_GL_VERSION_OVERRIDE - changes the value returned by
+glGetString(GL_VERSION). Valid values are point-separated version numbers,
+such as 3.0. Mesa will not really implement all the features of the given
+version if it's higher than what's normally reported.
liMESA_GLSL - a href=shading.html#envvarsshading language compiler
options/a
/ul
diff --git a/src/mesa/main/version.c b/src/mesa/main/version.c
index 3842814..a5deeab 100644
--- a/src/mesa/main/version.c
+++ b/src/mesa/main/version.c
@@ -27,7 +27,29 @@
#include version.h
#include git_sha1.h
+/**
+ * Override the context's GL version if the environment variable
+ * MESA_GL_VERSION_OVERRIDE is set. Valid values of MESA_GL_VERSION_OVERRIDE
+ * are point-separated version numbers, such as 3.0.
+ */
+static void
+override_version(struct gl_context *ctx, GLuint *major, GLuint *minor)
+{
+ const char *env_var = MESA_GL_VERSION_OVERRIDE;
+ const char *version;
+ int n;
+
+ version = getenv(env_var);
+ if (!version) {
+ return;
+ }
+ n = sscanf(version, %d.%d, major, minor);
+ if (n != 2) {
+ fprintf(stderr, error: invalid value for %s: %s\n, env_var, version);
+ return;
+ }
+}
/**
* Examine enabled GL extensions to determine GL version.
@@ -178,6 +200,9 @@ compute_version(struct gl_context *ctx)
ctx-VersionMajor = major;
ctx-VersionMinor = minor;
+
+ override_version(ctx, ctx-VersionMajor, ctx-VersionMinor);
+
ctx-VersionString = (char *) malloc(max);
if (ctx-VersionString) {
_mesa_snprintf(ctx-VersionString, max,
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Mesa (master): mesa: Allow overriding GLSL version with environment variable
Module: Mesa
Branch: master
Commit: a1eff5570f5e3f893fe4d453aef5ce143712ab09
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a1eff5570f5e3f893fe4d453aef5ce143712ab09
Author: Chad Versace c...@chad-versace.us
Date: Tue Sep 27 13:53:11 2011 -0700
mesa: Allow overriding GLSL version with environment variable
Override the context's GLSL version if the environment variable
MESA_GLSL_VERSION_OVERRIDE is set. Valid values for
MESA_GLSL_VERSION_OVERRIDE are integers, such as 130.
MESA_GLSL_VERSION_OVERRIDE has the same behavior as INTEL_GLSL_VERSION,
except that it applies to all drivers, not just Intel's. Since the former
supercedes the latter, this patch disables the latter.
Reviewed-by: Dave Airlie airl...@gmail.com
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
Signed-off-by: Chad Versace c...@chad-versace.us
---
docs/envvars.html |4
src/mesa/drivers/dri/intel/intel_extensions.c |3 ++-
src/mesa/drivers/dri/r600/r600_context.c |1 +
src/mesa/main/context.c |1 +
src/mesa/main/version.c | 24
src/mesa/main/version.h |2 ++
src/mesa/state_tracker/st_extensions.c|1 +
7 files changed, 35 insertions(+), 1 deletions(-)
diff --git a/docs/envvars.html b/docs/envvars.html
index 6402ec5..8c5c6ab 100644
--- a/docs/envvars.html
+++ b/docs/envvars.html
@@ -62,6 +62,10 @@ This is a work-around for that.
glGetString(GL_VERSION). Valid values are point-separated version numbers,
such as 3.0. Mesa will not really implement all the features of the given
version if it's higher than what's normally reported.
+liMESA_GLSL_VERSION_OVERRIDE - changes the value returned by
+glGetString(GL_SHADING_LANGUAGE_VERSION). Valid values are integers, such as
+130. Mesa will not really implement all the features of the given language
version
+if it's higher than what's normally reported. (for developers only)
liMESA_GLSL - a href=shading.html#envvarsshading language compiler
options/a
/ul
diff --git a/src/mesa/drivers/dri/intel/intel_extensions.c
b/src/mesa/drivers/dri/intel/intel_extensions.c
index 6ccd5b3..e9a36eb 100644
--- a/src/mesa/drivers/dri/intel/intel_extensions.c
+++ b/src/mesa/drivers/dri/intel/intel_extensions.c
@@ -112,7 +112,8 @@ intelInitExtensions(struct gl_context *ctx)
ctx-Extensions.OES_EGL_image = true;
#endif
- ctx-Const.GLSLVersion = get_glsl_version();
+ ctx-Const.GLSLVersion = 120;
+ _mesa_override_glsl_version(ctx);
if (intel-gen = 5)
ctx-Extensions.EXT_timer_query = true;
diff --git a/src/mesa/drivers/dri/r600/r600_context.c
b/src/mesa/drivers/dri/r600/r600_context.c
index 247d551..3e296ef 100644
--- a/src/mesa/drivers/dri/r600/r600_context.c
+++ b/src/mesa/drivers/dri/r600/r600_context.c
@@ -173,6 +173,7 @@ static void r600InitConstValues(struct gl_context *ctx,
radeonScreenPtr screen)
}
ctx-Const.GLSLVersion = 120;
+_mesa_override_glsl_version(ctx);
ctx-Const.MaxTextureImageUnits = 16;
/* 8 per clause on r6xx, 16 on r7xx
diff --git a/src/mesa/main/context.c b/src/mesa/main/context.c
index b20063c..2532c47 100644
--- a/src/mesa/main/context.c
+++ b/src/mesa/main/context.c
@@ -627,6 +627,7 @@ _mesa_init_constants(struct gl_context *ctx)
/* Shading language version */
if (ctx-API == API_OPENGL) {
ctx-Const.GLSLVersion = 120;
+ _mesa_override_glsl_version(ctx);
}
else if (ctx-API == API_OPENGLES2) {
ctx-Const.GLSLVersion = 100;
diff --git a/src/mesa/main/version.c b/src/mesa/main/version.c
index 00b423c..665b0e7 100644
--- a/src/mesa/main/version.c
+++ b/src/mesa/main/version.c
@@ -52,6 +52,30 @@ override_version(struct gl_context *ctx, GLuint *major,
GLuint *minor)
}
/**
+ * Override the context's GLSL version if the environment variable
+ * MESA_GLSL_VERSION_OVERRIDE is set. Valid values for
+ * MESA_GLSL_VERSION_OVERRIDE are integers, such as 130.
+ */
+void
+_mesa_override_glsl_version(struct gl_context *ctx)
+{
+ const char *env_var = MESA_GLSL_VERSION_OVERRIDE;
+ const char *version;
+ int n;
+
+ version = getenv(env_var);
+ if (!version) {
+ return;
+ }
+
+ n = sscanf(version, %d, ctx-Const.GLSLVersion);
+ if (n != 1) {
+ fprintf(stderr, error: invalid value for %s: %s\n, env_var, version);
+ return;
+ }
+}
+
+/**
* Examine enabled GL extensions to determine GL version.
* Return major and minor version numbers.
*/
diff --git a/src/mesa/main/version.h b/src/mesa/main/version.h
index 0a0512c..32e141f 100644
--- a/src/mesa/main/version.h
+++ b/src/mesa/main/version.h
@@ -56,5 +56,7 @@ struct gl_context;
extern void
_mesa_compute_version(struct gl_context *ctx);
+extern void
+_mesa_override_glsl_version(struct gl_context *ctx);
#endif /* VERSION_H */
diff --git a/src/mesa/state_tracker/st_extensions.c
b/src/mesa/state_tracker/st_extensions.c
index ef284ad..5506db6
Mesa (master): intel: Remove unused function get_glsl_version()
Module: Mesa
Branch: master
Commit: bb3e75d9a57a9d1a516d42487a6f0b4b23166f60
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bb3e75d9a57a9d1a516d42487a6f0b4b23166f60
Author: Chad Versace c...@chad-versace.us
Date: Tue Sep 27 13:56:49 2011 -0700
intel: Remove unused function get_glsl_version()
It was replaced by _mesa_override_glsl_version().
Reviewed-by: Dave Airlie airl...@gmail.com
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
Signed-off-by: Chad Versace c...@chad-versace.us
---
src/mesa/drivers/dri/intel/intel_extensions.c | 16
1 files changed, 0 insertions(+), 16 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_extensions.c
b/src/mesa/drivers/dri/intel/intel_extensions.c
index e9a36eb..104e096 100644
--- a/src/mesa/drivers/dri/intel/intel_extensions.c
+++ b/src/mesa/drivers/dri/intel/intel_extensions.c
@@ -33,22 +33,6 @@
#include utils.h
/**
- * \brief Get GLSL version from the environment.
- *
- * If the environment variable INTEL_GLSL_VERSION is set, convert its value
- * to an integer and return it. Otherwise, return the default version, 120.
- */
-static GLuint
-get_glsl_version()
-{
-const char * s = getenv(INTEL_GLSL_VERSION);
-if (s == NULL)
-return 120;
-else
-return (GLuint) atoi(s);
-}
-
-/**
* Initializes potential list of extensions if ctx == NULL, or actually enables
* extensions for a context.
*/
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Mesa (master): mesa: Remove unused tnl items from dd_functions
Module: Mesa
Branch: master
Commit: 9c72b729f34e1d544a66222c90561f93db6cb132
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9c72b729f34e1d544a66222c90561f93db6cb132
Author: Chad Versace c...@chad-versace.us
Date: Wed Sep 28 16:59:08 2011 -0700
mesa: Remove unused tnl items from dd_functions
Remove NeedValidate and ValidateTnlModule.
Reviewed-by: Eric Anholt e...@anholt.net
Signed-off-by: Chad Versace c...@chad-versace.us
---
src/mesa/drivers/common/driverfuncs.c |2 --
src/mesa/main/dd.h| 19 ---
2 files changed, 0 insertions(+), 21 deletions(-)
diff --git a/src/mesa/drivers/common/driverfuncs.c
b/src/mesa/drivers/common/driverfuncs.c
index 3e28969..33da934 100644
--- a/src/mesa/drivers/common/driverfuncs.c
+++ b/src/mesa/drivers/common/driverfuncs.c
@@ -200,8 +200,6 @@ _mesa_init_driver_functions(struct dd_function_table
*driver)
_mesa_init_sampler_object_functions(driver);
/* TL stuff */
- driver-NeedValidate = GL_FALSE;
- driver-ValidateTnlModule = NULL;
driver-CurrentExecPrimitive = 0;
driver-CurrentSavePrimitive = 0;
driver-NeedFlush = 0;
diff --git a/src/mesa/main/dd.h b/src/mesa/main/dd.h
index 91ecc0b..7875564 100644
--- a/src/mesa/main/dd.h
+++ b/src/mesa/main/dd.h
@@ -814,25 +814,6 @@ struct dd_function_table {
/*@{*/
/**
-* Bitmask of state changes that require the current TL module to be
-* validated, using ValidateTnlModule() below.
-*/
- GLuint NeedValidate;
-
- /**
-* Validate the current TL module.
-*
-* This is called directly after UpdateState() when a state change that has
-* occurred matches the dd_function_table::NeedValidate bitmask above. This
-* ensures all computed values are up to date, thus allowing the driver to
-* decide if the current TL module needs to be swapped out.
-*
-* This must be non-NULL if a driver installs a custom TL module and sets
-* the dd_function_table::NeedValidate bitmask, but may be NULL otherwise.
-*/
- void (*ValidateTnlModule)( struct gl_context *ctx, GLuint new_state );
-
- /**
* Set by the driver-supplied TL engine.
*
* Set to PRIM_OUTSIDE_BEGIN_END when outside glBegin()/glEnd().
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Mesa (master): i915, i830: Remove dead HiZ assertions in *update_draw_buffer ()
Module: Mesa
Branch: master
Commit: 53f858637319f0efa47dd9acdb547e7913f3f86b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=53f858637319f0efa47dd9acdb547e7913f3f86b
Author: Chad Versace c...@chad-versace.us
Date: Fri Oct 7 10:26:12 2011 -0700
i915,i830: Remove dead HiZ assertions in *update_draw_buffer()
i915 and i830 hardware doesn't have HiZ, so remove all HiZ related
assertions from *update_draw_buffer().
I've removed the dead format checks completely rather than replace them
with more appropriate checks. This doesn't reduce assertion coverage,
however, because when I added these HiZ related assertions in c8fdf66
there were no pre-existing checks there.
Signed-off-by: Chad Versace c...@chad-versace.us
---
src/mesa/drivers/dri/i915/i830_vtbl.c |2 --
src/mesa/drivers/dri/i915/i915_vtbl.c |2 --
2 files changed, 0 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i915/i830_vtbl.c
b/src/mesa/drivers/dri/i915/i830_vtbl.c
index 7810f56..e8045e3 100644
--- a/src/mesa/drivers/dri/i915/i830_vtbl.c
+++ b/src/mesa/drivers/dri/i915/i830_vtbl.c
@@ -715,7 +715,6 @@ i830_update_draw_buffer(struct intel_context *intel)
struct gl_framebuffer *fb = ctx-DrawBuffer;
struct intel_region *colorRegions[MAX_DRAW_BUFFERS], *depthRegion = NULL;
struct intel_renderbuffer *irbDepth = NULL, *irbStencil = NULL;
- bool fb_has_hiz = intel_framebuffer_has_hiz(fb);
if (!fb) {
/* this can happen during the initial context initialization */
@@ -792,7 +791,6 @@ i830_update_draw_buffer(struct intel_context *intel)
/* Check for depth fallback. */
if (irbDepth irbDepth-region) {
- assert(!fb_has_hiz || irbDepth-Base.Format != MESA_FORMAT_S8_Z24);
FALLBACK(intel, INTEL_FALLBACK_DEPTH_BUFFER, GL_FALSE);
depthRegion = irbDepth-region;
} else if (irbDepth !irbDepth-region) {
diff --git a/src/mesa/drivers/dri/i915/i915_vtbl.c
b/src/mesa/drivers/dri/i915/i915_vtbl.c
index 1e84c6d..e09c787 100644
--- a/src/mesa/drivers/dri/i915/i915_vtbl.c
+++ b/src/mesa/drivers/dri/i915/i915_vtbl.c
@@ -715,7 +715,6 @@ i915_update_draw_buffer(struct intel_context *intel)
struct gl_framebuffer *fb = ctx-DrawBuffer;
struct intel_region *colorRegion = NULL, *depthRegion = NULL;
struct intel_renderbuffer *irbDepth = NULL, *irbStencil = NULL;
- bool fb_has_hiz = intel_framebuffer_has_hiz(fb);
if (!fb) {
/* this can happen during the initial context initialization */
@@ -762,7 +761,6 @@ i915_update_draw_buffer(struct intel_context *intel)
/* Check for depth fallback. */
if (irbDepth irbDepth-region) {
- assert(!fb_has_hiz || irbDepth-Base.Format != MESA_FORMAT_S8_Z24);
FALLBACK(intel, INTEL_FALLBACK_DEPTH_BUFFER, GL_FALSE);
depthRegion = irbDepth-region;
} else if (irbDepth !irbDepth-region) {
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Mesa (master): mesa: Close Doxygen group
Module: Mesa
Branch: master
Commit: 2fae55666e298525fe3b5550aa2a2ebeea437710
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2fae55666e298525fe3b5550aa2a2ebeea437710
Author: Chad Versace c...@chad-versace.us
Date: Fri Oct 7 13:16:01 2011 -0700
mesa: Close Doxygen group
In dd_function_table, close the Doxygen group beginning with
\name Support for multiple TL engines
---
src/mesa/main/dd.h |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/src/mesa/main/dd.h b/src/mesa/main/dd.h
index 7875564..4e017ae 100644
--- a/src/mesa/main/dd.h
+++ b/src/mesa/main/dd.h
@@ -901,6 +901,7 @@ struct dd_function_table {
*/
void (*EndCallList)( struct gl_context *ctx );
+ /**@}*/
/**
* \name GL_ARB_sync interfaces
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Mesa (master): i965: Change type of brw_context. primitive from GLenum to hardware primitive
Module: Mesa
Branch: master
Commit: f378e8fea0e6bfda2018ee14a99757bde329e0a7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f378e8fea0e6bfda2018ee14a99757bde329e0a7
Author: Chad Versace c...@chad-versace.us
Date: Mon Sep 26 16:23:26 2011 -0700
i965: Change type of brw_context.primitive from GLenum to hardware primitive
For example, GL_TRIANLGES is converted to _3DPRIM_TRILIST.
The conversion is necessary because HiZ and MSAA resolve operations emit
a 3DPRIM_RECTLIST, which cannot be conveyed by GLenum.
As a consequence, brw_gs_prog_key.primitive is also converted.
v2
- [anholt] Split brw_set_prim into brw/gen6 variants in previous commit,
since not much code is really shared between the two.
- [anholt] Replace switch statements with table lookups, since this is
a hot path.
Reviewed-by: Eric Anholt e...@anho.net
Signed-off-by: Chad Versace c...@chad-versace.us
---
src/mesa/drivers/dri/i965/brw_context.h |2 +-
src/mesa/drivers/dri/i965/brw_draw.c| 43 ++
src/mesa/drivers/dri/i965/brw_gs.c | 37 +-
src/mesa/drivers/dri/i965/brw_gs.h |2 +-
4 files changed, 41 insertions(+), 43 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index b335954..bdad9fb 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -583,7 +583,7 @@ struct brw_query_object {
struct brw_context
{
struct intel_context intel; /** base class, must be first field */
- GLuint primitive;
+ GLuint primitive; /** Hardware primitive, such as _3DPRIM_TRILIST. */
GLboolean emit_state_always;
GLboolean has_surface_tile_offset;
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c
b/src/mesa/drivers/dri/i965/brw_draw.c
index 39d38a5..f58da55 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -79,53 +79,51 @@ static const GLenum reduced_prim[GL_POLYGON+1] = {
* programs be immune to the active primitive (ie. cope with all
* possibilities). That may not be realistic however.
*/
-static GLuint brw_set_prim(struct brw_context *brw,
- const struct _mesa_prim *prim)
+static void brw_set_prim(struct brw_context *brw,
+ const struct _mesa_prim *prim)
{
struct gl_context *ctx = brw-intel.ctx;
- GLenum mode = prim-mode;
+ uint32_t hw_prim = prim_to_hw_prim[prim-mode];
DBG(PRIM: %s\n, _mesa_lookup_enum_by_nr(prim-mode));
/* Slight optimization to avoid the GS program when not needed:
*/
- if (mode == GL_QUAD_STRIP
+ if (prim-mode == GL_QUAD_STRIP
ctx-Light.ShadeModel != GL_FLAT
ctx-Polygon.FrontMode == GL_FILL
ctx-Polygon.BackMode == GL_FILL)
- mode = GL_TRIANGLE_STRIP;
+ hw_prim = _3DPRIM_TRISTRIP;
if (prim-mode == GL_QUADS prim-count == 4
ctx-Light.ShadeModel != GL_FLAT
ctx-Polygon.FrontMode == GL_FILL
ctx-Polygon.BackMode == GL_FILL) {
- mode = GL_TRIANGLE_FAN;
+ hw_prim = _3DPRIM_TRIFAN;
}
- if (mode != brw-primitive) {
- brw-primitive = mode;
+ if (hw_prim != brw-primitive) {
+ brw-primitive = hw_prim;
brw-state.dirty.brw |= BRW_NEW_PRIMITIVE;
- if (reduced_prim[mode] != brw-intel.reduced_primitive) {
-brw-intel.reduced_primitive = reduced_prim[mode];
+ if (reduced_prim[prim-mode] != brw-intel.reduced_primitive) {
+brw-intel.reduced_primitive = reduced_prim[prim-mode];
brw-state.dirty.brw |= BRW_NEW_REDUCED_PRIMITIVE;
}
}
-
- return prim_to_hw_prim[mode];
}
-static GLuint gen6_set_prim(struct brw_context *brw,
-const struct _mesa_prim *prim)
+static void gen6_set_prim(struct brw_context *brw,
+ const struct _mesa_prim *prim)
{
+ uint32_t hw_prim = prim_to_hw_prim[prim-mode];
+
DBG(PRIM: %s\n, _mesa_lookup_enum_by_nr(prim-mode));
- if (prim-mode != brw-primitive) {
- brw-primitive = prim-mode;
+ if (hw_prim != brw-primitive) {
+ brw-primitive = hw_prim;
brw-state.dirty.brw |= BRW_NEW_PRIMITIVE;
}
-
- return prim_to_hw_prim[mode];
}
@@ -331,7 +329,6 @@ static GLboolean brw_try_draw_prims( struct gl_context *ctx,
intel_prepare_render(intel);
for (i = 0; i nr_prims; i++) {
- uint32_t hw_prim;
int estimated_max_prim_size;
estimated_max_prim_size = 512; /* batchbuffer commands */
@@ -349,9 +346,9 @@ static GLboolean brw_try_draw_prims( struct gl_context *ctx,
intel_batchbuffer_require_space(intel, estimated_max_prim_size, false);
if (intel-gen 6)
-hw_prim = brw_set_prim(brw, prim[i]);
+brw_set_prim(brw, prim[i]);
else
-hw_prim = gen6_set_prim(brw, prim[i]);
+gen6_set_prim(brw, prim[i]);
if (brw-state.dirty.brw) {
brw_validate_state(brw);
@@ -388,9
Mesa (master): i965: Split brw_set_prim into brw/gen6 variants
Module: Mesa
Branch: master
Commit: 9559ca600dde0877fe0abd04dd789bd5a3cdfbde
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9559ca600dde0877fe0abd04dd789bd5a3cdfbde
Author: Chad Versace c...@chad-versace.us
Date: Mon Sep 26 15:48:54 2011 -0700
i965: Split brw_set_prim into brw/gen6 variants
The slight optimization to avoid the GS program in brw_set_prim() is not
used by Gen 6, since Gen 6 doesn't use a GS program. Also, Gen 6 doesn't use
reduced primitives.
Also, document that intel_context.reduced_primitive is only used for Gen 6
Reviewed-by: Eric Anholt e...@anho.net
Signed-off-by: Chad Versace c...@chad-versace.us
---
src/mesa/drivers/dri/i965/brw_draw.c | 19 ++-
src/mesa/drivers/dri/intel/intel_context.h |2 +-
2 files changed, 19 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c
b/src/mesa/drivers/dri/i965/brw_draw.c
index bdb5b67..39d38a5 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -115,6 +115,19 @@ static GLuint brw_set_prim(struct brw_context *brw,
return prim_to_hw_prim[mode];
}
+static GLuint gen6_set_prim(struct brw_context *brw,
+const struct _mesa_prim *prim)
+{
+ DBG(PRIM: %s\n, _mesa_lookup_enum_by_nr(prim-mode));
+
+ if (prim-mode != brw-primitive) {
+ brw-primitive = prim-mode;
+ brw-state.dirty.brw |= BRW_NEW_PRIMITIVE;
+ }
+
+ return prim_to_hw_prim[mode];
+}
+
static GLuint trim(GLenum prim, GLuint length)
{
@@ -335,7 +348,11 @@ static GLboolean brw_try_draw_prims( struct gl_context
*ctx,
*/
intel_batchbuffer_require_space(intel, estimated_max_prim_size, false);
- hw_prim = brw_set_prim(brw, prim[i]);
+ if (intel-gen 6)
+hw_prim = brw_set_prim(brw, prim[i]);
+ else
+hw_prim = gen6_set_prim(brw, prim[i]);
+
if (brw-state.dirty.brw) {
brw_validate_state(brw);
diff --git a/src/mesa/drivers/dri/intel/intel_context.h
b/src/mesa/drivers/dri/intel/intel_context.h
index eb78c00..cf7ab9e 100644
--- a/src/mesa/drivers/dri/intel/intel_context.h
+++ b/src/mesa/drivers/dri/intel/intel_context.h
@@ -253,7 +253,7 @@ struct intel_context
GLuint RenderIndex;
GLmatrix ViewportMatrix;
GLenum render_primitive;
- GLenum reduced_primitive;
+ GLenum reduced_primitive; /* Only gen 6 */
GLuint vertex_size;
GLubyte *verts; /* points to tnl-clipspace.vertex_buf */
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