Mesa (master): intel: emit is_indexed_draw in the same VE than gl_DrawID

2018-05-02 Thread Antía Puentes Felpeto
Module: Mesa Branch: master Commit: 0cbf29fa5592b7feba6a307d597915cc07be828c URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0cbf29fa5592b7feba6a307d597915cc07be828c Author: Antia Puentes Date: Sat Apr 28 14:09:20 2018 +0200 intel: emit is_indexed_draw in the

Mesa (master): compiler/nir: Add conditional lowering for gl_BaseVertex

2018-05-02 Thread Antía Puentes Felpeto
Module: Mesa Branch: master Commit: 0fb204fac14cd2c7cf4a04f4060d4000bf5e3d35 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0fb204fac14cd2c7cf4a04f4060d4000bf5e3d35 Author: Antia Puentes Date: Sat Apr 28 14:09:21 2018 +0200 compiler/nir: Add conditional

Mesa (master): intel: activate the gl_BaseVertex lowering

2018-05-02 Thread Antía Puentes Felpeto
Module: Mesa Branch: master Commit: 3a1df14a7b5c1652aa72eb6cf43e69ab447c6273 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3a1df14a7b5c1652aa72eb6cf43e69ab447c6273 Author: Antia Puentes Date: Sat Apr 28 14:09:22 2018 +0200 intel: activate the gl_BaseVertex

Mesa (master): compiler: Add SYSTEM_VALUE_IS_INDEXED_DRAW and instrinsics

2018-05-02 Thread Antía Puentes Felpeto
Module: Mesa Branch: master Commit: 9e6b886cf25f88eea584d38c6763dbded99bd064 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9e6b886cf25f88eea584d38c6763dbded99bd064 Author: Antia Puentes Date: Sat Apr 28 14:09:18 2018 +0200 compiler: Add

Mesa (master): intel/compiler: Add uses_is_indexed_draw flag

2018-05-02 Thread Antía Puentes Felpeto
Module: Mesa Branch: master Commit: 6ba9088d9c692bfdafdf354ee96f662166582a79 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6ba9088d9c692bfdafdf354ee96f662166582a79 Author: Antia Puentes Date: Sat Apr 28 14:09:19 2018 +0200 intel/compiler: Add

Mesa (master): mesa: add missing RGB9_E5 format in _mesa_base_fbo_format

2018-02-23 Thread Antía Puentes Felpeto
Module: Mesa Branch: master Commit: e1623b303ccc7a880e34bddef7231dcf230826b3 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e1623b303ccc7a880e34bddef7231dcf230826b3 Author: Juan A. Suarez Romero Date: Mon Jan 15 10:58:50 2018 + mesa: add missing RGB9_E5

Mesa (master): Revert "mesa: add missing RGB9_E5 format in _mesa_base_fbo_format"

2018-01-31 Thread Antía Puentes Felpeto
Module: Mesa Branch: master Commit: 0da434fb47c19f3cbf0b2561ac9595a89fb236a1 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0da434fb47c19f3cbf0b2561ac9595a89fb236a1 Author: Antia Puentes Date: Fri Jan 26 12:10:30 2018 +0100 Revert "mesa: add missing RGB9_E5

Mesa (master): i965/gen8: Fix vertex attrib upload for dvec3/ 4 shader inputs

2016-11-01 Thread Antía Puentes Felpeto
Module: Mesa Branch: master Commit: 61a8a55f557784c8ec17fb1758775c6f18252201 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=61a8a55f557784c8ec17fb1758775c6f18252201 Author: Antia Puentes Date: Fri Oct 21 11:40:11 2016 +0200 i965/gen8: Fix vertex attrib upload

Mesa (master): i965: Fix calculation of the image height at start level

2016-09-10 Thread Antía Puentes Felpeto
Module: Mesa Branch: master Commit: 83e8617f4b13e75f44ba45dd156c0656a5e07b08 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=83e8617f4b13e75f44ba45dd156c0656a5e07b08 Author: Antia Puentes Date: Sat Sep 3 03:04:37 2016 +0200 i965: Fix calculation of the image

Mesa (master): glsl: use var with initializer on global var validation

2016-05-11 Thread Antía Puentes Felpeto
Module: Mesa Branch: master Commit: 9bea01899433ca6a8047b4172ffec6e89afe7625 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9bea01899433ca6a8047b4172ffec6e89afe7625 Author: Juan A. Suarez Romero Date: Wed May 11 13:48:18 2016 +0200 glsl: use var with

Mesa (master): i965/vec4: Don' t coalesce regs in Gen6 MATH ops if reswizzle/writemask needed

2015-09-23 Thread Antía Puentes Felpeto
Module: Mesa Branch: master Commit: f2e75ac88a92ab2180de576aca298929cfce03f2 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f2e75ac88a92ab2180de576aca298929cfce03f2 Author: Antia Puentes Date: Tue Sep 22 18:17:45 2015 +0200 i965/vec4: Don't coalesce regs in