Mesa (master): nir: Lower !f2b(x) to x == 0.0

[Ian Romanick]

Module: Mesa
Branch: master
Commit: f00fcfb7a2e137c7c0064b5e4167bb7fb49537a9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f00fcfb7a2e137c7c0064b5e4167bb7fb49537a9

Author: Ian Romanick 
Date:   Thu May 31 12:56:00 2018 -0700

nir: Lower !f2b(x) to x == 0.0

Some trivial help now, but it also prevents ~40 regressions caused by
Samuel's "nir: implement the GLSL equivalent of if simplication in
nir_opt_if" patch.

All Gen4+ platforms had similar results. (Skylake shown)
total instructions in shared programs: 14369557 -> 14369555 (<.01%)
instructions in affected programs: 442 -> 440 (-0.45%)
helped: 2
HURT: 0

total cycles in shared programs: 532425772 -> 532425743 (<.01%)
cycles in affected programs: 6086 -> 6057 (-0.48%)
helped: 2
HURT: 0

Signed-off-by: Ian Romanick 
Reviewed-by: Samuel Pitoiset 
Reviewed-by: Timothy Arceri 
Reviewed-by: Iago Toral Quiroga 

---

 src/compiler/nir/nir_opt_algebraic.py | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/compiler/nir/nir_opt_algebraic.py 
b/src/compiler/nir/nir_opt_algebraic.py
index f153570105..fdfb0250b0 100644
--- a/src/compiler/nir/nir_opt_algebraic.py
+++ b/src/compiler/nir/nir_opt_algebraic.py
@@ -441,6 +441,7 @@ optimizations = [
(('i2b', ('iabs', a)), ('i2b', a)),
(('fabs', ('b2f', a)), ('b2f', a)),
(('iabs', ('b2i', a)), ('b2i', a)),
+   (('inot', ('f2b', a)), ('feq', a, 0.0)),
 
# Packing and then unpacking does nothing
(('unpack_64_2x32_split_x', ('pack_64_2x32_split', a, b)), a),

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Mesa (master): nir: Add some missing "optimization undo" patterns

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 619c51722b7978366f15a03bec6751327f2b4b65
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=619c51722b7978366f15a03bec6751327f2b4b65

Author: Ian Romanick 
Date:   Wed May 30 18:06:57 2018 -0700

nir: Add some missing "optimization undo" patterns

d8d18516b0a and 03fb13f6467 added some patterns to undo conversions like

   (('ior', ('flt', a, b), ('flt', a, c)), ('flt', a, ('fmax', b, c)))

If further optimization cause some of the operands to either be the same
or be constants, undoing the transformation can lead to further savings.

I don't know why these patterns were not added in those patches.  I did
not check to see which specific patterns actually helped.  I just added
all of them for symmetry.  This prevents some loop unrolling regressions
Plane Shift caused by Samuel's "nir: implement the GLSL equivalent of if
simplication in nir_opt_if" patch.

Skylake and Broadwell had similar results. (Skylake shown)
total instructions in shared programs: 14369768 -> 14369557 (<.01%)
instructions in affected programs: 44076 -> 43865 (-0.48%)
helped: 141
HURT: 0
helped stats (abs) min: 1 max: 5 x̄: 1.50 x̃: 1
helped stats (rel) min: 0.07% max: 1.52% x̄: 0.66% x̃: 0.60%
95% mean confidence interval for instructions value: -1.67 -1.32
95% mean confidence interval for instructions %-change: -0.72% -0.59%
Instructions are helped.

total cycles in shared programs: 532430629 -> 532425772 (<.01%)
cycles in affected programs: 1170832 -> 1165975 (-0.41%)
helped: 101
HURT: 5
helped stats (abs) min: 1 max: 160 x̄: 48.54 x̃: 32
helped stats (rel) min: <.01% max: 8.49% x̄: 2.76% x̃: 2.03%
HURT stats (abs)   min: 2 max: 22 x̄: 9.20 x̃: 4
HURT stats (rel)   min: <.01% max: 0.05% x̄: 0.02% x̃: <.01%
95% mean confidence interval for cycles value: -53.64 -38.00
95% mean confidence interval for cycles %-change: -3.06% -2.20%
Cycles are helped.

Signed-off-by: Ian Romanick 
Reviewed-by: Samuel Pitoiset 
Reviewed-by: Timothy Arceri 

---

 src/compiler/nir/nir_opt_algebraic.py | 20 +++-
 1 file changed, 19 insertions(+), 1 deletion(-)

diff --git a/src/compiler/nir/nir_opt_algebraic.py 
b/src/compiler/nir/nir_opt_algebraic.py
index ba788f221a..f153570105 100644
--- a/src/compiler/nir/nir_opt_algebraic.py
+++ b/src/compiler/nir/nir_opt_algebraic.py
@@ -292,6 +292,8 @@ optimizations = [
(('~fge', ('fmax', a, b), a), True),
(('~flt', a, ('fmin', b, a)), False),
(('~flt', ('fmax', a, b), a), False),
+   (('~fge', a, ('fmax', b, a)), ('fge', a, b)),
+   (('~fge', ('fmin', a, b), a), ('fge', b, a)),
 
(('ilt', a, ('imax', b, a)), ('ilt', a, b)),
(('ilt', ('imin', a, b), a), ('ilt', b, a)),
@@ -301,7 +303,23 @@ optimizations = [
(('ult', ('umin', a, b), a), ('ult', b, a)),
(('uge', a, ('umin', b, a)), True),
(('uge', ('umax', a, b), a), True),
-
+   (('ilt', a, ('imin', b, a)), False),
+   (('ilt', ('imax', a, b), a), False),
+   (('ige', a, ('imax', b, a)), ('ige', a, b)),
+   (('ige', ('imin', a, b), a), ('ige', b, a)),
+   (('ult', a, ('umin', b, a)), False),
+   (('ult', ('umax', a, b), a), False),
+   (('uge', a, ('umax', b, a)), ('uge', a, b)),
+   (('uge', ('umin', a, b), a), ('uge', b, a)),
+
+   (('ilt', '#a', ('imax', '#b', c)), ('ior', ('ilt', a, b), ('ilt', a, c))),
+   (('ilt', ('imin', '#a', b), '#c'), ('ior', ('ilt', a, c), ('ilt', b, c))),
+   (('ige', '#a', ('imin', '#b', c)), ('ior', ('ige', a, b), ('ige', a, c))),
+   (('ige', ('imax', '#a', b), '#c'), ('ior', ('ige', a, c), ('ige', b, c))),
+   (('ult', '#a', ('umax', '#b', c)), ('ior', ('ult', a, b), ('ult', a, c))),
+   (('ult', ('umin', '#a', b), '#c'), ('ior', ('ult', a, c), ('ult', b, c))),
+   (('uge', '#a', ('umin', '#b', c)), ('ior', ('uge', a, b), ('uge', a, c))),
+   (('uge', ('umax', '#a', b), '#c'), ('ior', ('uge', a, c), ('uge', b, c))),
(('ilt', '#a', ('imin', '#b', c)), ('iand', ('ilt', a, b), ('ilt', a, c))),
(('ilt', ('imax', '#a', b), '#c'), ('iand', ('ilt', a, c), ('ilt', b, c))),
(('ige', '#a', ('imax', '#b', c)), ('iand', ('ige', a, b), ('ige', a, c))),

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Mesa (master): mesa: fix error handling in get_framebuffer_parameteriv

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 5ac16ed0476d9914927b8e7a592d8d7ac1589586
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5ac16ed0476d9914927b8e7a592d8d7ac1589586

Author: Rhys Perry <pendingchao...@gmail.com>
Date:   Fri May  4 23:27:51 2018 +0100

mesa: fix error handling in get_framebuffer_parameteriv

CC: <mesa-sta...@lists.freedesktop.org>
Signed-off-by: Rhys Perry <pendingchao...@gmail.com>
Reviewed-by: Tapani Pälli <tapani.pa...@intel.com>
Reviewed-by: Ian Romanick <ian.d.roman...@intel.com>

---

 src/mesa/main/fbobject.c | 72 +++-
 1 file changed, 41 insertions(+), 31 deletions(-)

diff --git a/src/mesa/main/fbobject.c b/src/mesa/main/fbobject.c
index c72204e11a..a63e8b8de5 100644
--- a/src/mesa/main/fbobject.c
+++ b/src/mesa/main/fbobject.c
@@ -1488,45 +1488,66 @@ _mesa_FramebufferParameteri(GLenum target, GLenum 
pname, GLint param)
 }
 
 static bool
-_pname_valid_for_default_framebuffer(struct gl_context *ctx,
- GLenum pname)
+validate_get_framebuffer_parameteriv_pname(struct gl_context *ctx,
+   struct gl_framebuffer *fb,
+   GLuint pname, const char *func)
 {
-   if (!_mesa_is_desktop_gl(ctx))
-  return false;
+   bool cannot_be_winsys_fbo = true;
 
switch (pname) {
+   case GL_FRAMEBUFFER_DEFAULT_LAYERS:
+  /*
+   * According to the OpenGL ES 3.1 specification section 9.2.3, the
+   * GL_FRAMEBUFFER_LAYERS parameter name is not supported.
+   */
+  if (_mesa_is_gles31(ctx) && !ctx->Extensions.OES_geometry_shader) {
+ _mesa_error(ctx, GL_INVALID_ENUM, "%s(pname=0x%x)", func, pname);
+ return false;
+  }
+  break;
+   case GL_FRAMEBUFFER_DEFAULT_WIDTH:
+   case GL_FRAMEBUFFER_DEFAULT_HEIGHT:
+   case GL_FRAMEBUFFER_DEFAULT_SAMPLES:
+   case GL_FRAMEBUFFER_DEFAULT_FIXED_SAMPLE_LOCATIONS:
+  break;
case GL_DOUBLEBUFFER:
case GL_IMPLEMENTATION_COLOR_READ_FORMAT:
case GL_IMPLEMENTATION_COLOR_READ_TYPE:
case GL_SAMPLES:
case GL_SAMPLE_BUFFERS:
case GL_STEREO:
-  return true;
+  /* From OpenGL 4.5 spec, section 9.2.3 "Framebuffer Object Queries:
+   *
+   *"An INVALID_OPERATION error is generated by 
GetFramebufferParameteriv
+   * if the default framebuffer is bound to target and pname is not one
+   * of the accepted values from table 23.73, other than
+   * SAMPLE_POSITION."
+   *
+   * For OpenGL ES, using default framebuffer raises INVALID_OPERATION
+   * for any pname.
+   */
+  cannot_be_winsys_fbo = !_mesa_is_desktop_gl(ctx);
+  break;
default:
+  _mesa_error(ctx, GL_INVALID_ENUM, "%s(pname=0x%x)", func, pname);
   return false;
}
+
+   if (cannot_be_winsys_fbo && _mesa_is_winsys_fbo(fb)) {
+  _mesa_error(ctx, GL_INVALID_OPERATION,
+  "%s(invalid pname=0x%x for default framebuffer)", func, 
pname);
+  return false;
+   }
+
+   return true;
 }
 
 static void
 get_framebuffer_parameteriv(struct gl_context *ctx, struct gl_framebuffer *fb,
 GLenum pname, GLint *params, const char *func)
 {
-   /* From OpenGL 4.5 spec, section 9.2.3 "Framebuffer Object Queries:
-*
-*"An INVALID_OPERATION error is generated by GetFramebufferParameteriv
-* if the default framebuffer is bound to target and pname is not one
-* of the accepted values from table 23.73, other than
-* SAMPLE_POSITION."
-*
-* For OpenGL ES, using default framebuffer still raises INVALID_OPERATION
-* for any pname.
-*/
-   if (_mesa_is_winsys_fbo(fb) &&
-   !_pname_valid_for_default_framebuffer(ctx, pname)) {
-  _mesa_error(ctx, GL_INVALID_OPERATION,
-  "%s(invalid pname=0x%x for default framebuffer)", func, 
pname);
+   if (!validate_get_framebuffer_parameteriv_pname(ctx, fb, pname, func))
   return;
-   }
 
switch (pname) {
case GL_FRAMEBUFFER_DEFAULT_WIDTH:
@@ -1536,14 +1557,6 @@ get_framebuffer_parameteriv(struct gl_context *ctx, 
struct gl_framebuffer *fb,
   *params = fb->DefaultGeometry.Height;
   break;
case GL_FRAMEBUFFER_DEFAULT_LAYERS:
-  /*
-   * According to the OpenGL ES 3.1 specification section 9.2.3, the
-   * GL_FRAMEBUFFER_LAYERS parameter name is not supported.
-   */
-  if (_mesa_is_gles31(ctx) && !ctx->Extensions.OES_geometry_shader) {
- _mesa_error(ctx, GL_INVALID_ENUM, "%s(pname=0x%x)", func, pname);
- break;
-  }
   *params = fb->DefaultGeometry.Layers;
   break;
case GL_FRAMEBUFFER_DEFAULT_SAMPLES:
@@ -1570,9 +1583,6 @@ get_framebuffer_parameteriv(struct gl_context *ctx, 
struct gl_framebuffer *fb,
case GL_STEREO:
  

Mesa (master): mesa: Silence an unused parameter warning

[Ian Romanick]

Module: Mesa
Branch: master
Commit: d350276b037b70b8d63023ad4f1411b8692a4b45
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d350276b037b70b8d63023ad4f1411b8692a4b45

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Mon May 22 15:21:00 2017 -0700

mesa: Silence an unused parameter warning

main/framebuffer.c: In function ‘update_color_draw_buffers’:
main/framebuffer.c:629:46: warning: unused parameter ‘ctx’ [-Wunused-parameter]
 update_color_draw_buffers(struct gl_context *ctx, struct gl_framebuffer *fb)
  ^~~

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>

---

 src/mesa/main/framebuffer.c | 9 -
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/src/mesa/main/framebuffer.c b/src/mesa/main/framebuffer.c
index 4ea18f6858..8e751b453b 100644
--- a/src/mesa/main/framebuffer.c
+++ b/src/mesa/main/framebuffer.c
@@ -549,7 +549,7 @@ _mesa_update_framebuffer_visual(struct gl_context *ctx,
  * writing colors.
  */
 static void
-update_color_draw_buffers(struct gl_context *ctx, struct gl_framebuffer *fb)
+update_color_draw_buffers(struct gl_framebuffer *fb)
 {
GLuint output;
 
@@ -573,9 +573,8 @@ update_color_draw_buffers(struct gl_context *ctx, struct 
gl_framebuffer *fb)
  * Unlike the DrawBuffer, we can only read from one (or zero) color buffers.
  */
 static void
-update_color_read_buffer(struct gl_context *ctx, struct gl_framebuffer *fb)
+update_color_read_buffer(struct gl_framebuffer *fb)
 {
-   (void) ctx;
if (fb->_ColorReadBufferIndex == BUFFER_NONE ||
fb->DeletePending ||
fb->Width == 0 ||
@@ -638,8 +637,8 @@ update_framebuffer(struct gl_context *ctx, struct 
gl_framebuffer *fb)
 * read-state if this FB is bound as ctx->DrawBuffer), but no
 * harm.
 */
-   update_color_draw_buffers(ctx, fb);
-   update_color_read_buffer(ctx, fb);
+   update_color_draw_buffers(fb);
+   update_color_read_buffer(fb);
 
compute_depth_max(fb);
 }

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Mesa (master): mesa: Add missing support for glFogiv(GL_FOG_DISTANCE_MODE_NV)

[Ian Romanick]

Module: Mesa
Branch: master
Commit: f2db3be6200410ffd269f8789f3c97292ce03b0f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f2db3be6200410ffd269f8789f3c97292ce03b0f

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Fri Jun 16 18:48:22 2017 -0700

mesa: Add missing support for glFogiv(GL_FOG_DISTANCE_MODE_NV)

Found by inspection, so I made a piglit test too.

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Cc: mesa-sta...@lists.freedesktop.org
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>

---

 src/mesa/main/fog.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mesa/main/fog.c b/src/mesa/main/fog.c
index c051aadded..0decf762a9 100644
--- a/src/mesa/main/fog.c
+++ b/src/mesa/main/fog.c
@@ -62,6 +62,7 @@ _mesa_Fogiv(GLenum pname, const GLint *params )
   case GL_FOG_END:
   case GL_FOG_INDEX:
   case GL_FOG_COORDINATE_SOURCE_EXT:
+  case GL_FOG_DISTANCE_MODE_NV:
 p[0] = (GLfloat) *params;
 break;
   case GL_FOG_COLOR:

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Mesa (master): i965: Enable NV_fog_distance

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 9d0bf720ed83fc4faf4682131057fc2a0b6e5938
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9d0bf720ed83fc4faf4682131057fc2a0b6e5938

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Fri Jun 16 19:15:56 2017 -0700

i965: Enable NV_fog_distance

With the previous fixes in place, it appears to just work.

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>

---

 src/mesa/drivers/dri/i965/intel_extensions.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c 
b/src/mesa/drivers/dri/i965/intel_extensions.c
index 73a6c73f53..e1e19217bc 100644
--- a/src/mesa/drivers/dri/i965/intel_extensions.c
+++ b/src/mesa/drivers/dri/i965/intel_extensions.c
@@ -122,6 +122,7 @@ intelInitExtensions(struct gl_context *ctx)
ctx->Extensions.ATI_texture_env_combine3 = true;
ctx->Extensions.MESA_pack_invert = true;
ctx->Extensions.NV_conditional_render = true;
+   ctx->Extensions.NV_fog_distance = true;
ctx->Extensions.NV_primitive_restart = true;
ctx->Extensions.NV_texture_barrier = true;
ctx->Extensions.NV_texture_env_combine4 = true;

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Mesa (master): r200: Enable NV_fog_distance

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 9a10a2fd5fc11ee08e8fa049f59fd129885cd332
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9a10a2fd5fc11ee08e8fa049f59fd129885cd332

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Sat Jun 17 18:56:13 2017 -0700

r200: Enable NV_fog_distance

With the previous fixes in place, it appears to just work.

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>

---

 src/mesa/drivers/dri/r200/r200_context.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mesa/drivers/dri/r200/r200_context.c 
b/src/mesa/drivers/dri/r200/r200_context.c
index 4524f06d10..9417dfc8a7 100644
--- a/src/mesa/drivers/dri/r200/r200_context.c
+++ b/src/mesa/drivers/dri/r200/r200_context.c
@@ -353,6 +353,7 @@ GLboolean r200CreateContext( gl_api api,
ctx->Extensions.EXT_texture_filter_anisotropic = true;
ctx->Extensions.EXT_texture_mirror_clamp = true;
ctx->Extensions.MESA_pack_invert = true;
+   ctx->Extensions.NV_fog_distance = true;
ctx->Extensions.NV_texture_rectangle = true;
ctx->Extensions.OES_EGL_image = true;
 

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Mesa (master): ffvertex: Don't try to read output registers in fog calculation

[Ian Romanick]

Module: Mesa
Branch: master
Commit: df80ffa4aaf18433d8e3e97b7cb86426a1e8654b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=df80ffa4aaf18433d8e3e97b7cb86426a1e8654b

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Fri Jun 16 19:02:48 2017 -0700

ffvertex: Don't try to read output registers in fog calculation

Gallium drivers use _mesa_remove_output_reads() via st_program to lower
output reads away.  It seems better to just generate the right thing in
the first place.

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>

---

 src/mesa/main/ffvertex_prog.c | 10 ++
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/src/mesa/main/ffvertex_prog.c b/src/mesa/main/ffvertex_prog.c
index 1c755592bd..dfb494bd8c 100644
--- a/src/mesa/main/ffvertex_prog.c
+++ b/src/mesa/main/ffvertex_prog.c
@@ -1297,12 +1297,14 @@ static void build_fog( struct tnl_program *p )
struct ureg input;
 
switch (p->state->fog_distance_mode) {
-   case FDM_EYE_RADIAL: /* Z = sqrt(Xe*Xe + Ye*Ye + Ze*Ze) */
+   case FDM_EYE_RADIAL: { /* Z = sqrt(Xe*Xe + Ye*Ye + Ze*Ze) */
+  struct ureg tmp = get_temp(p);
   input = get_eye_position(p);
-  emit_op2(p, OPCODE_DP3, fog, WRITEMASK_X, input, input);
-  emit_op1(p, OPCODE_RSQ, fog, WRITEMASK_X, fog);
-  emit_op1(p, OPCODE_RCP, fog, WRITEMASK_X, fog);
+  emit_op2(p, OPCODE_DP3, tmp, WRITEMASK_X, input, input);
+  emit_op1(p, OPCODE_RSQ, tmp, WRITEMASK_X, tmp);
+  emit_op1(p, OPCODE_RCP, fog, WRITEMASK_X, tmp);
   break;
+   }
case FDM_EYE_PLANE: /* Z = Ze */
   input = get_eye_position_z(p);
   emit_op1(p, OPCODE_MOV, fog, WRITEMASK_X, input);

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Mesa (master): mesa/main/readpix: Correct handling of packed floating point values

[Ian Romanick]

Module: Mesa
Branch: master
Commit: e695a35f40b085d524ccc9cc910dd49e1a864485
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e695a35f40b085d524ccc9cc910dd49e1a864485

Author: Gert Wollny <gert.wol...@collabora.com>
Date:   Fri Apr 27 18:04:01 2018 +0200

mesa/main/readpix: Correct handling of packed floating point values

Make sure that clamping in the pixel transfer operations is enabled/disabled
for packed floating point values just like it is done for single normal and
half precision floating point values.

This fixes a series of CTS tests with virgl that use r11f_g11f_b10f
buffers as target, and where virglrenderer reads these surfaces back
using the format GL_UNSIGNED_INT_10F_11F_11F_REV.

Signed-off-by: Gert Wollny <gert.wol...@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansi...@chromium.org>
Reviewed-by: Ian Romanick <ian.d.roman...@intel.com>

---

 src/mesa/main/readpix.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/mesa/main/readpix.c b/src/mesa/main/readpix.c
index a4eea3043d..c5fc66988b 100644
--- a/src/mesa/main/readpix.c
+++ b/src/mesa/main/readpix.c
@@ -106,7 +106,8 @@ _mesa_get_readpixels_transfer_ops(const struct gl_context 
*ctx,
   /* For blit-based ReadPixels packing, the clamping is done automatically
* unless the type is float. */
   if (_mesa_get_clamp_read_color(ctx, ctx->ReadBuffer) &&
-  (type == GL_FLOAT || type == GL_HALF_FLOAT)) {
+  (type == GL_FLOAT || type == GL_HALF_FLOAT ||
+   type == GL_UNSIGNED_INT_10F_11F_11F_REV)) {
  transferOps |= IMAGE_CLAMP_BIT;
   }
}
@@ -114,7 +115,8 @@ _mesa_get_readpixels_transfer_ops(const struct gl_context 
*ctx,
   /* For CPU-based ReadPixels packing, the clamping must always be done
* for non-float types, */
   if (_mesa_get_clamp_read_color(ctx, ctx->ReadBuffer) ||
-  (type != GL_FLOAT && type != GL_HALF_FLOAT)) {
+  (type != GL_FLOAT && type != GL_HALF_FLOAT &&
+   type != GL_UNSIGNED_INT_10F_11F_11F_REV)) {
  transferOps |= IMAGE_CLAMP_BIT;
   }
}

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Mesa (master): radeon: Use _mesa_is_front_buffer_drawing

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 0b3231966ffcba4188794924f6674cdde1ae2710
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0b3231966ffcba4188794924f6674cdde1ae2710

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Thu Sep 17 10:56:15 2015 -0400

radeon: Use _mesa_is_front_buffer_drawing

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Acked-by: Timothy Arceri <tarc...@itsqueeze.com>

---

 src/mesa/drivers/dri/radeon/radeon_common.c | 21 -
 src/mesa/drivers/dri/radeon/radeon_common.h |  1 -
 src/mesa/drivers/dri/radeon/radeon_screen.h |  1 -
 src/mesa/drivers/dri/radeon/radeon_span.c   |  7 +--
 4 files changed, 5 insertions(+), 25 deletions(-)

diff --git a/src/mesa/drivers/dri/radeon/radeon_common.c 
b/src/mesa/drivers/dri/radeon/radeon_common.c
index 6e4b4c4880..155d3a392c 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common.c
+++ b/src/mesa/drivers/dri/radeon/radeon_common.c
@@ -175,27 +175,6 @@ uint32_t radeonGetAge(radeonContextPtr radeon)
return age;
 }
 
-/**
- * Check if we're about to draw into the front color buffer.
- * If so, set the intel->front_buffer_dirty field to true.
- */
-void
-radeon_check_front_buffer_rendering(struct gl_context *ctx)
-{
-   radeonContextPtr radeon = RADEON_CONTEXT(ctx);
-   const struct gl_framebuffer *fb = ctx->DrawBuffer;
-
-   if (fb->Name == 0) {
-   /* drawing to window system buffer */
-   if (fb->_NumColorDrawBuffers > 0) {
-   if (fb->_ColorDrawBufferIndexes[0] == 
BUFFER_FRONT_LEFT) {
-   radeon->front_buffer_dirty = GL_TRUE;
-   }
-   }
-   }
-}
-
-
 void radeon_draw_buffer(struct gl_context *ctx, struct gl_framebuffer *fb)
 {
radeonContextPtr radeon = RADEON_CONTEXT(ctx);
diff --git a/src/mesa/drivers/dri/radeon/radeon_common.h 
b/src/mesa/drivers/dri/radeon/radeon_common.h
index fedaf5063a..ada4956066 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common.h
+++ b/src/mesa/drivers/dri/radeon/radeon_common.h
@@ -37,7 +37,6 @@ radeonReadPixels(struct gl_context * ctx,
GLenum format, GLenum type,
const struct gl_pixelstore_attrib *pack, GLvoid 
* pixels);
 
-void radeon_check_front_buffer_rendering(struct gl_context *ctx);
 static inline struct radeon_renderbuffer *radeon_renderbuffer(struct 
gl_renderbuffer *rb)
 {
struct radeon_renderbuffer *rrb = (struct radeon_renderbuffer *)rb;
diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.h 
b/src/mesa/drivers/dri/radeon/radeon_screen.h
index e70e334aba..efb2e6016b 100644
--- a/src/mesa/drivers/dri/radeon/radeon_screen.h
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.h
@@ -126,7 +126,6 @@ struct __DRIimageRec {
 #define radeon_prepare_render   r200_radeon_prepare_render
 #define radeonUnbindContext r200_radeonUnbindContext
 #define radeon_update_renderbuffers r200_radeon_update_renderbuffers
-#define radeon_check_front_buffer_rendering 
r200_radeon_check_front_buffer_rendering
 #define radeonCountStateEmitSizer200_radeonCountStateEmitSize
 #define radeon_draw_buffer  r200_radeon_draw_buffer
 #define radeonDrawBufferr200_radeonDrawBuffer
diff --git a/src/mesa/drivers/dri/radeon/radeon_span.c 
b/src/mesa/drivers/dri/radeon/radeon_span.c
index 42f62a0cb7..648df5cc14 100644
--- a/src/mesa/drivers/dri/radeon/radeon_span.c
+++ b/src/mesa/drivers/dri/radeon/radeon_span.c
@@ -44,6 +44,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 
SOFTWARE.
 #include "main/texformat.h"
 #include "main/renderbuffer.h"
 #include "main/samplerobj.h"
+#include "main/framebuffer.h"
 #include "swrast/swrast.h"
 #include "swrast/s_renderbuffer.h"
 
@@ -97,7 +98,8 @@ radeon_map_framebuffer(struct gl_context *ctx, struct 
gl_framebuffer *fb)
for (i = 0; i < BUFFER_COUNT; i++)
radeon_renderbuffer_map(ctx, fb->Attachment[i].Renderbuffer);
 
-   radeon_check_front_buffer_rendering(ctx);
+if (_mesa_is_front_buffer_drawing(fb))
+   RADEON_CONTEXT(ctx)->front_buffer_dirty = true;
 }
 
 static void
@@ -113,7 +115,8 @@ radeon_unmap_framebuffer(struct gl_context *ctx, struct 
gl_framebuffer *fb)
for (i = 0; i < BUFFER_COUNT; i++)
radeon_renderbuffer_unmap(ctx, fb->Attachment[i].Renderbuffer);
 
-   radeon_check_front_buffer_rendering(ctx);
+if (_mesa_is_front_buffer_drawing(fb))
+   RADEON_CONTEXT(ctx)->front_buffer_dirty = true;
 }
 
 static void radeonSpanRenderStart(struct gl_context * ctx)

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Mesa (master): radeon: Drop broken front_buffer_reading/drawing optimization

[Ian Romanick]

Module: Mesa
Branch: master
Commit: bf5e0276b6527fbcf51fd2af1769c83c25ec16e5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bf5e0276b6527fbcf51fd2af1769c83c25ec16e5

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Fri Sep 18 12:00:28 2015 -0400

radeon: Drop broken front_buffer_reading/drawing optimization

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Acked-by: Timothy Arceri <tarc...@itsqueeze.com>

---

 src/mesa/drivers/dri/radeon/radeon_common.c| 37 --
 .../drivers/dri/radeon/radeon_common_context.c | 10 +++---
 .../drivers/dri/radeon/radeon_common_context.h | 17 --
 3 files changed, 18 insertions(+), 46 deletions(-)

diff --git a/src/mesa/drivers/dri/radeon/radeon_common.c 
b/src/mesa/drivers/dri/radeon/radeon_common.c
index 155d3a392c..61cbf599f8 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common.c
+++ b/src/mesa/drivers/dri/radeon/radeon_common.c
@@ -323,22 +323,17 @@ void radeonDrawBuffer( struct gl_context *ctx, GLenum 
mode )
fprintf(stderr, "%s %s\n", __func__,
_mesa_enum_to_string( mode ));
 
-   if (_mesa_is_winsys_fbo(ctx->DrawBuffer)) {
+   if (_mesa_is_front_buffer_drawing(ctx->DrawBuffer)) {
radeonContextPtr radeon = RADEON_CONTEXT(ctx);
 
-   const GLboolean was_front_buffer_rendering =
-   radeon->is_front_buffer_rendering;
-
-   radeon->is_front_buffer_rendering = (mode == GL_FRONT_LEFT) ||
-(mode == GL_FRONT);
-
-  /* If we weren't front-buffer rendering before but we are now, make sure
-   * that the front-buffer has actually been allocated.
-   */
-   if (!was_front_buffer_rendering && 
radeon->is_front_buffer_rendering) {
-   radeon_update_renderbuffers(radeon->driContext,
-   radeon->driContext->driDrawablePriv, GL_FALSE);
-  }
+   /* If we might be front-buffer rendering on this buffer for
+* the first time, invalidate our DRI drawable so we'll ask
+* for new buffers (including the fake front) before we start
+* rendering again.
+*/
+   radeon_update_renderbuffers(radeon->driContext,
+   radeon->driContext->driDrawablePriv,
+   GL_FALSE);
}
 
radeon_draw_buffer(ctx, ctx->DrawBuffer);
@@ -346,16 +341,10 @@ void radeonDrawBuffer( struct gl_context *ctx, GLenum 
mode )
 
 void radeonReadBuffer( struct gl_context *ctx, GLenum mode )
 {
-   if (ctx->DrawBuffer && _mesa_is_winsys_fbo(ctx->DrawBuffer)) {
+   if (_mesa_is_front_buffer_reading(ctx->ReadBuffer)) {
struct radeon_context *const rmesa = RADEON_CONTEXT(ctx);
-   const GLboolean was_front_buffer_reading = 
rmesa->is_front_buffer_reading;
-   rmesa->is_front_buffer_reading = (mode == GL_FRONT_LEFT)
-   || (mode == GL_FRONT);
-
-   if (!was_front_buffer_reading && 
rmesa->is_front_buffer_reading) {
-   radeon_update_renderbuffers(rmesa->driContext,
-   
rmesa->driContext->driReadablePriv, GL_FALSE);
-   }
+   radeon_update_renderbuffers(rmesa->driContext,
+   rmesa->driContext->driReadablePriv, 
GL_FALSE);
}
/* nothing, until we implement h/w glRead/CopyPixels or CopyTexImage */
if (ctx->ReadBuffer == ctx->DrawBuffer) {
@@ -381,7 +370,7 @@ void radeon_viewport(struct gl_context *ctx)
void (*old_viewport)(struct gl_context *ctx);
 
if (_mesa_is_winsys_fbo(ctx->DrawBuffer)) {
-   if (radeon->is_front_buffer_rendering) {
+   if (_mesa_is_front_buffer_drawing(ctx->DrawBuffer)) {
ctx->Driver.Flush(ctx);
}
radeon_update_renderbuffers(driContext, 
driContext->driDrawablePriv, GL_FALSE);
diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.c 
b/src/mesa/drivers/dri/radeon/radeon_common_context.c
index 7e24f6d7f7..47719baa57 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common_context.c
+++ b/src/mesa/drivers/dri/radeon/radeon_common_context.c
@@ -352,7 +352,7 @@ void radeon_prepare_render(radeonContextPtr radeon)
  * that will happen next will probably dirty the front buffer.  So
  * mark it as dirty here.
  */
-if (radeon->is_front_buffer_rendering)
+if (_mesa_is_front_buffer_drawing(radeon->glCtx.DrawBuffer))
radeon->front_buffer_dirty = GL_TRUE;
 }
 
@@ -389,10 +389,10 @@ radeon_update_renderbuffers(__DRIcontext *con

Mesa (master): intel/compiler: Silence unused parameter warnings in empty vec4_instruction_scheduler methods

[Ian Romanick]

Module: Mesa
Branch: master
Commit: cd32a4e5f4239af79effcd907f1033fb4cde587c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cd32a4e5f4239af79effcd907f1033fb4cde587c

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Wed Mar 28 16:45:01 2018 -0700

intel/compiler: Silence unused parameter warnings in empty 
vec4_instruction_scheduler methods

src/intel/compiler/brw_schedule_instructions.cpp: In member function ‘virtual 
void vec4_instruction_scheduler::count_reads_remaining(backend_instruction*)’:
src/intel/compiler/brw_schedule_instructions.cpp:764:72: warning: unused 
parameter ‘be’ [-Wunused-parameter]
 vec4_instruction_scheduler::count_reads_remaining(backend_instruction *be)
^~
src/intel/compiler/brw_schedule_instructions.cpp: In member function ‘virtual 
void vec4_instruction_scheduler::setup_liveness(cfg_t*)’:
src/intel/compiler/brw_schedule_instructions.cpp:769:51: warning: unused 
parameter ‘cfg’ [-Wunused-parameter]
 vec4_instruction_scheduler::setup_liveness(cfg_t *cfg)
   ^~~
src/intel/compiler/brw_schedule_instructions.cpp: In member function ‘virtual 
void 
vec4_instruction_scheduler::update_register_pressure(backend_instruction*)’:
src/intel/compiler/brw_schedule_instructions.cpp:774:75: warning: unused 
parameter ‘be’ [-Wunused-parameter]
 vec4_instruction_scheduler::update_register_pressure(backend_instruction *be)
   ^~
src/intel/compiler/brw_schedule_instructions.cpp: In member function ‘virtual 
int 
vec4_instruction_scheduler::get_register_pressure_benefit(backend_instruction*)’:
src/intel/compiler/brw_schedule_instructions.cpp:779:80: warning: unused 
parameter ‘be’ [-Wunused-parameter]
 vec4_instruction_scheduler::get_register_pressure_benefit(backend_instruction 
*be)

^~
src/intel/compiler/brw_schedule_instructions.cpp: In member function ‘virtual 
int vec4_instruction_scheduler::issue_time(backend_instruction*)’:
src/intel/compiler/brw_schedule_instructions.cpp:1550:61: warning: unused 
parameter ‘inst’ [-Wunused-parameter]
 vec4_instruction_scheduler::issue_time(backend_instruction *inst)
 ^~~~

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>

---

 src/intel/compiler/brw_schedule_instructions.cpp | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/intel/compiler/brw_schedule_instructions.cpp 
b/src/intel/compiler/brw_schedule_instructions.cpp
index 0e793de4dd..fa85045de7 100644
--- a/src/intel/compiler/brw_schedule_instructions.cpp
+++ b/src/intel/compiler/brw_schedule_instructions.cpp
@@ -763,22 +763,22 @@ 
vec4_instruction_scheduler::vec4_instruction_scheduler(vec4_visitor *v,
 }
 
 void
-vec4_instruction_scheduler::count_reads_remaining(backend_instruction *be)
+vec4_instruction_scheduler::count_reads_remaining(backend_instruction *)
 {
 }
 
 void
-vec4_instruction_scheduler::setup_liveness(cfg_t *cfg)
+vec4_instruction_scheduler::setup_liveness(cfg_t *)
 {
 }
 
 void
-vec4_instruction_scheduler::update_register_pressure(backend_instruction *be)
+vec4_instruction_scheduler::update_register_pressure(backend_instruction *)
 {
 }
 
 int
-vec4_instruction_scheduler::get_register_pressure_benefit(backend_instruction 
*be)
+vec4_instruction_scheduler::get_register_pressure_benefit(backend_instruction 
*)
 {
return 0;
 }
@@ -1551,7 +1551,7 @@ fs_instruction_scheduler::issue_time(backend_instruction 
*inst)
 }
 
 int
-vec4_instruction_scheduler::issue_time(backend_instruction *inst)
+vec4_instruction_scheduler::issue_time(backend_instruction *)
 {
/* We always execute as two vec4s in parallel. */
return 2;

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Mesa (master): intel/compiler: Silence unused parameter warnings in generate_foo methods

[Ian Romanick]

Module: Mesa
Branch: master
Commit: d84b2ed1d71b9b65e48985d8b3030a3d7f01b60f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d84b2ed1d71b9b65e48985d8b3030a3d7f01b60f

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Wed Mar 28 16:29:45 2018 -0700

intel/compiler: Silence unused parameter warnings in generate_foo methods

Since all of the fs_generator::generate_foo methods take a fs_inst * as
the first parameter, just remove the name to quiet the compiler.

src/intel/compiler/brw_fs_generator.cpp: In member function ‘void 
fs_generator::generate_barrier(fs_inst*, brw_reg)’:
src/intel/compiler/brw_fs_generator.cpp:743:41: warning: unused parameter 
‘inst’ [-Wunused-parameter]
 fs_generator::generate_barrier(fs_inst *inst, struct brw_reg src)
 ^~~~
src/intel/compiler/brw_fs_generator.cpp: In member function ‘void 
fs_generator::generate_discard_jump(fs_inst*)’:
src/intel/compiler/brw_fs_generator.cpp:1326:46: warning: unused parameter 
‘inst’ [-Wunused-parameter]
 fs_generator::generate_discard_jump(fs_inst *inst)
  ^~~~
src/intel/compiler/brw_fs_generator.cpp: In member function ‘void 
fs_generator::generate_pack_half_2x16_split(fs_inst*, brw_reg, brw_reg, 
brw_reg)’:
src/intel/compiler/brw_fs_generator.cpp:1675:54: warning: unused parameter 
‘inst’ [-Wunused-parameter]
 fs_generator::generate_pack_half_2x16_split(fs_inst *inst,
  ^~~~
src/intel/compiler/brw_fs_generator.cpp: In member function ‘void 
fs_generator::generate_shader_time_add(fs_inst*, brw_reg, brw_reg, brw_reg)’:
src/intel/compiler/brw_fs_generator.cpp:1743:49: warning: unused parameter 
‘inst’ [-Wunused-parameter]
 fs_generator::generate_shader_time_add(fs_inst *inst,
 ^~~~
src/intel/compiler/brw_vec4_generator.cpp: In function ‘void 
generate_set_simd4x2_header_gen9(brw_codegen*, brw::vec4_instruction*, 
brw_reg)’:
src/intel/compiler/brw_vec4_generator.cpp:1412:52: warning: unused parameter 
‘inst’ [-Wunused-parameter]
  vec4_instruction *inst,
^~~~
src/intel/compiler/brw_vec4_generator.cpp: In function ‘void 
generate_mov_indirect(brw_codegen*, brw::vec4_instruction*, brw_reg, brw_reg, 
brw_reg, brw_reg)’:
src/intel/compiler/brw_vec4_generator.cpp:1430:41: warning: unused parameter 
‘inst’ [-Wunused-parameter]
   vec4_instruction *inst,
 ^~~~
src/intel/compiler/brw_vec4_generator.cpp:1432:63: warning: unused parameter 
‘length’ [-Wunused-parameter]
   struct brw_reg indirect, struct brw_reg length)
   ^~
Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>

---

 src/intel/compiler/brw_fs_generator.cpp   | 8 
 src/intel/compiler/brw_vec4_generator.cpp | 8 
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/src/intel/compiler/brw_fs_generator.cpp 
b/src/intel/compiler/brw_fs_generator.cpp
index 0c85eb8e1e..6d5306a0ee 100644
--- a/src/intel/compiler/brw_fs_generator.cpp
+++ b/src/intel/compiler/brw_fs_generator.cpp
@@ -740,7 +740,7 @@ fs_generator::generate_cs_terminate(fs_inst *inst, struct 
brw_reg payload)
 }
 
 void
-fs_generator::generate_barrier(fs_inst *inst, struct brw_reg src)
+fs_generator::generate_barrier(fs_inst *, struct brw_reg src)
 {
brw_barrier(p, src);
brw_WAIT(p);
@@ -1323,7 +1323,7 @@ fs_generator::generate_ddy(const fs_inst *inst,
 }
 
 void
-fs_generator::generate_discard_jump(fs_inst *inst)
+fs_generator::generate_discard_jump(fs_inst *)
 {
assert(devinfo->gen >= 6);
 
@@ -1672,7 +1672,7 @@ fs_generator::generate_set_sample_id(fs_inst *inst,
 }
 
 void
-fs_generator::generate_pack_half_2x16_split(fs_inst *inst,
+fs_generator::generate_pack_half_2x16_split(fs_inst *,
 struct brw_reg dst,
 struct brw_reg x,
 struct brw_reg y)
@@ -1740,7 +1740,7 @@ fs_generator::generate_unpack_half_2x16_split(fs_inst 
*inst,
 }
 
 void
-fs_generator::generate_shader_time_add(fs_inst *inst,
+fs_generator::generate_shader_time_add(fs_inst *,
struct brw_reg payload,
struct brw_reg offset,
struct brw_reg value)
diff --git a/src/intel/compiler/brw_vec4_generator.cpp 
b/src/intel/compiler/brw_vec4_generator.cpp
index a3ed8609a2..3d17ff9797 100644
--- a/src/intel/compiler/brw_vec4_generator.cpp
+++ b/src/intel/compiler/brw_vec4_generator.cpp
@@ -1409,7 +1409,7 @@ generate_pull_constant_load_gen7(struct brw_codegen *p,
 
 static void
 generate_set_si

Mesa (master): intel/compiler: Silence unused parameter warning in compile_cs_to_nir

[Ian Romanick]

Module: Mesa
Branch: master
Commit: bdb15c23440e8e40e2854c11a545846ee1eee1c8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bdb15c23440e8e40e2854c11a545846ee1eee1c8

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Wed Mar 28 16:35:10 2018 -0700

intel/compiler: Silence unused parameter warning in compile_cs_to_nir

src/intel/compiler/brw_fs.cpp: In function ‘nir_shader* compile_cs_to_nir(const 
brw_compiler*, void*, const brw_cs_prog_key*, brw_cs_prog_data*, const 
nir_shader*, unsigned int)’:
src/intel/compiler/brw_fs.cpp:7205:44: warning: unused parameter ‘prog_data’ 
[-Wunused-parameter]
   struct brw_cs_prog_data *prog_data,
^

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>

---

 src/intel/compiler/brw_fs.cpp | 7 +++
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 815650706c..b21996c168 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -7197,7 +7197,6 @@ static nir_shader *
 compile_cs_to_nir(const struct brw_compiler *compiler,
   void *mem_ctx,
   const struct brw_cs_prog_key *key,
-  struct brw_cs_prog_data *prog_data,
   const nir_shader *src_shader,
   unsigned dispatch_width)
 {
@@ -7238,7 +7237,7 @@ brw_compile_cs(const struct brw_compiler *compiler, void 
*log_data,
 */
if (min_dispatch_width <= 8) {
   nir_shader *nir8 = compile_cs_to_nir(compiler, mem_ctx, key,
-   prog_data, src_shader, 8);
+   src_shader, 8);
   v8 = new fs_visitor(compiler, log_data, mem_ctx, key, _data->base,
   NULL, /* Never used in core profile */
   nir8, 8, shader_time_index);
@@ -7259,7 +7258,7 @@ brw_compile_cs(const struct brw_compiler *compiler, void 
*log_data,
!fail_msg && min_dispatch_width <= 16) {
   /* Try a SIMD16 compile */
   nir_shader *nir16 = compile_cs_to_nir(compiler, mem_ctx, key,
-prog_data, src_shader, 16);
+src_shader, 16);
   v16 = new fs_visitor(compiler, log_data, mem_ctx, key, _data->base,
NULL, /* Never used in core profile */
nir16, 16, shader_time_index);
@@ -7292,7 +7291,7 @@ brw_compile_cs(const struct brw_compiler *compiler, void 
*log_data,
if (!fail_msg && (min_dispatch_width > 16 || (INTEL_DEBUG & DEBUG_DO32))) {
   /* Try a SIMD32 compile */
   nir_shader *nir32 = compile_cs_to_nir(compiler, mem_ctx, key,
-prog_data, src_shader, 32);
+src_shader, 32);
   v32 = new fs_visitor(compiler, log_data, mem_ctx, key, _data->base,
NULL, /* Never used in core profile */
nir32, 32, shader_time_index);

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Mesa (master): intel/compiler: Add scheduler deps for instructions that implicitly read g0

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 0d5ce25c1ca23abc6d91538f4374a18509091060
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0d5ce25c1ca23abc6d91538f4374a18509091060

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Mon Apr 16 16:32:41 2018 -0700

intel/compiler: Add scheduler deps for instructions that implicitly read g0

Otherwise the scheduler can move the writes after the reads.

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95009
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95012
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
Tested-by: Mark Janes <mark.a.ja...@intel.com>
Cc: Clayton A Craft <clayton.a.cr...@intel.com>
Cc: mesa-sta...@lists.freedesktop.org

---

 src/intel/compiler/brw_ir_vec4.h | 25 
 src/intel/compiler/brw_schedule_instructions.cpp |  3 +++
 2 files changed, 28 insertions(+)

diff --git a/src/intel/compiler/brw_ir_vec4.h b/src/intel/compiler/brw_ir_vec4.h
index 95c5119c6c..e401d8b4d1 100644
--- a/src/intel/compiler/brw_ir_vec4.h
+++ b/src/intel/compiler/brw_ir_vec4.h
@@ -334,6 +334,31 @@ public:
   opcode != BRW_OPCODE_IF &&
   opcode != BRW_OPCODE_WHILE));
}
+
+   bool reads_g0_implicitly() const
+   {
+  switch (opcode) {
+  case SHADER_OPCODE_TEX:
+  case SHADER_OPCODE_TXL:
+  case SHADER_OPCODE_TXD:
+  case SHADER_OPCODE_TXF:
+  case SHADER_OPCODE_TXF_CMS_W:
+  case SHADER_OPCODE_TXF_CMS:
+  case SHADER_OPCODE_TXF_MCS:
+  case SHADER_OPCODE_TXS:
+  case SHADER_OPCODE_TG4:
+  case SHADER_OPCODE_TG4_OFFSET:
+  case SHADER_OPCODE_SAMPLEINFO:
+  case VS_OPCODE_PULL_CONSTANT_LOAD:
+  case GS_OPCODE_SET_PRIMITIVE_ID:
+  case GS_OPCODE_GET_INSTANCE_ID:
+  case SHADER_OPCODE_GEN4_SCRATCH_READ:
+  case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
+ return true;
+  default:
+ return false;
+  }
+   }
 };
 
 /**
diff --git a/src/intel/compiler/brw_schedule_instructions.cpp 
b/src/intel/compiler/brw_schedule_instructions.cpp
index fa85045de7..f817142a8b 100644
--- a/src/intel/compiler/brw_schedule_instructions.cpp
+++ b/src/intel/compiler/brw_schedule_instructions.cpp
@@ -1267,6 +1267,9 @@ vec4_instruction_scheduler::calculate_deps()
  }
   }
 
+  if (inst->reads_g0_implicitly())
+ add_dep(last_fixed_grf_write, n);
+
   if (!inst->is_send_from_grf()) {
  for (int i = 0; i < inst->mlen; i++) {
 /* It looks like the MRF regs are released in the send

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Mesa (master): nir: Offset vertex_id by first_vertex instead of base_vertex

[Ian Romanick]

Module: Mesa
Branch: master
Commit: c366f422f0a68e6e440f419c506af24052159b6d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c366f422f0a68e6e440f419c506af24052159b6d

Author: Neil Roberts <nrobe...@igalia.com>
Date:   Thu Jan 25 19:15:43 2018 +0100

nir: Offset vertex_id by first_vertex instead of base_vertex

base_vertex will be zero for non-indexed calls and in that case we
need vertex_id to be offset by the ‘first’ parameter instead. That is
what we get with first_vertex. This is true for both GL and Vulkan.

The freedreno driver is also setting vertex_id_zero_based on
nir_options. In order to avoid breakage this patch switches the
relevant code to handle SYSTEM_VALUE_FIRST_VERTEX so that it can
retain the same behavior.

v2: change a3xx/fd3_emit.c and a4xx/fd4_emit.c from
SYSTEM_VALUE_BASE_VERTEX to SYSTEM_VALUE_FIRST_VERTEX (Kenneth).

Reviewed-by: Ian Romanick <ian.d.roman...@intel.com>
Cc: Rob Clark <robdcl...@gmail.com>
Acked-by: Marek Olšák <marek.ol...@amd.com>

---

 src/compiler/nir/nir_lower_system_values.c   | 2 +-
 src/gallium/drivers/freedreno/a3xx/fd3_emit.c| 2 +-
 src/gallium/drivers/freedreno/a4xx/fd4_emit.c| 2 +-
 src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c | 5 ++---
 src/intel/vulkan/genX_cmd_buffer.c   | 4 
 src/intel/vulkan/genX_pipeline.c | 4 +---
 6 files changed, 6 insertions(+), 13 deletions(-)

diff --git a/src/compiler/nir/nir_lower_system_values.c 
b/src/compiler/nir/nir_lower_system_values.c
index 40e0f85dee..47709e9887 100644
--- a/src/compiler/nir/nir_lower_system_values.c
+++ b/src/compiler/nir/nir_lower_system_values.c
@@ -115,7 +115,7 @@ convert_block(nir_block *block, nir_builder *b)
  if (b->shader->options->vertex_id_zero_based) {
 sysval = nir_iadd(b,
   nir_load_vertex_id_zero_base(b),
-  nir_load_base_vertex(b));
+  nir_load_first_vertex(b));
  } else {
 sysval = nir_load_vertex_id(b);
  }
diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_emit.c 
b/src/gallium/drivers/freedreno/a3xx/fd3_emit.c
index b9e1af00e2..3419ba86d4 100644
--- a/src/gallium/drivers/freedreno/a3xx/fd3_emit.c
+++ b/src/gallium/drivers/freedreno/a3xx/fd3_emit.c
@@ -374,7 +374,7 @@ fd3_emit_vertex_bufs(struct fd_ringbuffer *ring, struct 
fd3_emit *emit)
continue;
if (vp->inputs[i].sysval) {
switch(vp->inputs[i].slot) {
-   case SYSTEM_VALUE_BASE_VERTEX:
+   case SYSTEM_VALUE_FIRST_VERTEX:
/* handled elsewhere */
break;
case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE:
diff --git a/src/gallium/drivers/freedreno/a4xx/fd4_emit.c 
b/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
index 5fec2b6b08..42268ceea7 100644
--- a/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
+++ b/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
@@ -378,7 +378,7 @@ fd4_emit_vertex_bufs(struct fd_ringbuffer *ring, struct 
fd4_emit *emit)
continue;
if (vp->inputs[i].sysval) {
switch(vp->inputs[i].slot) {
-   case SYSTEM_VALUE_BASE_VERTEX:
+   case SYSTEM_VALUE_FIRST_VERTEX:
/* handled elsewhere */
break;
case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE:
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c 
b/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
index 174141b7fe..356d1bc44e 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
+++ b/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
@@ -2182,11 +2182,10 @@ emit_intrinsic(struct ir3_context *ctx, 
nir_intrinsic_instr *intr)
ctx->ir->outputs[n] = src[i];
}
break;
-   case nir_intrinsic_load_base_vertex:
+   case nir_intrinsic_load_first_vertex:
if (!ctx->basevertex) {
ctx->basevertex = create_driver_param(ctx, 
IR3_DP_VTXID_BASE);
-   add_sysval_input(ctx, SYSTEM_VALUE_BASE_VERTEX,
-   ctx->basevertex);
+   add_sysval_input(ctx, SYSTEM_VALUE_FIRST_VERTEX, 
ctx->basevertex);
}
dst[0] = ctx->basevertex;
break;
diff --git a/src/intel/vulkan/genX_cmd_buffer.c 
b/src/intel/vulkan/genX_cmd_buffer.c
index be4e9a6942..2882cf3650 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -2674,7 +2674,6 @@ void genX(CmdDraw)(
genX(cmd_buffer_flush_state)(cmd_buffer);
 
if (vs_prog_data->uses_firstvertex ||
-   vs_prog_data->uses_basevertex ||
 

Mesa (master): intel: Handle firstvertex in an identical way to BaseVertex

[Ian Romanick]

Module: Mesa
Branch: master
Commit: c32e1035cb4f1e0c2c1bd45611e3a35e7caf57b6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c32e1035cb4f1e0c2c1bd45611e3a35e7caf57b6

Author: Antia Puentes 
Date:   Thu Jan 25 19:15:40 2018 +0100

intel: Handle firstvertex in an identical way to BaseVertex

Until we set gl_BaseVertex to zero for non-indexed draw calls
both have an identical value.

The Vertex Elements are kept like that:
* VE 1: 
* VE 2: 

v2 (idr): Mark nir_intrinsic_load_first_vertex as "unreachable" in
emit_system_values_block and fs_visitor::nir_emit_vs_intrinsic.

---

 src/intel/compiler/brw_fs_nir.cpp |  4 
 src/intel/compiler/brw_nir.c  |  3 +++
 src/intel/compiler/brw_vec4.cpp   |  1 +
 src/mesa/drivers/dri/i965/brw_context.h   |  8 ++--
 src/mesa/drivers/dri/i965/brw_draw.c  | 14 +-
 src/mesa/drivers/dri/i965/brw_draw_upload.c   |  7 +--
 src/mesa/drivers/dri/i965/genX_state_upload.c | 11 +++
 7 files changed, 35 insertions(+), 13 deletions(-)

diff --git a/src/intel/compiler/brw_fs_nir.cpp 
b/src/intel/compiler/brw_fs_nir.cpp
index 6c4bcd1c11..a830bb9fcd 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -116,6 +116,7 @@ emit_system_values_block(nir_block *block, fs_visitor *v)
 
   case nir_intrinsic_load_vertex_id_zero_base:
   case nir_intrinsic_load_base_vertex:
+  case nir_intrinsic_load_first_vertex:
   case nir_intrinsic_load_instance_id:
   case nir_intrinsic_load_base_instance:
   case nir_intrinsic_load_draw_id:
@@ -2458,6 +2459,9 @@ fs_visitor::nir_emit_vs_intrinsic(const fs_builder ,
   break;
}
 
+   case nir_intrinsic_load_first_vertex:
+  unreachable("lowered by brw_nir_lower_vs_inputs");
+
default:
   nir_emit_intrinsic(bld, instr);
   break;
diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c
index 69ab162f88..16b0d86814 100644
--- a/src/intel/compiler/brw_nir.c
+++ b/src/intel/compiler/brw_nir.c
@@ -239,6 +239,7 @@ brw_nir_lower_vs_inputs(nir_shader *nir,
const bool has_sgvs =
   nir->info.system_values_read &
   (BITFIELD64_BIT(SYSTEM_VALUE_BASE_VERTEX) |
+   BITFIELD64_BIT(SYSTEM_VALUE_FIRST_VERTEX) |
BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE) |
BITFIELD64_BIT(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE) |
BITFIELD64_BIT(SYSTEM_VALUE_INSTANCE_ID));
@@ -261,6 +262,7 @@ brw_nir_lower_vs_inputs(nir_shader *nir,
 
 switch (intrin->intrinsic) {
 case nir_intrinsic_load_base_vertex:
+case nir_intrinsic_load_first_vertex:
 case nir_intrinsic_load_base_instance:
 case nir_intrinsic_load_vertex_id_zero_base:
 case nir_intrinsic_load_instance_id:
@@ -278,6 +280,7 @@ brw_nir_lower_vs_inputs(nir_shader *nir,
nir_intrinsic_set_base(load, num_inputs);
switch (intrin->intrinsic) {
case nir_intrinsic_load_base_vertex:
+   case nir_intrinsic_load_first_vertex:
   nir_intrinsic_set_component(load, 0);
   break;
case nir_intrinsic_load_base_instance:
diff --git a/src/intel/compiler/brw_vec4.cpp b/src/intel/compiler/brw_vec4.cpp
index 9459d61af6..1e384f5bf4 100644
--- a/src/intel/compiler/brw_vec4.cpp
+++ b/src/intel/compiler/brw_vec4.cpp
@@ -2826,6 +2826,7 @@ brw_compile_vs(const struct brw_compiler *compiler, void 
*log_data,
 */
if (shader->info.system_values_read &
(BITFIELD64_BIT(SYSTEM_VALUE_BASE_VERTEX) |
+BITFIELD64_BIT(SYSTEM_VALUE_FIRST_VERTEX) |
 BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE) |
 BITFIELD64_BIT(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE) |
 BITFIELD64_BIT(SYSTEM_VALUE_INSTANCE_ID))) {
diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
b/src/mesa/drivers/dri/i965/brw_context.h
index 6d42401918..cd76364542 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -887,8 +887,12 @@ struct brw_context
 
struct {
   struct {
- /** The value of gl_BaseVertex for the current _mesa_prim. */
- int gl_basevertex;
+ /**
+  * Either the value of gl_BaseVertex for indexed draw calls or the
+  * value of the argument  for non-indexed draw calls for the
+  * current _mesa_prim.
+  */
+ int firstvertex;
 
  /** The value of gl_BaseInstance for the current _mesa_prim. */
  int gl_baseinstance;
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c 
b/src/mesa/drivers/dri/i965/brw_draw.c
index 4caaadd560..f51f083178 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -819,25 +819,29 @@ brw_draw_single_prim(struct gl_context *ctx,
 * always flag if the shader uses one of the values. For direct draws,
 * we only flag if the values change.
 */
-   

Mesa (master): spirv: Lower BaseVertex to FIRST_VERTEX instead of BASE_VERTEX

[Ian Romanick]

Module: Mesa
Branch: master
Commit: c4f30a9100bfba7800162bdef267743a2419ec19
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c4f30a9100bfba7800162bdef267743a2419ec19

Author: Neil Roberts <nrobe...@igalia.com>
Date:   Thu Jan 25 19:15:41 2018 +0100

spirv: Lower BaseVertex to FIRST_VERTEX instead of BASE_VERTEX

The base vertex in Vulkan is different from GL in that for non-indexed
primitives the value is taken from the firstVertex parameter instead
of being set to zero. This coincides with the new SYSTEM_VALUE_FIRST_VERTEX
instead of BASE_VERTEX.

v2 (idr): Add comment describing why SYSTEM_VALUE_FIRST_VERTEX is used
for SpvBuiltInBaseVertex.  Suggested by Jason.

Reviewed-by: Ian Romanick <ian.d.roman...@intel.com> [v1]
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>

---

 src/compiler/spirv/vtn_variables.c |  5 -
 src/intel/vulkan/genX_cmd_buffer.c | 16 
 src/intel/vulkan/genX_pipeline.c   |  2 ++
 3 files changed, 18 insertions(+), 5 deletions(-)

diff --git a/src/compiler/spirv/vtn_variables.c 
b/src/compiler/spirv/vtn_variables.c
index 0673fe8067..9679ff6526 100644
--- a/src/compiler/spirv/vtn_variables.c
+++ b/src/compiler/spirv/vtn_variables.c
@@ -1296,7 +1296,10 @@ vtn_get_builtin_location(struct vtn_builder *b,
   set_mode_system_value(b, mode);
   break;
case SpvBuiltInBaseVertex:
-  *location = SYSTEM_VALUE_BASE_VERTEX;
+  /* OpenGL gl_BaseVertex (SYSTEM_VALUE_BASE_VERTEX) is not the same
+   * semantic as SPIR-V BaseVertex (SYSTEM_VALUE_FIRST_VERTEX).
+   */
+  *location = SYSTEM_VALUE_FIRST_VERTEX;
   set_mode_system_value(b, mode);
   break;
case SpvBuiltInBaseInstance:
diff --git a/src/intel/vulkan/genX_cmd_buffer.c 
b/src/intel/vulkan/genX_cmd_buffer.c
index cbe623802e..be4e9a6942 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -2673,7 +2673,9 @@ void genX(CmdDraw)(
 
genX(cmd_buffer_flush_state)(cmd_buffer);
 
-   if (vs_prog_data->uses_basevertex || vs_prog_data->uses_baseinstance)
+   if (vs_prog_data->uses_firstvertex ||
+   vs_prog_data->uses_basevertex ||
+   vs_prog_data->uses_baseinstance)
   emit_base_vertex_instance(cmd_buffer, firstVertex, firstInstance);
if (vs_prog_data->uses_drawid)
   emit_draw_index(cmd_buffer, 0);
@@ -2711,7 +2713,9 @@ void genX(CmdDrawIndexed)(
 
genX(cmd_buffer_flush_state)(cmd_buffer);
 
-   if (vs_prog_data->uses_basevertex || vs_prog_data->uses_baseinstance)
+   if (vs_prog_data->uses_firstvertex ||
+   vs_prog_data->uses_basevertex ||
+   vs_prog_data->uses_baseinstance)
   emit_base_vertex_instance(cmd_buffer, vertexOffset, firstInstance);
if (vs_prog_data->uses_drawid)
   emit_draw_index(cmd_buffer, 0);
@@ -2850,7 +2854,9 @@ void genX(CmdDrawIndirect)(
   struct anv_bo *bo = buffer->bo;
   uint32_t bo_offset = buffer->offset + offset;
 
-  if (vs_prog_data->uses_basevertex || vs_prog_data->uses_baseinstance)
+  if (vs_prog_data->uses_firstvertex ||
+  vs_prog_data->uses_basevertex ||
+  vs_prog_data->uses_baseinstance)
  emit_base_vertex_instance_bo(cmd_buffer, bo, bo_offset + 8);
   if (vs_prog_data->uses_drawid)
  emit_draw_index(cmd_buffer, i);
@@ -2889,7 +2895,9 @@ void genX(CmdDrawIndexedIndirect)(
   uint32_t bo_offset = buffer->offset + offset;
 
   /* TODO: We need to stomp base vertex to 0 somehow */
-  if (vs_prog_data->uses_basevertex || vs_prog_data->uses_baseinstance)
+  if (vs_prog_data->uses_firstvertex ||
+  vs_prog_data->uses_basevertex ||
+  vs_prog_data->uses_baseinstance)
  emit_base_vertex_instance_bo(cmd_buffer, bo, bo_offset + 12);
   if (vs_prog_data->uses_drawid)
  emit_draw_index(cmd_buffer, i);
diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c
index eb2d414735..a473f42c7e 100644
--- a/src/intel/vulkan/genX_pipeline.c
+++ b/src/intel/vulkan/genX_pipeline.c
@@ -98,6 +98,7 @@ emit_vertex_input(struct anv_pipeline *pipeline,
const bool needs_svgs_elem = vs_prog_data->uses_vertexid ||
 vs_prog_data->uses_instanceid ||
 vs_prog_data->uses_basevertex ||
+vs_prog_data->uses_firstvertex ||
 vs_prog_data->uses_baseinstance;
 
uint32_t elem_count = __builtin_popcount(elements) -
@@ -178,6 +179,7 @@ emit_vertex_input(struct anv_pipeline *pipeline,
* well.  Just do all or nothing.
*/
   uint32_t base_ctrl = (vs_prog_data->uses_basevertex ||
+vs_prog_data->uses_firstvertex ||
 vs_prog_data->uses_baseinstance) ?
VFCOMP_STORE_SRC : VFCOMP_STORE_0;
 

__

Mesa (master): intel/compiler: Add a uses_firstvertex flag

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 0c8395e15d295d328f68574e71afaf04596e2a82
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0c8395e15d295d328f68574e71afaf04596e2a82

Author: Neil Roberts 
Date:   Thu Jan 25 19:15:39 2018 +0100

intel/compiler: Add a uses_firstvertex flag

Reviewed-by: Kenneth Graunke 

---

 src/intel/compiler/brw_compiler.h | 1 +
 src/intel/compiler/brw_vec4.cpp   | 4 
 2 files changed, 5 insertions(+)

diff --git a/src/intel/compiler/brw_compiler.h 
b/src/intel/compiler/brw_compiler.h
index 875b2936fd..24196248b8 100644
--- a/src/intel/compiler/brw_compiler.h
+++ b/src/intel/compiler/brw_compiler.h
@@ -978,6 +978,7 @@ struct brw_vs_prog_data {
bool uses_vertexid;
bool uses_instanceid;
bool uses_basevertex;
+   bool uses_firstvertex;
bool uses_baseinstance;
bool uses_drawid;
 };
diff --git a/src/intel/compiler/brw_vec4.cpp b/src/intel/compiler/brw_vec4.cpp
index 218925ccb1..9459d61af6 100644
--- a/src/intel/compiler/brw_vec4.cpp
+++ b/src/intel/compiler/brw_vec4.cpp
@@ -2837,6 +2837,10 @@ brw_compile_vs(const struct brw_compiler *compiler, void 
*log_data,
   prog_data->uses_basevertex = true;
 
if (shader->info.system_values_read &
+   BITFIELD64_BIT(SYSTEM_VALUE_FIRST_VERTEX))
+  prog_data->uses_firstvertex = true;
+
+   if (shader->info.system_values_read &
BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE))
   prog_data->uses_baseinstance = true;
 

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Mesa (master): compiler: Add SYSTEM_VALUE_FIRST_VERTEX and instrinsics

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 5ff848df7be34bdc4c2e0ad509ad43b4ae1fc3b9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5ff848df7be34bdc4c2e0ad509ad43b4ae1fc3b9

Author: Antia Puentes 
Date:   Thu Jan 25 19:15:38 2018 +0100

compiler: Add SYSTEM_VALUE_FIRST_VERTEX and instrinsics

This VS system value will contain the value passed as  for
indexed draw calls or the value passed as  for non-indexed draw
calls. It can be used to calculate the gl_VertexID as
SYSTEM_VALUE_VERTEX_ID_ZERO_BASE plus SYSTEM_VALUE_FIRST_VERTEX.

From the OpenGL 4.6 spec, 10.4 "Drawing Commands Using Vertex Arrays":

-  Page 352:
"The index of any element transferred to the GL by DrawArraysOneInstance
is referred to as its vertex ID, and may be read by a vertex shader as
gl_VertexID.  The vertex ID of the ith element transferred is first +
i."

- Page 355:
"The index of any element transferred to the GL by
DrawElementsOneInstance is referred to as its vertex ID, and may be read
by a vertex shader as gl_VertexID.  The vertex ID of the ith element
transferred is the sum of basevertex and the value stored in the
currently bound element array buffer at offset indices + i."

Currently the gl_VertexID calculation uses SYSTEM_VALUE_BASE_VERTEX but
this will have to change when the value of gl_BaseVertex is
fixed. Currently its value is broken for non-indexed draw calls because
it must be zero but we are setting it to .

v2: use SYSTEM_VALUE_FIRST_VERTEX as name for the value, instead of
SYSTEM_VALUE_BASE_VERTEX_ID (Kenneth).

v3 (idr): Rebase on Rob Clark converting nir_intrinsics.h to be
generated.  Reformat commit message to 72 columns.

Reviewed-by: Neil Roberts 
Reviewed-by: Kenneth Graunke 

---

 src/compiler/nir/nir.c |  4 
 src/compiler/nir/nir_gather_info.c |  1 +
 src/compiler/nir/nir_intrinsics.py |  1 +
 src/compiler/shader_enums.c|  1 +
 src/compiler/shader_enums.h| 14 ++
 5 files changed, 21 insertions(+)

diff --git a/src/compiler/nir/nir.c b/src/compiler/nir/nir.c
index ef911540f3..ea28fbd1af 100644
--- a/src/compiler/nir/nir.c
+++ b/src/compiler/nir/nir.c
@@ -1991,6 +1991,8 @@ nir_intrinsic_from_system_value(gl_system_value val)
   return nir_intrinsic_load_base_instance;
case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE:
   return nir_intrinsic_load_vertex_id_zero_base;
+   case SYSTEM_VALUE_FIRST_VERTEX:
+  return nir_intrinsic_load_first_vertex;
case SYSTEM_VALUE_BASE_VERTEX:
   return nir_intrinsic_load_base_vertex;
case SYSTEM_VALUE_INVOCATION_ID:
@@ -2066,6 +2068,8 @@ nir_system_value_from_intrinsic(nir_intrinsic_op intrin)
   return SYSTEM_VALUE_BASE_INSTANCE;
case nir_intrinsic_load_vertex_id_zero_base:
   return SYSTEM_VALUE_VERTEX_ID_ZERO_BASE;
+   case nir_intrinsic_load_first_vertex:
+  return SYSTEM_VALUE_FIRST_VERTEX;
case nir_intrinsic_load_base_vertex:
   return SYSTEM_VALUE_BASE_VERTEX;
case nir_intrinsic_load_invocation_id:
diff --git a/src/compiler/nir/nir_gather_info.c 
b/src/compiler/nir/nir_gather_info.c
index eaf0ca68b0..a6a699ab25 100644
--- a/src/compiler/nir/nir_gather_info.c
+++ b/src/compiler/nir/nir_gather_info.c
@@ -265,6 +265,7 @@ gather_intrinsic_info(nir_intrinsic_instr *instr, 
nir_shader *shader)
case nir_intrinsic_load_vertex_id:
case nir_intrinsic_load_vertex_id_zero_base:
case nir_intrinsic_load_base_vertex:
+   case nir_intrinsic_load_first_vertex:
case nir_intrinsic_load_base_instance:
case nir_intrinsic_load_instance_id:
case nir_intrinsic_load_sample_id:
diff --git a/src/compiler/nir/nir_intrinsics.py 
b/src/compiler/nir/nir_intrinsics.py
index 1bc99552cd..f26aaf35ee 100644
--- a/src/compiler/nir/nir_intrinsics.py
+++ b/src/compiler/nir/nir_intrinsics.py
@@ -413,6 +413,7 @@ system_value("frag_coord", 4)
 system_value("front_face", 1)
 system_value("vertex_id", 1)
 system_value("vertex_id_zero_base", 1)
+system_value("first_vertex", 1)
 system_value("base_vertex", 1)
 system_value("instance_id", 1)
 system_value("base_instance", 1)
diff --git a/src/compiler/shader_enums.c b/src/compiler/shader_enums.c
index d0ff11b41e..ebee076b43 100644
--- a/src/compiler/shader_enums.c
+++ b/src/compiler/shader_enums.c
@@ -216,6 +216,7 @@ gl_system_value_name(gl_system_value sysval)
  ENUM(SYSTEM_VALUE_INSTANCE_ID),
  ENUM(SYSTEM_VALUE_INSTANCE_INDEX),
  ENUM(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE),
+ ENUM(SYSTEM_VALUE_FIRST_VERTEX),
  ENUM(SYSTEM_VALUE_BASE_VERTEX),
  ENUM(SYSTEM_VALUE_BASE_INSTANCE),
  ENUM(SYSTEM_VALUE_DRAW_ID),
diff --git a/src/compiler/shader_enums.h b/src/compiler/shader_enums.h
index 2aedbb9b3f..8a277a14f2 100644
--- a/src/compiler/shader_enums.h
+++ b/src/compiler/shader_enums.h
@@ -504,6 +504,20 @@ typedef enum
SYSTEM_VALUE_BASE_VERTEX,
 
/**
+* Depending on the type of the draw call (indexed or non-indexed),
+* is the value of \c basevertex 

Mesa (master): mesa: Silence unused parameter warning in compressedteximage_only_format

[Ian Romanick]

Module: Mesa
Branch: master
Commit: fa44941072cb43c14c749cc991a7e4001c57f5ca
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fa44941072cb43c14c749cc991a7e4001c57f5ca

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Tue Feb 27 11:24:44 2018 -0800

mesa: Silence unused parameter warning in compressedteximage_only_format

Passing ctx to compressedteximage_only_format was the only use of the
ctx parameter in _mesa_format_no_online_compression, so that parameter
had to go too.

../../SOURCE/master/src/mesa/main/teximage.c: In function 
‘compressedteximage_only_format’:
../../SOURCE/master/src/mesa/main/teximage.c:1355:57: warning: unused parameter 
‘ctx’ [-Wunused-parameter]
 compressedteximage_only_format(const struct gl_context *ctx, GLenum format)
 ^~~

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Brian Paul <bri...@vmware.com>

---

 src/mesa/main/formatquery.c |  2 +-
 src/mesa/main/teximage.c| 16 
 src/mesa/main/teximage.h|  2 +-
 3 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/src/mesa/main/formatquery.c b/src/mesa/main/formatquery.c
index 834f8e..3b000fac5c 100644
--- a/src/mesa/main/formatquery.c
+++ b/src/mesa/main/formatquery.c
@@ -502,7 +502,7 @@ _is_resource_supported(struct gl_context *ctx, GLenum 
target,
   /* additional checks for compressed textures */
   if (_mesa_is_compressed_format(ctx, internalformat) &&
   (!_mesa_target_can_be_compressed(ctx, target, internalformat, NULL) 
||
-   _mesa_format_no_online_compression(ctx, internalformat)))
+   _mesa_format_no_online_compression(internalformat)))
  return false;
 
   break;
diff --git a/src/mesa/main/teximage.c b/src/mesa/main/teximage.c
index f560512fb4..bec1274f39 100644
--- a/src/mesa/main/teximage.c
+++ b/src/mesa/main/teximage.c
@@ -1353,7 +1353,7 @@ _mesa_test_proxy_teximage(struct gl_context *ctx, GLenum 
target,
  * Return true if the format is only valid for glCompressedTexImage.
  */
 static bool
-compressedteximage_only_format(const struct gl_context *ctx, GLenum format)
+compressedteximage_only_format(GLenum format)
 {
switch (format) {
case GL_PALETTE4_RGB8_OES:
@@ -1376,11 +1376,11 @@ compressedteximage_only_format(const struct gl_context 
*ctx, GLenum format)
  * Return true if the format doesn't support online compression.
  */
 bool
-_mesa_format_no_online_compression(const struct gl_context *ctx, GLenum format)
+_mesa_format_no_online_compression(GLenum format)
 {
return _mesa_is_astc_format(format) ||
   _mesa_is_etc2_format(format) ||
-  compressedteximage_only_format(ctx, format);
+  compressedteximage_only_format(format);
 }
 
 /* Writes to an GL error pointer if non-null and returns whether or not the
@@ -1980,7 +1980,7 @@ texture_error_check( struct gl_context *ctx,
  "glTexImage%dD(target can't be compressed)", dimensions);
  return GL_TRUE;
   }
-  if (_mesa_format_no_online_compression(ctx, internalFormat)) {
+  if (_mesa_format_no_online_compression(internalFormat)) {
  _mesa_error(ctx, GL_INVALID_OPERATION,
  "glTexImage%dD(no compression for format)", dimensions);
  return GL_TRUE;
@@ -2253,7 +2253,7 @@ texsubimage_error_check(struct gl_context *ctx, GLuint 
dimensions,
}
 
if (_mesa_is_format_compressed(texImage->TexFormat)) {
-  if (_mesa_format_no_online_compression(ctx, texImage->InternalFormat)) {
+  if (_mesa_format_no_online_compression(texImage->InternalFormat)) {
  _mesa_error(ctx, GL_INVALID_OPERATION,
"%s(no compression for format)", callerName);
  return GL_TRUE;
@@ -2530,7 +2530,7 @@ copytexture_error_check( struct gl_context *ctx, GLuint 
dimensions,
  "glCopyTexImage%dD(target can't be compressed)", 
dimensions);
  return GL_TRUE;
   }
-  if (_mesa_format_no_online_compression(ctx, internalFormat)) {
+  if (_mesa_format_no_online_compression(internalFormat)) {
  _mesa_error(ctx, GL_INVALID_OPERATION,
"glCopyTexImage%dD(no compression for format)", dimensions);
  return GL_TRUE;
@@ -2612,7 +2612,7 @@ copytexsubimage_error_check(struct gl_context *ctx, 
GLuint dimensions,
}
 
if (_mesa_is_format_compressed(texImage->TexFormat)) {
-  if (_mesa_format_no_online_compression(ctx, texImage->InternalFormat)) {
+  if (_mesa_format_no_online_compression(texImage->InternalFormat)) {
  _mesa_error(ctx, GL_INVALID_OPERATION,
"%s(no compression for format)", caller);
  return GL_TRUE;
@@ -4848,7 +4848,7 @@ compressed_subtexture_error_check(struct gl_context *ctx, 
GLint dims,
   return 

Mesa (master): mesa: Silence remaining unused parameter warnings in teximage.c

[Ian Romanick]

Module: Mesa
Branch: master
Commit: f3b14ca2e1cb4655300272a44f63c9474c48689e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f3b14ca2e1cb4655300272a44f63c9474c48689e

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Tue Feb 27 11:34:43 2018 -0800

mesa: Silence remaining unused parameter warnings in teximage.c

src/mesa/main/teximage.c: In function ‘_mesa_test_proxy_teximage’:
src/mesa/main/teximage.c:1301:51: warning: unused parameter ‘level’ 
[-Wunused-parameter]
   GLuint numLevels, GLint level,
   ^
src/mesa/main/teximage.c: In function ‘texsubimage_error_check’:
src/mesa/main/teximage.c:2186:30: warning: unused parameter ‘dsa’ 
[-Wunused-parameter]
 bool dsa, const char *callerName)
  ^~~
src/mesa/main/teximage.c: In function ‘copytexture_error_check’:
src/mesa/main/teximage.c:2297:32: warning: unused parameter ‘width’ 
[-Wunused-parameter]
  GLint width, GLint height, GLint border )
^
src/mesa/main/teximage.c:2297:45: warning: unused parameter ‘height’ 
[-Wunused-parameter]
  GLint width, GLint height, GLint border )
 ^~
src/mesa/main/teximage.c: In function ‘check_rtt_cb’:
src/mesa/main/teximage.c:2679:21: warning: unused parameter ‘key’ 
[-Wunused-parameter]
 check_rtt_cb(GLuint key, void *data, void *userData)
 ^~~
src/mesa/main/teximage.c: In function ‘override_internal_format’:
src/mesa/main/teximage.c:2756:55: warning: unused parameter ‘width’ 
[-Wunused-parameter]
 override_internal_format(GLenum internalFormat, GLint width, GLint height)
   ^
src/mesa/main/teximage.c:2756:68: warning: unused parameter ‘height’ 
[-Wunused-parameter]
 override_internal_format(GLenum internalFormat, GLint width, GLint height)
^~
src/mesa/main/teximage.c: In function ‘texture_sub_image’:
src/mesa/main/teximage.c:3293:24: warning: unused parameter ‘dsa’ 
[-Wunused-parameter]
   bool dsa)
^~~
src/mesa/main/teximage.c: In function ‘can_avoid_reallocation’:
src/mesa/main/teximage.c:3788:53: warning: unused parameter ‘x’ 
[-Wunused-parameter]
mesa_format texFormat, GLint x, GLint y, GLsizei width,
 ^
src/mesa/main/teximage.c:3788:62: warning: unused parameter ‘y’ 
[-Wunused-parameter]
mesa_format texFormat, GLint x, GLint y, GLsizei width,
  ^
src/mesa/main/teximage.c: In function ‘valid_texstorage_ms_parameters’:
src/mesa/main/teximage.c:5987:40: warning: unused parameter ‘samples’ 
[-Wunused-parameter]
GLsizei samples, unsigned dims)
^~~

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Brian Paul <bri...@vmware.com>

---

 src/mesa/main/teximage.c | 42 +-
 1 file changed, 21 insertions(+), 21 deletions(-)

diff --git a/src/mesa/main/teximage.c b/src/mesa/main/teximage.c
index bec1274f39..8d5f8aa545 100644
--- a/src/mesa/main/teximage.c
+++ b/src/mesa/main/teximage.c
@@ -1299,7 +1299,7 @@ error_check_subtexture_dimensions(struct gl_context *ctx, 
GLuint dims,
  */
 GLboolean
 _mesa_test_proxy_teximage(struct gl_context *ctx, GLenum target,
-  GLuint numLevels, GLint level,
+  GLuint numLevels, MAYBE_UNUSED GLint level,
   mesa_format format, GLuint numSamples,
   GLint width, GLint height, GLint depth)
 {
@@ -2184,7 +2184,7 @@ texsubimage_error_check(struct gl_context *ctx, GLuint 
dimensions,
 GLint xoffset, GLint yoffset, GLint zoffset,
 GLint width, GLint height, GLint depth,
 GLenum format, GLenum type, const GLvoid *pixels,
-bool dsa, const char *callerName)
+const char *callerName)
 {
struct gl_texture_image *texImage;
GLenum err;
@@ -2295,7 +2295,7 @@ texsubimage_error_check(struct gl_context *ctx, GLuint 
dimensions,
 static GLboolean
 copytexture_error_check( struct gl_context *ctx, GLuint dimensions,
  GLenum target, GLint level, GLint internalFormat,
- GLint width, GLint height, GLint border )
+ GLint border )
 {
GLint baseFormat;
GLint rb_base_format;
@@ -2691,7 +2691,7 @@ struct cb_info
  * Check render to texture callback.  Called from _mesa_HashWalk().
  */
 static void
-check

Mesa (master): intel/compiler: Explicitly cast register type in switch

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 81ed629b385af62bbac2d7975986ea7ad4ed2d1a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=81ed629b385af62bbac2d7975986ea7ad4ed2d1a

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Thu Mar 29 11:29:09 2018 -0700

intel/compiler: Explicitly cast register type in switch

brw_reg::type is "enum brw_reg_type type:4".  For whatever reason, GCC
is treating this as an int instead of an enum.  As a result, it doesn't
detect missing switch cases and it doesn't detect that flow can get out
of the switch.

This silences the warning:

src/intel/compiler/brw_reg.h: In function ‘bool brw_regs_negative_equal(const 
brw_reg*, const brw_reg*)’:
src/intel/compiler/brw_reg.h:305:1: warning: control reaches end of non-void 
function [-Wreturn-type]
 }
 ^

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Matt Turner <matts...@gmail.com>
Reviewed-by: Brian Paul <bri...@vmware.com>

---

 src/intel/compiler/brw_reg.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/intel/compiler/brw_reg.h b/src/intel/compiler/brw_reg.h
index afcd146de2..dff9b970b2 100644
--- a/src/intel/compiler/brw_reg.h
+++ b/src/intel/compiler/brw_reg.h
@@ -262,7 +262,7 @@ brw_regs_negative_equal(const struct brw_reg *a, const 
struct brw_reg *b)
   if (a->bits != b->bits)
  return false;
 
-  switch (a->type) {
+  switch ((enum brw_reg_type) a->type) {
   case BRW_REGISTER_TYPE_UQ:
   case BRW_REGISTER_TYPE_Q:
  return a->d64 == -b->d64;

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Mesa (master): spirv: Move SPIR-V building to Makefile.spirv.am and spirv/meson.build

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 042ee4bea26272bd7c358cc9541e576a8352890c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=042ee4bea26272bd7c358cc9541e576a8352890c

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Mon Aug 14 10:40:09 2017 -0700

spirv: Move SPIR-V building to Makefile.spirv.am and spirv/meson.build

Future changes will add generated files used only from
src/compiler/glsl.  These can't be built from Makefile.nir.am, and we
can't move all the rules from Makefile.nir.am to Makefile.spirv.am (and
it would be silly anyway).

v2: Do it for meson too.

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Eric Engestrom <eric.engest...@imgtec.com> (the meson bits)
Reviewed-by: Alejandro Piñeiro <apinhe...@igalia.com> (the automake bits)

---

 src/compiler/Makefile.am   |  2 ++
 src/compiler/Makefile.nir.am   | 36 ++
 src/compiler/Makefile.spirv.am | 58 ++
 src/compiler/meson.build   |  5 
 src/compiler/nir/meson.build   | 15 ---
 src/compiler/spirv/meson.build | 33 
 6 files changed, 100 insertions(+), 49 deletions(-)

diff --git a/src/compiler/Makefile.am b/src/compiler/Makefile.am
index 18c062019f..8ec9b0449c 100644
--- a/src/compiler/Makefile.am
+++ b/src/compiler/Makefile.am
@@ -69,6 +69,8 @@ EXTRA_DIST = \
 MKDIR_GEN = $(AM_V_at)$(MKDIR_P) $(@D)
 PYTHON_GEN = $(AM_V_GEN)$(PYTHON2) $(PYTHON_FLAGS)
 
+include Makefile.spirv.am
+
 include Makefile.glsl.am
 
 include Makefile.nir.am
diff --git a/src/compiler/Makefile.nir.am b/src/compiler/Makefile.nir.am
index d805f573d5..32e4145b70 100644
--- a/src/compiler/Makefile.nir.am
+++ b/src/compiler/Makefile.nir.am
@@ -60,33 +60,6 @@ nir/nir_opt_algebraic.c: nir/nir_opt_algebraic.py 
nir/nir_algebraic.py
$(MKDIR_GEN)
$(PYTHON_GEN) $(srcdir)/nir/nir_opt_algebraic.py > $@ || ($(RM) $@; 
false)
 
-spirv/spirv_info.c: spirv/spirv_info_c.py spirv/spirv.core.grammar.json
-   $(MKDIR_GEN)
-   $(PYTHON_GEN) $(srcdir)/spirv/spirv_info_c.py 
$(srcdir)/spirv/spirv.core.grammar.json $@ || ($(RM) $@; false)
-
-spirv/vtn_gather_types.c: spirv/vtn_gather_types_c.py 
spirv/spirv.core.grammar.json
-   $(MKDIR_GEN)
-   $(PYTHON_GEN) $(srcdir)/spirv/vtn_gather_types_c.py 
$(srcdir)/spirv/spirv.core.grammar.json $@ || ($(RM) $@; false)
-
-noinst_PROGRAMS += spirv2nir
-
-spirv2nir_SOURCES = \
-   spirv/spirv2nir.c
-
-spirv2nir_CPPFLAGS =   \
-   $(AM_CPPFLAGS)  \
-   -I$(top_builddir)/src/compiler/nir  \
-   -I$(top_srcdir)/src/compiler/nir\
-   -I$(top_srcdir)/src/compiler/spirv
-
-spirv2nir_LDADD =  \
-   nir/libnir.la   \
-   $(top_builddir)/src/util/libmesautil.la \
-   -lm \
-   $(PTHREAD_LIBS)
-
-nodist_EXTRA_spirv2nir_SOURCES = dummy.cpp
-
 check_PROGRAMS += nir/tests/control_flow_tests
 
 nir_tests_control_flow_tests_CPPFLAGS = \
@@ -109,12 +82,10 @@ TESTS += nir/tests/control_flow_tests
 
 
 BUILT_SOURCES += \
-   $(NIR_GENERATED_FILES) \
-   $(SPIRV_GENERATED_FILES)
+   $(NIR_GENERATED_FILES)
 
 CLEANFILES += \
-   $(NIR_GENERATED_FILES) \
-   $(SPIRV_GENERATED_FILES)
+   $(NIR_GENERATED_FILES)
 
 EXTRA_DIST += \
nir/nir_algebraic.py\
@@ -129,7 +100,4 @@ EXTRA_DIST += \
nir/nir_opt_algebraic.py\
nir/tests \
nir/README \
-   spirv/spirv_info_c.py   \
-   spirv/spirv.core.grammar.json   \
-   spirv/vtn_gather_types_c.py \
SConscript.nir
diff --git a/src/compiler/Makefile.spirv.am b/src/compiler/Makefile.spirv.am
new file mode 100644
index 00..a9f90c26e7
--- /dev/null
+++ b/src/compiler/Makefile.spirv.am
@@ -0,0 +1,58 @@
+#
+# Copyright (C) 2017 Intel Corporation
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice (including the next
+# paragraph) shall be included in all copies or substantial portions of the
+# Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE

Mesa (master): i965: Don't request GLSL IR lowering of gl_VertexID

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 19e0dd1ad3ad43ddc3aeba1e11852dce3f55d1f1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=19e0dd1ad3ad43ddc3aeba1e11852dce3f55d1f1

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Wed Oct 18 08:59:47 2017 -0700

i965: Don't request GLSL IR lowering of gl_VertexID

Let the lowering in NIR handle it instead.

This hurts one shader that occurs twice in shader-db (SynMark GSCloth)
on IVB and HSW.  No other shaders or platforms were affected.

total cycles in shared programs: 253438422 -> 253438426 (0.00%)
cycles in affected programs: 412 -> 416 (0.97%)
helped: 0
HURT: 2

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Antia Puentes <apuen...@igalia.com>

---

 src/mesa/drivers/dri/i965/brw_context.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.c 
b/src/mesa/drivers/dri/i965/brw_context.c
index fca5c8e307..4e37425099 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -595,7 +595,6 @@ brw_initialize_context_constants(struct brw_context *brw)
   ctx->Const.QuadsFollowProvokingVertexConvention = false;
 
ctx->Const.NativeIntegers = true;
-   ctx->Const.VertexID_is_zero_based = true;
 
/* Regarding the CMP instruction, the Ivybridge PRM says:
 *

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Mesa (master): util: Optimize util_is_power_of_two_nonzero

[Ian Romanick]

Module: Mesa
Branch: master
Commit: ef7a4c90155cb180a4f0d289594ef11da9a2b21a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ef7a4c90155cb180a4f0d289594ef11da9a2b21a

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Mon Nov 13 13:11:09 2017 -0800

util: Optimize util_is_power_of_two_nonzero

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Suggested-by: Matt Turner <matts...@gmail.com>
Reviewed-by: Eduardo Lima Mitev <el...@igalia.com>

---

 src/util/bitscan.h | 17 +
 1 file changed, 17 insertions(+)

diff --git a/src/util/bitscan.h b/src/util/bitscan.h
index a3f2d414bd..5cc75f0beb 100644
--- a/src/util/bitscan.h
+++ b/src/util/bitscan.h
@@ -38,6 +38,10 @@
 #include 
 #endif
 
+#if defined(__POPCNT__)
+#include 
+#endif
+
 #include "c99_compat.h"
 
 #ifdef __cplusplus
@@ -127,7 +131,20 @@ util_is_power_of_two_or_zero(unsigned v)
 static inline bool
 util_is_power_of_two_nonzero(unsigned v)
 {
+   /* __POPCNT__ is different from HAVE___BUILTIN_POPCOUNT.  The latter
+* indicates the existence of the __builtin_popcount function.  The former
+* indicates that _mm_popcnt_u32 exists and is a native instruction.
+*
+* The other alternative is to use SSE 4.2 compile-time flags.  This has
+* two drawbacks.  First, there is currently no build infrastructure for
+* SSE 4.2 (only 4.1), so that would have to be added.  Second, some AMD
+* CPUs support POPCNT but not SSE 4.2 (e.g., Barcelona).
+*/
+#ifdef __POPCNT__
+   return _mm_popcnt_u32(v) == 1;
+#else
return v != 0 && (v & (v - 1)) == 0;
+#endif
 }
 
 /* For looping over a bitmask when you want to loop over consecutive bits

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Mesa (master): util: Add and use util_is_power_of_two_nonzero

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 22fbb5c5949b1590ef04b6432dd7f3a93a37c2ed
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=22fbb5c5949b1590ef04b6432dd7f3a93a37c2ed

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Mon Nov 13 13:00:53 2017 -0800

util: Add and use util_is_power_of_two_nonzero

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Eduardo Lima Mitev <el...@igalia.com>

---

 src/compiler/nir/nir_search_helpers.h | 13 -
 src/compiler/nir/nir_validate.c   |  2 +-
 src/gallium/drivers/etnaviv/etnaviv_blt.c |  2 +-
 src/intel/compiler/brw_fs.cpp |  4 ++--
 src/util/bitscan.h| 11 +++
 5 files changed, 19 insertions(+), 13 deletions(-)

diff --git a/src/compiler/nir/nir_search_helpers.h 
b/src/compiler/nir/nir_search_helpers.h
index 2d399bd5dc..8bc6d723c3 100644
--- a/src/compiler/nir/nir_search_helpers.h
+++ b/src/compiler/nir/nir_search_helpers.h
@@ -28,12 +28,7 @@
 #define _NIR_SEARCH_HELPERS_
 
 #include "nir.h"
-
-static inline bool
-__is_power_of_two(unsigned int x)
-{
-   return ((x != 0) && !(x & (x - 1)));
-}
+#include "util/bitscan.h"
 
 static inline bool
 is_pos_power_of_two(nir_alu_instr *instr, unsigned src, unsigned 
num_components,
@@ -50,11 +45,11 @@ is_pos_power_of_two(nir_alu_instr *instr, unsigned src, 
unsigned num_components,
   case nir_type_int:
  if (val->i32[swizzle[i]] < 0)
 return false;
- if (!__is_power_of_two(val->i32[swizzle[i]]))
+ if (!util_is_power_of_two_nonzero(val->i32[swizzle[i]]))
 return false;
  break;
   case nir_type_uint:
- if (!__is_power_of_two(val->u32[swizzle[i]]))
+ if (!util_is_power_of_two_nonzero(val->u32[swizzle[i]]))
 return false;
  break;
   default:
@@ -80,7 +75,7 @@ is_neg_power_of_two(nir_alu_instr *instr, unsigned src, 
unsigned num_components,
   case nir_type_int:
  if (val->i32[swizzle[i]] > 0)
 return false;
- if (!__is_power_of_two(abs(val->i32[swizzle[i]])))
+ if (!util_is_power_of_two_nonzero(abs(val->i32[swizzle[i]])))
 return false;
  break;
   default:
diff --git a/src/compiler/nir/nir_validate.c b/src/compiler/nir/nir_validate.c
index 725ba43152..565cb2ef16 100644
--- a/src/compiler/nir/nir_validate.c
+++ b/src/compiler/nir/nir_validate.c
@@ -982,7 +982,7 @@ validate_var_decl(nir_variable *var, bool is_global, 
validate_state *state)
validate_assert(state, is_global == nir_variable_is_global(var));
 
/* Must have exactly one mode set */
-   validate_assert(state, util_bitcount(var->data.mode) == 1);
+   validate_assert(state, util_is_power_of_two_nonzero(var->data.mode));
 
if (var->data.compact) {
   /* The "compact" flag is only valid on arrays of scalars. */
diff --git a/src/gallium/drivers/etnaviv/etnaviv_blt.c 
b/src/gallium/drivers/etnaviv/etnaviv_blt.c
index c30c11ab61..52731a9c77 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_blt.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_blt.c
@@ -178,7 +178,7 @@ emit_blt_copyimage(struct etna_cmd_stream *stream, const 
struct blt_imgcopy_op *
 static void
 emit_blt_inplace(struct etna_cmd_stream *stream, const struct blt_inplace_op 
*op)
 {
-   assert(op->bpp > 0 && util_is_power_of_two_or_zero(op->bpp));
+   assert(op->bpp > 0 && util_is_power_of_two_nonzero(op->bpp));
etna_cmd_stream_reserve(stream, 64*2); /* Never allow BLT sequences to be 
broken up */
etna_set_state(stream, VIVS_BLT_ENABLE, 0x0001);
etna_set_state(stream, VIVS_BLT_CONFIG,
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index fdcc909a3d..40896db26b 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -1976,7 +1976,7 @@ struct cplx_align {
 static void
 cplx_align_assert_sane(struct cplx_align a)
 {
-   assert(a.mul > 0 && util_is_power_of_two_or_zero(a.mul));
+   assert(a.mul > 0 && util_is_power_of_two_nonzero(a.mul));
assert(a.offset < a.mul);
 }
 
@@ -2028,7 +2028,7 @@ static void
 mark_uniform_slots_read(struct uniform_slot_info *slots,
 unsigned num_slots, unsigned alignment)
 {
-   assert(alignment > 0 && util_is_power_of_two_or_zero(alignment));
+   assert(alignment > 0 && util_is_power_of_two_nonzero(alignment));
assert(alignment <= CPLX_ALIGN_MAX_MUL);
 
/* We can't align a slot to anything less than the slot size */
diff --git a/src/util/bitscan.h b/src/util/bitscan.h
index 2d4e46ec0f..a3f2d414bd 100644
--- a/src/util/bitscan.h
+++ b/src/util/bitscan.h
@@ -119,6 +119,17 @@ util_is_power_of_two_or_zero(unsigned v)
return (v & (v - 1)) == 0;
 }
 
+/* Determine if an unsigned value is a power of two.
+ *
+ * \note
+ * Zero is \b

Mesa (master): compiler: All leaf Makefile.am should use +=

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 2c9621ee5c5fa40be071858f99fb256fc37369b4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2c9621ee5c5fa40be071858f99fb256fc37369b4

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Mon Aug 14 10:38:10 2017 -0700

compiler: All leaf Makefile.am should use +=

This slightly simplifies later changes that add more Makefile.*.am
files.

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Eduardo Lima Mitev <el...@igalia.com>

---

 src/compiler/Makefile.am  | 1 +
 src/compiler/Makefile.glsl.am | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/compiler/Makefile.am b/src/compiler/Makefile.am
index fd6811ff26..18c062019f 100644
--- a/src/compiler/Makefile.am
+++ b/src/compiler/Makefile.am
@@ -53,6 +53,7 @@ noinst_LTLIBRARIES = libcompiler.la
 
 libcompiler_la_SOURCES = $(LIBCOMPILER_FILES)
 
+noinst_PROGRAMS =
 check_PROGRAMS =
 TESTS =
 BUILT_SOURCES =
diff --git a/src/compiler/Makefile.glsl.am b/src/compiler/Makefile.glsl.am
index 179f415fe6..ad19b14e44 100644
--- a/src/compiler/Makefile.glsl.am
+++ b/src/compiler/Makefile.glsl.am
@@ -54,7 +54,7 @@ check_PROGRAMS += \
glsl/tests/sampler-types-test   \
glsl/tests/uniform-initializer-test
 
-noinst_PROGRAMS = glsl_compiler
+noinst_PROGRAMS += glsl_compiler
 
 glsl_tests_blob_test_SOURCES = \
glsl/tests/blob_test.c

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Mesa (master): util: Move util_is_power_of_two to bitscan.h and rename to util_is_power_of_two_or_zero

[Ian Romanick]

Module: Mesa
Branch: master
Commit: d76c204d0564701b4b8b6a2bdda50e2939683e66
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d76c204d0564701b4b8b6a2bdda50e2939683e66

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Mon Nov 13 11:17:41 2017 -0800

util: Move util_is_power_of_two to bitscan.h and rename to 
util_is_power_of_two_or_zero

The new name make the zero-input behavior more obvious.  The next
patch adds a new function with different zero-input behavior.

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Suggested-by: Matt Turner <matts...@gmail.com>
Reviewed-by: Alejandro Piñeiro <apinhe...@igalia.com>

---

 src/amd/common/ac_gpu_info.c |  4 ++--
 src/amd/common/ac_surface.c  |  2 +-
 src/amd/vulkan/radv_formats.c|  4 ++--
 src/broadcom/compiler/nir_to_vir.c   |  4 ++--
 src/gallium/auxiliary/gallivm/lp_bld_arit.c  |  2 +-
 src/gallium/auxiliary/gallivm/lp_bld_debug.cpp   |  2 +-
 src/gallium/auxiliary/gallivm/lp_bld_format_aos.c|  4 ++--
 src/gallium/auxiliary/gallivm/lp_bld_gather.c|  8 
 src/gallium/auxiliary/gallivm/lp_bld_pack.c  |  2 +-
 src/gallium/auxiliary/gallivm/lp_bld_sample.c|  6 +++---
 src/gallium/auxiliary/util/u_math.h  | 10 +-
 src/gallium/auxiliary/util/u_ringbuffer.c|  2 +-
 src/gallium/drivers/etnaviv/etnaviv_blt.c|  2 +-
 src/gallium/drivers/etnaviv/etnaviv_texture_state.c  |  3 ++-
 src/gallium/drivers/freedreno/freedreno_query_hw.c   |  2 +-
 src/gallium/drivers/i915/i915_state_sampler.c|  3 ++-
 src/gallium/drivers/llvmpipe/lp_state_fs.c   |  2 +-
 src/gallium/drivers/llvmpipe/lp_texture.c|  2 +-
 src/gallium/drivers/nouveau/codegen/nv50_ir.cpp  |  2 +-
 src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp |  4 ++--
 src/gallium/drivers/nouveau/nv30/nv30_miptree.c  |  6 +++---
 src/gallium/drivers/nouveau/nvc0/nvc0_state_validate.c   |  2 +-
 src/gallium/drivers/r300/r300_texture_desc.c |  6 +++---
 src/gallium/drivers/r600/r600_texture.c  |  2 +-
 src/gallium/drivers/radeon/r600_texture.c|  2 +-
 src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c  |  2 +-
 src/gallium/drivers/softpipe/sp_texture.c| 12 ++--
 src/gallium/drivers/swr/swr_screen.cpp   |  4 ++--
 src/gallium/drivers/vc4/vc4_program.c|  4 ++--
 src/intel/compiler/brw_fs.cpp|  4 ++--
 src/intel/vulkan/anv_allocator.c |  6 +++---
 src/intel/vulkan/anv_formats.c   |  4 ++--
 src/intel/vulkan/anv_nir_lower_multiview.c   |  2 +-
 src/mesa/state_tracker/st_cb_readpixels.c|  4 ++--
 src/mesa/state_tracker/st_cb_texture.c   |  6 +++---
 src/util/bitscan.h   | 12 
 src/util/u_vector.c  |  4 ++--
 37 files changed, 79 insertions(+), 73 deletions(-)

diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index 73fc36203c..f93ef4cbad 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -333,8 +333,8 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
}
info->has_virtual_memory = true;
 
-   assert(util_is_power_of_two(dma.available_rings + 1));
-   assert(util_is_power_of_two(compute.available_rings + 1));
+   assert(util_is_power_of_two_or_zero(dma.available_rings + 1));
+   assert(util_is_power_of_two_or_zero(compute.available_rings + 1));
 
info->num_sdma_rings = util_bitcount(dma.available_rings);
info->num_compute_rings = util_bitcount(compute.available_rings);
diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index 81882576ba..1e1641daee 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -275,7 +275,7 @@ static int gfx6_compute_level(ADDR_HANDLE addrlib,
AddrSurfInfoIn->bpp) {
unsigned alignment = 256 / (AddrSurfInfoIn->bpp / 8);
 
-   assert(util_is_power_of_two(AddrSurfInfoIn->bpp));
+   assert(util_is_power_of_two_or_zero(AddrSurfInfoIn->bpp));
AddrSurfInfoIn->width = align(AddrSurfInfoIn->width, alignment);
}
 
diff --git a/src/amd/vulkan/radv_formats.c b/src/amd/vulkan/radv_formats.c
index efb1d78790..1bafe09e77 100644
--- a/src/amd/vulkan/radv_formats.c
+++ b/src/amd/vulkan/radv_formats.c
@@ -638,13 +638,13 @@ radv_physical_device_get_format_properties(struct 
radv_physical_device *physical
tiled |= 
VK_FORMAT_FEATURE_COLOR_ATTACHMENT_BLEND_BIT;
  

Mesa (master): util: Include bitscan.h directly

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 4925347ec5d469574f1280e972940cfea345ed6e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4925347ec5d469574f1280e972940cfea345ed6e

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Wed Jul 26 13:32:01 2017 -0700

util: Include bitscan.h directly

Previously bitset.h would include u_math.h to get bitscan.h.  u_math.h
lives in src/gallium/auxiliary/util while both bitset.h and bitscan.h
live in src/util.  Having the one file directly include another file
that lives in the same directory makes much more sense.

As a side-effect, several files need to directly include standard header
files that were previously indirectly included.

v2: Fix build break in src/amd/common/ac_nir_to_llvm.c.

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Eduardo Lima Mitev <el...@igalia.com>

---

 src/amd/common/ac_nir_to_llvm.c  | 1 +
 src/compiler/nir/nir.c   | 1 +
 src/compiler/spirv/vtn_alu.c | 1 +
 src/compiler/spirv/vtn_glsl450.c | 1 +
 src/util/bitset.h| 2 +-
 5 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 7efbe4b31a..053c19808f 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -28,6 +28,7 @@
 #include "sid.h"
 #include "nir/nir.h"
 #include "util/bitscan.h"
+#include "util/u_math.h"
 #include "ac_shader_abi.h"
 #include "ac_shader_util.h"
 
diff --git a/src/compiler/nir/nir.c b/src/compiler/nir/nir.c
index a97b119bf7..3fb16e6ca5 100644
--- a/src/compiler/nir/nir.c
+++ b/src/compiler/nir/nir.c
@@ -28,6 +28,7 @@
 #include "nir.h"
 #include "nir_control_flow_private.h"
 #include "util/half_float.h"
+#include 
 #include 
 #include 
 
diff --git a/src/compiler/spirv/vtn_alu.c b/src/compiler/spirv/vtn_alu.c
index 01be397e27..fc378495b8 100644
--- a/src/compiler/spirv/vtn_alu.c
+++ b/src/compiler/spirv/vtn_alu.c
@@ -21,6 +21,7 @@
  * IN THE SOFTWARE.
  */
 
+#include 
 #include "vtn_private.h"
 
 /*
diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c
index 7d32914d51..eb0b90f797 100644
--- a/src/compiler/spirv/vtn_glsl450.c
+++ b/src/compiler/spirv/vtn_glsl450.c
@@ -25,6 +25,7 @@
  *
  */
 
+#include 
 #include "vtn_private.h"
 #include "GLSL.std.450.h"
 
diff --git a/src/util/bitset.h b/src/util/bitset.h
index b4c2152023..75e29a9a51 100644
--- a/src/util/bitset.h
+++ b/src/util/bitset.h
@@ -31,7 +31,7 @@
 #ifndef BITSET_H
 #define BITSET_H
 
-#include "util/u_math.h"
+#include "util/bitscan.h"
 
 /
  * generic bitset implementation

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Mesa (master): i965: Silence unused parameter warning

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 2765633116da69c194fd815303605e91285201bb
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2765633116da69c194fd815303605e91285201bb

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Mon Mar 26 17:25:27 2018 -0700

i965: Silence unused parameter warning

src/mesa/drivers/dri/i965/brw_draw_upload.c: In function ‘double_types’:
src/mesa/drivers/dri/i965/brw_draw_upload.c:225:34: warning: unused parameter 
‘brw’ [-Wunused-parameter]
 double_types(struct brw_context *brw,
  ^~~

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Alejandro Piñeiro <apinhe...@igalia.com>

---

 src/mesa/drivers/dri/i965/brw_draw_upload.c | 8 +++-
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c 
b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index 4ede33aea1..344e2f2b4e 100644
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -222,9 +222,7 @@ static const GLuint byte_types_scale[5] = {
 };
 
 static GLuint
-double_types(struct brw_context *brw,
- int size,
- GLboolean doubles)
+double_types(int size, GLboolean doubles)
 {
/* From the BDW PRM, Volume 2d, page 588 (VERTEX_ELEMENT_STATE):
 * "When SourceElementFormat is set to one of the *64*_PASSTHRU formats,
@@ -292,7 +290,7 @@ brw_get_vertex_surface_type(struct brw_context *brw,
   return ISL_FORMAT_R11G11B10_FLOAT;
} else if (glattrib->Normalized) {
   switch (glattrib->Type) {
-  case GL_DOUBLE: return double_types(brw, size, glattrib->Doubles);
+  case GL_DOUBLE: return double_types(size, glattrib->Doubles);
   case GL_FLOAT: return float_types[size];
   case GL_HALF_FLOAT:
   case GL_HALF_FLOAT_OES:
@@ -371,7 +369,7 @@ brw_get_vertex_surface_type(struct brw_context *brw,
   }
   assert(glattrib->Format == GL_RGBA); /* sanity check */
   switch (glattrib->Type) {
-  case GL_DOUBLE: return double_types(brw, size, glattrib->Doubles);
+  case GL_DOUBLE: return double_types(size, glattrib->Doubles);
   case GL_FLOAT: return float_types[size];
   case GL_HALF_FLOAT:
   case GL_HALF_FLOAT_OES:

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Mesa (master): util: Use util_is_power_of_two_nonzero in u_vector

[Ian Romanick]

Module: Mesa
Branch: master
Commit: cd18aa1e50e4668c8d992816bcdb74376dd1064c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cd18aa1e50e4668c8d992816bcdb74376dd1064c

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Mon Mar 26 10:52:43 2018 -0700

util: Use util_is_power_of_two_nonzero in u_vector

Previously size=0, element_size=0 would have been allowed.  That
combination can only lead to despair.

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Alejandro Piñeiro <apinhe...@igalia.com>

---

 src/util/u_vector.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/util/u_vector.c b/src/util/u_vector.c
index bec6e5bbc3..15f8ed6bda 100644
--- a/src/util/u_vector.c
+++ b/src/util/u_vector.c
@@ -37,8 +37,8 @@
 int
 u_vector_init(struct u_vector *vector, uint32_t element_size, uint32_t size)
 {
-   assert(util_is_power_of_two_or_zero(size));
-   assert(element_size < size && util_is_power_of_two_or_zero(element_size));
+   assert(util_is_power_of_two_nonzero(size));
+   assert(element_size < size && util_is_power_of_two_nonzero(element_size));
 
vector->head = 0;
vector->tail = 0;

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Mesa (master): i965: Add negative_equals methods

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 8f83eea71e233227d34dc8547dac79d2912c2311
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8f83eea71e233227d34dc8547dac79d2912c2311

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Tue Apr  7 16:11:37 2015 -0700

i965: Add negative_equals methods

This method is similar to the existing ::equals methods.  Instead of
testing that two src_regs are equal to each other, it tests that one is
the negation of the other.

v2: Simplify various checks based on suggestions from Matt.  Use
src_reg::type instead of fixed_hw_reg.type in a check.  Also suggested
by Matt.

v3: Rebase on 3 years.  Fix some problems with negative_equals with VF
constants.  Add fs_reg::negative_equals.

v4: Replace the existing default case with BRW_REGISTER_TYPE_UB,
BRW_REGISTER_TYPE_B, and BRW_REGISTER_TYPE_NF.  Suggested by Matt.
Expand the FINISHME comment to better explain why it isn't already
finished.

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Alejandro Piñeiro <apinhe...@igalia.com> [v3]
Reviewed-by: Matt Turner <matts...@gmail.com>

---

 src/intel/compiler/brw_fs.cpp |  7 ++
 src/intel/compiler/brw_ir_fs.h|  1 +
 src/intel/compiler/brw_ir_vec4.h  |  1 +
 src/intel/compiler/brw_reg.h  | 49 +++
 src/intel/compiler/brw_shader.cpp |  6 +
 src/intel/compiler/brw_shader.h   |  1 +
 src/intel/compiler/brw_vec4.cpp   |  7 ++
 7 files changed, 72 insertions(+)

diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 6eea532f56..3d454c3db1 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -454,6 +454,13 @@ fs_reg::equals(const fs_reg ) const
 }
 
 bool
+fs_reg::negative_equals(const fs_reg ) const
+{
+   return (this->backend_reg::negative_equals(r) &&
+   stride == r.stride);
+}
+
+bool
 fs_reg::is_contiguous() const
 {
return stride == 1;
diff --git a/src/intel/compiler/brw_ir_fs.h b/src/intel/compiler/brw_ir_fs.h
index 54797ff0fa..f06a33c516 100644
--- a/src/intel/compiler/brw_ir_fs.h
+++ b/src/intel/compiler/brw_ir_fs.h
@@ -41,6 +41,7 @@ public:
fs_reg(enum brw_reg_file file, int nr, enum brw_reg_type type);
 
bool equals(const fs_reg ) const;
+   bool negative_equals(const fs_reg ) const;
bool is_contiguous() const;
 
/**
diff --git a/src/intel/compiler/brw_ir_vec4.h b/src/intel/compiler/brw_ir_vec4.h
index cbaff2feff..95c5119c6c 100644
--- a/src/intel/compiler/brw_ir_vec4.h
+++ b/src/intel/compiler/brw_ir_vec4.h
@@ -43,6 +43,7 @@ public:
src_reg(struct ::brw_reg reg);
 
bool equals(const src_reg ) const;
+   bool negative_equals(const src_reg ) const;
 
src_reg(class vec4_visitor *v, const struct glsl_type *type);
src_reg(class vec4_visitor *v, const struct glsl_type *type, int size);
diff --git a/src/intel/compiler/brw_reg.h b/src/intel/compiler/brw_reg.h
index 7ad144bdfd..68158cc0cc 100644
--- a/src/intel/compiler/brw_reg.h
+++ b/src/intel/compiler/brw_reg.h
@@ -255,6 +255,55 @@ brw_regs_equal(const struct brw_reg *a, const struct 
brw_reg *b)
return a->bits == b->bits && (df ? a->u64 == b->u64 : a->ud == b->ud);
 }
 
+static inline bool
+brw_regs_negative_equal(const struct brw_reg *a, const struct brw_reg *b)
+{
+   if (a->file == IMM) {
+  if (a->bits != b->bits)
+ return false;
+
+  switch (a->type) {
+  case BRW_REGISTER_TYPE_UQ:
+  case BRW_REGISTER_TYPE_Q:
+ return a->d64 == -b->d64;
+  case BRW_REGISTER_TYPE_DF:
+ return a->df == -b->df;
+  case BRW_REGISTER_TYPE_UD:
+  case BRW_REGISTER_TYPE_D:
+ return a->d == -b->d;
+  case BRW_REGISTER_TYPE_F:
+ return a->f == -b->f;
+  case BRW_REGISTER_TYPE_VF:
+ /* It is tempting to treat 0 as a negation of 0 (and -0 as a negation
+  * of -0).  There are occasions where 0 or -0 is used and the exact
+  * bit pattern is desired.  At the very least, changing this to allow
+  * 0 as a negation of 0 causes some fp64 tests to fail on IVB.
+  */
+ return a->ud == (b->ud ^ 0x80808080);
+  case BRW_REGISTER_TYPE_UW:
+  case BRW_REGISTER_TYPE_W:
+  case BRW_REGISTER_TYPE_UV:
+  case BRW_REGISTER_TYPE_V:
+  case BRW_REGISTER_TYPE_HF:
+ /* FINISHME: Implement support for these types once there is
+  * something in the compiler that can generate them.  Until then,
+  * they cannot be tested.
+  */
+ return false;
+  case BRW_REGISTER_TYPE_UB:
+  case BRW_REGISTER_TYPE_B:
+  case BRW_REGISTER_TYPE_NF:
+ unreachable("not reached");
+  }
+   } else {
+  struct brw_reg tmp = *a;
+
+  tmp.negate = !tmp.negate;
+
+  return brw_regs_equal(, b);
+   }
+}
+
 struct brw_indirect {
unsigned addr_subnr:4;
int addr_offset:10;
diff -

Mesa (master): i965/vec4: Propagate conditional modifiers from compares to adds

[Ian Romanick]

Module: Mesa
Branch: master
Commit: cd635d149b23f0522cb1a73d6a007851896883e3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cd635d149b23f0522cb1a73d6a007851896883e3

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Wed Mar 21 15:22:51 2018 -0700

i965/vec4: Propagate conditional modifiers from compares to adds

No changes on Broadwell or later as those platforms do not use the vec4
backend.

Ivy Bridge and Haswell had similar results. (Ivy Bridge shown)
total instructions in shared programs: 11682119 -> 11681056 (<.01%)
instructions in affected programs: 150403 -> 149340 (-0.71%)
helped: 950
HURT: 0
helped stats (abs) min: 1 max: 16 x̄: 1.12 x̃: 1
helped stats (rel) min: 0.23% max: 2.78% x̄: 0.82% x̃: 0.71%
95% mean confidence interval for instructions value: -1.19 -1.04
95% mean confidence interval for instructions %-change: -0.84% -0.79%
Instructions are helped.

total cycles in shared programs: 257495842 -> 257495238 (<.01%)
cycles in affected programs: 270302 -> 269698 (-0.22%)
helped: 271
HURT: 13
helped stats (abs) min: 2 max: 14 x̄: 2.42 x̃: 2
helped stats (rel) min: 0.06% max: 1.13% x̄: 0.32% x̃: 0.28%
HURT stats (abs)   min: 2 max: 12 x̄: 4.00 x̃: 4
HURT stats (rel)   min: 0.15% max: 1.18% x̄: 0.30% x̃: 0.26%
95% mean confidence interval for cycles value: -2.41 -1.84
95% mean confidence interval for cycles %-change: -0.31% -0.26%
Cycles are helped.

Sandy Bridge
total instructions in shared programs: 10430493 -> 10429727 (<.01%)
instructions in affected programs: 120860 -> 120094 (-0.63%)
helped: 766
HURT: 0
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 0.30% max: 2.70% x̄: 0.78% x̃: 0.73%
95% mean confidence interval for instructions value: -1.00 -1.00
95% mean confidence interval for instructions %-change: -0.80% -0.75%
Instructions are helped.

total cycles in shared programs: 146138718 -> 146138446 (<.01%)
cycles in affected programs: 244114 -> 243842 (-0.11%)
helped: 132
HURT: 0
helped stats (abs) min: 2 max: 4 x̄: 2.06 x̃: 2
helped stats (rel) min: 0.03% max: 0.43% x̄: 0.16% x̃: 0.19%
95% mean confidence interval for cycles value: -2.12 -2.00
95% mean confidence interval for cycles %-change: -0.18% -0.15%
Cycles are helped.

GM45 and Iron Lake had identical results. (Iron Lake shown)
total instructions in shared programs: 7780251 -> 7780248 (<.01%)
instructions in affected programs: 175 -> 172 (-1.71%)
helped: 3
HURT: 0
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 1.49% max: 2.44% x̄: 1.81% x̃: 1.49%

total cycles in shared programs: 177851584 -> 177851578 (<.01%)
cycles in affected programs: 9796 -> 9790 (-0.06%)
helped: 3
HURT: 0
helped stats (abs) min: 2 max: 2 x̄: 2.00 x̃: 2
helped stats (rel) min: 0.05% max: 0.08% x̄: 0.06% x̃: 0.05%

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Alejandro Piñeiro <apinhe...@igalia.com>
Reviewed-by: Matt Turner <matts...@gmail.com>

---

 src/intel/compiler/brw_vec4_cmod_propagation.cpp | 70 ++--
 1 file changed, 65 insertions(+), 5 deletions(-)

diff --git a/src/intel/compiler/brw_vec4_cmod_propagation.cpp 
b/src/intel/compiler/brw_vec4_cmod_propagation.cpp
index 7f1001b6d1..5205da4983 100644
--- a/src/intel/compiler/brw_vec4_cmod_propagation.cpp
+++ b/src/intel/compiler/brw_vec4_cmod_propagation.cpp
@@ -50,8 +50,14 @@ opt_cmod_propagation_local(bblock_t *block)
   inst->predicate != BRW_PREDICATE_NONE ||
   !inst->dst.is_null() ||
   (inst->src[0].file != VGRF && inst->src[0].file != ATTR &&
-   inst->src[0].file != UNIFORM) ||
-  inst->src[0].abs)
+   inst->src[0].file != UNIFORM))
+ continue;
+
+  /* An ABS source modifier can only be handled when processing a compare
+   * with a value other than zero.
+   */
+  if (inst->src[0].abs &&
+  (inst->opcode != BRW_OPCODE_CMP || inst->src[1].is_zero()))
  continue;
 
   if (inst->opcode == BRW_OPCODE_AND &&
@@ -60,15 +66,68 @@ opt_cmod_propagation_local(bblock_t *block)
 !inst->src[0].negate))
  continue;
 
-  if (inst->opcode == BRW_OPCODE_CMP && !inst->src[1].is_zero())
- continue;
-
   if (inst->opcode == BRW_OPCODE_MOV &&
   inst->conditional_mod != BRW_CONDITIONAL_NZ)
  continue;
 
   bool read_flag = false;
   foreach_inst_in_block_reverse_starting_from(vec4_instruction, scan_inst, 
inst) {
+ /* A CMP with a second source of zero can match with anything.  A CMP
+  * with a second source that is not zero can only match with an ADD
+  * instruction.
+  */
+ if (inst->opcode == BRW_OPCODE_CMP && !inst->src[1].is_zero()) {
+bool negate;
+
+if (scan_inst->opcode != BR

Mesa (master): i965/fs: Allow cmod propagation when src0 is a uniform or shader input

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 5bbb3d60d358cf906ca7078641ae7fb50c4d4e06
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5bbb3d60d358cf906ca7078641ae7fb50c4d4e06

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Wed Mar 14 10:19:19 2018 -0700

i965/fs: Allow cmod propagation when src0 is a uniform or shader input

No shader-db changes.  This source must have been written by a previous
instruction, so it cannot be a uniform or a shader input.  However, this
change allows the next commit to help about 900 more shaders.

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Alejandro Piñeiro <apinhe...@igalia.com>
Reviewed-by: Matt Turner <matts...@gmail.com>

---

 src/intel/compiler/brw_fs_cmod_propagation.cpp | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/intel/compiler/brw_fs_cmod_propagation.cpp 
b/src/intel/compiler/brw_fs_cmod_propagation.cpp
index 4625d69f89..b995a51d3c 100644
--- a/src/intel/compiler/brw_fs_cmod_propagation.cpp
+++ b/src/intel/compiler/brw_fs_cmod_propagation.cpp
@@ -62,7 +62,8 @@ opt_cmod_propagation_local(const gen_device_info *devinfo, 
bblock_t *block)
inst->opcode != BRW_OPCODE_MOV) ||
   inst->predicate != BRW_PREDICATE_NONE ||
   !inst->dst.is_null() ||
-  inst->src[0].file != VGRF ||
+  (inst->src[0].file != VGRF && inst->src[0].file != ATTR &&
+   inst->src[0].file != UNIFORM) ||
   inst->src[0].abs)
  continue;
 

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Mesa (master): i965/fs: Propagate conditional modifiers from compares to adds

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 020b0055e7a085a6a8c961ad12ce94e58606a1ae
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=020b0055e7a085a6a8c961ad12ce94e58606a1ae

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Fri Mar  9 13:45:01 2018 -0800

i965/fs: Propagate conditional modifiers from compares to adds

The math inside the add and the cmp in this instruction sequence is the
same.  We can utilize this to eliminate the compare.

add(8)  g5<1>F  g2<8,8,1>F  g64.5<0,1,0>F   { align1 1Q 
compacted };
cmp.z.f0(8) null<1>Fg2<8,8,1>F  -g64.5<0,1,0>F  { align1 1Q 
switch };
(-f0) sel(8)g8<1>F  (abs)g5<8,8,1>F 3e-37F  { align1 1Q };

This is reduced to:

add.z.f0(8) g5<1>F  g2<8,8,1>F  g64.5<0,1,0>F   { align1 1Q 
compacted };
(-f0) sel(8)g8<1>F  (abs)g5<8,8,1>F 3e-37F  { align1 1Q };

This optimization pass could do even better.  The nature of converting
vectorized code from the GLSL front end to scalar code in NIR results in
sequences like:

add(8)  g7<1>F  g4<8,8,1>F  g64.5<0,1,0>F   { align1 1Q 
compacted };
add(8)  g6<1>F  g3<8,8,1>F  g64.5<0,1,0>F   { align1 1Q 
compacted };
add(8)  g5<1>F  g2<8,8,1>F  g64.5<0,1,0>F   { align1 1Q 
compacted };
cmp.z.f0(8) null<1>Fg2<8,8,1>F  -g64.5<0,1,0>F  { align1 1Q 
switch };
(-f0) sel(8)g8<1>F  (abs)g5<8,8,1>F 3e-37F  { align1 1Q };
cmp.z.f0(8) null<1>Fg3<8,8,1>F  -g64.5<0,1,0>F  { align1 1Q 
switch };
(-f0) sel(8)g10<1>F (abs)g6<8,8,1>F 3e-37F  { align1 1Q };
cmp.z.f0(8) null<1>Fg4<8,8,1>F  -g64.5<0,1,0>F  { align1 1Q 
switch };
(-f0) sel(8)g12<1>F (abs)g7<8,8,1>F 3e-37F  { align1 1Q };

In this sequence, only the first cmp.z is removed.  With different
scheduling, all 3 could get removed.

Skylake
total instructions in shared programs: 14407009 -> 14400173 (-0.05%)
instructions in affected programs: 1307274 -> 1300438 (-0.52%)
helped: 4880
HURT: 0
helped stats (abs) min: 1 max: 33 x̄: 1.40 x̃: 1
helped stats (rel) min: 0.03% max: 8.70% x̄: 0.70% x̃: 0.52%
95% mean confidence interval for instructions value: -1.45 -1.35
95% mean confidence interval for instructions %-change: -0.72% -0.69%
Instructions are helped.

total cycles in shared programs: 532943169 -> 532923528 (<.01%)
cycles in affected programs: 14065798 -> 14046157 (-0.14%)
helped: 2703
HURT: 339
helped stats (abs) min: 1 max: 1062 x̄: 12.27 x̃: 2
helped stats (rel) min: <.01% max: 28.72% x̄: 0.38% x̃: 0.21%
HURT stats (abs)   min: 1 max: 739 x̄: 39.86 x̃: 12
HURT stats (rel)   min: 0.02% max: 27.69% x̄: 1.38% x̃: 0.41%
95% mean confidence interval for cycles value: -8.66 -4.26
95% mean confidence interval for cycles %-change: -0.24% -0.14%
Cycles are helped.

LOST:   0
GAINED: 1

Broadwell
total instructions in shared programs: 14719636 -> 14712949 (-0.05%)
instructions in affected programs: 1288188 -> 1281501 (-0.52%)
helped: 4845
HURT: 0
helped stats (abs) min: 1 max: 33 x̄: 1.38 x̃: 1
helped stats (rel) min: 0.03% max: 8.00% x̄: 0.70% x̃: 0.52%
95% mean confidence interval for instructions value: -1.43 -1.33
95% mean confidence interval for instructions %-change: -0.72% -0.68%
Instructions are helped.

total cycles in shared programs: 559599253 -> 559581699 (<.01%)
cycles in affected programs: 13315565 -> 13298011 (-0.13%)
helped: 2600
HURT: 269
helped stats (abs) min: 1 max: 2128 x̄: 12.24 x̃: 2
helped stats (rel) min: <.01% max: 23.95% x̄: 0.41% x̃: 0.20%
HURT stats (abs)   min: 1 max: 790 x̄: 53.07 x̃: 20
HURT stats (rel)   min: 0.02% max: 15.96% x̄: 1.55% x̃: 0.75%
95% mean confidence interval for cycles value: -8.47 -3.77
95% mean confidence interval for cycles %-change: -0.27% -0.18%
Cycles are helped.

LOST:   0
GAINED: 8

Haswell
total instructions in shared programs: 12978609 -> 12973483 (-0.04%)
instructions in affected programs: 932921 -> 927795 (-0.55%)
helped: 3480
HURT: 0
helped stats (abs) min: 1 max: 33 x̄: 1.47 x̃: 1
helped stats (rel) min: 0.03% max: 7.84% x̄: 0.78% x̃: 0.58%
95% mean confidence interval for instructions value: -1.53 -1.42
95% mean confidence interval for instructions %-change: -0.80% -0.75%
Instructions are helped.

total cycles in shared programs: 410270788 -> 410250531 (<.01%)
cycles in affected programs: 10986161 -> 10965904 (-0.18%)
helped: 2087
HURT: 254
helped stats (abs) min: 1 max: 2672 x̄: 14.63 x̃: 4
helped stats (rel) min: <.01% max: 39.61% x̄: 0.42% x̃: 0.21%
HURT stats (abs)   min: 1 max: 519 x̄: 40.49 x̃: 16
HURT stats (rel)   min: 0.01% max: 12.83% x̄: 1.20% x̃: 0.47%
95% mean confidence interval f

Mesa (master): i965/vec4: Allow cmod propagation when src0 is a uniform or shader input

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 780f307ba860e3d8f85df8d6e1e60a1d612b97d9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=780f307ba860e3d8f85df8d6e1e60a1d612b97d9

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Wed Mar 21 15:22:15 2018 -0700

i965/vec4: Allow cmod propagation when src0 is a uniform or shader input

No shader-db changes.  This source must have been written by a previous
instruction, so it cannot be a uniform or a shader input.  However, this
change allows the next commit to help more shaders.

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Alejandro Piñeiro <apinhe...@igalia.com>
Reviewed-by: Matt Turner <matts...@gmail.com>

---

 src/intel/compiler/brw_vec4_cmod_propagation.cpp | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/intel/compiler/brw_vec4_cmod_propagation.cpp 
b/src/intel/compiler/brw_vec4_cmod_propagation.cpp
index 0d72d82a57..7f1001b6d1 100644
--- a/src/intel/compiler/brw_vec4_cmod_propagation.cpp
+++ b/src/intel/compiler/brw_vec4_cmod_propagation.cpp
@@ -49,7 +49,8 @@ opt_cmod_propagation_local(bblock_t *block)
inst->opcode != BRW_OPCODE_MOV) ||
   inst->predicate != BRW_PREDICATE_NONE ||
   !inst->dst.is_null() ||
-  inst->src[0].file != VGRF ||
+  (inst->src[0].file != VGRF && inst->src[0].file != ATTR &&
+   inst->src[0].file != UNIFORM) ||
   inst->src[0].abs)
  continue;
 

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Mesa (master): i965/vec4: Fix null destination register in 3-source instructions

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 91225cb33f0baede872114bd416084b3b52937a1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=91225cb33f0baede872114bd416084b3b52937a1

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Fri Mar 23 11:46:12 2018 -0700

i965/vec4: Fix null destination register in 3-source instructions

A recent commit (see below) triggered some cases where conditional
modifier propagation and dead code elimination would cause a MAD
instruction like the following to be generated:

mad.l.f0  null, ...

Matt pointed out that fs_visitor::fixup_3src_null_dest() fixes cases
like this in the scalar backend.  This commit basically ports that code
to the vec4 backend.

NOTE: I have sent a couple tests to the piglit list that reproduce this
bug *without* the commit mentioned below.  This commit fixes those
tests.

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Matt Turner <matts...@gmail.com>
Tested-by: Tapani Pälli <tapani.pa...@intel.com>
Cc: mesa-sta...@lists.freedesktop.org
Fixes: ee63933a7 ("nir: Distribute binary operations with constants into bcsel")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105704

---

 src/intel/compiler/brw_vec4.cpp | 26 ++
 src/intel/compiler/brw_vec4.h   |  1 +
 2 files changed, 27 insertions(+)

diff --git a/src/intel/compiler/brw_vec4.cpp b/src/intel/compiler/brw_vec4.cpp
index 6680410a52..2f352a1118 100644
--- a/src/intel/compiler/brw_vec4.cpp
+++ b/src/intel/compiler/brw_vec4.cpp
@@ -1952,6 +1952,30 @@ is_align1_df(vec4_instruction *inst)
}
 }
 
+/**
+ * Three source instruction must have a GRF/MRF destination register.
+ * ARF NULL is not allowed.  Fix that up by allocating a temporary GRF.
+ */
+void
+vec4_visitor::fixup_3src_null_dest()
+{
+   bool progress = false;
+
+   foreach_block_and_inst_safe (block, vec4_instruction, inst, cfg) {
+  if (inst->is_3src(devinfo) && inst->dst.is_null()) {
+ const unsigned size_written = type_sz(inst->dst.type);
+ const unsigned num_regs = DIV_ROUND_UP(size_written, REG_SIZE);
+
+ inst->dst = retype(dst_reg(VGRF, alloc.allocate(num_regs)),
+inst->dst.type);
+ progress = true;
+  }
+   }
+
+   if (progress)
+  invalidate_live_intervals();
+}
+
 void
 vec4_visitor::convert_to_hw_regs()
 {
@@ -2703,6 +2727,8 @@ vec4_visitor::run()
   OPT(scalarize_df);
}
 
+   fixup_3src_null_dest();
+
bool allocated_without_spills = reg_allocate();
 
if (!allocated_without_spills) {
diff --git a/src/intel/compiler/brw_vec4.h b/src/intel/compiler/brw_vec4.h
index 39ce51c7dc..71880db969 100644
--- a/src/intel/compiler/brw_vec4.h
+++ b/src/intel/compiler/brw_vec4.h
@@ -158,6 +158,7 @@ public:
void opt_set_dependency_control();
void opt_schedule_instructions();
void convert_to_hw_regs();
+   void fixup_3src_null_dest();
 
bool is_supported_64bit_region(vec4_instruction *inst, unsigned arg);
bool lower_simd_width();

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Mesa (master): nir: Don't condition 'a-b < 0' -> 'a < b' on is_not_used_by_conditional

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 2c643fd978c43205b9620820038ba6246ed045e2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2c643fd978c43205b9620820038ba6246ed045e2

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Wed Mar 14 16:25:07 2018 -0700

nir: Don't condition 'a-b < 0' -> 'a < b' on is_not_used_by_conditional

Now that i965 recognizes that a-b generates the same conditions as 'a <
b', there is no reason to condition this transformation on 'is not used
by conditional.'

Since this was the only user of the is_not_used_by_conditional function,
delete it.

All Gen6+ platforms had similar results. (Skylake shown)
total instructions in shared programs: 14400775 -> 14400595 (<.01%)
instructions in affected programs: 36712 -> 36532 (-0.49%)
helped: 182
HURT: 26
helped stats (abs) min: 1 max: 2 x̄: 1.13 x̃: 1
helped stats (rel) min: 0.15% max: 1.82% x̄: 0.70% x̃: 0.62%
HURT stats (abs)   min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel)   min: 0.24% max: 1.02% x̄: 0.82% x̃: 0.90%
95% mean confidence interval for instructions value: -0.97 -0.76
95% mean confidence interval for instructions %-change: -0.59% -0.43%
Instructions are helped.

total cycles in shared programs: 532929592 -> 532926345 (<.01%)
cycles in affected programs: 478660 -> 475413 (-0.68%)
helped: 187
HURT: 22
helped stats (abs) min: 2 max: 200 x̄: 20.99 x̃: 18
helped stats (rel) min: 0.23% max: 24.10% x̄: 1.48% x̃: 1.03%
HURT stats (abs)   min: 1 max: 214 x̄: 30.86 x̃: 11
HURT stats (rel)   min: 0.01% max: 23.06% x̄: 3.12% x̃: 0.86%
95% mean confidence interval for cycles value: -19.50 -11.57
95% mean confidence interval for cycles %-change: -1.42% -0.58%
Cycles are helped.

GM45 and Iron Lake had similar results. (Iron Lake shown)
total cycles in shared programs: 177851578 -> 177851810 (<.01%)
cycles in affected programs: 24408 -> 24640 (0.95%)
helped: 2
HURT: 4
helped stats (abs) min: 4 max: 4 x̄: 4.00 x̃: 4
helped stats (rel) min: 0.42% max: 0.47% x̄: 0.44% x̃: 0.44%
HURT stats (abs)   min: 24 max: 108 x̄: 60.00 x̃: 54
HURT stats (rel)   min: 0.52% max: 1.62% x̄: 1.04% x̃: 1.02%
95% mean confidence interval for cycles value: -7.75 85.08
95% mean confidence interval for cycles %-change: -0.39% 1.49%
Inconclusive result (value mean confidence interval includes 0).

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Matt Turner <matts...@gmail.com>

---

 src/compiler/nir/nir_opt_algebraic.py |  4 +---
 src/compiler/nir/nir_search_helpers.h | 15 ---
 2 files changed, 1 insertion(+), 18 deletions(-)

diff --git a/src/compiler/nir/nir_opt_algebraic.py 
b/src/compiler/nir/nir_opt_algebraic.py
index b9565cea7b..96232f0e54 100644
--- a/src/compiler/nir/nir_opt_algebraic.py
+++ b/src/compiler/nir/nir_opt_algebraic.py
@@ -208,9 +208,7 @@ optimizations = [
# fmax.  If b is > 1.0, the bcsel will be replaced with a b2f.
(('fmin', ('b2f', a), '#b'), ('bcsel', a, ('fmin', b, 1.0), ('fmin', b, 
0.0))),
 
-   # ignore this opt when the result is used by a bcsel or if so we can make
-   # use of conditional modifiers on supported hardware.
-   (('flt(is_not_used_by_conditional)', ('fadd(is_used_once)', a, ('fneg', 
b)), 0.0), ('flt', a, b)),
+   (('flt', ('fadd(is_used_once)', a, ('fneg', b)), 0.0), ('flt', a, b)),
 
(('fge', ('fneg', ('fabs', a)), 0.0), ('feq', a, 0.0)),
(('~bcsel', ('flt', b, a), b, a), ('fmin', a, b)),
diff --git a/src/compiler/nir/nir_search_helpers.h 
b/src/compiler/nir/nir_search_helpers.h
index 2e3bd137d6..2d399bd5dc 100644
--- a/src/compiler/nir/nir_search_helpers.h
+++ b/src/compiler/nir/nir_search_helpers.h
@@ -170,19 +170,4 @@ is_not_used_by_if(nir_alu_instr *instr)
return list_empty(>dest.dest.ssa.if_uses);
 }
 
-static inline bool
-is_not_used_by_conditional(nir_alu_instr *instr)
-{
-   if (!is_not_used_by_if(instr))
-  return false;
-
-   nir_foreach_use(use, >dest.dest.ssa) {
-  if (use->parent_instr->type == nir_instr_type_alu &&
-  nir_instr_as_alu(use->parent_instr)->op == nir_op_bcsel)
- return false;
-   }
-
-   return true;
-}
-
 #endif /* _NIR_SEARCH_ */

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Mesa (master): nir: Don't compare b2f or b2i with zero

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 6aeaa7d363d45f4d09ff51ad925e893f931f502e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6aeaa7d363d45f4d09ff51ad925e893f931f502e

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Tue Mar  1 19:05:14 2016 -0800

nir: Don't compare b2f or b2i with zero

All of the shaders that had loops changed were in Tomb Raider.  The one
shader that lost SIMD16 is one of those.

Skylake
total instructions in shared programs: 14391653 -> 14390468 (<.01%)
instructions in affected programs: 111891 -> 110706 (-1.06%)
helped: 501
HURT: 0
helped stats (abs) min: 1 max: 155 x̄: 2.37 x̃: 1
helped stats (rel) min: 0.05% max: 21.54% x̄: 1.61% x̃: 1.01%
95% mean confidence interval for instructions value: -3.23 -1.50
95% mean confidence interval for instructions %-change: -1.77% -1.45%
Instructions are helped.

total cycles in shared programs: 532793024 -> 532776598 (<.01%)
cycles in affected programs: 987682 -> 971256 (-1.66%)
helped: 348
nnHURT: 41
helped stats (abs) min: 1 max: 3074 x̄: 54.91 x̃: 18
helped stats (rel) min: 0.05% max: 32.24% x̄: 3.36% x̃: 1.68%
HURT stats (abs)   min: 1 max: 422 x̄: 65.39 x̃: 24
HURT stats (rel)   min: 0.09% max: 39.29% x̄: 9.50% x̃: 2.02%
95% mean confidence interval for cycles value: -64.08 -20.38
95% mean confidence interval for cycles %-change: -2.78% -1.23%
Cycles are helped.

total loops in shared programs: 4854 -> 4829 (-0.52%)
loops in affected programs: 27 -> 2 (-92.59%)
helped: 18
HURT: 0

LOST:   1
GAINED: 0

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Timothy Arceri <tarc...@itsqueeze.com>

---

 src/compiler/nir/nir_opt_algebraic.py | 5 +
 1 file changed, 5 insertions(+)

diff --git a/src/compiler/nir/nir_opt_algebraic.py 
b/src/compiler/nir/nir_opt_algebraic.py
index c9575e6be4..b9565cea7b 100644
--- a/src/compiler/nir/nir_opt_algebraic.py
+++ b/src/compiler/nir/nir_opt_algebraic.py
@@ -183,6 +183,11 @@ optimizations = [
(('fge', ('fmin', ('fneg', ('b2f', a)), b), 0.0), ('iand', ('inot', a), 
('fge', b, 0.0))),
(('feq', ('fmin', ('fneg', ('b2f', a)), b), 0.0), ('iand', ('inot', a), 
('fge', b, 0.0))),
 
+   (('feq', ('b2f', a), 0.0), ('inot', a)),
+   (('fne', ('b2f', a), 0.0), a),
+   (('ieq', ('b2i', a), 0),   ('inot', a)),
+   (('ine', ('b2i', a), 0),   a),
+
# 0.0 < fabs(a)
# fabs(a) > 0.0
# fabs(a) != 0.0 because fabs(a) must be >= 0

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Mesa (master): mesa: Don't write to user buffer in glGetTexParameterIuiv on error

[Ian Romanick]

Module: Mesa
Branch: master
Commit: def0030e64dd3a4eb3487dd40bf64b9a71a70af3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=def0030e64dd3a4eb3487dd40bf64b9a71a70af3

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Wed Mar  7 21:05:34 2018 -0800

mesa: Don't write to user buffer in glGetTexParameterIuiv on error

With some sets of optimization flags, GCC will generate warnings like
this:

src/mesa/main/texparam.c:2327:27: warning: ‘*((void *)+12)’ may be used 
uninitialized in this function [-Wmaybe-uninitialized]
 params[3] = ip[3];
 ~~^~~
src/mesa/main/texparam.c:2320:16: note: ‘*((void *)+12)’ was declared here
  GLint ip[4];
^~

ip is not initialized in cases where a GL error is generated.  In these
cases, we should *not* write to the user's buffer, so this is actually a
bug.  I wrote a new piglit test gl-3.0-texparameteri to show this bug.

I suspect that Coverity also detected this, but the scan site is
currently down.

Fixes: c2c507786 "main: Added entry points for glGetTextureParameteriv, Iiv, 
and Iuiv."
Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Matt Turner <matts...@gmail.com>

---

 src/mesa/main/texparam.c | 28 ++--
 1 file changed, 2 insertions(+), 26 deletions(-)

diff --git a/src/mesa/main/texparam.c b/src/mesa/main/texparam.c
index 7cc9d9e8fa..301407e738 100644
--- a/src/mesa/main/texparam.c
+++ b/src/mesa/main/texparam.c
@@ -2306,30 +2306,6 @@ get_tex_parameterIiv(struct gl_context *ctx,
}
 }
 
-static void
-get_tex_parameterIuiv(struct gl_context *ctx,
-  struct gl_texture_object *obj,
-  GLenum pname, GLuint *params, bool dsa)
-{
-   switch (pname) {
-   case GL_TEXTURE_BORDER_COLOR:
-  COPY_4V(params, obj->Sampler.BorderColor.i);
-  break;
-   default:
-  {
- GLint ip[4];
- get_tex_parameteriv(ctx, obj, pname, ip, dsa);
- params[0] = ip[0];
- if (pname == GL_TEXTURE_SWIZZLE_RGBA_EXT ||
- pname == GL_TEXTURE_CROP_RECT_OES) {
-params[1] = ip[1];
-params[2] = ip[2];
-params[3] = ip[3];
- }
-  }
-   }
-}
-
 void GLAPIENTRY
 _mesa_GetTexParameterfv(GLenum target, GLenum pname, GLfloat *params)
 {
@@ -2382,7 +2358,7 @@ _mesa_GetTexParameterIuiv(GLenum target, GLenum pname, 
GLuint *params)
if (!texObj)
   return;
 
-   get_tex_parameterIuiv(ctx, texObj, pname, params, false);
+   get_tex_parameterIiv(ctx, texObj, pname, (GLint *) params, false);
 }
 
 
@@ -2436,5 +2412,5 @@ _mesa_GetTextureParameterIuiv(GLuint texture, GLenum 
pname, GLuint *params)
if (!texObj)
   return;
 
-   get_tex_parameterIuiv(ctx, texObj, pname, params, true);
+   get_tex_parameterIiv(ctx, texObj, pname, (GLint *) params, true);
 }

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Mesa (master): i965/fs: Add infrastructure for generating CSEL instructions.

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 70de61594dcf99f24eb31ebf98d62f13e1f44c2e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=70de61594dcf99f24eb31ebf98d62f13e1f44c2e

Author: Kenneth Graunke <kenn...@whitecape.org>
Date:   Sun Nov 22 20:12:17 2015 -0800

i965/fs: Add infrastructure for generating CSEL instructions.

v2 (idr): Don't allow CSEL with a non-float src2.

v3 (idr): Add CSEL to fs_inst::flags_written.  Suggested by Matt.

v4 (idr): Only set BRW_ALIGN_16 on Gen < 10 (suggested by Matt).  Don't
reset the access mode afterwards (suggested by Samuel and Matt).  Add
support for CSEL not modifying the flags to more places (requested by
Matt).

Signed-off-by: Kenneth Graunke <kenn...@whitecape.org>
Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> [v3]
Reviewed-by: Matt Turner <matts...@gmail.com>

---

 src/intel/compiler/brw_disasm.c |  1 +
 src/intel/compiler/brw_eu.h |  1 +
 src/intel/compiler/brw_eu_emit.c|  1 +
 src/intel/compiler/brw_fs.cpp   |  2 ++
 src/intel/compiler/brw_fs_builder.h | 22 +-
 src/intel/compiler/brw_fs_generator.cpp |  6 ++
 src/intel/compiler/brw_ir_vec4.h|  1 +
 src/intel/compiler/brw_vec4.cpp |  1 +
 8 files changed, 34 insertions(+), 1 deletion(-)

diff --git a/src/intel/compiler/brw_disasm.c b/src/intel/compiler/brw_disasm.c
index a9a108f8ac..5f75c67942 100644
--- a/src/intel/compiler/brw_disasm.c
+++ b/src/intel/compiler/brw_disasm.c
@@ -1508,6 +1508,7 @@ brw_disassemble_inst(FILE *file, const struct 
gen_device_info *devinfo,
*/
   if (brw_inst_cond_modifier(devinfo, inst) &&
   (devinfo->gen < 6 || (opcode != BRW_OPCODE_SEL &&
+opcode != BRW_OPCODE_CSEL &&
 opcode != BRW_OPCODE_IF &&
 opcode != BRW_OPCODE_WHILE))) {
  format(file, ".f%"PRIu64,
diff --git a/src/intel/compiler/brw_eu.h b/src/intel/compiler/brw_eu.h
index a5f28d8fc6..ca72666a55 100644
--- a/src/intel/compiler/brw_eu.h
+++ b/src/intel/compiler/brw_eu.h
@@ -171,6 +171,7 @@ ALU2(SHR)
 ALU2(SHL)
 ALU1(DIM)
 ALU2(ASR)
+ALU3(CSEL)
 ALU1(F32TO16)
 ALU1(F16TO32)
 ALU2(ADD)
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index f8102e014e..f039af56d0 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -959,6 +959,7 @@ ALU2(SHR)
 ALU2(SHL)
 ALU1(DIM)
 ALU2(ASR)
+ALU3(CSEL)
 ALU1(FRC)
 ALU1(RNDD)
 ALU2(MAC)
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 53ba94..02a8ea0fd9 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -945,6 +945,7 @@ unsigned
 fs_inst::flags_written() const
 {
if ((conditional_mod && (opcode != BRW_OPCODE_SEL &&
+opcode != BRW_OPCODE_CSEL &&
 opcode != BRW_OPCODE_IF &&
 opcode != BRW_OPCODE_WHILE)) ||
opcode == FS_OPCODE_MOV_DISPATCH_TO_FLAGS ||
@@ -5578,6 +5579,7 @@ fs_visitor::dump_instruction(backend_instruction 
*be_inst, FILE *file)
   fprintf(file, "%s", conditional_modifier[inst->conditional_mod]);
   if (!inst->predicate &&
   (devinfo->gen < 5 || (inst->opcode != BRW_OPCODE_SEL &&
+inst->opcode != BRW_OPCODE_CSEL &&
 inst->opcode != BRW_OPCODE_IF &&
 inst->opcode != BRW_OPCODE_WHILE))) {
  fprintf(file, ".f%d.%d", inst->flag_subreg / 2,
diff --git a/src/intel/compiler/brw_fs_builder.h 
b/src/intel/compiler/brw_fs_builder.h
index cf603b0c86..4203c8c27c 100644
--- a/src/intel/compiler/brw_fs_builder.h
+++ b/src/intel/compiler/brw_fs_builder.h
@@ -567,7 +567,6 @@ namespace brw {
   ALU1(BFREV)
   ALU1(CBIT)
   ALU2(CMPN)
-  ALU3(CSEL)
   ALU1(DIM)
   ALU2(DP2)
   ALU2(DP3)
@@ -643,6 +642,27 @@ namespace brw {
   }
 
   /**
+   * CSEL: dst = src2  0.0f ? src0 : src1
+   */
+  instruction *
+  CSEL(const dst_reg , const src_reg , const src_reg ,
+   const src_reg , brw_conditional_mod condition) const
+  {
+ /* CSEL only operates on floats, so we can't do integer =/>
+  * comparisons.  Zero/non-zero (== and !=) comparisons almost work.
+  * 0x8000 fails because it is -0.0, and -0.0 == 0.0.
+  */
+ assert(src2.type == BRW_REGISTER_TYPE_F);
+
+ return set_condmod(condition,
+emit(BRW_OPCODE_CSEL,
+ retype(dst, BRW_REGISTER_TYPE_F),
+ retype(src0, BRW_REGIS

Mesa (master): i965/vec4: Allow CSE on subset VF constant loads

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 1583f49eaae0292eba1a04e67125bb4b92b33b0a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1583f49eaae0292eba1a04e67125bb4b92b33b0a

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Fri Feb 16 17:33:13 2018 -0800

i965/vec4: Allow CSE on subset VF constant loads

v2: Rewrite the code that generates the VF mask.  Suggested by Ken.

No changes on other platforms.

Haswell, Ivy Bridge, and Sandy Bridge had similar results. (Haswell shown)
total instructions in shared programs: 13059891 -> 13059884 (<.01%)
instructions in affected programs: 431 -> 424 (-1.62%)
helped: 7
HURT: 0
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 1.19% max: 5.26% x̄: 2.05% x̃: 1.49%
95% mean confidence interval for instructions value: -1.00 -1.00
95% mean confidence interval for instructions %-change: -3.39% -0.71%
Instructions are helped.

total cycles in shared programs: 409260032 -> 409260018 (<.01%)
cycles in affected programs: 4228 -> 4214 (-0.33%)
helped: 7
HURT: 0
helped stats (abs) min: 2 max: 2 x̄: 2.00 x̃: 2
helped stats (rel) min: 0.28% max: 2.04% x̄: 0.54% x̃: 0.28%
95% mean confidence interval for cycles value: -2.00 -2.00
95% mean confidence interval for cycles %-change: -1.15% 0.07%

Inconclusive result (%-change mean confidence interval includes 0).

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>

---

 src/intel/compiler/brw_vec4_cse.cpp | 19 +++
 1 file changed, 19 insertions(+)

diff --git a/src/intel/compiler/brw_vec4_cse.cpp 
b/src/intel/compiler/brw_vec4_cse.cpp
index d9f08c9631..c9cf54c6f7 100644
--- a/src/intel/compiler/brw_vec4_cse.cpp
+++ b/src/intel/compiler/brw_vec4_cse.cpp
@@ -104,6 +104,25 @@ operands_match(const vec4_instruction *a, const 
vec4_instruction *b)
   return xs[0].equals(ys[0]) &&
  ((xs[1].equals(ys[1]) && xs[2].equals(ys[2])) ||
   (xs[2].equals(ys[1]) && xs[1].equals(ys[2])));
+   } else if (a->opcode == BRW_OPCODE_MOV &&
+  xs[0].file == IMM &&
+  xs[0].type == BRW_REGISTER_TYPE_VF) {
+  src_reg tmp_x = xs[0];
+  src_reg tmp_y = ys[0];
+
+  /* Smash out the values that are not part of the writemask.  Otherwise
+   * the equals operator will fail due to mismatches in unused components.
+   */
+  const unsigned ab_writemask = a->dst.writemask & b->dst.writemask;
+  const uint32_t mask = ((ab_writemask & WRITEMASK_X) ? 0x00ff : 0) |
+((ab_writemask & WRITEMASK_Y) ? 0xff00 : 0) |
+((ab_writemask & WRITEMASK_Z) ? 0x00ff : 0) |
+((ab_writemask & WRITEMASK_W) ? 0xff00 : 0);
+
+  tmp_x.ud &= mask;
+  tmp_y.ud &= mask;
+
+  return tmp_x.equals(tmp_y);
} else if (!a->is_commutative()) {
   return xs[0].equals(ys[0]) && xs[1].equals(ys[1]) && xs[2].equals(ys[2]);
} else {

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Mesa (master): nir: Don't i2b a value that is already Boolean

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 6878c9aabc6077e6de75b269fdfb8ff423d05042
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6878c9aabc6077e6de75b269fdfb8ff423d05042

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Wed Feb 21 18:15:52 2018 -0800

nir: Don't i2b a value that is already Boolean

A bunch of shaders have sequences like:

i2b(u2i(floatBitsToUint(intBitsToFloat(x == y ? -1 : 0

Other optimizations (and NIR's typeless nature) reduce this to

i2b(x == y)

which is silly.

Skylake
total instructions in shared programs: 14498698 -> 14497948 (<.01%)
instructions in affected programs: 74480 -> 73730 (-1.01%)
helped: 277
HURT: 0
helped stats (abs) min: 1 max: 32 x̄: 2.71 x̃: 2
helped stats (rel) min: 0.04% max: 13.79% x̄: 1.45% x̃: 0.68%
95% mean confidence interval for instructions value: -3.35 -2.06
95% mean confidence interval for instructions %-change: -1.74% -1.16%
Instructions are helped.

total cycles in shared programs: 532015500 -> 531999238 (<.01%)
cycles in affected programs: 5943878 -> 5927616 (-0.27%)
helped: 251
HURT: 74
helped stats (abs) min: 1 max: 13149 x̄: 127.89 x̃: 14
helped stats (rel) min: 0.01% max: 17.31% x̄: 1.55% x̃: 0.53%
HURT stats (abs)   min: 1 max: 4550 x̄: 214.04 x̃: 15
HURT stats (rel)   min: <.01% max: 44.43% x̄: 2.81% x̃: 0.33%
95% mean confidence interval for cycles value: -158.51 58.43
95% mean confidence interval for cycles %-change: -1.07% -0.04%
Inconclusive result (value mean confidence interval includes 0).

total loops in shared programs: 4753 -> 4735 (-0.38%)
loops in affected programs: 18 -> 0
helped: 18
HURT: 0
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 100.00% max: 100.00% x̄: 100.00% x̃: 100.00%
95% mean confidence interval for loops value: -1.00 -1.00
95% mean confidence interval for loops %-change: -100.00% -100.00%
Loops are helped.

Haswell and Broadwell had simliar results. (Broadwell shown)
total instructions in shared programs: 14791877 -> 14791127 (<.01%)
instructions in affected programs: 77326 -> 76576 (-0.97%)
helped: 278
HURT: 1
helped stats (abs) min: 1 max: 32 x̄: 2.70 x̃: 2
helped stats (rel) min: 0.04% max: 13.79% x̄: 1.42% x̃: 0.68%
HURT stats (abs)   min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel)   min: 0.49% max: 0.49% x̄: 0.49% x̃: 0.49%
95% mean confidence interval for instructions value: -3.33 -2.05
95% mean confidence interval for instructions %-change: -1.70% -1.13%
Instructions are helped.

total cycles in shared programs: 558250067 -> 558252872 (<.01%)
cycles in affected programs: 5806328 -> 5809133 (0.05%)
helped: 235
HURT: 83
helped stats (abs) min: 1 max: 10630 x̄: 81.73 x̃: 16
helped stats (rel) min: 0.03% max: 18.58% x̄: 1.60% x̃: 0.51%
HURT stats (abs)   min: 1 max: 10590 x̄: 265.19 x̃: 20
HURT stats (rel)   min: <.01% max: 15.28% x̄: 1.89% x̃: 0.54%
95% mean confidence interval for cycles value: -89.87 107.51
95% mean confidence interval for cycles %-change: -1.06% -0.32%
Inconclusive result (value mean confidence interval includes 0).

total loops in shared programs: 4735 -> 4717 (-0.38%)
loops in affected programs: 18 -> 0
helped: 18
HURT: 0
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 100.00% max: 100.00% x̄: 100.00% x̃: 100.00%
95% mean confidence interval for loops value: -1.00 -1.00
95% mean confidence interval for loops %-change: -100.00% -100.00%
Loops are helped.

total fills in shared programs: 83111 -> 83110 (<.01%)
fills in affected programs: 28 -> 27 (-3.57%)
helped: 1
HURT: 0

Ivy Bridge
total instructions in shared programs: 11774173 -> 11773436 (<.01%)
instructions in affected programs: 70819 -> 70082 (-1.04%)
helped: 267
HURT: 0
helped stats (abs) min: 1 max: 48 x̄: 2.76 x̃: 2
helped stats (rel) min: 0.21% max: 19.51% x̄: 1.57% x̃: 0.63%
95% mean confidence interval for instructions value: -3.51 -2.01
95% mean confidence interval for instructions %-change: -1.94% -1.21%
Instructions are helped.

total cycles in shared programs: 257153833 -> 257148932 (<.01%)
cycles in affected programs: 585341 -> 580440 (-0.84%)
helped: 167
HURT: 100
helped stats (abs) min: 1 max: 1327 x̄: 44.89 x̃: 16
helped stats (rel) min: 0.04% max: 26.54% x̄: 2.41% x̃: 0.88%
HURT stats (abs)   min: 1 max: 200 x̄: 25.95 x̃: 16
HURT stats (rel)   min: 0.04% max: 9.81% x̄: 1.34% x̃: 0.65%
95% mean confidence interval for cycles value: -33.25 -3.46
95% mean confidence interval for cycles %-change: -1.47% -0.54%
Cycles are helped.

total loops in shared programs: 3416 -> 3398 (-0.53%)
loops in affected programs: 18 -> 0
helped: 18
HURT: 0
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 100.00% max: 100.00% x̄: 100.00% x̃: 100.00%
95% mean confidence interval for loops value: -1.00 -1.00
95% mean confidence interval for loops %-change: -100.00% -100.00%
Loops are helped.

LOST:   2
GAINED: 0

Sandy Bridge
total instructions in shared 

Mesa (master): nir: Narrow some dot product operations

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 54e8d2268de37f320b2d206295d0b519f5be5ab7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=54e8d2268de37f320b2d206295d0b519f5be5ab7

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Thu Feb 15 14:49:55 2018 -0800

nir: Narrow some dot product operations

On vector platforms, this helps elide some constant loads.

v2: Reorder the transformations.

No changes on Broadwell or Skylake.

Haswell
total instructions in shared programs: 13093793 -> 13060163 (-0.26%)
instructions in affected programs: 1277532 -> 1243902 (-2.63%)
helped: 13216
HURT: 95
helped stats (abs) min: 1 max: 18 x̄: 2.56 x̃: 2
helped stats (rel) min: 0.21% max: 20.00% x̄: 3.63% x̃: 2.78%
HURT stats (abs)   min: 1 max: 6 x̄: 1.77 x̃: 1
HURT stats (rel)   min: 0.09% max: 5.56% x̄: 1.25% x̃: 1.19%
95% mean confidence interval for instructions value: -2.57 -2.49
95% mean confidence interval for instructions %-change: -3.65% -3.54%
Instructions are helped.

total cycles in shared programs: 409580819 -> 409268463 (-0.08%)
cycles in affected programs: 71730652 -> 71418296 (-0.44%)
helped: 9898
HURT: 2352
helped stats (abs) min: 2 max: 16014 x̄: 37.08 x̃: 16
helped stats (rel) min: <.01% max: 35.55% x̄: 6.26% x̃: 4.50%
HURT stats (abs)   min: 2 max: 276 x̄: 23.25 x̃: 6
HURT stats (rel)   min: <.01% max: 40.00% x̄: 3.54% x̃: 1.97%
95% mean confidence interval for cycles value: -33.19 -17.80
95% mean confidence interval for cycles %-change: -4.50% -4.26%
Cycles are helped.

total fills in shared programs: 82059 -> 82052 (<.01%)
fills in affected programs: 21 -> 14 (-33.33%)
helped: 7
HURT: 0

Sandy Bridge and Ivy Bridge had similar results (Ivy Bridge shown)
total instructions in shared programs: 11811851 -> 11780605 (-0.26%)
instructions in affected programs: 1155007 -> 1123761 (-2.71%)
helped: 12304
HURT: 95
helped stats (abs) min: 1 max: 18 x̄: 2.55 x̃: 2
helped stats (rel) min: 0.21% max: 20.00% x̄: 3.69% x̃: 2.86%
HURT stats (abs)   min: 1 max: 6 x̄: 1.77 x̃: 1
HURT stats (rel)   min: 0.09% max: 5.56% x̄: 1.25% x̃: 1.19%
95% mean confidence interval for instructions value: -2.56 -2.48
95% mean confidence interval for instructions %-change: -3.71% -3.59%
Instructions are helped.

total cycles in shared programs: 257618409 -> 257316805 (-0.12%)
cycles in affected programs: 71999580 -> 71697976 (-0.42%)
helped: 9155
HURT: 2380
helped stats (abs) min: 2 max: 16014 x̄: 38.44 x̃: 16
helped stats (rel) min: <.01% max: 35.75% x̄: 6.39% x̃: 4.62%
HURT stats (abs)   min: 2 max: 290 x̄: 21.14 x̃: 4
HURT stats (rel)   min: <.01% max: 41.55% x̄: 3.14% x̃: 1.33%
95% mean confidence interval for cycles value: -34.32 -17.97
95% mean confidence interval for cycles %-change: -4.55% -4.29%
Cycles are helped.

GM45 and Iron Lake had nearly identical results (Iron Lake shown)
total instructions in shared programs: 7886750 -> 7879944 (-0.09%)
instructions in affected programs: 373781 -> 366975 (-1.82%)
helped: 3715
HURT: 47
helped stats (abs) min: 1 max: 8 x̄: 1.86 x̃: 1
helped stats (rel) min: 0.22% max: 16.67% x̄: 2.88% x̃: 2.06%
HURT stats (abs)   min: 1 max: 6 x̄: 2.55 x̃: 2
HURT stats (rel)   min: 1.09% max: 5.00% x̄: 1.93% x̃: 2.35%
95% mean confidence interval for instructions value: -1.85 -1.77
95% mean confidence interval for instructions %-change: -2.91% -2.73%
Instructions are helped.

total cycles in shared programs: 178114636 -> 178095452 (-0.01%)
cycles in affected programs: 7227666 -> 7208482 (-0.27%)
helped: 3349
HURT: 301
helped stats (abs) min: 2 max: 90 x̄: 6.55 x̃: 4
helped stats (rel) min: <.01% max: 14.18% x̄: 0.95% x̃: 0.63%
HURT stats (abs)   min: 2 max: 42 x̄: 9.13 x̃: 10
HURT stats (rel)   min: 0.01% max: 11.19% x̄: 1.22% x̃: 1.50%
95% mean confidence interval for cycles value: -5.52 -4.99
95% mean confidence interval for cycles %-change: -0.81% -0.73%
Cycles are helped.

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> [v1]

---

 src/compiler/nir/nir_opt_algebraic.py | 8 
 1 file changed, 8 insertions(+)

diff --git a/src/compiler/nir/nir_opt_algebraic.py 
b/src/compiler/nir/nir_opt_algebraic.py
index e500a31d8e..c42b72eedd 100644
--- a/src/compiler/nir/nir_opt_algebraic.py
+++ b/src/compiler/nir/nir_opt_algebraic.py
@@ -125,6 +125,14 @@ optimizations = [
(('ffma', a, b, c), ('fadd', ('fmul', a, b), c), 'options->lower_ffma'),
(('~fadd', ('fmul', a, b), c), ('ffma', a, b, c), 'options->fuse_ffma'),
 
+   (('fdot4', ('vec4', a, b,   c,   1.0), d), ('fdph',  ('vec3', a, b, c), d)),
+   (('fdot4', ('vec4', a, 0.0, 0.0, 0.0), b), ('fmul', a, b)),
+   (('fdot4', ('vec4', a, b,   0.0, 0.0), c), ('fdot2', ('vec2', a, b), c)),
+   (('fdot4', ('vec4', a, b,   c,   0.0), d), ('fdot3', ('vec3', a, b, c), d)),
+
+   (('fdot3', ('vec3', a, 0.0, 0.0), b), ('fmul', a, b)),
+   (('fdot3', ('vec3', a, b,   0.0), c), ('fdot2', ('vec2', a, b),

Mesa (master): i965/fs: Merge CMP and SEL into CSEL on Gen8+

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 52c7df1643ec9af119fd66f916f7fbdbcc798d2d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=52c7df1643ec9af119fd66f916f7fbdbcc798d2d

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Wed Feb 21 18:06:56 2018 -0800

i965/fs: Merge CMP and SEL into CSEL on Gen8+

v2: Fix several problems handling inverted predicates.  Add a much
bigger comment around the BRW_CONDITIONAL_NZ case.

v3: Allow uniforms and shader inputs as sources for the original SEL and
CMP instructions.  This enables a LOT more shaders to receive CSEL
merging (5816 vs 8564 on SKL).

v4: Report progress.

Broadwell and Skylake had similar results. (Broadwell shown)
helped: 8527
HURT: 0
helped stats (abs) min: 1 max: 27 x̄: 2.44 x̃: 1
helped stats (rel) min: 0.03% max: 17.80% x̄: 1.12% x̃: 0.70%
95% mean confidence interval for instructions value: -2.51 -2.36
95% mean confidence interval for instructions %-change: -1.15% -1.10%
Instructions are helped.

total cycles in shared programs: 559442317 -> 558288357 (-0.21%)
cycles in affected programs: 372699860 -> 371545900 (-0.31%)
helped: 6748
HURT: 1450
helped stats (abs) min: 1 max: 32000 x̄: 182.41 x̃: 12
helped stats (rel) min: <.01% max: 66.08% x̄: 3.42% x̃: 0.70%
HURT stats (abs)   min: 1 max: 2538 x̄: 53.08 x̃: 14
HURT stats (rel)   min: <.01% max: 96.72% x̄: 3.32% x̃: 0.90%
95% mean confidence interval for cycles value: -179.01 -102.51
95% mean confidence interval for cycles %-change: -2.37% -2.08%
Cycles are helped.

LOST:   0
GAINED: 6

No changes on earlier platforms.

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> [v1]
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> [v3]
Reviewed-by: Matt Turner <matts...@gmail.com>

---

 src/intel/compiler/brw_fs.cpp | 106 ++
 src/intel/compiler/brw_fs.h   |   1 +
 2 files changed, 107 insertions(+)

diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 02a8ea0fd9..422eedcf0a 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -2844,6 +2844,106 @@ mask_relative_to(const fs_reg , const fs_reg , 
unsigned ds)
 }
 
 bool
+fs_visitor::opt_peephole_csel()
+{
+   if (devinfo->gen < 8)
+  return false;
+
+   bool progress = false;
+
+   foreach_block_reverse(block, cfg) {
+  int ip = block->end_ip + 1;
+
+  foreach_inst_in_block_reverse_safe(fs_inst, inst, block) {
+ ip--;
+
+ if (inst->opcode != BRW_OPCODE_SEL ||
+ inst->predicate != BRW_PREDICATE_NORMAL ||
+ (inst->dst.type != BRW_REGISTER_TYPE_F &&
+  inst->dst.type != BRW_REGISTER_TYPE_D &&
+  inst->dst.type != BRW_REGISTER_TYPE_UD))
+continue;
+
+ /* Because it is a 3-src instruction, CSEL cannot have an immediate
+  * value as a source, but we can sometimes handle zero.
+  */
+ if ((inst->src[0].file != VGRF && inst->src[0].file != ATTR &&
+  inst->src[0].file != UNIFORM) ||
+ (inst->src[1].file != VGRF && inst->src[1].file != ATTR &&
+  inst->src[1].file != UNIFORM && !inst->src[1].is_zero()))
+continue;
+
+ foreach_inst_in_block_reverse_starting_from(fs_inst, scan_inst, inst) 
{
+if (!scan_inst->flags_written())
+   continue;
+
+if ((scan_inst->opcode != BRW_OPCODE_CMP &&
+ scan_inst->opcode != BRW_OPCODE_MOV) ||
+scan_inst->predicate != BRW_PREDICATE_NONE ||
+(scan_inst->src[0].file != VGRF &&
+ scan_inst->src[0].file != ATTR &&
+ scan_inst->src[0].file != UNIFORM) ||
+scan_inst->src[0].type != BRW_REGISTER_TYPE_F)
+   break;
+
+if (scan_inst->opcode == BRW_OPCODE_CMP && 
!scan_inst->src[1].is_zero())
+   break;
+
+const brw::fs_builder ibld(this, block, inst);
+
+const enum brw_conditional_mod cond =
+   inst->predicate_inverse
+   ? brw_negate_cmod(scan_inst->conditional_mod)
+   : scan_inst->conditional_mod;
+
+fs_inst *csel_inst = NULL;
+
+if (inst->src[1].file != IMM) {
+   csel_inst = ibld.CSEL(inst->dst,
+ inst->src[0],
+ inst->src[1],
+ scan_inst->src[0],
+ cond);
+} else if (cond == BRW_CONDITIONAL_NZ) {
+   /* Consider the sequence
+*
+* cmp.nz.f0  null<1>F   g3<8,8,1>F   0F
+* (+f0) sel  g

Mesa (master): i965/vec4: Relax writemask condition in CSE

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 360899d4577a2431dc73b5c702d60ac6bd59ca07
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=360899d4577a2431dc73b5c702d60ac6bd59ca07

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Fri Feb 16 17:26:11 2018 -0800

i965/vec4: Relax writemask condition in CSE

If the previously seen instruction generates more fields than the new
instruction, still allow CSE to happen.  This doesn't do much, but it
also enables a couple more shaders in the next patch.  It helped quite a
bit in another change series that I have (at least for now) abandoned.

v2: Add some extra comentary about the parameters to instructions_match.
Suggested by Ken.

No changes on Skylake, Broadwell, Iron Lake or GM45.

Ivy Bridge and Haswell had similar results. (Ivy Bridge shown)
total instructions in shared programs: 11780295 -> 11780294 (<.01%)
instructions in affected programs: 302 -> 301 (-0.33%)
helped: 1
HURT: 0

total cycles in shared programs: 257308315 -> 257308313 (<.01%)
cycles in affected programs: 2074 -> 2072 (-0.10%)
helped: 1
HURT: 0

Sandy Bridge
total instructions in shared programs: 10506687 -> 10506686 (<.01%)
instructions in affected programs: 335 -> 334 (-0.30%)
helped: 1
HURT: 0

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>

---

 src/intel/compiler/brw_vec4_cse.cpp | 10 +-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/src/intel/compiler/brw_vec4_cse.cpp 
b/src/intel/compiler/brw_vec4_cse.cpp
index 2e65ef7854..d9f08c9631 100644
--- a/src/intel/compiler/brw_vec4_cse.cpp
+++ b/src/intel/compiler/brw_vec4_cse.cpp
@@ -112,6 +112,14 @@ operands_match(const vec4_instruction *a, const 
vec4_instruction *b)
}
 }
 
+/**
+ * Checks if instructions match, exactly for sources, but loosely for
+ * destination writemasks.
+ *
+ * \param 'a' is the generating expression from the AEB entry.
+ * \param 'b' is the second occurrence of the expression that we're
+ *considering eliminating.
+ */
 static bool
 instructions_match(vec4_instruction *a, vec4_instruction *b)
 {
@@ -127,7 +135,7 @@ instructions_match(vec4_instruction *a, vec4_instruction *b)
   a->base_mrf == b->base_mrf &&
   a->header_size == b->header_size &&
   a->shadow_compare == b->shadow_compare &&
-  a->dst.writemask == b->dst.writemask &&
+  ((a->dst.writemask & b->dst.writemask) == a->dst.writemask) &&
   a->force_writemask_all == b->force_writemask_all &&
   a->size_written == b->size_written &&
   a->exec_size == b->exec_size &&

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Mesa (master): nir: Simplify some comparisons like a+b < a

[Ian Romanick]

Module: Mesa
Branch: master
Commit: e3ea166a2c5d2bfcea54c08898c940c4abfb3537
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e3ea166a2c5d2bfcea54c08898c940c4abfb3537

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Mon Feb 12 18:58:53 2018 -0800

nir: Simplify some comparisons like a+b < a

All Gen7+ platforms had similar results. (Skylake shown)
total instructions in shared programs: 14514555 -> 14514547 (<.01%)
instructions in affected programs: 1972 -> 1964 (-0.41%)
helped: 8
HURT: 0
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 0.39% max: 0.42% x̄: 0.41% x̃: 0.41%
95% mean confidence interval for instructions value: -1.00 -1.00
95% mean confidence interval for instructions %-change: -0.41% -0.40%
Instructions are helped.

total cycles in shared programs: 533141444 -> 533136780 (<.01%)
cycles in affected programs: 164728 -> 160064 (-2.83%)
helped: 181
HURT: 3
helped stats (abs) min: 2 max: 94 x̄: 26.17 x̃: 30
helped stats (rel) min: 0.12% max: 5.33% x̄: 3.42% x̃: 3.80%
HURT stats (abs)   min: 4 max: 54 x̄: 24.00 x̃: 14
HURT stats (rel)   min: 0.20% max: 2.39% x̄: 1.09% x̃: 0.68%
95% mean confidence interval for cycles value: -27.12 -23.58
95% mean confidence interval for cycles %-change: -3.54% -3.16%
Cycles are helped.

Sandy Bridge
total instructions in shared programs: 10533667 -> 10533539 (<.01%)
instructions in affected programs: 10148 -> 10020 (-1.26%)
helped: 124
HURT: 0
helped stats (abs) min: 1 max: 2 x̄: 1.03 x̃: 1
helped stats (rel) min: 0.39% max: 4.35% x̄: 2.20% x̃: 2.04%
95% mean confidence interval for instructions value: -1.06 -1.00
95% mean confidence interval for instructions %-change: -2.46% -1.95%
Instructions are helped.

total cycles in shared programs: 146136887 -> 146132122 (<.01%)
cycles in affected programs: 206382 -> 201617 (-2.31%)
helped: 171
HURT: 0
helped stats (abs) min: 2 max: 40 x̄: 27.87 x̃: 30
helped stats (rel) min: 0.08% max: 5.73% x̄: 2.98% x̃: 2.67%
95% mean confidence interval for cycles value: -29.19 -26.54
95% mean confidence interval for cycles %-change: -3.20% -2.76%
Cycles are helped.

Iron Lake
total instructions in shared programs: 7886515 -> 7886507 (<.01%)
instructions in affected programs: 3016 -> 3008 (-0.27%)
helped: 8
HURT: 0
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 0.25% max: 0.28% x̄: 0.27% x̃: 0.27%
95% mean confidence interval for instructions value: -1.00 -1.00
95% mean confidence interval for instructions %-change: -0.27% -0.26%
Instructions are helped.

total cycles in shared programs: 178100396 -> 178100388 (<.01%)
cycles in affected programs: 156128 -> 156120 (<.01%)
helped: 4
HURT: 4
helped stats (abs) min: 4 max: 4 x̄: 4.00 x̃: 4
helped stats (rel) min: 0.02% max: 0.04% x̄: 0.03% x̃: 0.03%
HURT stats (abs)   min: 2 max: 2 x̄: 2.00 x̃: 2
HURT stats (rel)   min: <.01% max: 0.01% x̄: <.01% x̃: <.01%
95% mean confidence interval for cycles value: -3.68 1.68
95% mean confidence interval for cycles %-change: -0.03% <.01%
Inconclusive result (value mean confidence interval includes 0).

GM45
total instructions in shared programs: 4857872 -> 4857868 (<.01%)
instructions in affected programs: 1544 -> 1540 (-0.26%)
helped: 4
HURT: 0
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 0.25% max: 0.27% x̄: 0.26% x̃: 0.26%
95% mean confidence interval for instructions value: -1.00 -1.00
95% mean confidence interval for instructions %-change: -0.28% -0.24%
Instructions are helped.

total cycles in shared programs: 122167654 -> 122167662 (<.01%)
cycles in affected programs: 96248 -> 96256 (<.01%)
helped: 0
HURT: 4
HURT stats (abs)   min: 2 max: 2 x̄: 2.00 x̃: 2
HURT stats (rel)   min: <.01% max: 0.01% x̄: <.01% x̃: <.01%
95% mean confidence interval for cycles value: 2.00 2.00
95% mean confidence interval for cycles %-change: <.01% 0.02%
Cycles are HURT.

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com>

---

 src/compiler/nir/nir_opt_algebraic.py | 9 +
 1 file changed, 9 insertions(+)

diff --git a/src/compiler/nir/nir_opt_algebraic.py 
b/src/compiler/nir/nir_opt_algebraic.py
index f6800b419b..e500a31d8e 100644
--- a/src/compiler/nir/nir_opt_algebraic.py
+++ b/src/compiler/nir/nir_opt_algebraic.py
@@ -153,6 +153,15 @@ optimizations = [
 
(('fge', ('fneg', ('b2f', a)), 0.0), ('inot', a)),
 
+   (('~flt', ('fadd', a, b), a), ('flt', b, 0.0)),
+   (('~fge', ('fadd', a, b), a), ('fge', b, 0.0)),
+   (('~feq', ('fadd', a, b), a), ('feq', b, 0.0)),
+   (('~fne', ('fadd', a, b), a), ('fne', b, 0.0)),
+
+   # Cannot remove the addition from ilt or ige due to overflow.
+   (('ieq', ('iadd', a, b), a), ('ieq', b, 0)),
+   (('ine', ('iadd', a, b), a), ('ine', b, 0)),
+
# fmin(-b2f(a), b) >= 0.0
# -b2f(a) >= 0.0 && b >= 0.0
# -b2f(a) ==

Mesa (master): nir: Use De Morgan's Law on logic compounded comparisons

[Ian Romanick]

Module: Mesa
Branch: master
Commit: d1ed4ffe0b70762477709e699f95c73602f9dc5a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d1ed4ffe0b70762477709e699f95c73602f9dc5a

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Tue Feb  6 17:27:53 2018 -0800

nir: Use De Morgan's Law on logic compounded comparisons

The replacement of the comparison operators must happen during this
step.  If it does not, the next pass of nir_opt_algebraic will reapply
De Morgan's Law in the "opposite direction" before performing dead code
elimination.  The resulting infinite loop will eventually get OOM
killed.

Haswell, Broadwell, and Skylake had similar results. (Broadwell shown)
total instructions in shared programs: 14808185 -> 14808036 (<.01%)
instructions in affected programs: 13758 -> 13609 (-1.08%)
helped: 39
HURT: 0
helped stats (abs) min: 1 max: 10 x̄: 3.82 x̃: 3
helped stats (rel) min: 0.44% max: 1.55% x̄: 0.98% x̃: 1.01%
95% mean confidence interval for instructions value: -4.67 -2.97
95% mean confidence interval for instructions %-change: -1.09% -0.88%
Instructions are helped.

total cycles in shared programs: 559438333 -> 559435832 (<.01%)
cycles in affected programs: 199160 -> 196659 (-1.26%)
helped: 42
HURT: 3
helped stats (abs) min: 2 max: 184 x̄: 61.50 x̃: 51
helped stats (rel) min: 0.02% max: 6.94% x̄: 1.41% x̃: 1.40%
HURT stats (abs)   min: 2 max: 40 x̄: 27.33 x̃: 40
HURT stats (rel)   min: 0.05% max: 0.74% x̄: 0.51% x̃: 0.74%
95% mean confidence interval for cycles value: -71.47 -39.69
95% mean confidence interval for cycles %-change: -1.64% -0.93%
Cycles are helped.

Sandy Bridge and Ivy Bridge had similar results. (Ivy Bridge shown)
total instructions in shared programs: 11811776 -> 11811553 (<.01%)
instructions in affected programs: 15201 -> 14978 (-1.47%)
helped: 39
HURT: 0
helped stats (abs) min: 1 max: 20 x̄: 5.72 x̃: 6
helped stats (rel) min: 0.44% max: 2.53% x̄: 1.30% x̃: 1.26%
95% mean confidence interval for instructions value: -7.21 -4.23
95% mean confidence interval for instructions %-change: -1.48% -1.12%
Instructions are helped.

total cycles in shared programs: 257617270 -> 257614589 (<.01%)
cycles in affected programs: 212107 -> 209426 (-1.26%)
helped: 45
HURT: 0
helped stats (abs) min: 2 max: 180 x̄: 59.58 x̃: 54
helped stats (rel) min: 0.02% max: 6.02% x̄: 1.30% x̃: 1.32%
95% mean confidence interval for cycles value: -74.02 -45.14
95% mean confidence interval for cycles %-change: -1.59% -1.01%
Cycles are helped.

Iron Lake
total instructions in shared programs: 7886648 -> 7886515 (<.01%)
instructions in affected programs: 14106 -> 13973 (-0.94%)
helped: 29
HURT: 0
helped stats (abs) min: 1 max: 10 x̄: 4.59 x̃: 4
helped stats (rel) min: 0.35% max: 1.83% x̄: 0.90% x̃: 0.81%
95% mean confidence interval for instructions value: -5.65 -3.52
95% mean confidence interval for instructions %-change: -1.03% -0.76%
Instructions are helped.

total cycles in shared programs: 178100812 -> 178100396 (<.01%)
cycles in affected programs: 67970 -> 67554 (-0.61%)
helped: 29
HURT: 0
helped stats (abs) min: 2 max: 40 x̄: 14.34 x̃: 12
helped stats (rel) min: 0.15% max: 1.69% x̄: 0.58% x̃: 0.54%
95% mean confidence interval for cycles value: -18.30 -10.39
95% mean confidence interval for cycles %-change: -0.71% -0.45%
Cycles are helped.

GM45
total instructions in shared programs: 4857939 -> 4857872 (<.01%)
instructions in affected programs: 7426 -> 7359 (-0.90%)
helped: 15
HURT: 0
helped stats (abs) min: 1 max: 10 x̄: 4.47 x̃: 4
helped stats (rel) min: 0.33% max: 1.80% x̄: 0.87% x̃: 0.77%
95% mean confidence interval for instructions value: -6.06 -2.87
95% mean confidence interval for instructions %-change: -1.06% -0.67%
Instructions are helped.

total cycles in shared programs: 122167930 -> 122167654 (<.01%)
cycles in affected programs: 43118 -> 42842 (-0.64%)
helped: 15
HURT: 0
helped stats (abs) min: 4 max: 40 x̄: 18.40 x̃: 16
helped stats (rel) min: 0.15% max: 1.69% x̄: 0.62% x̃: 0.54%
95% mean confidence interval for cycles value: -25.03 -11.77
95% mean confidence interval for cycles %-change: -0.82% -0.41%
Cycles are helped.

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com>

---

 src/compiler/nir/nir_opt_algebraic.py | 9 +
 1 file changed, 9 insertions(+)

diff --git a/src/compiler/nir/nir_opt_algebraic.py 
b/src/compiler/nir/nir_opt_algebraic.py
index b1e266259f..f6800b419b 100644
--- a/src/compiler/nir/nir_opt_algebraic.py
+++ b/src/compiler/nir/nir_opt_algebraic.py
@@ -24,6 +24,7 @@
 #Jason Ekstrand (ja...@jlekstrand.net)
 
 import nir_algebraic
+import itertools
 
 # Convenience variables
 a = 'a'
@@ -545,6 +546,14 @@ optimizations = [
  'options->lower_unpack_snorm_4x8'),
 ]
 
+invert = {'feq': 'fne', 'fne': 'feq', 'fge': 'flt', 'flt': 'fge' }
+
+for left, right in list(itertools.combinations(invert.

Mesa (master): nir: Recognize some more open-coded fmin / fmax

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 4addd34b0477cf87787afbcea989b3391a81d0a1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4addd34b0477cf87787afbcea989b3391a81d0a1

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Mon Jan 22 17:29:48 2018 +0800

nir: Recognize some more open-coded fmin / fmax

This transformation is inexact because section 4.7.1 (Range and
Precision) says:

Operations and built-in functions that operate on a NaN are not
required to return a NaN as the result.

The fmin or fmax might not return NaN in cases where the original
expression would be required to return NaN.

v2: Reorder operands and mark as inexact.  The latter suggested by
Jason.

shader-db results:

Haswell, Broadwell, and Skylake had similar results. (Skylake shown)
total instructions in shared programs: 14514817 -> 14514808 (<.01%)
instructions in affected programs: 229 -> 220 (-3.93%)
helped: 3
HURT: 0
helped stats (abs) min: 1 max: 4 x̄: 3.00 x̃: 4
helped stats (rel) min: 2.86% max: 4.12% x̄: 3.70% x̃: 4.12%

total cycles in shared programs: 533145211 -> 533144939 (<.01%)
cycles in affected programs: 37268 -> 36996 (-0.73%)
helped: 8
HURT: 0
helped stats (abs) min: 2 max: 134 x̄: 34.00 x̃: 2
helped stats (rel) min: 0.02% max: 14.22% x̄: 3.53% x̃: 0.05%

Sandy Bridge and Ivy Bridge had similar results. (Ivy Bridge shown)
total cycles in shared programs: 257618409 -> 257618403 (<.01%)
cycles in affected programs: 12582 -> 12576 (-0.05%)
helped: 3
HURT: 0
helped stats (abs) min: 2 max: 2 x̄: 2.00 x̃: 2
helped stats (rel) min: 0.05% max: 0.05% x̄: 0.05% x̃: 0.05%

No changes on Iron Lake or GM45.

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>

---

 src/compiler/nir/nir_opt_algebraic.py | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/compiler/nir/nir_opt_algebraic.py 
b/src/compiler/nir/nir_opt_algebraic.py
index 296f067138..ef240ae0e9 100644
--- a/src/compiler/nir/nir_opt_algebraic.py
+++ b/src/compiler/nir/nir_opt_algebraic.py
@@ -170,6 +170,8 @@ optimizations = [
(('fge', ('fneg', ('fabs', a)), 0.0), ('feq', a, 0.0)),
(('bcsel', ('flt', b, a), b, a), ('fmin', a, b)),
(('bcsel', ('flt', a, b), b, a), ('fmax', a, b)),
+   (('~bcsel', ('fge', a, b), b, a), ('fmin', a, b)),
+   (('~bcsel', ('fge', b, a), b, a), ('fmax', a, b)),
(('bcsel', ('inot', a), b, c), ('bcsel', a, c, b)),
(('bcsel', a, ('bcsel', a, b, c), d), ('bcsel', a, b, d)),
(('bcsel', a, True, 'b@bool'), ('ior', a, b)),

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Mesa (master): nir: Replace an odd comparison involving fmin of -b2f

[Ian Romanick]

Module: Mesa
Branch: master
Commit: f50400cc8040cf2d07de97e76d9b1ed144c5c8b4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f50400cc8040cf2d07de97e76d9b1ed144c5c8b4

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Wed Jan 31 11:11:02 2018 -0800

nir: Replace an odd comparison involving fmin of -b2f

I noticed the fge version while looking at a shader for an unrelated
reason.  The feq version prevents a regression in a later change that
performs strength reduction of some compares.

Broadwell and Skylake had similar results. (Skylake shown)
total instructions in shared programs: 14514808 -> 14514796 (<.01%)
instructions in affected programs: 750 -> 738 (-1.60%)
helped: 4
HURT: 0
helped stats (abs) min: 1 max: 5 x̄: 3.00 x̃: 3
helped stats (rel) min: 0.83% max: 1.96% x̄: 1.40% x̃: 1.40%
95% mean confidence interval for instructions value: -6.67 0.67
95% mean confidence interval for instructions %-change: -2.43% -0.36%
Inconclusive result (value mean confidence interval includes 0).

total cycles in shared programs: 533144939 -> 533144853 (<.01%)
cycles in affected programs: 8911 -> 8825 (-0.97%)
helped: 4
HURT: 0
helped stats (abs) min: 16 max: 32 x̄: 21.50 x̃: 19
helped stats (rel) min: 0.60% max: 1.89% x̄: 1.28% x̃: 1.31%
95% mean confidence interval for cycles value: -32.94 -10.06
95% mean confidence interval for cycles %-change: -2.30% -0.26%
Cycles are helped.

Haswell
total instructions in shared programs: 13093785 -> 13093775 (<.01%)
instructions in affected programs: 924 -> 914 (-1.08%)
helped: 4
HURT: 2
helped stats (abs) min: 1 max: 5 x̄: 3.00 x̃: 3
helped stats (rel) min: 0.82% max: 1.95% x̄: 1.39% x̃: 1.39%
HURT stats (abs)   min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel)   min: 1.19% max: 1.19% x̄: 1.19% x̃: 1.19%
95% mean confidence interval for instructions value: -4.53 1.20
95% mean confidence interval for instructions %-change: -2.02% 0.97%
Inconclusive result (value mean confidence interval includes 0).

total cycles in shared programs: 409580553 -> 409580118 (<.01%)
cycles in affected programs: 10909 -> 10474 (-3.99%)
helped: 5
HURT: 1
helped stats (abs) min: 6 max: 222 x̄: 89.60 x̃: 18
helped stats (rel) min: 0.16% max: 24.72% x̄: 9.54% x̃: 1.78%
HURT stats (abs)   min: 13 max: 13 x̄: 13.00 x̃: 13
HURT stats (rel)   min: 0.39% max: 0.39% x̄: 0.39% x̃: 0.39%
95% mean confidence interval for cycles value: -180.68 35.68
95% mean confidence interval for cycles %-change: -19.55% 3.79%
Inconclusive result (value mean confidence interval includes 0).

Ivy Bridge
total instructions in shared programs: 11811851 -> 11811840 (<.01%)
instructions in affected programs: 1032 -> 1021 (-1.07%)
helped: 5
HURT: 1
helped stats (abs) min: 1 max: 5 x̄: 2.40 x̃: 1
helped stats (rel) min: 0.63% max: 1.95% x̄: 1.13% x̃: 0.97%
HURT stats (abs)   min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel)   min: 1.19% max: 1.19% x̄: 1.19% x̃: 1.19%
95% mean confidence interval for instructions value: -4.17 0.51
95% mean confidence interval for instructions %-change: -1.86% 0.36%
Inconclusive result (value mean confidence interval includes 0).

total cycles in shared programs: 257618403 -> 257618168 (<.01%)
cycles in affected programs: 10784 -> 10549 (-2.18%)
helped: 4
HURT: 2
helped stats (abs) min: 4 max: 220 x̄: 64.50 x̃: 17
helped stats (rel) min: 0.50% max: 24.34% x̄: 7.07% x̃: 1.72%
HURT stats (abs)   min: 9 max: 14 x̄: 11.50 x̃: 11
HURT stats (rel)   min: 0.24% max: 0.42% x̄: 0.33% x̃: 0.33%
95% mean confidence interval for cycles value: -133.11 54.78
95% mean confidence interval for cycles %-change: -14.79% 5.59%
Inconclusive result (value mean confidence interval includes 0).

GM45, Iron Lake, and Sandy Bridge had similar results. (Sandy Bridge shown)
total instructions in shared programs: 10533871 -> 10533859 (<.01%)
instructions in affected programs: 865 -> 853 (-1.39%)
helped: 4
HURT: 0
helped stats (abs) min: 1 max: 5 x̄: 3.00 x̃: 3
helped stats (rel) min: 0.63% max: 1.83% x̄: 1.22% x̃: 1.21%
95% mean confidence interval for instructions value: -6.67 0.67
95% mean confidence interval for instructions %-change: -2.16% -0.29%
Inconclusive result (value mean confidence interval includes 0).

total cycles in shared programs: 146139904 -> 146139852 (<.01%)
cycles in affected programs: 15213 -> 15161 (-0.34%)
helped: 4
HURT: 0
helped stats (abs) min: 3 max: 18 x̄: 13.00 x̃: 15
helped stats (rel) min: 0.15% max: 0.84% x̄: 0.39% x̃: 0.29%
95% mean confidence interval for cycles value: -23.79 -2.21
95% mean confidence interval for cycles %-change: -0.88% 0.09%
Inconclusive result (%-change mean confidence interval includes 0).

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com>

---

 src/compiler/nir/nir_opt_algebraic.py | 13 +
 1 file changed, 13 insertions(+)

diff --git a/src/compiler/nir/nir_opt_algebraic.py 
b/src/co

Mesa (master): nir: Pull b2f out of bcsel

[Ian Romanick]

Module: Mesa
Branch: master
Commit: b974dfee114cc7a4857af324e86ab81318c78176
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b974dfee114cc7a4857af324e86ab81318c78176

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Thu Feb  1 15:33:04 2018 -0800

nir: Pull b2f out of bcsel

All platforms had similar results. (Skylake shown)
total instructions in shared programs: 14516592 -> 14516586 (<.01%)
instructions in affected programs: 500 -> 494 (-1.20%)
helped: 2
HURT: 0

total cycles in shared programs: 533167044 -> 533166998 (<.01%)
cycles in affected programs: 6988 -> 6942 (-0.66%)
helped: 2
HURT: 0

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com>

---

 src/compiler/nir/nir_opt_algebraic.py | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/compiler/nir/nir_opt_algebraic.py 
b/src/compiler/nir/nir_opt_algebraic.py
index 553f82065a..d94536439c 100644
--- a/src/compiler/nir/nir_opt_algebraic.py
+++ b/src/compiler/nir/nir_opt_algebraic.py
@@ -372,6 +372,7 @@ optimizations = [
(('bcsel@32', a, -0.0, -1.0), ('fneg', ('b2f', ('inot', a,
(('bcsel', True, b, c), b),
(('bcsel', False, b, c), c),
+   (('bcsel', a, ('b2f(is_used_once)', b), ('b2f', c)), ('b2f', ('bcsel', a, 
b, c))),
# The result of this should be hit by constant propagation and, in the
# next round of opt_algebraic, get picked up by one of the above two.
(('bcsel', '#a', b, c), ('bcsel', ('ine', 'a', 0), b, c)),

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Mesa (master): nir: Replace fmin(b2f(a), b) with a bcsel

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 52607658ff7ffe8a4022678f04287b70248c37ab
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=52607658ff7ffe8a4022678f04287b70248c37ab

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Fri Feb  2 17:39:54 2018 -0800

nir: Replace fmin(b2f(a), b) with a bcsel

All of the affected shaders are HDR mappers from Serious Sam 3.

All Gen7+ platforms had similar results. (Skylake shown)
total instructions in shared programs: 14516285 -> 14516273 (<.01%)
instructions in affected programs: 348 -> 336 (-3.45%)
helped: 12
HURT: 0
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 2.08% max: 6.67% x̄: 4.31% x̃: 4.17%
95% mean confidence interval for instructions value: -1.00 -1.00
95% mean confidence interval for instructions %-change: -5.55% -3.06%
Instructions are helped.

total cycles in shared programs: 533163876 -> 533163808 (<.01%)
cycles in affected programs: 1144 -> 1076 (-5.94%)
helped: 4
HURT: 0
helped stats (abs) min: 16 max: 18 x̄: 17.00 x̃: 17
helped stats (rel) min: 5.80% max: 6.08% x̄: 5.94% x̃: 5.94%
95% mean confidence interval for cycles value: -18.84 -15.16
95% mean confidence interval for cycles %-change: -6.20% -5.68%
Cycles are helped.

Sandy Bridge
total instructions in shared programs: 10533321 -> 10533309 (<.01%)
instructions in affected programs: 372 -> 360 (-3.23%)
helped: 12
HURT: 0
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 2.00% max: 5.88% x̄: 3.91% x̃: 3.85%
95% mean confidence interval for instructions value: -1.00 -1.00
95% mean confidence interval for instructions %-change: -4.96% -2.86%
Instructions are helped.

total cycles in shared programs: 146136632 -> 146136428 (<.01%)
cycles in affected programs: 11668 -> 11464 (-1.75%)
helped: 12
HURT: 0
helped stats (abs) min: 16 max: 18 x̄: 17.00 x̃: 17
helped stats (rel) min: 0.99% max: 3.44% x̄: 2.20% x̃: 2.29%
95% mean confidence interval for cycles value: -17.66 -16.34
95% mean confidence interval for cycles %-change: -2.82% -1.58%
Cycles are helped.

Iron Lake
total instructions in shared programs: 7886301 -> 7886277 (<.01%)
instructions in affected programs: 576 -> 552 (-4.17%)
helped: 12
HURT: 0
helped stats (abs) min: 2 max: 2 x̄: 2.00 x̃: 2
helped stats (rel) min: 2.94% max: 6.06% x̄: 4.51% x̃: 4.65%
95% mean confidence interval for instructions value: -2.00 -2.00
95% mean confidence interval for instructions %-change: -5.30% -3.72%
Instructions are helped.

total cycles in shared programs: 178113176 -> 178113176 (0.00%)
cycles in affected programs: 2116 -> 2116 (0.00%)
helped: 2
HURT: 4
helped stats (abs) min: 4 max: 4 x̄: 4.00 x̃: 4
helped stats (rel) min: 1.14% max: 1.14% x̄: 1.14% x̃: 1.14%
HURT stats (abs)   min: 2 max: 2 x̄: 2.00 x̃: 2
HURT stats (rel)   min: 0.50% max: 0.65% x̄: 0.58% x̃: 0.58%
95% mean confidence interval for cycles value: -3.25 3.25
95% mean confidence interval for cycles %-change: -0.93% 0.94%
Inconclusive result (value mean confidence interval includes 0).

GM45
total instructions in shared programs: 4857756 -> 4857744 (<.01%)
instructions in affected programs: 294 -> 282 (-4.08%)
helped: 6
HURT: 0
helped stats (abs) min: 2 max: 2 x̄: 2.00 x̃: 2
helped stats (rel) min: 2.94% max: 5.71% x̄: 4.40% x̃: 4.55%
95% mean confidence interval for instructions value: -2.00 -2.00
95% mean confidence interval for instructions %-change: -5.71% -3.09%
Instructions are helped.

total cycles in shared programs: 122178730 -> 122178722 (<.01%)
cycles in affected programs: 700 -> 692 (-1.14%)
helped: 2
HURT: 0

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com>

---

 src/compiler/nir/nir_opt_algebraic.py | 9 +
 1 file changed, 9 insertions(+)

diff --git a/src/compiler/nir/nir_opt_algebraic.py 
b/src/compiler/nir/nir_opt_algebraic.py
index d94536439c..b1e266259f 100644
--- a/src/compiler/nir/nir_opt_algebraic.py
+++ b/src/compiler/nir/nir_opt_algebraic.py
@@ -176,6 +176,15 @@ optimizations = [
(('fmin',('b2f(is_used_once)', a),   
('b2f', b)),   ('b2f', ('iand', a, b))),
(('fmin', ('fneg(is_used_once)', ('b2f(is_used_once)', a)), ('fneg', 
('b2f', b))), ('fneg', ('b2f', ('iand', a, b,
 
+   # fmin(b2f(a), b)
+   # bcsel(a, fmin(b2f(a), b), fmin(b2f(a), b))
+   # bcsel(a, fmin(b2f(True), b), fmin(b2f(False), b))
+   # bcsel(a, fmin(1.0, b), fmin(0.0, b))
+   #
+   # Since b is a constant, constant folding will eliminate the fmin and the
+   # fmax.  If b is > 1.0, the bcsel will be replaced with a b2f.
+   (('fmin', ('b2f', a), '#b'), ('bcsel', a, ('fmin', b, 1.0), ('fmin', b, 
0.0))),
+
# ignore this opt when the result is used by a bcsel or if so we can make
# use of conditional modifiers on supported hardware.
(('flt(is_not_used_by_conditional)', ('fadd(is_used_once)', a, ('fneg', 
b)), 0.0), ('fl

Mesa (master): nir: Mark bcsel-to-fmin (or fmax) transformations as inexact

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 380136e998f8d89380adba7d071249d6469339db
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=380136e998f8d89380adba7d071249d6469339db

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Mon Feb 26 14:49:47 2018 -0800

nir: Mark bcsel-to-fmin (or fmax) transformations as inexact

These transformations are inexact because section 4.7.1 (Range and
Precision) says:

Operations and built-in functions that operate on a NaN are not
required to return a NaN as the result.

The fmin or fmax might not return NaN in cases where the original
expression would be required to return NaN.

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>

---

 src/compiler/nir/nir_opt_algebraic.py | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/compiler/nir/nir_opt_algebraic.py 
b/src/compiler/nir/nir_opt_algebraic.py
index ef240ae0e9..43b2948431 100644
--- a/src/compiler/nir/nir_opt_algebraic.py
+++ b/src/compiler/nir/nir_opt_algebraic.py
@@ -168,8 +168,8 @@ optimizations = [
(('flt(is_not_used_by_conditional)', ('fadd(is_used_once)', a, ('fneg', 
b)), 0.0), ('flt', a, b)),
 
(('fge', ('fneg', ('fabs', a)), 0.0), ('feq', a, 0.0)),
-   (('bcsel', ('flt', b, a), b, a), ('fmin', a, b)),
-   (('bcsel', ('flt', a, b), b, a), ('fmax', a, b)),
+   (('~bcsel', ('flt', b, a), b, a), ('fmin', a, b)),
+   (('~bcsel', ('flt', a, b), b, a), ('fmax', a, b)),
(('~bcsel', ('fge', a, b), b, a), ('fmin', a, b)),
(('~bcsel', ('fge', b, a), b, a), ('fmax', a, b)),
(('bcsel', ('inot', a), b, c), ('bcsel', a, c, b)),

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Mesa (master): intel/compiler: Silence unused parameter warnings in release builds

[Ian Romanick]

Module: Mesa
Branch: master
Commit: feefb7810e694ab902adda36b9d92bdaf1802178
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=feefb7810e694ab902adda36b9d92bdaf1802178

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Mon Feb 12 10:57:06 2018 -0800

intel/compiler: Silence unused parameter warnings in release builds

Reduces my build from 7005 warnings to 6451 warnings by silencing 554
instances of

In file included from ../../SOURCE/master/src/intel/compiler/brw_disasm.c:28:0:
../../SOURCE/master/src/intel/compiler/brw_inst.h: In function 
‘brw_inst_3src_a1_src0_imm’:
../../SOURCE/master/src/intel/compiler/brw_inst.h:346:57: warning: unused 
parameter ‘devinfo’ [-Wunused-parameter]
 brw_inst_3src_a1_src0_imm(const struct gen_device_info *devinfo,
 ^~~
../../SOURCE/master/src/intel/compiler/brw_inst.h: In function 
‘brw_inst_3src_a1_src2_imm’:
../../SOURCE/master/src/intel/compiler/brw_inst.h:354:57: warning: unused 
parameter ‘devinfo’ [-Wunused-parameter]
 brw_inst_3src_a1_src2_imm(const struct gen_device_info *devinfo,
 ^~~
../../SOURCE/master/src/intel/compiler/brw_inst.h: In function 
‘brw_inst_set_3src_a1_src0_imm’:
../../SOURCE/master/src/intel/compiler/brw_inst.h:362:61: warning: unused 
parameter ‘devinfo’ [-Wunused-parameter]
 brw_inst_set_3src_a1_src0_imm(const struct gen_device_info *devinfo,
 ^~~
../../SOURCE/master/src/intel/compiler/brw_inst.h: In function 
‘brw_inst_set_3src_a1_src2_imm’:
../../SOURCE/master/src/intel/compiler/brw_inst.h:370:61: warning: unused 
parameter ‘devinfo’ [-Wunused-parameter]
 brw_inst_set_3src_a1_src2_imm(const struct gen_device_info *devinfo,
 ^~~
../../SOURCE/master/src/intel/compiler/brw_inst.h: In function 
‘brw_inst_imm_uq’:
../../SOURCE/master/src/intel/compiler/brw_inst.h:703:47: warning: unused 
parameter ‘devinfo’ [-Wunused-parameter]
 brw_inst_imm_uq(const struct gen_device_info *devinfo, const brw_inst *insn)
   ^~~
In file included from ../../SOURCE/master/src/intel/compiler/brw_shader.h:29:0,
 from ../../SOURCE/master/src/intel/compiler/brw_disasm.c:29:
../../SOURCE/master/src/intel/compiler/brw_compiler.h: In function 
‘brw_stage_has_packed_dispatch’:
../../SOURCE/master/src/intel/compiler/brw_compiler.h:1277:61: warning: unused 
parameter ‘devinfo’ [-Wunused-parameter]
 brw_stage_has_packed_dispatch(const struct gen_device_info *devinfo,
 ^~~
../../SOURCE/master/src/intel/compiler/brw_disasm.c: In function ‘src_ia1’:
../../SOURCE/master/src/intel/compiler/brw_disasm.c:849:18: warning: unused 
parameter ‘_reg_file’ [-Wunused-parameter]
 unsigned _reg_file,
  ^

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com>

---

 src/intel/compiler/brw_compiler.h |  2 +-
 src/intel/compiler/brw_inst.h | 11 ++-
 2 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/src/intel/compiler/brw_compiler.h 
b/src/intel/compiler/brw_compiler.h
index b1086bbcee..fb68a34ab9 100644
--- a/src/intel/compiler/brw_compiler.h
+++ b/src/intel/compiler/brw_compiler.h
@@ -1274,7 +1274,7 @@ encode_slm_size(unsigned gen, uint32_t bytes)
  * '2^n - 1' for some n.
  */
 static inline bool
-brw_stage_has_packed_dispatch(const struct gen_device_info *devinfo,
+brw_stage_has_packed_dispatch(MAYBE_UNUSED const struct gen_device_info 
*devinfo,
   gl_shader_stage stage,
   const struct brw_stage_prog_data *prog_data)
 {
diff --git a/src/intel/compiler/brw_inst.h b/src/intel/compiler/brw_inst.h
index 99e637e660..0f5e4ac988 100644
--- a/src/intel/compiler/brw_inst.h
+++ b/src/intel/compiler/brw_inst.h
@@ -343,7 +343,7 @@ REG_TYPE(src2)
  *  @{
  */
 static inline uint16_t
-brw_inst_3src_a1_src0_imm(const struct gen_device_info *devinfo,
+brw_inst_3src_a1_src0_imm(MAYBE_UNUSED const struct gen_device_info *devinfo,
   const brw_inst *insn)
 {
assert(devinfo->gen >= 10);
@@ -351,7 +351,7 @@ brw_inst_3src_a1_src0_imm(const struct gen_device_info 
*devinfo,
 }
 
 static inline uint16_t
-brw_inst_3src_a1_src2_imm(const struct gen_device_info *devinfo,
+brw_inst_3src_a1_src2_imm(MAYBE_UNUSED const struct gen_device_info *devinfo,
   const brw_inst *insn)
 {
assert(devinfo->gen >= 10);
@@ -359,7 +359,7 @@ brw_inst_3src_a1_src2_imm(const struct gen_device_info 
*devinfo,
 }
 
 static inline void
-brw_inst_set_3src_a1_src0_imm(const struct gen_device_info *devinfo,
+brw_inst_set_3src_a1_src0_imm(MAYBE_UNUSED const struct gen_device_info 
*devinfo,
 

Mesa (master): isl: Silence unused parameter warnings in __gen_combine_address implementations

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 50bf1868295ecd5ef5d9673d4f5c1259b9fa2b3f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=50bf1868295ecd5ef5d9673d4f5c1259b9fa2b3f

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Tue Feb 20 18:42:02 2018 -0800

isl: Silence unused parameter warnings in __gen_combine_address implementations

Reduces my build from 1808 warnings to 1772 warnings by silencing 36
instances of things like

../../SOURCE/master/src/intel/isl/isl_emit_depth_stencil.c: In function 
‘__gen_combine_address’:
../../SOURCE/master/src/intel/isl/isl_emit_depth_stencil.c:30:29: warning: 
unused parameter ‘data’ [-Wunused-parameter]
 __gen_combine_address(void *data, void *loc, uint64_t addr, uint32_t delta)
 ^~~~
../../SOURCE/master/src/intel/isl/isl_emit_depth_stencil.c:30:41: warning: 
unused parameter ‘loc’ [-Wunused-parameter]
 __gen_combine_address(void *data, void *loc, uint64_t addr, uint32_t delta)
 ^~~

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com>

---

 src/intel/isl/isl_emit_depth_stencil.c | 4 +++-
 src/intel/isl/isl_surface_state.c  | 4 +++-
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/src/intel/isl/isl_emit_depth_stencil.c 
b/src/intel/isl/isl_emit_depth_stencil.c
index 90ce8893e5..51b3f005c0 100644
--- a/src/intel/isl/isl_emit_depth_stencil.c
+++ b/src/intel/isl/isl_emit_depth_stencil.c
@@ -27,7 +27,9 @@
 #define __gen_user_data void
 
 static uint64_t
-__gen_combine_address(void *data, void *loc, uint64_t addr, uint32_t delta)
+__gen_combine_address(__attribute__((unused)) void *data,
+  __attribute__((unused)) void *loc, uint64_t addr,
+  uint32_t delta)
 {
return addr + delta;
 }
diff --git a/src/intel/isl/isl_surface_state.c 
b/src/intel/isl/isl_surface_state.c
index c205b3d2c0..1f729f89f4 100644
--- a/src/intel/isl/isl_surface_state.c
+++ b/src/intel/isl/isl_surface_state.c
@@ -27,7 +27,9 @@
 #define __gen_user_data void
 
 static uint64_t
-__gen_combine_address(void *data, void *loc, uint64_t addr, uint32_t delta)
+__gen_combine_address(__attribute__((unused)) void *data,
+  __attribute__((unused)) void *loc, uint64_t addr,
+  uint32_t delta)
 {
return addr + delta;
 }

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Mesa (master): nir: Silence unused parameter warnings in generated nir_constant_expressions code

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 3a944316c44621ad824c812907d9d1e0d3ddda46
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3a944316c44621ad824c812907d9d1e0d3ddda46

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Fri Feb 16 17:48:57 2018 -0800

nir: Silence unused parameter warnings in generated nir_constant_expressions 
code

Reduces my build from 2075 warnings to 2023 warnings by silencing 52
instances of things like

src/compiler/nir/nir_constant_expressions.c: In function ‘evaluate_bfi’:
src/compiler/nir/nir_constant_expressions.c:1812:61: warning: unused parameter 
‘bit_size’ [-Wunused-parameter]
 evaluate_bfi(MAYBE_UNUSED unsigned num_components, unsigned bit_size,
 ^~~~

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com>

---

 src/compiler/nir/nir_constant_expressions.py | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/compiler/nir/nir_constant_expressions.py 
b/src/compiler/nir/nir_constant_expressions.py
index 6571d3b98b..ee92be51db 100644
--- a/src/compiler/nir/nir_constant_expressions.py
+++ b/src/compiler/nir/nir_constant_expressions.py
@@ -389,7 +389,8 @@ struct bool32_vec {
 
 % for name, op in sorted(opcodes.iteritems()):
 static nir_const_value
-evaluate_${name}(MAYBE_UNUSED unsigned num_components, unsigned bit_size,
+evaluate_${name}(MAYBE_UNUSED unsigned num_components,
+ ${"UNUSED" if op_bit_sizes(op) is None else ""} unsigned 
bit_size,
  MAYBE_UNUSED nir_const_value *_src)
 {
nir_const_value _dst_val = { {0, } };

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Mesa (master): mesa: Silence unused parameter warnings from TEXSTORE_PARAMS

[Ian Romanick]

Module: Mesa
Branch: master
Commit: a9eb455e297d227bc4ca423e8470ed897d82b57b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a9eb455e297d227bc4ca423e8470ed897d82b57b

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Wed Feb 21 19:23:44 2018 -0800

mesa: Silence unused parameter warnings from TEXSTORE_PARAMS

Reduces my build from 1717 warnings to 1547 warnings by silencing 170
instances of things like

In file included from ../../SOURCE/master/src/mesa/main/texcompress_bptc.h:30:0,
 from ../../SOURCE/master/src/mesa/main/texcompress_bptc.c:31:
../../SOURCE/master/src/mesa/main/texcompress_bptc.c: In function 
‘_mesa_texstore_bptc_rgba_unorm’:
../../SOURCE/master/src/mesa/main/texstore.h:60:14: warning: unused parameter 
‘dstFormat’ [-Wunused-parameter]
  mesa_format dstFormat, \
  ^
../../SOURCE/master/src/mesa/main/texcompress_bptc.c:1276:32: note: in 
expansion of macro ‘TEXSTORE_PARAMS’
 _mesa_texstore_bptc_rgba_unorm(TEXSTORE_PARAMS)
^~~

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com>

---

 src/mesa/main/texcompress_etc.c | 22 +++---
 src/mesa/main/texstore.h| 18 --
 2 files changed, 27 insertions(+), 13 deletions(-)

diff --git a/src/mesa/main/texcompress_etc.c b/src/mesa/main/texcompress_etc.c
index d465010985..faeaae9093 100644
--- a/src/mesa/main/texcompress_etc.c
+++ b/src/mesa/main/texcompress_etc.c
@@ -105,7 +105,7 @@ static const int etc2_modifier_tables_non_opaque[8][4] = {
 #undef UINT8_TYPE
 
 GLboolean
-_mesa_texstore_etc1_rgb8(TEXSTORE_PARAMS)
+_mesa_texstore_etc1_rgb8(UNUSED_TEXSTORE_PARAMS)
 {
/* GL_ETC1_RGB8_OES is only valid in glCompressedTexImage2D */
assert(0);
@@ -1097,7 +1097,7 @@ etc2_unpack_srgb8_punchthrough_alpha1(uint8_t *dst_row,
 /* ETC2 texture formats are valid in glCompressedTexImage2D and
  * glCompressedTexSubImage2D functions */
 GLboolean
-_mesa_texstore_etc2_rgb8(TEXSTORE_PARAMS)
+_mesa_texstore_etc2_rgb8(UNUSED_TEXSTORE_PARAMS)
 {
assert(0);
 
@@ -1105,7 +1105,7 @@ _mesa_texstore_etc2_rgb8(TEXSTORE_PARAMS)
 }
 
 GLboolean
-_mesa_texstore_etc2_srgb8(TEXSTORE_PARAMS)
+_mesa_texstore_etc2_srgb8(UNUSED_TEXSTORE_PARAMS)
 {
assert(0);
 
@@ -1113,7 +1113,7 @@ _mesa_texstore_etc2_srgb8(TEXSTORE_PARAMS)
 }
 
 GLboolean
-_mesa_texstore_etc2_rgba8_eac(TEXSTORE_PARAMS)
+_mesa_texstore_etc2_rgba8_eac(UNUSED_TEXSTORE_PARAMS)
 {
assert(0);
 
@@ -1121,7 +1121,7 @@ _mesa_texstore_etc2_rgba8_eac(TEXSTORE_PARAMS)
 }
 
 GLboolean
-_mesa_texstore_etc2_srgb8_alpha8_eac(TEXSTORE_PARAMS)
+_mesa_texstore_etc2_srgb8_alpha8_eac(UNUSED_TEXSTORE_PARAMS)
 {
assert(0);
 
@@ -1129,7 +1129,7 @@ _mesa_texstore_etc2_srgb8_alpha8_eac(TEXSTORE_PARAMS)
 }
 
 GLboolean
-_mesa_texstore_etc2_r11_eac(TEXSTORE_PARAMS)
+_mesa_texstore_etc2_r11_eac(UNUSED_TEXSTORE_PARAMS)
 {
assert(0);
 
@@ -1137,7 +1137,7 @@ _mesa_texstore_etc2_r11_eac(TEXSTORE_PARAMS)
 }
 
 GLboolean
-_mesa_texstore_etc2_signed_r11_eac(TEXSTORE_PARAMS)
+_mesa_texstore_etc2_signed_r11_eac(UNUSED_TEXSTORE_PARAMS)
 {
assert(0);
 
@@ -1145,7 +1145,7 @@ _mesa_texstore_etc2_signed_r11_eac(TEXSTORE_PARAMS)
 }
 
 GLboolean
-_mesa_texstore_etc2_rg11_eac(TEXSTORE_PARAMS)
+_mesa_texstore_etc2_rg11_eac(UNUSED_TEXSTORE_PARAMS)
 {
assert(0);
 
@@ -1153,7 +1153,7 @@ _mesa_texstore_etc2_rg11_eac(TEXSTORE_PARAMS)
 }
 
 GLboolean
-_mesa_texstore_etc2_signed_rg11_eac(TEXSTORE_PARAMS)
+_mesa_texstore_etc2_signed_rg11_eac(UNUSED_TEXSTORE_PARAMS)
 {
assert(0);
 
@@ -1161,7 +1161,7 @@ _mesa_texstore_etc2_signed_rg11_eac(TEXSTORE_PARAMS)
 }
 
 GLboolean
-_mesa_texstore_etc2_rgb8_punchthrough_alpha1(TEXSTORE_PARAMS)
+_mesa_texstore_etc2_rgb8_punchthrough_alpha1(UNUSED_TEXSTORE_PARAMS)
 {
assert(0);
 
@@ -1169,7 +1169,7 @@ 
_mesa_texstore_etc2_rgb8_punchthrough_alpha1(TEXSTORE_PARAMS)
 }
 
 GLboolean
-_mesa_texstore_etc2_srgb8_punchthrough_alpha1(TEXSTORE_PARAMS)
+_mesa_texstore_etc2_srgb8_punchthrough_alpha1(UNUSED_TEXSTORE_PARAMS)
 {
assert(0);
 
diff --git a/src/mesa/main/texstore.h b/src/mesa/main/texstore.h
index f08dc08edd..b8281c51e2 100644
--- a/src/mesa/main/texstore.h
+++ b/src/mesa/main/texstore.h
@@ -56,8 +56,8 @@
  */
 #define TEXSTORE_PARAMS \
struct gl_context *ctx, GLuint dims, \
-   GLenum baseInternalFormat, \
-   mesa_format dstFormat, \
+MAYBE_UNUSED GLenum baseInternalFormat, \
+MAYBE_UNUSED mesa_format dstFormat, \
 GLint dstRowStride, \
 GLubyte **dstSlices, \
GLint srcWidth, GLint srcHeight, GLint srcDepth, \
@@ -65,6 +65,20 @@
const GLvoid *srcAddr, \
const struct gl_pixelstore_attrib *srcPacking
 
+/* This macro must be kept in sync with TEXSTORE_PARAMS.  It is used in the
+ * few places where none of the parameters are used (i.e., the ETC texstore
+ * functions).
+ */
+#define UNUS

Mesa (master): i965: Silence warnings about mixing enum and non-enum in conditional

[Ian Romanick]

Module: Mesa
Branch: master
Commit: a55dae6ea2cdf37d0ddd06d5f3b34ac1faf3848c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a55dae6ea2cdf37d0ddd06d5f3b34ac1faf3848c

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Mon Feb 12 11:16:55 2018 -0800

i965: Silence warnings about mixing enum and non-enum in conditional

Reduces my build from 6451 warnings to 6301 warnings by silencing 150
instances of

../../SOURCE/master/src/intel/compiler/brw_inst.h: In function ‘brw_reg_type 
brw_inst_src1_type(const gen_device_info*, const brw_inst*)’:
../../SOURCE/master/src/intel/compiler/brw_inst.h:802:55: warning: enumeral and 
non-enumeral type in conditional expression [-Wextra]
unsigned file = __builtin_strcmp("dst", #reg) == 0 ?   \
~~~^
BRW_GENERAL_REGISTER_FILE :\

brw_inst_##reg##_reg_file(devinfo, inst);  \

../../SOURCE/master/src/intel/compiler/brw_inst.h:811:1: note: in expansion of 
macro ‘REG_TYPE’
 REG_TYPE(src1)
 ^~~~

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com>

---

 src/intel/compiler/brw_inst.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/intel/compiler/brw_inst.h b/src/intel/compiler/brw_inst.h
index 0f5e4ac988..a67225ca6b 100644
--- a/src/intel/compiler/brw_inst.h
+++ b/src/intel/compiler/brw_inst.h
@@ -800,7 +800,7 @@ brw_inst_##reg##_type(const struct gen_device_info 
*devinfo,  \
   const brw_inst *inst)   \
 { \
unsigned file = __builtin_strcmp("dst", #reg) == 0 ?   \
-   BRW_GENERAL_REGISTER_FILE :\
+   (unsigned) BRW_GENERAL_REGISTER_FILE : \
brw_inst_##reg##_reg_file(devinfo, inst);  \
unsigned hw_type = brw_inst_##reg##_reg_hw_type(devinfo, inst);\
return brw_hw_type_to_reg_type(devinfo, (enum brw_reg_file)file, hw_type); \

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Mesa (master): i965: Silence unused parameter warnings in generated OA code

[Ian Romanick]

Module: Mesa
Branch: master
Commit: ab8f2e30b8ea3565c00a76b546b7ef3b78ab7ff6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ab8f2e30b8ea3565c00a76b546b7ef3b78ab7ff6

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Mon Feb 12 11:26:39 2018 -0800

i965: Silence unused parameter warnings in generated OA code

Reduces my build from 6301 warnings to 2075 warnings by silencing 4226
instances of things like

src/mesa/drivers/dri/i965/i965@sta/brw_oa_hsw.c: In function 
‘hsw__render_basic__gpu_core_clocks__read’:
src/mesa/drivers/dri/i965/i965@sta/brw_oa_hsw.c:41:62: warning: unused 
parameter ‘brw’ [-Wunused-parameter]
 hsw__render_basic__gpu_core_clocks__read(struct brw_context *brw,
  ^~~

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com>

---

 src/mesa/drivers/dri/i965/brw_oa.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_oa.py 
b/src/mesa/drivers/dri/i965/brw_oa.py
index 576ea6687f..7931c825f0 100644
--- a/src/mesa/drivers/dri/i965/brw_oa.py
+++ b/src/mesa/drivers/dri/i965/brw_oa.py
@@ -260,7 +260,7 @@ def output_counter_read(set, counter, counter_vars):
 
 c("static " + ret_type)
 read_sym = "{0}__{1}__{2}__read".format(set.get('chipset').lower(), 
set.get('underscore_name'), counter.get('underscore_name'))
-c(read_sym + "(struct brw_context *brw,\n")
+c(read_sym + "(MAYBE_UNUSED struct brw_context *brw,\n")
 c_indent(len(read_sym) + 1)
 c("const struct brw_perf_query_info *query,\n")
 c("uint64_t *accumulator)\n")

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Mesa (master): i965: Silence unused parameter warnings

[Ian Romanick]

Module: Mesa
Branch: master
Commit: c8a03ab453b5a162c1268aa9f45e4aa6bfa24c6f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c8a03ab453b5a162c1268aa9f45e4aa6bfa24c6f

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Mon Feb 12 10:52:49 2018 -0800

i965: Silence unused parameter warnings

Reduces my build from 7119 warnings to 7005 warnings by silencing 114
instances of

In file included from 
../../SOURCE/master/src/mesa/drivers/dri/i965/brw_context.h:46:0,
 from 
../../SOURCE/master/src/mesa/drivers/dri/i965/intel_pixel_read.c:38:
../../SOURCE/master/src/mesa/drivers/dri/i965/brw_bufmgr.h: In function 
‘brw_bo_unmap’:
../../SOURCE/master/src/mesa/drivers/dri/i965/brw_bufmgr.h:258:47: warning: 
unused parameter ‘bo’ [-Wunused-parameter]
 static inline int brw_bo_unmap(struct brw_bo *bo) { return 0; }
   ^~

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com>

---

 src/mesa/drivers/dri/i965/brw_bufmgr.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.h 
b/src/mesa/drivers/dri/i965/brw_bufmgr.h
index 0f2badd006..f33b6b5a3b 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.h
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.h
@@ -252,7 +252,7 @@ MUST_CHECK void *brw_bo_map(struct brw_context *brw, struct 
brw_bo *bo, unsigned
  * Reduces the refcount on the userspace mapping of the buffer
  * object.
  */
-static inline int brw_bo_unmap(struct brw_bo *bo) { return 0; }
+static inline int brw_bo_unmap(UNUSED struct brw_bo *bo) { return 0; }
 
 /** Write data into an object. */
 int brw_bo_subdata(struct brw_bo *bo, uint64_t offset,

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Mesa (master): i965: Silence unused parameter warnings in blorp

[Ian Romanick]

Module: Mesa
Branch: master
Commit: f726695ccee6c13be7e5fd01226a53c5028dd7b7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f726695ccee6c13be7e5fd01226a53c5028dd7b7

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Fri Feb 16 19:00:21 2018 -0800

i965: Silence unused parameter warnings in blorp

Reduces my build from 2023 warnings to 1960 warnings by silencing 63
instances of things like

In file included from 
../../SOURCE/master/src/mesa/drivers/dri/i965/genX_blorp_exec.c:33:0:
../../SOURCE/master/src/intel/blorp/blorp_genX_exec.h: In function 
‘blorp_emit_cc_viewport’:
../../SOURCE/master/src/intel/blorp/blorp_genX_exec.h:500:51: warning: unused 
parameter ‘params’ [-Wunused-parameter]
const struct blorp_params *params)
   ^~
../../SOURCE/master/src/intel/blorp/blorp_genX_exec.h: In function 
‘blorp_emit_sampler_state’:
../../SOURCE/master/src/intel/blorp/blorp_genX_exec.h:524:53: warning: unused 
parameter ‘params’ [-Wunused-parameter]
  const struct blorp_params *params)
 ^~
In file included from 
../../SOURCE/master/src/mesa/drivers/dri/i965/genX_blorp_exec.c:36:0:
../../SOURCE/master/src/mesa/drivers/dri/i965/gen4_blorp_exec.h: In function 
‘blorp_emit_vs_state’:
../../SOURCE/master/src/mesa/drivers/dri/i965/gen4_blorp_exec.h:50:48: warning: 
unused parameter ‘params’ [-Wunused-parameter]
 const struct blorp_params *params)
^~
../../SOURCE/master/src/mesa/drivers/dri/i965/genX_blorp_exec.c: In function 
‘blorp_flush_range’:
../../SOURCE/master/src/mesa/drivers/dri/i965/genX_blorp_exec.c:197:39: 
warning: unused parameter ‘batch’ [-Wunused-parameter]
 blorp_flush_range(struct blorp_batch *batch, void *start, size_t size)
   ^
../../SOURCE/master/src/mesa/drivers/dri/i965/genX_blorp_exec.c:197:52: 
warning: unused parameter ‘start’ [-Wunused-parameter]
 blorp_flush_range(struct blorp_batch *batch, void *start, size_t size)
^
../../SOURCE/master/src/mesa/drivers/dri/i965/genX_blorp_exec.c:197:66: 
warning: unused parameter ‘size’ [-Wunused-parameter]
 blorp_flush_range(struct blorp_batch *batch, void *start, size_t size)
  ^~~~

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com>

---

 src/intel/blorp/blorp_genX_exec.h   | 12 +---
 src/mesa/drivers/dri/i965/gen4_blorp_exec.h | 14 ++
 src/mesa/drivers/dri/i965/genX_blorp_exec.c |  6 --
 3 files changed, 15 insertions(+), 17 deletions(-)

diff --git a/src/intel/blorp/blorp_genX_exec.h 
b/src/intel/blorp/blorp_genX_exec.h
index cc408ca71c..6dd92d236a 100644
--- a/src/intel/blorp/blorp_genX_exec.h
+++ b/src/intel/blorp/blorp_genX_exec.h
@@ -529,8 +529,7 @@ blorp_emit_vertex_elements(struct blorp_batch *batch,
 
 /* 3DSTATE_VIEWPORT_STATE_POINTERS */
 static uint32_t
-blorp_emit_cc_viewport(struct blorp_batch *batch,
-   const struct blorp_params *params)
+blorp_emit_cc_viewport(struct blorp_batch *batch)
 {
uint32_t cc_vp_offset;
blorp_emit_dynamic(batch, GENX(CC_VIEWPORT), vp, 32, _vp_offset) {
@@ -553,8 +552,7 @@ blorp_emit_cc_viewport(struct blorp_batch *batch,
 }
 
 static uint32_t
-blorp_emit_sampler_state(struct blorp_batch *batch,
- const struct blorp_params *params)
+blorp_emit_sampler_state(struct blorp_batch *batch)
 {
uint32_t offset;
blorp_emit_dynamic(batch, GENX(SAMPLER_STATE), sampler, 32, ) {
@@ -1013,7 +1011,7 @@ blorp_emit_blend_state(struct blorp_batch *batch,
 
 static uint32_t
 blorp_emit_color_calc_state(struct blorp_batch *batch,
-const struct blorp_params *params)
+MAYBE_UNUSED const struct blorp_params *params)
 {
uint32_t offset;
blorp_emit_dynamic(batch, GENX(COLOR_CALC_STATE), cc, 64, ) {
@@ -1204,7 +1202,7 @@ blorp_emit_pipeline(struct blorp_batch *batch,
blorp_emit(batch, GENX(3DSTATE_CONSTANT_PS), ps);
 
if (params->src.enabled)
-  blorp_emit_sampler_state(batch, params);
+  blorp_emit_sampler_state(batch);
 
blorp_emit_3dstate_multisample(batch, params);
 
@@ -1238,7 +1236,7 @@ blorp_emit_pipeline(struct blorp_batch *batch,
blorp_emit_sf_config(batch, params);
blorp_emit_ps_config(batch, params);
 
-   blorp_emit_cc_viewport(batch, params);
+   blorp_emit_cc_viewport(batch);
 }
 
 / This is the end of the pipeline setup code /
diff --git a/src/mesa/drivers/dri/i965/gen4_blorp_exec.h 
b/src/mesa/drivers/dri/i965/gen4_blorp_exec.h
index 7e5199c56e..e59bc9f2c2 100644
--- a/src/mesa/drivers/dri/i965/gen4_blorp_exec.h
+++ b/src/mesa/drivers/dri/i

Mesa (master): genxml: Silence unused parameter warnings in generated pack code

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 492a472b28b0a73c50a87427585cf95520588d5d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=492a472b28b0a73c50a87427585cf95520588d5d

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Fri Feb 16 19:09:13 2018 -0800

genxml: Silence unused parameter warnings in generated pack code

Reduces my build from 1960 warnings to 1808 warnings by silencing 152
instances of things like

In file included from ../../SOURCE/master/src/intel/genxml/genX_pack.h:32:0,
 from 
../../SOURCE/master/src/intel/isl/isl_emit_depth_stencil.c:36:
src/intel/genxml/gen4_pack.h: In function ‘__gen_uint’:
src/intel/genxml/gen4_pack.h:58:49: warning: unused parameter ‘end’ 
[-Wunused-parameter]
 __gen_uint(uint64_t v, uint32_t start, uint32_t end)
 ^~~
src/intel/genxml/gen4_pack.h: In function ‘__gen_offset’:
src/intel/genxml/gen4_pack.h:94:35: warning: unused parameter ‘start’ 
[-Wunused-parameter]
 __gen_offset(uint64_t v, uint32_t start, uint32_t end)
   ^
src/intel/genxml/gen4_pack.h:94:51: warning: unused parameter ‘end’ 
[-Wunused-parameter]
 __gen_offset(uint64_t v, uint32_t start, uint32_t end)
   ^~~
src/intel/genxml/gen4_pack.h: In function ‘__gen_ufixed’:
src/intel/genxml/gen4_pack.h:133:48: warning: unused parameter ‘end’ 
[-Wunused-parameter]
 __gen_ufixed(float v, uint32_t start, uint32_t end, uint32_t fract_bits)
^~~

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com>

---

 src/intel/genxml/gen_pack_header.py | 14 +++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/src/intel/genxml/gen_pack_header.py 
b/src/intel/genxml/gen_pack_header.py
index e6cea8646f..7dcada86fa 100644
--- a/src/intel/genxml/gen_pack_header.py
+++ b/src/intel/genxml/gen_pack_header.py
@@ -57,6 +57,12 @@ pack_header = """%(license)s
 #ifndef __gen_field_functions
 #define __gen_field_functions
 
+#ifdef NDEBUG
+#define NDEBUG_UNUSED __attribute__((unused))
+#else
+#define NDEBUG_UNUSED
+#endif
+
 union __gen_value {
float f;
uint32_t dw;
@@ -69,7 +75,7 @@ __gen_mbo(uint32_t start, uint32_t end)
 }
 
 static inline uint64_t
-__gen_uint(uint64_t v, uint32_t start, uint32_t end)
+__gen_uint(uint64_t v, uint32_t start, NDEBUG_UNUSED uint32_t end)
 {
__gen_validate_value(v);
 
@@ -105,7 +111,7 @@ __gen_sint(int64_t v, uint32_t start, uint32_t end)
 }
 
 static inline uint64_t
-__gen_offset(uint64_t v, uint32_t start, uint32_t end)
+__gen_offset(uint64_t v, NDEBUG_UNUSED uint32_t start, NDEBUG_UNUSED uint32_t 
end)
 {
__gen_validate_value(v);
 #ifndef NDEBUG
@@ -144,7 +150,7 @@ __gen_sfixed(float v, uint32_t start, uint32_t end, 
uint32_t fract_bits)
 }
 
 static inline uint64_t
-__gen_ufixed(float v, uint32_t start, uint32_t end, uint32_t fract_bits)
+__gen_ufixed(float v, uint32_t start, NDEBUG_UNUSED uint32_t end, uint32_t 
fract_bits)
 {
__gen_validate_value(v);
 
@@ -169,6 +175,8 @@ __gen_ufixed(float v, uint32_t start, uint32_t end, 
uint32_t fract_bits)
 #error #define __gen_combine_address before including this file
 #endif
 
+#undef NDEBUG_UNUSED
+
 #endif
 
 """

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Mesa (master): i965: Silence unused parameter warnings in genX_state_upload

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 1049b57bf262a6afb2e2ab73062376258b33a442
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1049b57bf262a6afb2e2ab73062376258b33a442

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Wed Feb 21 16:16:53 2018 -0800

i965: Silence unused parameter warnings in genX_state_upload

Reduces my build from 1772 warnings to 1717 warnings by silencing 55
instances of things like

../../SOURCE/master/src/mesa/drivers/dri/i965/genX_state_upload.c: In function 
‘gen4_emit_vertex_buffer_state’:
../../SOURCE/master/src/mesa/drivers/dri/i965/genX_state_upload.c:313:41: 
warning: unused parameter ‘end_offset’ [-Wunused-parameter]
unsigned end_offset,
 ^~
../../SOURCE/master/src/mesa/drivers/dri/i965/genX_state_upload.c: In function 
‘gen4_emit_sampler_state_pointers_xs’:
../../SOURCE/master/src/mesa/drivers/dri/i965/genX_state_upload.c:4689:58: 
warning: unused parameter ‘brw’ [-Wunused-parameter]
 genX(emit_sampler_state_pointers_xs)(struct brw_context *brw,
  ^~~
../../SOURCE/master/src/mesa/drivers/dri/i965/genX_state_upload.c:4690:62: 
warning: unused parameter ‘stage_state’ [-Wunused-parameter]
  struct brw_stage_state *stage_state)
  ^~~
../../SOURCE/master/src/mesa/drivers/dri/i965/genX_state_upload.c: In function 
‘gen4_upload_default_color’:
../../SOURCE/master/src/mesa/drivers/dri/i965/genX_state_upload.c:4730:40: 
warning: unused parameter ‘format’ [-Wunused-parameter]
mesa_format format, GLenum base_format,
^~
../../SOURCE/master/src/mesa/drivers/dri/i965/genX_state_upload.c: In function 
‘translate_wrap_mode’:
../../SOURCE/master/src/mesa/drivers/dri/i965/genX_state_upload.c:4906:41: 
warning: unused parameter ‘brw’ [-Wunused-parameter]
 translate_wrap_mode(struct brw_context *brw, GLenum wrap, bool using_nearest)
 ^~~
../../SOURCE/master/src/mesa/drivers/dri/i965/genX_state_upload.c: In function 
‘gen4_update_sampler_state’:
../../SOURCE/master/src/mesa/drivers/dri/i965/genX_state_upload.c:4972:37: 
warning: unused parameter ‘batch_offset_for_sampler_state’ [-Wunused-parameter]
uint32_t batch_offset_for_sampler_state)
 ^~

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com>

---

 src/mesa/drivers/dri/i965/genX_state_upload.c | 34 +++
 1 file changed, 14 insertions(+), 20 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c 
b/src/mesa/drivers/dri/i965/genX_state_upload.c
index d43f0ed2ad..001589a8df 100644
--- a/src/mesa/drivers/dri/i965/genX_state_upload.c
+++ b/src/mesa/drivers/dri/i965/genX_state_upload.c
@@ -158,7 +158,7 @@ KSP(struct brw_context *brw, uint32_t offset)
 }
 #else
 static uint32_t
-KSP(struct brw_context *brw, uint32_t offset)
+KSP(UNUSED struct brw_context *brw, uint32_t offset)
 {
return offset;
 }
@@ -330,9 +330,9 @@ genX(emit_vertex_buffer_state)(struct brw_context *brw,
unsigned buffer_nr,
struct brw_bo *bo,
unsigned start_offset,
-   unsigned end_offset,
+   MAYBE_UNUSED unsigned end_offset,
unsigned stride,
-   unsigned step_rate)
+   MAYBE_UNUSED unsigned step_rate)
 {
struct GENX(VERTEX_BUFFER_STATE) buf_state = {
   .VertexBufferIndex = buffer_nr,
@@ -4732,8 +4732,8 @@ genX(emit_mi_report_perf_count)(struct brw_context *brw,
  * Emit a 3DSTATE_SAMPLER_STATE_POINTERS_{VS,HS,GS,DS,PS} packet.
  */
 static void
-genX(emit_sampler_state_pointers_xs)(struct brw_context *brw,
- struct brw_stage_state *stage_state)
+genX(emit_sampler_state_pointers_xs)(MAYBE_UNUSED struct brw_context *brw,
+ MAYBE_UNUSED struct brw_stage_state 
*stage_state)
 {
 #if GEN_GEN >= 7
static const uint16_t packet_headers[] = {
@@ -4773,7 +4773,7 @@ has_component(mesa_format format, int i)
 static void
 genX(upload_default_color)(struct brw_context *brw,
const struct gl_sampler_object *sampler,
-   mesa_format format, GLenum base_format,
+   MAYBE_UNUSED mesa_format format, GLenum base_format,
bool is_integer_format, bool is_stencil_sampling,
uint32_t *sdc_offset)
 {
@@ -4949,7 +4949,7 @@ genX(upload_default_color)(struct brw_context *brw,

Mesa (master): nir: Rearrange and-compounded float compares

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 053be9f0201db183a761a2a4ce813a114a766b72
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=053be9f0201db183a761a2a4ce813a114a766b72

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Thu Jan  4 15:21:30 2018 -0800

nir: Rearrange and-compounded float compares

If both comparisons are used as sources for instructions other than the
iand, this transformation is detrimental.  If the non-identical value in
both compares is constant, the fmin or fmax will be constant-folded
away, so the transformation is always a win.

It is interesting to me that on Iron Lake only 81 shaders have
instruction counts changed, but 726 shaders have cycle counts changed.

shader-db results:

Skylake
total instructions in shared programs: 14525728 -> 14521017 (-0.03%)
instructions in affected programs: 1164726 -> 1160015 (-0.40%)
helped: 1692
HURT: 5
helped stats (abs) min: 1 max: 637 x̄: 2.79 x̃: 2
helped stats (rel) min: 0.07% max: 16.36% x̄: 0.81% x̃: 0.33%
HURT stats (abs)   min: 1 max: 12 x̄: 3.20 x̃: 1
HURT stats (rel)   min: 0.38% max: 2.86% x̄: 2.36% x̃: 2.86%
95% mean confidence interval for instructions value: -3.52 -2.03
95% mean confidence interval for instructions %-change: -0.86% -0.74%
Instructions are helped.

total cycles in shared programs: 533115449 -> 532991404 (-0.02%)
cycles in affected programs: 119401803 -> 119277758 (-0.10%)
helped: 1145
HURT: 467
helped stats (abs) min: 1 max: 34644 x̄: 145.92 x̃: 18
helped stats (rel) min: <.01% max: 45.33% x̄: 1.58% x̃: 0.42%
HURT stats (abs)   min: 1 max: 1590 x̄: 92.15 x̃: 15
HURT stats (rel)   min: <.01% max: 13.48% x̄: 1.26% x̃: 0.39%
95% mean confidence interval for cycles value: -122.16 -31.74
95% mean confidence interval for cycles %-change: -0.94% -0.57%
Cycles are helped.

total spills in shared programs: 9597 -> 9534 (-0.66%)
spills in affected programs: 403 -> 340 (-15.63%)
helped: 1
HURT: 1

total fills in shared programs: 13904 -> 13790 (-0.82%)
fills in affected programs: 1627 -> 1513 (-7.01%)
helped: 2
HURT: 1

LOST:   0
GAINED: 2

Broadwell
total instructions in shared programs: 14816966 -> 14812590 (-0.03%)
instructions in affected programs: 1499885 -> 1495509 (-0.29%)
helped: 1672
HURT: 15
helped stats (abs) min: 1 max: 455 x̄: 2.70 x̃: 2
helped stats (rel) min: 0.05% max: 16.36% x̄: 0.81% x̃: 0.33%
HURT stats (abs)   min: 1 max: 21 x̄: 9.20 x̃: 8
HURT stats (rel)   min: 0.08% max: 2.86% x̄: 1.06% x̃: 0.53%
95% mean confidence interval for instructions value: -3.14 -2.05
95% mean confidence interval for instructions %-change: -0.85% -0.73%
Instructions are helped.

total cycles in shared programs: 559353622 -> 559345595 (<.01%)
cycles in affected programs: 139893703 -> 139885676 (<.01%)
helped: 921
HURT: 697
helped stats (abs) min: 1 max: 42424 x̄: 143.45 x̃: 18
helped stats (rel) min: <.01% max: 36.23% x̄: 2.02% x̃: 0.87%
HURT stats (abs)   min: 1 max: 2370 x̄: 178.03 x̃: 38
HURT stats (rel)   min: <.01% max: 17.35% x̄: 0.71% x̃: 0.14%
95% mean confidence interval for cycles value: -59.64 49.72
95% mean confidence interval for cycles %-change: -1.02% -0.66%
Inconclusive result (value mean confidence interval includes 0).

total spills in shared programs: 78902 -> 78861 (-0.05%)
spills in affected programs: 2418 -> 2377 (-1.70%)
helped: 1
HURT: 11

total fills in shared programs: 83782 -> 83678 (-0.12%)
fills in affected programs: 3515 -> 3411 (-2.96%)
helped: 2
HURT: 11

LOST:   0
GAINED: 5

Haswell and Ivy Bridge had similar results. Haswell shown.
total instructions in shared programs: 9033898 -> 9032010 (-0.02%)
instructions in affected programs: 308064 -> 306176 (-0.61%)
helped: 921
HURT: 4
helped stats (abs) min: 1 max: 20 x̄: 2.05 x̃: 1
helped stats (rel) min: 0.17% max: 17.54% x̄: 0.80% x̃: 0.35%
HURT stats (abs)   min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel)   min: 3.23% max: 3.23% x̄: 3.23% x̃: 3.23%
95% mean confidence interval for instructions value: -2.21 -1.87
95% mean confidence interval for instructions %-change: -0.88% -0.68%
Instructions are helped.

total cycles in shared programs: 84628949 -> 84620520 (<.01%)
cycles in affected programs: 2164913 -> 2156484 (-0.39%)
helped: 518
HURT: 359
helped stats (abs) min: 1 max: 440 x̄: 41.52 x̃: 20
helped stats (rel) min: <.01% max: 17.17% x̄: 1.95% x̃: 1.01%
HURT stats (abs)   min: 1 max: 586 x̄: 36.43 x̃: 8
HURT stats (rel)   min: 0.04% max: 18.65% x̄: 1.47% x̃: 0.40%
95% mean confidence interval for cycles value: -15.17 -4.05
95% mean confidence interval for cycles %-change: -0.77% -0.32%
Cycles are helped.

LOST:   0
GAINED: 4

Sandy Bridge
total instructions in shared programs: 10544860 -> 10542933 (-0.02%)
instructions in affected programs: 360019 -> 358092 (-0.54%)
helped: 931
HURT: 4
helped stats (abs) min: 1 max: 20 x̄: 2.07 x̃: 1
helped stats (rel) min: 0.11% max: 15.52% x̄: 0.68% x̃: 0.30%
HURT stats (abs)   min: 1 max: 1 x̄: 1.00

Mesa (master): nir: Simplify min and max of b2f

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 68420d8322c2b304a0b15f94b43dec19f082dfae
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=68420d8322c2b304a0b15f94b43dec19f082dfae

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Tue Mar  8 11:11:00 2016 -0800

nir: Simplify min and max of b2f

v2: Rebase on almost 2 years.  Require that one of the arguments to fmin
or fmax be used only once.  This prevents some regressions.

shader-db results:

Skylake and Broadwell had similar results.  Skylake shown.
total instructions in shared programs: 14526021 -> 14525913 (<.01%)
instructions in affected programs: 4613 -> 4505 (-2.34%)
helped: 31
HURT: 0
helped stats (abs) min: 1 max: 4 x̄: 3.48 x̃: 4
helped stats (rel) min: 0.62% max: 6.67% x̄: 3.31% x̃: 2.42%

total cycles in shared programs: 533118710 -> 533118403 (<.01%)
cycles in affected programs: 34334 -> 34027 (-0.89%)
helped: 24
HURT: 0
helped stats (abs) min: 4 max: 24 x̄: 12.79 x̃: 14
helped stats (rel) min: 0.25% max: 2.40% x̄: 1.08% x̃: 1.03%

No changes on GM45, Iron Lake, Sandy Bridge, Ivy Bridge, or Haswell.

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com>
Reviewed-by: Elie Tournier <elie.tourn...@collabora.com>

---

 src/compiler/nir/nir_opt_algebraic.py | 5 +
 1 file changed, 5 insertions(+)

diff --git a/src/compiler/nir/nir_opt_algebraic.py 
b/src/compiler/nir/nir_opt_algebraic.py
index b141f2414d..c097f12832 100644
--- a/src/compiler/nir/nir_opt_algebraic.py
+++ b/src/compiler/nir/nir_opt_algebraic.py
@@ -158,6 +158,11 @@ optimizations = [
# a != 0.0
(('flt', 0.0, ('fabs', a)), ('fne', a, 0.0)),
 
+   (('fmax',('b2f(is_used_once)', a),   
('b2f', b)),   ('b2f', ('ior', a, b))),
+   (('fmax', ('fneg(is_used_once)', ('b2f(is_used_once)', a)), ('fneg', 
('b2f', b))), ('fneg', ('b2f', ('ior', a, b,
+   (('fmin',('b2f(is_used_once)', a),   
('b2f', b)),   ('b2f', ('iand', a, b))),
+   (('fmin', ('fneg(is_used_once)', ('b2f(is_used_once)', a)), ('fneg', 
('b2f', b))), ('fneg', ('b2f', ('iand', a, b,
+
# ignore this opt when the result is used by a bcsel or if so we can make
# use of conditional modifiers on supported hardware.
(('flt(is_not_used_by_conditional)', ('fadd(is_used_once)', a, ('fneg', 
b)), 0.0), ('flt', a, b)),

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Mesa (master): nir: Rearrange logic op-compounded integer compares

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 03fb13f646732d234d3698acfa089ee0216cbe8f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=03fb13f646732d234d3698acfa089ee0216cbe8f

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Fri Jan  5 13:20:46 2018 -0800

nir: Rearrange logic op-compounded integer compares

Skylake and Broadwell had similar results.  Skylake shown.
total instructions in shared programs: 14521769 -> 14521753 (<.01%)
instructions in affected programs: 8782 -> 8766 (-0.18%)
helped: 16
HURT: 0
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 0.12% max: 0.40% x̄: 0.20% x̃: 0.18%
95% mean confidence interval for instructions value: -1.00 -1.00
95% mean confidence interval for instructions %-change: -0.23% -0.16%
Instructions are helped.

total cycles in shared programs: 533000376 -> 533000205 (<.01%)
cycles in affected programs: 447035 -> 446864 (-0.04%)
helped: 9
HURT: 9
helped stats (abs) min: 2 max: 40 x̄: 35.78 x̃: 40
helped stats (rel) min: 0.02% max: 0.18% x̄: 0.10% x̃: 0.09%
HURT stats (abs)   min: 1 max: 52 x̄: 16.78 x̃: 10
HURT stats (rel)   min: <.01% max: 1.11% x̄: 0.29% x̃: 0.12%
95% mean confidence interval for cycles value: -25.07 6.07
95% mean confidence interval for cycles %-change: -0.08% 0.27%
Inconclusive result (value mean confidence interval includes 0).

No changes on GM45, Iron Lake, Sandy Bridge, Ivy Bridge, or Haswell.

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com>
Reviewed-by: Elie Tournier <elie.tourn...@collabora.com>

---

 src/compiler/nir/nir_opt_algebraic.py | 35 +++
 1 file changed, 35 insertions(+)

diff --git a/src/compiler/nir/nir_opt_algebraic.py 
b/src/compiler/nir/nir_opt_algebraic.py
index 9dadb67bd2..3cc910a8a6 100644
--- a/src/compiler/nir/nir_opt_algebraic.py
+++ b/src/compiler/nir/nir_opt_algebraic.py
@@ -218,6 +218,23 @@ optimizations = [
(('~iand', ('fge', a, '#b'), ('fge', a, '#c')), ('fge', a, ('fmax', b, c))),
(('~iand', ('fge', '#a', c), ('fge', '#b', c)), ('fge', ('fmin', a, b), c)),
 
+   (('ior', ('ilt(is_used_once)', a, b), ('ilt', a, c)), ('ilt', a, ('imax', 
b, c))),
+   (('ior', ('ilt(is_used_once)', a, c), ('ilt', b, c)), ('ilt', ('imin', a, 
b), c)),
+   (('ior', ('ige(is_used_once)', a, b), ('ige', a, c)), ('ige', a, ('imin', 
b, c))),
+   (('ior', ('ige(is_used_once)', a, c), ('ige', b, c)), ('ige', ('imax', a, 
b), c)),
+   (('ior', ('ult(is_used_once)', a, b), ('ult', a, c)), ('ult', a, ('umax', 
b, c))),
+   (('ior', ('ult(is_used_once)', a, c), ('ult', b, c)), ('ult', ('umin', a, 
b), c)),
+   (('ior', ('uge(is_used_once)', a, b), ('uge', a, c)), ('uge', a, ('umin', 
b, c))),
+   (('ior', ('uge(is_used_once)', a, c), ('uge', b, c)), ('uge', ('umax', a, 
b), c)),
+   (('iand', ('ilt(is_used_once)', a, b), ('ilt', a, c)), ('ilt', a, ('imin', 
b, c))),
+   (('iand', ('ilt(is_used_once)', a, c), ('ilt', b, c)), ('ilt', ('imax', a, 
b), c)),
+   (('iand', ('ige(is_used_once)', a, b), ('ige', a, c)), ('ige', a, ('imax', 
b, c))),
+   (('iand', ('ige(is_used_once)', a, c), ('ige', b, c)), ('ige', ('imin', a, 
b), c)),
+   (('iand', ('ult(is_used_once)', a, b), ('ult', a, c)), ('ult', a, ('umin', 
b, c))),
+   (('iand', ('ult(is_used_once)', a, c), ('ult', b, c)), ('ult', ('umax', a, 
b), c)),
+   (('iand', ('uge(is_used_once)', a, b), ('uge', a, c)), ('uge', a, ('umax', 
b, c))),
+   (('iand', ('uge(is_used_once)', a, c), ('uge', b, c)), ('uge', ('umin', a, 
b), c)),
+
# These patterns can result when (a < b || a < c) => (a < min(b, c))
# transformations occur before constant propagation and loop-unrolling.
(('~flt', a, ('fmax', b, a)), ('flt', a, b)),
@@ -227,6 +244,24 @@ optimizations = [
(('~flt', a, ('fmin', b, a)), False),
(('~flt', ('fmax', a, b), a), False),
 
+   (('ilt', a, ('imax', b, a)), ('ilt', a, b)),
+   (('ilt', ('imin', a, b), a), ('ilt', b, a)),
+   (('ige', a, ('imin', b, a)), True),
+   (('ige', ('imax', a, b), a), True),
+   (('ult', a, ('umax', b, a)), ('ult', a, b)),
+   (('ult', ('umin', a, b), a), ('ult', b, a)),
+   (('uge', a, ('umin', b, a)), True),
+   (('uge', ('umax', a, b), a), True),
+
+   (('ilt', '#a', ('imin', '#b', c)), ('iand', ('ilt', a, b), ('ilt', a, c))),
+   (('ilt', ('imax', '#a', b), '#c'), ('iand', ('ilt', a, c), ('ilt', b, c))),
+   (('ige', '#a', ('imax', '#b', c)), ('iand', ('ige', a, b), ('ige', a, c))),
+   (('ige', ('imin', '#a', b), '#c'), ('iand', ('ige', a, c), ('ige', b, c))),
+   (('ult', '#a', ('umin', '#b', c)), ('iand', ('ult', a, b), ('ult', a, c))),
+   (('ult', ('umax', '#a', b), '#c'), ('iand', ('ult', a, c), ('ult', b, c))),
+   (('uge', '#a', ('umax', '#b', c)), ('iand', ('uge', a, b), ('uge', a, c))),
+   (('uge', ('umin', '#a', b), '#c'), ('iand', ('uge', a, c), ('uge', b, c))),
+
(('fabs', ('slt', a, b)), ('slt', a, b)),
(('fabs', ('sge', a,

Mesa (master): nir: See through an fneg to apply existing optimizations

[Ian Romanick]

Module: Mesa
Branch: master
Commit: cfc0d34802b13a7436f8d0029e9b1370f2bc585e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cfc0d34802b13a7436f8d0029e9b1370f2bc585e

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Tue Jan  9 15:32:47 2018 -0800

nir: See through an fneg to apply existing optimizations

Doing the same for the existing feq and fne transformations didn't help
anything in shader-db.

shader-db results:

Broadwell and Skylake (Skylake shown)
total instructions in shared programs: 14529463 -> 14526147 (-0.02%)
instructions in affected programs: 402420 -> 399104 (-0.82%)
helped: 2136
HURT: 131
helped stats (abs) min: 1 max: 10 x̄: 1.61 x̃: 1
helped stats (rel) min: 0.03% max: 16.22% x̄: 3.14% x̃: 1.12%
HURT stats (abs)   min: 1 max: 2 x̄: 1.01 x̃: 1
HURT stats (rel)   min: 0.13% max: 7.69% x̄: 0.75% x̃: 0.57%
95% mean confidence interval for instructions value: -1.51 -1.41
95% mean confidence interval for instructions %-change: -3.06% -2.78%
Instructions are helped.

total cycles in shared programs: 533146915 -> 533120531 (<.01%)
cycles in affected programs: 10356261 -> 10329877 (-0.25%)
helped: 1933
HURT: 844
helped stats (abs) min: 1 max: 490 x̄: 29.44 x̃: 16
helped stats (rel) min: <.01% max: 28.57% x̄: 3.43% x̃: 1.88%
HURT stats (abs)   min: 1 max: 423 x̄: 36.17 x̃: 12
HURT stats (rel)   min: <.01% max: 23.75% x̄: 1.90% x̃: 0.59%
95% mean confidence interval for cycles value: -11.78 -7.22
95% mean confidence interval for cycles %-change: -1.98% -1.65%
Cycles are helped.

Haswell
total instructions in shared programs: 9037416 -> 9034106 (-0.04%)
instructions in affected programs: 389831 -> 386521 (-0.85%)
helped: 2184
HURT: 120
helped stats (abs) min: 1 max: 11 x̄: 1.57 x̃: 1
helped stats (rel) min: 0.03% max: 25.00% x̄: 2.73% x̃: 1.02%
HURT stats (abs)   min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel)   min: 0.19% max: 7.69% x̄: 0.81% x̃: 0.57%
95% mean confidence interval for instructions value: -1.49 -1.39
95% mean confidence interval for instructions %-change: -2.68% -2.41%
Instructions are helped.

total cycles in shared programs: 84636243 -> 84631628 (<.01%)
cycles in affected programs: 4745058 -> 4740443 (-0.10%)
helped: 1904
HURT: 960
helped stats (abs) min: 1 max: 466 x̄: 30.21 x̃: 18
helped stats (rel) min: 0.02% max: 36.36% x̄: 3.57% x̃: 2.38%
HURT stats (abs)   min: 1 max: 1080 x̄: 55.11 x̃: 14
HURT stats (rel)   min: 0.02% max: 51.33% x̄: 2.77% x̃: 0.81%
95% mean confidence interval for cycles value: -4.51 1.29
95% mean confidence interval for cycles %-change: -1.64% -1.25%
Inconclusive result (value mean confidence interval includes 0).

LOST:   1
GAINED: 0

Sandy Bridge and Ivy Bridge (Ivy Bridge shown)
total instructions in shared programs: 10018873 -> 10015456 (-0.03%)
instructions in affected programs: 512820 -> 509403 (-0.67%)
helped: 2268
HURT: 162
helped stats (abs) min: 1 max: 11 x̄: 1.62 x̃: 1
helped stats (rel) min: 0.03% max: 25.00% x̄: 2.47% x̃: 0.88%
HURT stats (abs)   min: 1 max: 4 x̄: 1.59 x̃: 1
HURT stats (rel)   min: 0.09% max: 7.69% x̄: 0.86% x̃: 0.50%
95% mean confidence interval for instructions value: -1.46 -1.35
95% mean confidence interval for instructions %-change: -2.38% -2.12%
Instructions are helped.

total cycles in shared programs: 87538223 -> 87524771 (-0.02%)
cycles in affected programs: 5435520 -> 5422068 (-0.25%)
helped: 1916
HURT: 946
helped stats (abs) min: 1 max: 1392 x̄: 29.44 x̃: 18
helped stats (rel) min: <.01% max: 34.51% x̄: 3.34% x̃: 1.97%
HURT stats (abs)   min: 1 max: 633 x̄: 45.41 x̃: 11
HURT stats (rel)   min: 0.02% max: 25.95% x̄: 2.41% x̃: 0.62%
95% mean confidence interval for cycles value: -7.34 -2.06
95% mean confidence interval for cycles %-change: -1.62% -1.26%
Cycles are helped.

LOST:   1
GAINED: 0

Iron Lake
total instructions in shared programs: 7888446 -> 7886959 (-0.02%)
instructions in affected programs: 331581 -> 330094 (-0.45%)
helped: 1160
HURT: 97
helped stats (abs) min: 1 max: 10 x̄: 1.37 x̃: 1
helped stats (rel) min: 0.02% max: 9.68% x̄: 0.93% x̃: 0.43%
HURT stats (abs)   min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel)   min: 0.17% max: 4.17% x̄: 0.37% x̃: 0.25%
95% mean confidence interval for instructions value: -1.25 -1.12
95% mean confidence interval for instructions %-change: -0.91% -0.75%
Instructions are helped.

total cycles in shared programs: 178130766 -> 178116996 (<.01%)
cycles in affected programs: 12534564 -> 12520794 (-0.11%)
helped: 1856
HURT: 187
helped stats (abs) min: 2 max: 202 x̄: 7.78 x̃: 4
helped stats (rel) min: <.01% max: 6.47% x̄: 0.28% x̃: 0.11%
HURT stats (abs)   min: 2 max: 26 x̄: 3.55 x̃: 2
HURT stats (rel)   min: 0.01% max: 2.14% x̄: 0.08% x̃: 0.02%
95% mean confidence interval for cycles value: -7.41 -6.07
95% mean confidence interval for cycles %-change: -0.28% -0.22%
Cycles are helped.

GM45
total instructions in shared programs: 4858912 -> 4857887 (-0.02%)
instructions in affected prog

Mesa (master): nir: Separate a weird compare with zero to two compares with zero

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 821e7a4d329f8460d0d27683580a703d9ed8431c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=821e7a4d329f8460d0d27683580a703d9ed8431c

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Thu Jan 11 14:14:25 2018 -0800

nir: Separate a weird compare with zero to two compares with zero

min(a+b, c+d) >= 0 becomes (a+b >= 0 && c+d >= 0).

No shader-db changes, but it does prevent 6 to 12 instruction
regressions in the next patch on all measured Intel platforms.

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com>
Reviewed-by: Elie Tournier <elie.tourn...@collabora.com>

---

 src/compiler/nir/nir_opt_algebraic.py | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/compiler/nir/nir_opt_algebraic.py 
b/src/compiler/nir/nir_opt_algebraic.py
index c097f12832..bee135c235 100644
--- a/src/compiler/nir/nir_opt_algebraic.py
+++ b/src/compiler/nir/nir_opt_algebraic.py
@@ -596,6 +596,8 @@ late_optimizations = [
(('~feq', ('fadd', a, b), 0.0), ('feq', a, ('fneg', b))),
(('~fne', ('fadd', a, b), 0.0), ('fne', a, ('fneg', b))),
 
+   (('~fge', ('fmin(is_used_once)', ('fadd(is_used_once)', a, b), ('fadd', c, 
d)), 0.0), ('iand', ('fge', a, ('fneg', b)), ('fge', c, ('fneg', d,
+
(('fdot2', a, b), ('fdot_replicated2', a, b), 'options->fdot_replicates'),
(('fdot3', a, b), ('fdot_replicated3', a, b), 'options->fdot_replicates'),
(('fdot4', a, b), ('fdot_replicated4', a, b), 'options->fdot_replicates'),

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Mesa (master): nir: Distribute binary operations with constants into bcsel

[Ian Romanick]

Module: Mesa
Branch: master
Commit: ee63933a73653564c490cff1f841d98e6265df97
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ee63933a73653564c490cff1f841d98e6265df97

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Wed Mar  2 15:39:09 2016 -0800

nir: Distribute binary operations with constants into bcsel

This was specifically designed to simplify 1+mix(0, a-1, condition) to
mix(1, a, condition) by pushing the 1+ inside.

Skylake, Broadwell, and Haswell had similar results.  Skylake shown.
total instructions in shared programs: 14521753 -> 14521716 (<.01%)
instructions in affected programs: 10619 -> 10582 (-0.35%)
helped: 51
HURT: 14
helped stats (abs) min: 1 max: 12 x̄: 1.43 x̃: 1
helped stats (rel) min: 0.20% max: 3.58% x̄: 1.01% x̃: 0.95%
HURT stats (abs)   min: 1 max: 11 x̄: 2.57 x̃: 1
HURT stats (rel)   min: 0.22% max: 1.75% x̄: 1.20% x̃: 1.32%
95% mean confidence interval for instructions value: -1.31 0.17
95% mean confidence interval for instructions %-change: -0.80% -0.27%
Inconclusive result (value mean confidence interval includes 0).

total cycles in shared programs: 533000205 -> 533003533 (<.01%)
cycles in affected programs: 110610 -> 113938 (3.01%)
helped: 43
HURT: 28
helped stats (abs) min: 6 max: 440 x̄: 27.12 x̃: 16
helped stats (rel) min: 0.39% max: 4.84% x̄: 1.60% x̃: 1.67%
HURT stats (abs)   min: 2 max: 3066 x̄: 160.50 x̃: 14
HURT stats (rel)   min: 0.08% max: 77.78% x̄: 5.16% x̃: 0.62%
95% mean confidence interval for cycles value: -43.81 137.56
95% mean confidence interval for cycles %-change: -1.47% 3.60%
Inconclusive result (value mean confidence interval includes 0).

Ivy Bridge
total instructions in shared programs: 10018840 -> 10018713 (<.01%)
instructions in affected programs: 9431 -> 9304 (-1.35%)
helped: 51
HURT: 3
helped stats (abs) min: 1 max: 80 x̄: 2.76 x̃: 1
helped stats (rel) min: 0.20% max: 16.43% x̄: 1.16% x̃: 0.81%
HURT stats (abs)   min: 1 max: 12 x̄: 4.67 x̃: 1
HURT stats (rel)   min: 0.22% max: 1.33% x̄: 0.59% x̃: 0.22%
95% mean confidence interval for instructions value: -5.36 0.66
95% mean confidence interval for instructions %-change: -1.66% -0.46%
Inconclusive result (value mean confidence interval includes 0).

total cycles in shared programs: 87571944 -> 87572785 (<.01%)
cycles in affected programs: 117234 -> 118075 (0.72%)
helped: 42
HURT: 23
helped stats (abs) min: 2 max: 114 x̄: 51.90 x̃: 30
helped stats (rel) min: 0.11% max: 11.01% x̄: 4.45% x̃: 2.74%
HURT stats (abs)   min: 1 max: 2341 x̄: 131.35 x̃: 10
HURT stats (rel)   min: 0.06% max: 37.11% x̄: 2.75% x̃: 0.61%
95% mean confidence interval for cycles value: -61.05 86.93
95% mean confidence interval for cycles %-change: -3.47% -0.33%
Inconclusive result (value mean confidence interval includes 0).

Sandy Bridge
total instructions in shared programs: 10542933 -> 10542844 (<.01%)
instructions in affected programs: 11487 -> 11398 (-0.77%)
helped: 52
HURT: 3
helped stats (abs) min: 1 max: 40 x̄: 1.96 x̃: 1
helped stats (rel) min: 0.08% max: 8.16% x̄: 0.90% x̃: 0.72%
HURT stats (abs)   min: 1 max: 11 x̄: 4.33 x̃: 1
HURT stats (rel)   min: 0.22% max: 1.22% x̄: 0.55% x̃: 0.22%
95% mean confidence interval for instructions value: -3.17 -0.07
95% mean confidence interval for instructions %-change: -1.13% -0.52%
Instructions are helped.

total cycles in shared programs: 146098397 -> 146097094 (<.01%)
cycles in affected programs: 128140 -> 126837 (-1.02%)
helped: 47
HURT: 8
helped stats (abs) min: 2 max: 333 x̄: 29.21 x̃: 18
helped stats (rel) min: 0.13% max: 5.04% x̄: 1.18% x̃: 0.95%
HURT stats (abs)   min: 1 max: 16 x̄: 8.75 x̃: 9
HURT stats (rel)   min: 0.08% max: 0.43% x̄: 0.30% x̃: 0.34%
95% mean confidence interval for cycles value: -37.49 -9.90
95% mean confidence interval for cycles %-change: -1.22% -0.71%
Cycles are helped.

Iron Lake
total instructions in shared programs: 7886711 -> 7886509 (<.01%)
instructions in affected programs: 10425 -> 10223 (-1.94%)
helped: 50
HURT: 2
helped stats (abs) min: 1 max: 78 x̄: 4.08 x̃: 1
helped stats (rel) min: 0.34% max: 15.38% x̄: 1.12% x̃: 0.54%
HURT stats (abs)   min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel)   min: 0.86% max: 0.91% x̄: 0.89% x̃: 0.89%
95% mean confidence interval for instructions value: -8.05 0.28
95% mean confidence interval for instructions %-change: -1.83% -0.26%
Inconclusive result (value mean confidence interval includes 0).

total cycles in shared programs: 178115324 -> 178114612 (<.01%)
cycles in affected programs: 765726 -> 765014 (-0.09%)
helped: 39
HURT: 1
helped stats (abs) min: 2 max: 276 x̄: 18.31 x̃: 8
helped stats (rel) min: <.01% max: 8.47% x̄: 0.39% x̃: 0.04%
HURT stats (abs)   min: 2 max: 2 x̄: 2.00 x̃: 2
HURT stats (rel)   min: 0.03% max: 0.03% x̄: 0.03% x̃: 0.03%
95% mean confidence interval for cycles value: -32.07 -3.53
95% mean confidence interval for cycles %-change: -0.86% 0.10%
Inconclusive result (%-change mean conf

Mesa (master): nir: Undo possible damage caused by rearranging or-compounded float compares

[Ian Romanick]

Module: Mesa
Branch: master
Commit: d8d18516b0aa81f6791889bab7ce14703e65d8b4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d8d18516b0aa81f6791889bab7ce14703e65d8b4

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Fri Jan  5 13:29:26 2018 -0800

nir: Undo possible damage caused by rearranging or-compounded float compares

shader-db results:

Skylake and Broadwell had similar results (Skylake shown)
total instructions in shared programs: 14525898 -> 14525836 (<.01%)
instructions in affected programs: 1964 -> 1902 (-3.16%)
helped: 14
HURT: 0
helped stats (abs) min: 1 max: 25 x̄: 4.43 x̃: 1
helped stats (rel) min: 0.68% max: 9.77% x̄: 2.10% x̃: 0.86%
95% mean confidence interval for instructions value: -9.46 0.60
95% mean confidence interval for instructions %-change: -3.97% -0.24%
Inconclusive result (value mean confidence interval includes 0).

total cycles in shared programs: 533119892 -> 533115756 (<.01%)
cycles in affected programs: 96061 -> 91925 (-4.31%)
helped: 13
HURT: 1
helped stats (abs) min: 60 max: 596 x̄: 318.77 x̃: 300
helped stats (rel) min: 1.15% max: 5.49% x̄: 4.27% x̃: 4.42%
HURT stats (abs)   min: 8 max: 8 x̄: 8.00 x̃: 8
HURT stats (rel)   min: 0.46% max: 0.46% x̄: 0.46% x̃: 0.46%
95% mean confidence interval for cycles value: -379.43 -211.43
95% mean confidence interval for cycles %-change: -4.84% -3.01%
Cycles are helped.

Haswell, Ivy Bridge and Sandy Bridge had similar results (Haswell shown).
total instructions in shared programs: 9033948 -> 9033898 (<.01%)
instructions in affected programs: 535 -> 485 (-9.35%)
helped: 2
HURT: 0

total cycles in shared programs: 84631402 -> 84628949 (<.01%)
cycles in affected programs: 63197 -> 60744 (-3.88%)
helped: 13
HURT: 2
helped stats (abs) min: 1 max: 594 x̄: 189.62 x̃: 140
helped stats (rel) min: 0.07% max: 5.04% x̄: 3.79% x̃: 4.01%
HURT stats (abs)   min: 4 max: 8 x̄: 6.00 x̃: 6
HURT stats (rel)   min: 0.17% max: 0.45% x̄: 0.31% x̃: 0.31%
95% mean confidence interval for cycles value: -253.40 -73.67
95% mean confidence interval for cycles %-change: -4.24% -2.25%
Cycles are helped.

No changes on GM45 or Iron Lake.

v2: Add a couple more tautological compares.  Suggested by Elie.

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com>
Reviewed-by: Elie Tournier <elie.tourn...@collabora.com>

---

 src/compiler/nir/nir_opt_algebraic.py | 9 +
 1 file changed, 9 insertions(+)

diff --git a/src/compiler/nir/nir_opt_algebraic.py 
b/src/compiler/nir/nir_opt_algebraic.py
index 09538ba25a..b141f2414d 100644
--- a/src/compiler/nir/nir_opt_algebraic.py
+++ b/src/compiler/nir/nir_opt_algebraic.py
@@ -205,6 +205,15 @@ optimizations = [
(('~ior', ('fge', a, '#b'), ('fge', a, '#c')), ('fge', a, ('fmin', b, c))),
(('~ior', ('fge', '#a', c), ('fge', '#b', c)), ('fge', ('fmax', a, b), c)),
 
+   # These patterns can result when (a < b || a < c) => (a < min(b, c))
+   # transformations occur before constant propagation and loop-unrolling.
+   (('~flt', a, ('fmax', b, a)), ('flt', a, b)),
+   (('~flt', ('fmin', a, b), a), ('flt', b, a)),
+   (('~fge', a, ('fmin', b, a)), True),
+   (('~fge', ('fmax', a, b), a), True),
+   (('~flt', a, ('fmin', b, a)), False),
+   (('~flt', ('fmax', a, b), a), False),
+
(('fabs', ('slt', a, b)), ('slt', a, b)),
(('fabs', ('sge', a, b)), ('sge', a, b)),
(('fabs', ('seq', a, b)), ('seq', a, b)),

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Mesa (master): nir: Be more conservative about rearranging or-compounded compares

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 3941cba0f76d2e004cd26df3cabf063f68eed899
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3941cba0f76d2e004cd26df3cabf063f68eed899

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Thu Jan  4 13:30:49 2018 -0800

nir: Be more conservative about rearranging or-compounded compares

If both comparisons are used as sources for instructions other than the
ior, this transformation is detrimental.  If the non-identical value in
both compares is constant, the fmin or fmax will be constant-folded
away, so the transformation is always a win.

shader-db results:

Skylake
total instructions in shared programs: 14526147 -> 14525898 (<.01%)
instructions in affected programs: 70239 -> 69990 (-0.35%)
helped: 102
HURT: 0
helped stats (abs) min: 1 max: 8 x̄: 2.44 x̃: 1
helped stats (rel) min: 0.07% max: 2.30% x̄: 0.38% x̃: 0.20%
95% mean confidence interval for instructions value: -2.86 -2.02
95% mean confidence interval for instructions %-change: -0.46% -0.31%
Instructions are helped.

total cycles in shared programs: 533120531 -> 533119892 (<.01%)
cycles in affected programs: 994875 -> 994236 (-0.06%)
helped: 76
HURT: 26
helped stats (abs) min: 1 max: 324 x̄: 27.09 x̃: 13
helped stats (rel) min: <.01% max: 4.21% x̄: 0.45% x̃: 0.18%
HURT stats (abs)   min: 1 max: 167 x̄: 54.62 x̃: 26
HURT stats (rel)   min: <.01% max: 4.36% x̄: 1.01% x̃: 0.39%
95% mean confidence interval for cycles value: -19.44 6.91
95% mean confidence interval for cycles %-change: -0.30% 0.15%
Inconclusive result (value mean confidence interval includes 0).

Broadwell
total instructions in shared programs: 14816005 -> 14815787 (<.01%)
instructions in affected programs: 64658 -> 64440 (-0.34%)
helped: 97
HURT: 0
helped stats (abs) min: 1 max: 8 x̄: 2.25 x̃: 1
helped stats (rel) min: 0.07% max: 2.30% x̄: 0.38% x̃: 0.20%
95% mean confidence interval for instructions value: -2.62 -1.87
95% mean confidence interval for instructions %-change: -0.45% -0.30%
Instructions are helped.

total cycles in shared programs: 559340386 -> 559339907 (<.01%)
cycles in affected programs: 1090491 -> 1090012 (-0.04%)
helped: 66
HURT: 28
helped stats (abs) min: 2 max: 198 x̄: 23.83 x̃: 16
helped stats (rel) min: 0.01% max: 4.21% x̄: 0.47% x̃: 0.27%
HURT stats (abs)   min: 2 max: 226 x̄: 39.07 x̃: 11
HURT stats (rel)   min: <.01% max: 4.61% x̄: 0.64% x̃: 0.20%
95% mean confidence interval for cycles value: -15.94 5.75
95% mean confidence interval for cycles %-change: -0.35% 0.07%
Inconclusive result (value mean confidence interval includes 0).

LOST:   0
GAINED: 1

Haswell
total instructions in shared programs: 9034106 -> 9033948 (<.01%)
instructions in affected programs: 24096 -> 23938 (-0.66%)
helped: 38
HURT: 0
helped stats (abs) min: 1 max: 8 x̄: 4.16 x̃: 4
helped stats (rel) min: 0.42% max: 2.29% x̄: 0.71% x̃: 0.64%
95% mean confidence interval for instructions value: -4.71 -3.60
95% mean confidence interval for instructions %-change: -0.84% -0.58%
Instructions are helped.

total cycles in shared programs: 84631628 -> 84631402 (<.01%)
cycles in affected programs: 148674 -> 148448 (-0.15%)
helped: 14
HURT: 14
helped stats (abs) min: 1 max: 114 x̄: 22.14 x̃: 12
helped stats (rel) min: 0.02% max: 2.98% x̄: 0.66% x̃: 0.21%
HURT stats (abs)   min: 1 max: 10 x̄: 6.00 x̃: 5
HURT stats (rel)   min: 0.01% max: 0.20% x̄: 0.12% x̃: 0.11%
95% mean confidence interval for cycles value: -19.42 3.28
95% mean confidence interval for cycles %-change: -0.59% 0.05%
Inconclusive result (value mean confidence interval includes 0).

Ivy Bridge
total instructions in shared programs: 10015456 -> 10015293 (<.01%)
instructions in affected programs: 27701 -> 27538 (-0.59%)
helped: 38
HURT: 0
helped stats (abs) min: 1 max: 9 x̄: 4.29 x̃: 4
helped stats (rel) min: 0.33% max: 2.79% x̄: 0.66% x̃: 0.52%
95% mean confidence interval for instructions value: -4.87 -3.71
95% mean confidence interval for instructions %-change: -0.82% -0.51%
Instructions are helped.

total cycles in shared programs: 87524771 -> 87524569 (<.01%)
cycles in affected programs: 112324 -> 112122 (-0.18%)
helped: 6
HURT: 12
helped stats (abs) min: 2 max: 111 x̄: 44.67 x̃: 20
helped stats (rel) min: 0.02% max: 2.94% x̄: 1.45% x̃: 1.26%
HURT stats (abs)   min: 1 max: 16 x̄: 5.50 x̃: 5
HURT stats (rel)   min: <.01% max: 0.16% x̄: 0.08% x̃: 0.08%
95% mean confidence interval for cycles value: -29.14 6.69
95% mean confidence interval for cycles %-change: -0.93% 0.08%
Inconclusive result (value mean confidence interval includes 0).

LOST:   0
GAINED: 2

Sandy Bridge
total instructions in shared programs: 10545655 -> 10545465 (<.01%)
instructions in affected programs: 37198 -> 37008 (-0.51%)
helped: 42
HURT: 0
helped stats (abs) min: 1 max: 8 x̄: 4.52 x̃: 4
helped stats (rel) min: 0.31% max: 2.15% x̄: 0.58% x̃: 0.49%
95% mean confidence interval for instructions value: -5.14 -3.91
95% mean 

Mesa (master): i965: Make intelEmitCopyBlit static

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 9eed6bea6b781d2df21720df440594dc87805e1d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9eed6bea6b781d2df21720df440594dc87805e1d

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Wed Jan  3 12:40:00 2018 -0800

i965: Make intelEmitCopyBlit static

And rename to emit_copy_blit.

v2: sed --in-place -e 's/color_logic_ops/gl_logicop_mode/g' $(grep -lr
color_logic_ops src/) suggested by Brian.

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> [v1]

---

 src/mesa/drivers/dri/i965/intel_blit.c | 398 -
 src/mesa/drivers/dri/i965/intel_blit.h |  16 --
 2 files changed, 199 insertions(+), 215 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_blit.c 
b/src/mesa/drivers/dri/i965/intel_blit.c
index 96e5aba85d..dcecab677e 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.c
+++ b/src/mesa/drivers/dri/i965/intel_blit.c
@@ -203,6 +203,183 @@ get_blit_intratile_offset_el(const struct brw_context 
*brw,
 }
 
 static bool
+alignment_valid(struct brw_context *brw, unsigned offset,
+enum isl_tiling tiling)
+{
+   const struct gen_device_info *devinfo = >screen->devinfo;
+
+   /* Tiled buffers must be page-aligned (4K). */
+   if (tiling != ISL_TILING_LINEAR)
+  return (offset & 4095) == 0;
+
+   /* On Gen8+, linear buffers must be cacheline-aligned. */
+   if (devinfo->gen >= 8)
+  return (offset & 63) == 0;
+
+   return true;
+}
+
+static uint32_t
+xy_blit_cmd(enum isl_tiling src_tiling, enum isl_tiling dst_tiling,
+uint32_t cpp)
+{
+   uint32_t CMD = 0;
+
+   assert(cpp <= 4);
+   switch (cpp) {
+   case 1:
+   case 2:
+  CMD = XY_SRC_COPY_BLT_CMD;
+  break;
+   case 4:
+  CMD = XY_SRC_COPY_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
+  break;
+   default:
+  unreachable("not reached");
+   }
+
+   if (dst_tiling != ISL_TILING_LINEAR)
+  CMD |= XY_DST_TILED;
+
+   if (src_tiling != ISL_TILING_LINEAR)
+  CMD |= XY_SRC_TILED;
+
+   return CMD;
+}
+
+/* Copy BitBlt
+ */
+static bool
+emit_copy_blit(struct brw_context *brw,
+   GLuint cpp,
+   int32_t src_pitch,
+   struct brw_bo *src_buffer,
+   GLuint src_offset,
+   enum isl_tiling src_tiling,
+   int32_t dst_pitch,
+   struct brw_bo *dst_buffer,
+   GLuint dst_offset,
+   enum isl_tiling dst_tiling,
+   GLshort src_x, GLshort src_y,
+   GLshort dst_x, GLshort dst_y,
+   GLshort w, GLshort h,
+   enum gl_logicop_mode logic_op)
+{
+   const struct gen_device_info *devinfo = >screen->devinfo;
+   GLuint CMD, BR13;
+   int dst_y2 = dst_y + h;
+   int dst_x2 = dst_x + w;
+   bool dst_y_tiled = dst_tiling == ISL_TILING_Y0;
+   bool src_y_tiled = src_tiling == ISL_TILING_Y0;
+   uint32_t src_tile_w, src_tile_h;
+   uint32_t dst_tile_w, dst_tile_h;
+
+   if ((dst_y_tiled || src_y_tiled) && devinfo->gen < 6)
+  return false;
+
+   const unsigned bo_sizes = dst_buffer->size + src_buffer->size;
+
+   /* do space check before going any further */
+   if (!brw_batch_has_aperture_space(brw, bo_sizes))
+  intel_batchbuffer_flush(brw);
+
+   if (!brw_batch_has_aperture_space(brw, bo_sizes))
+  return false;
+
+   unsigned length = devinfo->gen >= 8 ? 10 : 8;
+
+   intel_batchbuffer_require_space(brw, length * 4, BLT_RING);
+   DBG("%s src:buf(%p)/%d+%d %d,%d dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n",
+   __func__,
+   src_buffer, src_pitch, src_offset, src_x, src_y,
+   dst_buffer, dst_pitch, dst_offset, dst_x, dst_y, w, h);
+
+   intel_get_tile_dims(src_tiling, cpp, _tile_w, _tile_h);
+   intel_get_tile_dims(dst_tiling, cpp, _tile_w, _tile_h);
+
+   /* For Tiled surfaces, the pitch has to be a multiple of the Tile width
+* (X direction width of the Tile). This is ensured while allocating the
+* buffer object.
+*/
+   assert(src_tiling == ISL_TILING_LINEAR || (src_pitch % src_tile_w) == 0);
+   assert(dst_tiling == ISL_TILING_LINEAR || (dst_pitch % dst_tile_w) == 0);
+
+   /* For big formats (such as floating point), do the copy using 16 or
+* 32bpp and multiply the coordinates.
+*/
+   if (cpp > 4) {
+  if (cpp % 4 == 2) {
+ dst_x *= cpp / 2;
+ dst_x2 *= cpp / 2;
+ src_x *= cpp / 2;
+ cpp = 2;
+  } else {
+ assert(cpp % 4 == 0);
+ dst_x *= cpp / 4;
+ dst_x2 *= cpp / 4;
+ src_x *= cpp / 4;
+ cpp = 4;
+  }
+   }
+
+   if (!alignment_valid(brw, dst_offset, dst_tiling))
+  return false;
+   if (!alignment_valid(brw, src_offset, src_tiling))
+  return false;
+
+   /* Blit pitch must be dword-aligned.  Otherwise, the hardware appears to 
drop
+* the low bits.  Offsets must be naturally al

Mesa (master): st/mesa: Use the translated color logic op from the context

[Ian Romanick]

Module: Mesa
Branch: master
Commit: cf0b26ec1250567fe0c5e9cc556806e64e843d19
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cf0b26ec1250567fe0c5e9cc556806e64e843d19

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Wed Jan  3 11:44:17 2018 -0800

st/mesa: Use the translated color logic op from the context

And delete the resulting dead code.

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Brian Paul <bri...@vmware.com>
Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>

---

 src/mesa/state_tracker/st_atom_blend.c | 48 +-
 1 file changed, 1 insertion(+), 47 deletions(-)

diff --git a/src/mesa/state_tracker/st_atom_blend.c 
b/src/mesa/state_tracker/st_atom_blend.c
index 103c500802..8bc5a5fd12 100644
--- a/src/mesa/state_tracker/st_atom_blend.c
+++ b/src/mesa/state_tracker/st_atom_blend.c
@@ -107,52 +107,6 @@ translate_blend(GLenum blend)
}
 }
 
-
-/**
- * Convert GLenum logicop tokens to pipe tokens.
- */
-static GLuint
-translate_logicop(GLenum logicop)
-{
-   switch (logicop) {
-   case GL_CLEAR:
-  return PIPE_LOGICOP_CLEAR;
-   case GL_NOR:
-  return PIPE_LOGICOP_NOR;
-   case GL_AND_INVERTED:
-  return PIPE_LOGICOP_AND_INVERTED;
-   case GL_COPY_INVERTED:
-  return PIPE_LOGICOP_COPY_INVERTED;
-   case GL_AND_REVERSE:
-  return PIPE_LOGICOP_AND_REVERSE;
-   case GL_INVERT:
-  return PIPE_LOGICOP_INVERT;
-   case GL_XOR:
-  return PIPE_LOGICOP_XOR;
-   case GL_NAND:
-  return PIPE_LOGICOP_NAND;
-   case GL_AND:
-  return PIPE_LOGICOP_AND;
-   case GL_EQUIV:
-  return PIPE_LOGICOP_EQUIV;
-   case GL_NOOP:
-  return PIPE_LOGICOP_NOOP;
-   case GL_OR_INVERTED:
-  return PIPE_LOGICOP_OR_INVERTED;
-   case GL_COPY:
-  return PIPE_LOGICOP_COPY;
-   case GL_OR_REVERSE:
-  return PIPE_LOGICOP_OR_REVERSE;
-   case GL_OR:
-  return PIPE_LOGICOP_OR;
-   case GL_SET:
-  return PIPE_LOGICOP_SET;
-   default:
-  assert("invalid GL token in translate_logicop()" == NULL);
-  return 0;
-   }
-}
-
 /**
  * Figure out if colormasks are different per rt.
  */
@@ -204,7 +158,7 @@ st_update_blend( struct st_context *st )
if (ctx->Color.ColorLogicOpEnabled) {
   /* logicop enabled */
   blend->logicop_enable = 1;
-  blend->logicop_func = translate_logicop(ctx->Color.LogicOp);
+  blend->logicop_func = ctx->Color._LogicOp;
}
else if (ctx->Color.BlendEnabled && !ctx->Color._AdvancedBlendMode) {
   /* blending enabled */

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Mesa (master): i915: Use enum color_logic_ops for blits

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 4e9e964de6cbf540f15b481d37b310f514331d1b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4e9e964de6cbf540f15b481d37b310f514331d1b

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Wed Jan  3 12:33:20 2018 -0800

i915: Use enum color_logic_ops for blits

v2: sed --in-place -e 's/color_logic_ops/gl_logicop_mode/g' $(grep -lr
color_logic_ops src/) suggested by Brian.

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> [v1]

---

 src/mesa/drivers/dri/i915/intel_blit.c | 34 ++
 src/mesa/drivers/dri/i915/intel_blit.h |  6 ++---
 src/mesa/drivers/dri/i915/intel_fbo.c  |  2 +-
 src/mesa/drivers/dri/i915/intel_mipmap_tree.c  |  6 ++---
 src/mesa/drivers/dri/i915/intel_pixel_bitmap.c |  4 +--
 src/mesa/drivers/dri/i915/intel_pixel_copy.c   |  2 +-
 src/mesa/drivers/dri/i915/intel_pixel_read.c   |  2 +-
 src/mesa/drivers/dri/i915/intel_tex_copy.c |  2 +-
 src/mesa/drivers/dri/i915/intel_tex_image.c|  2 +-
 src/mesa/drivers/dri/i915/intel_tex_subimage.c |  2 +-
 10 files changed, 22 insertions(+), 40 deletions(-)

diff --git a/src/mesa/drivers/dri/i915/intel_blit.c 
b/src/mesa/drivers/dri/i915/intel_blit.c
index 279db28b7e..551f18ffd2 100644
--- a/src/mesa/drivers/dri/i915/intel_blit.c
+++ b/src/mesa/drivers/dri/i915/intel_blit.c
@@ -48,27 +48,9 @@ intel_miptree_set_alpha_to_one(struct intel_context *intel,
struct intel_mipmap_tree *mt,
int x, int y, int width, int height);
 
-static GLuint translate_raster_op(GLenum logicop)
+static GLuint translate_raster_op(enum gl_logicop_mode logicop)
 {
-   switch(logicop) {
-   case GL_CLEAR: return 0x00;
-   case GL_AND: return 0x88;
-   case GL_AND_REVERSE: return 0x44;
-   case GL_COPY: return 0xCC;
-   case GL_AND_INVERTED: return 0x22;
-   case GL_NOOP: return 0xAA;
-   case GL_XOR: return 0x66;
-   case GL_OR: return 0xEE;
-   case GL_NOR: return 0x11;
-   case GL_EQUIV: return 0x99;
-   case GL_INVERT: return 0x55;
-   case GL_OR_REVERSE: return 0xDD;
-   case GL_COPY_INVERTED: return 0x33;
-   case GL_OR_INVERTED: return 0xBB;
-   case GL_NAND: return 0x77;
-   case GL_SET: return 0xFF;
-   default: return 0;
-   }
+   return logicop | (logicop << 4);
 }
 
 static uint32_t
@@ -114,7 +96,7 @@ intel_miptree_blit(struct intel_context *intel,
int dst_level, int dst_slice,
uint32_t dst_x, uint32_t dst_y, bool dst_flip,
uint32_t width, uint32_t height,
-   GLenum logicop)
+   enum gl_logicop_mode logicop)
 {
/* No sRGB decode or encode is done by the hardware blitter, which is
 * consistent with what we want in the callers (glCopyTexSubImage(),
@@ -227,7 +209,7 @@ intelEmitCopyBlit(struct intel_context *intel,
  GLshort src_x, GLshort src_y,
  GLshort dst_x, GLshort dst_y,
  GLshort w, GLshort h,
- GLenum logic_op)
+ enum gl_logicop_mode logic_op)
 {
GLuint CMD, BR13, pass = 0;
int dst_y2 = dst_y + h;
@@ -523,7 +505,7 @@ intelEmitImmediateColorExpandBlit(struct intel_context 
*intel,
  uint32_t dst_tiling,
  GLshort x, GLshort y,
  GLshort w, GLshort h,
- GLenum logic_op)
+ enum gl_logicop_mode logic_op)
 {
int dwords = ALIGN(src_size, 8) / 4;
uint32_t opcode, br13, blit_cmd;
@@ -535,7 +517,7 @@ intelEmitImmediateColorExpandBlit(struct intel_context 
*intel,
 return false;
}
 
-   assert((logic_op >= GL_CLEAR) && (logic_op <= (GL_CLEAR + 0x0f)));
+   assert((unsigned)logic_op <= 0x0f);
assert(dst_pitch > 0);
 
if (w < 0 || h < 0)
@@ -613,7 +595,7 @@ intel_emit_linear_blit(struct intel_context *intel,
  0, 0, /* src x/y */
  0, 0, /* dst x/y */
  pitch, height, /* w, h */
- GL_COPY);
+ COLOR_LOGICOP_COPY);
if (!ok)
   _mesa_problem(ctx, "Failed to linear blit %dx%d\n", pitch, height);
 
@@ -629,7 +611,7 @@ intel_emit_linear_blit(struct intel_context *intel,
 0, 0, /* src x/y */
 0, 0, /* dst x/y */
 size, 1, /* w, h */
-GL_COPY);
+COLOR_LOGICOP_COPY);
   if (!ok)
  _mesa_problem(ctx, "Failed to linear blit %dx%d\n", size, 1);
}
diff --git a/src/mesa/drivers/dri/i915/intel_blit.h 
b/src/mesa/drivers/dri/i915/intel_blit.h
index 1e76126aad..5c0d3597f1 100644
--- a/src/mesa/drivers/dri/i915/intel_blit.h
+++ b/src/mesa/dr

Mesa (master): i915: Make intelEmitCopyBlit static

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 39f875a6b7b15833ff448aaeae5b1a3fc4905583
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=39f875a6b7b15833ff448aaeae5b1a3fc4905583

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Wed Jan  3 12:43:24 2018 -0800

i915: Make intelEmitCopyBlit static

And rename to emit_copy_blit.

v2: sed --in-place -e 's/color_logic_ops/gl_logicop_mode/g' $(grep -lr
color_logic_ops src/) suggested by Brian.

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> [v1]

---

 src/mesa/drivers/dri/i915/intel_blit.c   | 299 +++
 src/mesa/drivers/dri/i915/intel_blit.h   |  16 --
 src/mesa/drivers/dri/i915/intel_screen.h |   1 -
 3 files changed, 149 insertions(+), 167 deletions(-)

diff --git a/src/mesa/drivers/dri/i915/intel_blit.c 
b/src/mesa/drivers/dri/i915/intel_blit.c
index 551f18ffd2..98cffaf248 100644
--- a/src/mesa/drivers/dri/i915/intel_blit.c
+++ b/src/mesa/drivers/dri/i915/intel_blit.c
@@ -72,144 +72,23 @@ br13_for_cpp(int cpp)
}
 }
 
-/**
- * Implements a rectangular block transfer (blit) of pixels between two
- * miptrees.
- *
- * Our blitter can operate on 1, 2, or 4-byte-per-pixel data, with generous,
- * but limited, pitches and sizes allowed.
- *
- * The src/dst coordinates are relative to the given level/slice of the
- * miptree.
- *
- * If @src_flip or @dst_flip is set, then the rectangle within that miptree
- * will be inverted (including scanline order) when copying.  This is common
- * in GL when copying between window system and user-created
- * renderbuffers/textures.
- */
-bool
-intel_miptree_blit(struct intel_context *intel,
-   struct intel_mipmap_tree *src_mt,
-   int src_level, int src_slice,
-   uint32_t src_x, uint32_t src_y, bool src_flip,
-   struct intel_mipmap_tree *dst_mt,
-   int dst_level, int dst_slice,
-   uint32_t dst_x, uint32_t dst_y, bool dst_flip,
-   uint32_t width, uint32_t height,
-   enum gl_logicop_mode logicop)
-{
-   /* No sRGB decode or encode is done by the hardware blitter, which is
-* consistent with what we want in the callers (glCopyTexSubImage(),
-* glBlitFramebuffer(), texture validation, etc.).
-*/
-   mesa_format src_format = _mesa_get_srgb_format_linear(src_mt->format);
-   mesa_format dst_format = _mesa_get_srgb_format_linear(dst_mt->format);
-
-   /* The blitter doesn't support doing any format conversions.  We do also
-* support blitting ARGB to XRGB (trivial, the values dropped into
-* the X channel don't matter), and XRGB to ARGB by setting the A
-* channel to 1.0 at the end.
-*/
-   if (src_format != dst_format &&
-  ((src_format != MESA_FORMAT_B8G8R8A8_UNORM &&
-src_format != MESA_FORMAT_B8G8R8X8_UNORM) ||
-   (dst_format != MESA_FORMAT_B8G8R8A8_UNORM &&
-dst_format != MESA_FORMAT_B8G8R8X8_UNORM))) {
-  perf_debug("%s: Can't use hardware blitter from %s to %s, "
- "falling back.\n", __func__,
- _mesa_get_format_name(src_format),
- _mesa_get_format_name(dst_format));
-  return false;
-   }
-
-   /* According to the Ivy Bridge PRM, Vol1 Part4, section 1.2.1.2 (Graphics
-* Data Size Limitations):
-*
-*The BLT engine is capable of transferring very large quantities of
-*graphics data. Any graphics data read from and written to the
-*destination is permitted to represent a number of pixels that
-*occupies up to 65,536 scan lines and up to 32,768 bytes per scan line
-*at the destination. The maximum number of pixels that may be
-*represented per scan line’s worth of graphics data depends on the
-*color depth.
-*
-* Furthermore, intelEmitCopyBlit (which is called below) uses a signed
-* 16-bit integer to represent buffer pitch, so it can only handle buffer
-* pitches < 32k.
-*
-* As a result of these two limitations, we can only use the blitter to do
-* this copy when the region's pitch is less than 32k.
-*/
-   if (src_mt->region->pitch > 32768 ||
-   dst_mt->region->pitch > 32768) {
-  perf_debug("Falling back due to >32k pitch\n");
-  return false;
-   }
-
-   if (src_flip)
-  src_y = src_mt->level[src_level].height - src_y - height;
-
-   if (dst_flip)
-  dst_y = dst_mt->level[dst_level].height - dst_y - height;
-
-   int src_pitch = src_mt->region->pitch;
-   if (src_flip != dst_flip)
-  src_pitch = -src_pitch;
-
-   uint32_t src_image_x, src_image_y;
-   intel_miptree_get_image_offset(src_mt, src_level, src_slice,
-  _image_x, _image_y);
-   src_x += src_image_x;
-   src_y += src

Mesa (master): mesa: Also track a remapped version of the color logic op

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 9c1f010f3463d4e1ea488200390fa21f3db0b814
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9c1f010f3463d4e1ea488200390fa21f3db0b814

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Wed Jan  3 11:26:41 2018 -0800

mesa: Also track a remapped version of the color logic op

With the exception of NVIDIA hardware, these are is the values that all
hardware and Gallium want.  The remapping is currently implemented in at
least 6 places.  This starts the process of consolidating to a single
place.

v2: sed --in-place -e 's/color_logic_ops/gl_logicop_mode/g' $(grep -lr
color_logic_ops src/) suggested by Brian.  Added some comments about the
selection of bit patterns for gl_logicop_mode and the GLenums.
Suggested by Nicolai.  Folded the GLenum_to_color_logicop macro into its
only users.

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Brian Paul <bri...@vmware.com> [v1]
Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>

---

 src/mesa/main/blend.c  | 20 
 src/mesa/main/mtypes.h | 38 ++
 2 files changed, 58 insertions(+)

diff --git a/src/mesa/main/blend.c b/src/mesa/main/blend.c
index 01721ab615..1c3711766e 100644
--- a/src/mesa/main/blend.c
+++ b/src/mesa/main/blend.c
@@ -849,6 +849,24 @@ _mesa_AlphaFunc( GLenum func, GLclampf ref )
}
 }
 
+static const enum gl_logicop_mode color_logicop_mapping[16] = {
+   COLOR_LOGICOP_CLEAR,
+   COLOR_LOGICOP_AND,
+   COLOR_LOGICOP_AND_REVERSE,
+   COLOR_LOGICOP_COPY,
+   COLOR_LOGICOP_AND_INVERTED,
+   COLOR_LOGICOP_NOOP,
+   COLOR_LOGICOP_XOR,
+   COLOR_LOGICOP_OR,
+   COLOR_LOGICOP_NOR,
+   COLOR_LOGICOP_EQUIV,
+   COLOR_LOGICOP_INVERT,
+   COLOR_LOGICOP_OR_REVERSE,
+   COLOR_LOGICOP_COPY_INVERTED,
+   COLOR_LOGICOP_OR_INVERTED,
+   COLOR_LOGICOP_NAND,
+   COLOR_LOGICOP_SET
+};
 
 static ALWAYS_INLINE void
 logic_op(struct gl_context *ctx, GLenum opcode, bool no_error)
@@ -884,6 +902,7 @@ logic_op(struct gl_context *ctx, GLenum opcode, bool 
no_error)
FLUSH_VERTICES(ctx, ctx->DriverFlags.NewLogicOp ? 0 : _NEW_COLOR);
ctx->NewDriverState |= ctx->DriverFlags.NewLogicOp;
ctx->Color.LogicOp = opcode;
+   ctx->Color._LogicOp = color_logicop_mapping[opcode & 0x0f];
 
if (ctx->Driver.LogicOpcode)
   ctx->Driver.LogicOpcode(ctx, opcode);
@@ -1189,6 +1208,7 @@ void _mesa_init_color( struct gl_context * ctx )
ctx->Color.IndexLogicOpEnabled = GL_FALSE;
ctx->Color.ColorLogicOpEnabled = GL_FALSE;
ctx->Color.LogicOp = GL_COPY;
+   ctx->Color._LogicOp = COLOR_LOGICOP_COPY;
ctx->Color.DitherFlag = GL_TRUE;
 
/* GL_FRONT is not possible on GLES. Instead GL_BACK will render to either
diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index e587f63df2..0c47be4ec7 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -413,6 +413,43 @@ union gl_color_union
GLuint ui[4];
 };
 
+/**
+ * Remapped color logical operations
+ *
+ * With the exception of NVIDIA hardware, which consumes the OpenGL enumerants
+ * directly, everything wants this mapping of color logical operations.
+ *
+ * Fun fact: These values are just the bit-reverse of the low-nibble of the GL
+ * enumerant values (i.e., `GL_NOOP & 0x0f` is `b0101' while
+ * \c COLOR_LOGICOP_NOOP is `b1010`).
+ *
+ * Fun fact #2: These values are just an encoding of the operation as a table
+ * of bit values. The result of the logic op is:
+ *
+ *result_bit = (logic_op >> (2 * src_bit + dst_bit)) & 1
+ *
+ * For the GL enums, the result is:
+ *
+ *result_bit = logic_op & (1 << (2 * src_bit + dst_bit))
+ */
+enum PACKED gl_logicop_mode {
+   COLOR_LOGICOP_CLEAR = 0,
+   COLOR_LOGICOP_NOR = 1,
+   COLOR_LOGICOP_AND_INVERTED = 2,
+   COLOR_LOGICOP_COPY_INVERTED = 3,
+   COLOR_LOGICOP_AND_REVERSE = 4,
+   COLOR_LOGICOP_INVERT = 5,
+   COLOR_LOGICOP_XOR = 6,
+   COLOR_LOGICOP_NAND = 7,
+   COLOR_LOGICOP_AND = 8,
+   COLOR_LOGICOP_EQUIV = 9,
+   COLOR_LOGICOP_NOOP = 10,
+   COLOR_LOGICOP_OR_INVERTED = 11,
+   COLOR_LOGICOP_COPY = 12,
+   COLOR_LOGICOP_OR_REVERSE = 13,
+   COLOR_LOGICOP_OR = 14,
+   COLOR_LOGICOP_SET = 15
+};
 
 /**
  * Color buffer attribute group (GL_COLOR_BUFFER_BIT).
@@ -488,6 +525,7 @@ struct gl_colorbuffer_attrib
GLboolean IndexLogicOpEnabled;  /**< Color index logic op enabled flag 
*/
GLboolean ColorLogicOpEnabled;  /**< RGBA logic op enabled flag */
GLenum LogicOp; /**< Logic operator */
+   enum gl_logicop_mode _LogicOp;
 
/*@}*/
 

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Mesa (master): i965: Use the translated color logic op from the context

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 0c69db895f790a9d59f7b5cc784f91f570775225
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0c69db895f790a9d59f7b5cc784f91f570775225

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Wed Jan  3 11:43:10 2018 -0800

i965: Use the translated color logic op from the context

And delete the resulting dead code.

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com>

---

 src/mesa/drivers/dri/i965/brw_context.h   |  1 -
 src/mesa/drivers/dri/i965/genX_state_upload.c |  3 +-
 src/mesa/drivers/dri/i965/intel_state.c   | 41 ---
 3 files changed, 1 insertion(+), 44 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
b/src/mesa/drivers/dri/i965/brw_context.h
index 9046acd175..c30207e313 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1499,7 +1499,6 @@ extern void intelInitExtensions(struct gl_context *ctx);
 extern int intel_translate_shadow_compare_func(GLenum func);
 extern int intel_translate_compare_func(GLenum func);
 extern int intel_translate_stencil_op(GLenum op);
-extern int intel_translate_logic_op(GLenum opcode);
 
 /* brw_sync.c */
 void brw_init_syncobj_functions(struct dd_function_table *functions);
diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c 
b/src/mesa/drivers/dri/i965/genX_state_upload.c
index 50ac5bc59f..aa4d64d08e 100644
--- a/src/mesa/drivers/dri/i965/genX_state_upload.c
+++ b/src/mesa/drivers/dri/i965/genX_state_upload.c
@@ -2819,8 +2819,7 @@ set_blend_entry_bits(struct brw_context *brw, 
BLEND_ENTRY_GENXML *entry, int i,
 _mesa_enum_to_string(rb_type));
   if (GEN_GEN >= 8 || rb_type == GL_UNSIGNED_NORMALIZED) {
  entry->LogicOpEnable = true;
- entry->LogicOpFunction =
-intel_translate_logic_op(ctx->Color.LogicOp);
+ entry->LogicOpFunction = ctx->Color._LogicOp;
   }
} else if (blend_enabled && !ctx->Color._AdvancedBlendMode
   && (GEN_GEN <= 5 || !integer)) {
diff --git a/src/mesa/drivers/dri/i965/intel_state.c 
b/src/mesa/drivers/dri/i965/intel_state.c
index 5001a49faf..3d477dfcf0 100644
--- a/src/mesa/drivers/dri/i965/intel_state.c
+++ b/src/mesa/drivers/dri/i965/intel_state.c
@@ -117,44 +117,3 @@ intel_translate_stencil_op(GLenum op)
   return BRW_STENCILOP_ZERO;
}
 }
-
-int
-intel_translate_logic_op(GLenum opcode)
-{
-   switch (opcode) {
-   case GL_CLEAR:
-  return BRW_LOGICOPFUNCTION_CLEAR;
-   case GL_AND:
-  return BRW_LOGICOPFUNCTION_AND;
-   case GL_AND_REVERSE:
-  return BRW_LOGICOPFUNCTION_AND_REVERSE;
-   case GL_COPY:
-  return BRW_LOGICOPFUNCTION_COPY;
-   case GL_COPY_INVERTED:
-  return BRW_LOGICOPFUNCTION_COPY_INVERTED;
-   case GL_AND_INVERTED:
-  return BRW_LOGICOPFUNCTION_AND_INVERTED;
-   case GL_NOOP:
-  return BRW_LOGICOPFUNCTION_NOOP;
-   case GL_XOR:
-  return BRW_LOGICOPFUNCTION_XOR;
-   case GL_OR:
-  return BRW_LOGICOPFUNCTION_OR;
-   case GL_OR_INVERTED:
-  return BRW_LOGICOPFUNCTION_OR_INVERTED;
-   case GL_NOR:
-  return BRW_LOGICOPFUNCTION_NOR;
-   case GL_EQUIV:
-  return BRW_LOGICOPFUNCTION_EQUIV;
-   case GL_INVERT:
-  return BRW_LOGICOPFUNCTION_INVERT;
-   case GL_OR_REVERSE:
-  return BRW_LOGICOPFUNCTION_OR_REVERSE;
-   case GL_NAND:
-  return BRW_LOGICOPFUNCTION_NAND;
-   case GL_SET:
-  return BRW_LOGICOPFUNCTION_SET;
-   default:
-  return BRW_LOGICOPFUNCTION_SET;
-   }
-}

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Mesa (master): mesa: Pass the translated color logic op dd_function_table::LogicOpcode

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 0aaa27f29187ffb739c7ba2d789b82114f59f054
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0aaa27f29187ffb739c7ba2d789b82114f59f054

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Wed Jan  3 11:45:58 2018 -0800

mesa: Pass the translated color logic op dd_function_table::LogicOpcode

And delete the resulting dead code.  This has only been compile-tested.

v2: sed --in-place -e 's/color_logic_ops/gl_logicop_mode/g' $(grep -lr
color_logic_ops src/) suggested by Brian.

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Brian Paul <bri...@vmware.com>
Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>

---

 src/mesa/drivers/common/driverfuncs.c|  2 +-
 src/mesa/drivers/dri/i915/i830_state.c   |  8 +++---
 src/mesa/drivers/dri/i915/i915_state.c   |  8 +++---
 src/mesa/drivers/dri/i915/intel_context.h|  1 -
 src/mesa/drivers/dri/i915/intel_screen.h |  1 -
 src/mesa/drivers/dri/i915/intel_state.c  | 41 
 src/mesa/drivers/dri/nouveau/nouveau_state.c |  2 +-
 src/mesa/drivers/dri/r200/r200_state.c   |  7 ++---
 src/mesa/drivers/dri/radeon/radeon_state.c   | 27 ++
 src/mesa/main/blend.c|  2 +-
 src/mesa/main/dd.h   |  2 +-
 11 files changed, 18 insertions(+), 83 deletions(-)

diff --git a/src/mesa/drivers/common/driverfuncs.c 
b/src/mesa/drivers/common/driverfuncs.c
index 94dc0e6275..99c1520d2a 100644
--- a/src/mesa/drivers/common/driverfuncs.c
+++ b/src/mesa/drivers/common/driverfuncs.c
@@ -277,7 +277,7 @@ _mesa_init_driver_state(struct gl_context *ctx)
}
 
ctx->Driver.LineWidth(ctx, ctx->Line.Width);
-   ctx->Driver.LogicOpcode(ctx, ctx->Color.LogicOp);
+   ctx->Driver.LogicOpcode(ctx, ctx->Color._LogicOp);
ctx->Driver.PointSize(ctx, ctx->Point.Size);
ctx->Driver.PolygonStipple(ctx, (const GLubyte *) ctx->PolygonStipple);
ctx->Driver.Scissor(ctx);
diff --git a/src/mesa/drivers/dri/i915/i830_state.c 
b/src/mesa/drivers/dri/i915/i830_state.c
index 7ce5ef7e41..c8f48fbfa5 100644
--- a/src/mesa/drivers/dri/i915/i830_state.c
+++ b/src/mesa/drivers/dri/i915/i830_state.c
@@ -573,16 +573,16 @@ i830Scissor(struct gl_context * ctx)
 }
 
 static void
-i830LogicOp(struct gl_context * ctx, GLenum opcode)
+i830LogicOp(struct gl_context * ctx, enum gl_logicop_mode opcode)
 {
struct i830_context *i830 = i830_context(ctx);
-   int tmp = intel_translate_logic_op(opcode);
 
DBG("%s\n", __func__);
-   
+
+   assert((unsigned)opcode <= 15);
I830_STATECHANGE(i830, I830_UPLOAD_CTX);
i830->state.Ctx[I830_CTXREG_STATE4] &= ~LOGICOP_MASK;
-   i830->state.Ctx[I830_CTXREG_STATE4] |= LOGIC_OP_FUNC(tmp);
+   i830->state.Ctx[I830_CTXREG_STATE4] |= opcode;
 }
 
 
diff --git a/src/mesa/drivers/dri/i915/i915_state.c 
b/src/mesa/drivers/dri/i915/i915_state.c
index 685af046b5..bf7005a06f 100644
--- a/src/mesa/drivers/dri/i915/i915_state.c
+++ b/src/mesa/drivers/dri/i915/i915_state.c
@@ -539,16 +539,16 @@ i915Scissor(struct gl_context * ctx)
 }
 
 static void
-i915LogicOp(struct gl_context * ctx, GLenum opcode)
+i915LogicOp(struct gl_context * ctx, enum gl_logicop_mode opcode)
 {
struct i915_context *i915 = I915_CONTEXT(ctx);
-   int tmp = intel_translate_logic_op(opcode);
 
DBG("%s\n", __func__);
-   
+
+   assert((unsigned)opcode <= 15);
I915_STATECHANGE(i915, I915_UPLOAD_CTX);
i915->state.Ctx[I915_CTXREG_STATE4] &= ~LOGICOP_MASK;
-   i915->state.Ctx[I915_CTXREG_STATE4] |= LOGIC_OP_FUNC(tmp);
+   i915->state.Ctx[I915_CTXREG_STATE4] |= LOGIC_OP_FUNC(opcode);
 }
 
 
diff --git a/src/mesa/drivers/dri/i915/intel_context.h 
b/src/mesa/drivers/dri/i915/intel_context.h
index c59436aa2a..5361dcf5e3 100644
--- a/src/mesa/drivers/dri/i915/intel_context.h
+++ b/src/mesa/drivers/dri/i915/intel_context.h
@@ -421,7 +421,6 @@ extern int intel_translate_shadow_compare_func(GLenum func);
 extern int intel_translate_compare_func(GLenum func);
 extern int intel_translate_stencil_op(GLenum op);
 extern int intel_translate_blend_factor(GLenum factor);
-extern int intel_translate_logic_op(GLenum opcode);
 
 void intel_update_renderbuffers(__DRIcontext *context,
__DRIdrawable *drawable);
diff --git a/src/mesa/drivers/dri/i915/intel_screen.h 
b/src/mesa/drivers/dri/i915/intel_screen.h
index a22888b391..ec4592d1e1 100644
--- a/src/mesa/drivers/dri/i915/intel_screen.h
+++ b/src/mesa/drivers/dri/i915/intel_screen.h
@@ -139,7 +139,6 @@ struct intel_screen
 #define get_timeold_get_time
 #define intel_translate_blend_factorold_intel_translate_blend_factor
 #define intel_translate_compare_funcold_intel_translate_compare_func
-#define intel_translate_logic_opold_intel_translate_logic_op
 #define intel_translate_shadow_compare_func 
old_in

Mesa (master): i965: Use enum color_logic_ops for blits

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 21be331401f32b9cde8b4514e5bec322b16a88f8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=21be331401f32b9cde8b4514e5bec322b16a88f8

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Wed Jan  3 12:03:58 2018 -0800

i965: Use enum color_logic_ops for blits

v2: sed --in-place -e 's/color_logic_ops/gl_logicop_mode/g' $(grep -lr
color_logic_ops src/) suggested by Brian.

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> [v1]

---

 src/mesa/drivers/dri/i965/intel_blit.c | 36 +++---
 src/mesa/drivers/dri/i965/intel_blit.h |  6 ++---
 src/mesa/drivers/dri/i965/intel_fbo.c  |  3 ++-
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c  |  2 +-
 src/mesa/drivers/dri/i965/intel_pixel_bitmap.c |  4 +--
 src/mesa/drivers/dri/i965/intel_pixel_copy.c   |  2 +-
 src/mesa/drivers/dri/i965/intel_pixel_draw.c   |  2 +-
 src/mesa/drivers/dri/i965/intel_tex_copy.c |  2 +-
 8 files changed, 20 insertions(+), 37 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_blit.c 
b/src/mesa/drivers/dri/i965/intel_blit.c
index 46945b2995..96e5aba85d 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.c
+++ b/src/mesa/drivers/dri/i965/intel_blit.c
@@ -44,27 +44,9 @@ intel_miptree_set_alpha_to_one(struct brw_context *brw,
struct intel_mipmap_tree *mt,
int x, int y, int width, int height);
 
-static GLuint translate_raster_op(GLenum logicop)
+static GLuint translate_raster_op(enum gl_logicop_mode logicop)
 {
-   switch(logicop) {
-   case GL_CLEAR: return 0x00;
-   case GL_AND: return 0x88;
-   case GL_AND_REVERSE: return 0x44;
-   case GL_COPY: return 0xCC;
-   case GL_AND_INVERTED: return 0x22;
-   case GL_NOOP: return 0xAA;
-   case GL_XOR: return 0x66;
-   case GL_OR: return 0xEE;
-   case GL_NOR: return 0x11;
-   case GL_EQUIV: return 0x99;
-   case GL_INVERT: return 0x55;
-   case GL_OR_REVERSE: return 0xDD;
-   case GL_COPY_INVERTED: return 0x33;
-   case GL_OR_INVERTED: return 0xBB;
-   case GL_NAND: return 0x77;
-   case GL_SET: return 0xFF;
-   default: return 0;
-   }
+   return logicop | (logicop << 4);
 }
 
 static uint32_t
@@ -227,7 +209,7 @@ emit_miptree_blit(struct brw_context *brw,
   struct intel_mipmap_tree *dst_mt,
   uint32_t dst_x, uint32_t dst_y,
   uint32_t width, uint32_t height,
-  bool reverse, GLenum logicop)
+  bool reverse, enum gl_logicop_mode logicop)
 {
/* According to the Ivy Bridge PRM, Vol1 Part4, section 1.2.1.2 (Graphics
 * Data Size Limitations):
@@ -319,7 +301,7 @@ intel_miptree_blit(struct brw_context *brw,
int dst_level, int dst_slice,
uint32_t dst_x, uint32_t dst_y, bool dst_flip,
uint32_t width, uint32_t height,
-   GLenum logicop)
+   enum gl_logicop_mode logicop)
 {
/* The blitter doesn't understand multisampling at all. */
if (src_mt->surf.samples > 1 || dst_mt->surf.samples > 1)
@@ -463,7 +445,7 @@ intel_miptree_copy(struct brw_context *brw,
 
return emit_miptree_blit(brw, src_mt, src_x, src_y,
 dst_mt, dst_x, dst_y,
-src_width, src_height, false, GL_COPY);
+src_width, src_height, false, COLOR_LOGICOP_COPY);
 }
 
 static bool
@@ -527,7 +509,7 @@ intelEmitCopyBlit(struct brw_context *brw,
  GLshort src_x, GLshort src_y,
  GLshort dst_x, GLshort dst_y,
  GLshort w, GLshort h,
- GLenum logic_op)
+ enum gl_logicop_mode logic_op)
 {
const struct gen_device_info *devinfo = >screen->devinfo;
GLuint CMD, BR13;
@@ -654,7 +636,7 @@ intelEmitImmediateColorExpandBlit(struct brw_context *brw,
  enum isl_tiling dst_tiling,
  GLshort x, GLshort y,
  GLshort w, GLshort h,
- GLenum logic_op)
+ enum gl_logicop_mode logic_op)
 {
const struct gen_device_info *devinfo = >screen->devinfo;
int dwords = ALIGN(src_size, 8) / 4;
@@ -667,7 +649,7 @@ intelEmitImmediateColorExpandBlit(struct brw_context *brw,
 return false;
}
 
-   assert((logic_op >= GL_CLEAR) && (logic_op <= (GL_CLEAR + 0x0f)));
+   assert((unsigned) logic_op <= 0x0f);
assert(dst_pitch > 0);
 
if (w < 0 || h < 0)
@@ -763,7 +745,7 @@ intel_emit_linear_blit(struct brw_context *brw,
  src_x, 0, /* src x/y */
  dst_x, 0, /* dst x/y */
  MIN2(size, pitch), height, /* w, h */
- GL_COPY);
+ 

Mesa (master): nouveau: Remove no-op nvgl_logicop_func function

[Ian Romanick]

Module: Mesa
Branch: master
Commit: c7deeb71a8fc1d7c8e3b51924bdce3356dee7e70
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c7deeb71a8fc1d7c8e3b51924bdce3356dee7e70

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Wed Jan  3 18:28:57 2018 -0800

nouveau: Remove no-op nvgl_logicop_func function

The values that this function returned were always the values passed
in.  The only thing that happened was either an assertion or undefined
results when an unknown value was passed in.  This doesn't seem that
useful.  Most of nouveau_gldefs.h could be removed in this manner.

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Francisco Jerez <curroje...@riseup.net>

---

 src/mesa/drivers/dri/nouveau/nouveau_gldefs.h| 41 
 src/mesa/drivers/dri/nouveau/nv10_state_raster.c |  2 +-
 src/mesa/drivers/dri/nouveau/nv20_state_raster.c |  2 +-
 3 files changed, 2 insertions(+), 43 deletions(-)

diff --git a/src/mesa/drivers/dri/nouveau/nouveau_gldefs.h 
b/src/mesa/drivers/dri/nouveau/nouveau_gldefs.h
index 7df04c1177..11c3dbd3de 100644
--- a/src/mesa/drivers/dri/nouveau/nouveau_gldefs.h
+++ b/src/mesa/drivers/dri/nouveau/nouveau_gldefs.h
@@ -86,47 +86,6 @@ nvgl_blend_eqn(unsigned eqn)
 }
 
 static inline unsigned
-nvgl_logicop_func(unsigned func)
-{
-   switch (func) {
-   case GL_CLEAR:
-   return 0x1500;
-   case GL_NOR:
-   return 0x1508;
-   case GL_AND_INVERTED:
-   return 0x1504;
-   case GL_COPY_INVERTED:
-   return 0x150c;
-   case GL_AND_REVERSE:
-   return 0x1502;
-   case GL_INVERT:
-   return 0x150a;
-   case GL_XOR:
-   return 0x1506;
-   case GL_NAND:
-   return 0x150e;
-   case GL_AND:
-   return 0x1501;
-   case GL_EQUIV:
-   return 0x1509;
-   case GL_NOOP:
-   return 0x1505;
-   case GL_OR_INVERTED:
-   return 0x150d;
-   case GL_COPY:
-   return 0x1503;
-   case GL_OR_REVERSE:
-   return 0x150b;
-   case GL_OR:
-   return 0x1507;
-   case GL_SET:
-   return 0x150f;
-   default:
-   assert(0);
-   }
-}
-
-static inline unsigned
 nvgl_comparison_op(unsigned op)
 {
switch (op) {
diff --git a/src/mesa/drivers/dri/nouveau/nv10_state_raster.c 
b/src/mesa/drivers/dri/nouveau/nv10_state_raster.c
index d537f7bc22..047f539dbc 100644
--- a/src/mesa/drivers/dri/nouveau/nv10_state_raster.c
+++ b/src/mesa/drivers/dri/nouveau/nv10_state_raster.c
@@ -126,7 +126,7 @@ nv10_emit_logic_opcode(struct gl_context *ctx, int emit)
 
BEGIN_NV04(push, NV11_3D(COLOR_LOGIC_OP_ENABLE), 2);
PUSH_DATAb(push, ctx->Color.ColorLogicOpEnabled);
-   PUSH_DATA (push, nvgl_logicop_func(ctx->Color.LogicOp));
+   PUSH_DATA (push, ctx->Color.LogicOp);
 }
 
 void
diff --git a/src/mesa/drivers/dri/nouveau/nv20_state_raster.c 
b/src/mesa/drivers/dri/nouveau/nv20_state_raster.c
index 4856053aa6..c24c5bbaec 100644
--- a/src/mesa/drivers/dri/nouveau/nv20_state_raster.c
+++ b/src/mesa/drivers/dri/nouveau/nv20_state_raster.c
@@ -38,5 +38,5 @@ nv20_emit_logic_opcode(struct gl_context *ctx, int emit)
 
BEGIN_NV04(push, NV20_3D(COLOR_LOGIC_OP_ENABLE), 2);
PUSH_DATAb(push, ctx->Color.ColorLogicOpEnabled);
-   PUSH_DATA (push, nvgl_logicop_func(ctx->Color.LogicOp));
+   PUSH_DATA (push, ctx->Color.LogicOp);
 }

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Mesa (master): i915: Silence unused parameter warnings

[Ian Romanick]

Module: Mesa
Branch: master
Commit: f5b9c2a6e3a899dfd9f8b8908200a6ea25affa41
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f5b9c2a6e3a899dfd9f8b8908200a6ea25affa41

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Wed Jan  3 13:29:13 2018 -0800

i915: Silence unused parameter warnings

../../SOURCE/master/src/mesa/drivers/dri/i915/intel_fbo.c: In function 
‘intel_alloc_window_storage’:
../../SOURCE/master/src/mesa/drivers/dri/i915/intel_fbo.c:290:48: warning: 
unused parameter ‘ctx’ [-Wunused-parameter]
 intel_alloc_window_storage(struct gl_context * ctx, struct gl_renderbuffer *rb,
^~~
../../SOURCE/master/src/mesa/drivers/dri/i915/intel_fbo.c: In function 
‘intel_nop_alloc_storage’:
../../SOURCE/master/src/mesa/drivers/dri/i915/intel_fbo.c:303:74: warning: 
unused parameter ‘rb’ [-Wunused-parameter]
 intel_nop_alloc_storage(struct gl_context * ctx, struct gl_renderbuffer *rb,
  ^~
../../SOURCE/master/src/mesa/drivers/dri/i915/intel_fbo.c:304:32: warning: 
unused parameter ‘internalFormat’ [-Wunused-parameter]
 GLenum internalFormat, GLuint width, GLuint height)
^~
../../SOURCE/master/src/mesa/drivers/dri/i915/intel_fbo.c:304:55: warning: 
unused parameter ‘width’ [-Wunused-parameter]
 GLenum internalFormat, GLuint width, GLuint height)
   ^
../../SOURCE/master/src/mesa/drivers/dri/i915/intel_fbo.c:304:69: warning: 
unused parameter ‘height’ [-Wunused-parameter]
 GLenum internalFormat, GLuint width, GLuint height)
 ^~
../../SOURCE/master/src/mesa/drivers/dri/i915/intel_fbo.c: In function 
‘intel_bind_framebuffer’:
../../SOURCE/master/src/mesa/drivers/dri/i915/intel_fbo.c:396:47: warning: 
unused parameter ‘fb’ [-Wunused-parameter]
struct gl_framebuffer *fb, struct gl_framebuffer 
*fbread)
   ^~
../../SOURCE/master/src/mesa/drivers/dri/i915/intel_fbo.c:396:74: warning: 
unused parameter ‘fbread’ [-Wunused-parameter]
struct gl_framebuffer *fb, struct gl_framebuffer 
*fbread)
  ^~
../../SOURCE/master/src/mesa/drivers/dri/i915/intel_fbo.c: In function 
‘intel_renderbuffer_update_wrapper’:
../../SOURCE/master/src/mesa/drivers/dri/i915/intel_fbo.c:422:57: warning: 
unused parameter ‘intel’ [-Wunused-parameter]
 intel_renderbuffer_update_wrapper(struct intel_context *intel,
 ^
../../SOURCE/master/src/mesa/drivers/dri/i915/intel_fbo.c: In function 
‘intel_blit_framebuffer_with_blitter’:
../../SOURCE/master/src/mesa/drivers/dri/i915/intel_fbo.c:644:61: warning: 
unused parameter ‘filter’ [-Wunused-parameter]
 GLbitfield mask, GLenum filter)
 ^~

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com>

---

 src/mesa/drivers/dri/i915/intel_fbo.c | 21 +++--
 1 file changed, 11 insertions(+), 10 deletions(-)

diff --git a/src/mesa/drivers/dri/i915/intel_fbo.c 
b/src/mesa/drivers/dri/i915/intel_fbo.c
index 0fb2fcdda0..827a77f722 100644
--- a/src/mesa/drivers/dri/i915/intel_fbo.c
+++ b/src/mesa/drivers/dri/i915/intel_fbo.c
@@ -287,7 +287,7 @@ intel_image_target_renderbuffer_storage(struct gl_context 
*ctx,
  * intel_process_dri2_buffer().
  */
 static GLboolean
-intel_alloc_window_storage(struct gl_context * ctx, struct gl_renderbuffer *rb,
+intel_alloc_window_storage(UNUSED struct gl_context *ctx, struct 
gl_renderbuffer *rb,
GLenum internalFormat, GLuint width, GLuint height)
 {
assert(rb->Name == 0);
@@ -300,8 +300,10 @@ intel_alloc_window_storage(struct gl_context * ctx, struct 
gl_renderbuffer *rb,
 
 /** Dummy function for gl_renderbuffer::AllocStorage() */
 static GLboolean
-intel_nop_alloc_storage(struct gl_context * ctx, struct gl_renderbuffer *rb,
-GLenum internalFormat, GLuint width, GLuint height)
+intel_nop_alloc_storage(UNUSED struct gl_context *ctx,
+UNUSED struct gl_renderbuffer *rb,
+UNUSED GLenum internalFormat,
+UNUSED GLuint width, UNUSED GLuint height)
 {
_mesa_problem(ctx, "intel_op_alloc_storage should never be called.");
return false;
@@ -393,7 +395,8 @@ intel_new_renderbuffer(struct gl_context * ctx, GLuint name)
  */
 static void
 intel_bind_framebuffer(struct gl_context * ctx, GLenum target,
-   struct gl_framebuffer *fb,

Mesa (master): glsl: Remove unnecessary assignments to type

[Ian Romanick]

Module: Mesa
Branch: master
Commit: a170f279581fc0cbdd112a1e01d37e8858895bb3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a170f279581fc0cbdd112a1e01d37e8858895bb3

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Fri Jan  5 17:50:24 2018 -0800

glsl: Remove unnecessary assignments to type

None of these are necessary because result->type is the only thing used
outside the giant switch-statement.

CID: 1230983, 1230984
Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Alejandro Piñeiro <apinhe...@igalia.com>

---

 src/compiler/glsl/ast_to_hir.cpp | 4 
 1 file changed, 4 deletions(-)

diff --git a/src/compiler/glsl/ast_to_hir.cpp b/src/compiler/glsl/ast_to_hir.cpp
index 7abb8199e1..41e74815f3 100644
--- a/src/compiler/glsl/ast_to_hir.cpp
+++ b/src/compiler/glsl/ast_to_hir.cpp
@@ -1589,7 +1589,6 @@ ast_expression::do_hir(exec_list *instructions,
 
   if (rhs_instructions.is_empty()) {
  result = new(ctx) ir_expression(ir_binop_logic_and, op[0], op[1]);
- type = result->type;
   } else {
  ir_variable *const tmp = new(ctx) ir_variable(glsl_type::bool_type,
"and_tmp",
@@ -1611,7 +1610,6 @@ ast_expression::do_hir(exec_list *instructions,
  stmt->else_instructions.push_tail(else_assign);
 
  result = new(ctx) ir_dereference_variable(tmp);
- type = tmp->type;
   }
   break;
}
@@ -1625,7 +1623,6 @@ ast_expression::do_hir(exec_list *instructions,
 
   if (rhs_instructions.is_empty()) {
  result = new(ctx) ir_expression(ir_binop_logic_or, op[0], op[1]);
- type = result->type;
   } else {
  ir_variable *const tmp = new(ctx) ir_variable(glsl_type::bool_type,
"or_tmp",
@@ -1647,7 +1644,6 @@ ast_expression::do_hir(exec_list *instructions,
  stmt->else_instructions.push_tail(else_assign);
 
  result = new(ctx) ir_dereference_variable(tmp);
- type = tmp->type;
   }
   break;
}

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Mesa (master): glsl/linker: Safely generate mask of possible locations

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 336afe7d7a8e066e1286bb93791d5c3d96ccc317
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=336afe7d7a8e066e1286bb93791d5c3d96ccc317

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Fri Jan  5 18:43:32 2018 -0800

glsl/linker: Safely generate mask of possible locations

If MaxAttribs were ever raised to 32, undefined behavior would occur.
We had already gone to the effort (albeit incorrectly) handle this in
one case, so fix them all.

CID: 1369628
Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Alejandro Piñeiro <apinhe...@igalia.com>

---

 src/compiler/glsl/linker.cpp | 9 +
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/src/compiler/glsl/linker.cpp b/src/compiler/glsl/linker.cpp
index d1f10eeecd..86ef5831b7 100644
--- a/src/compiler/glsl/linker.cpp
+++ b/src/compiler/glsl/linker.cpp
@@ -2552,6 +2552,8 @@ find_available_slots(unsigned used_mask, unsigned 
needed_count)
 }
 
 
+#define SAFE_MASK_FROM_INDEX(i) (((i) >= 32) ? ~0 : ((1 << (i)) - 1))
+
 /**
  * Assign locations for either VS inputs or FS outputs
  *
@@ -2582,8 +2584,7 @@ assign_attribute_or_color_locations(void *mem_ctx,
 
/* Mark invalid locations as being used.
 */
-   unsigned used_locations = (max_index >= 32)
-  ? 0 : ~((1 << max_index) - 1);
+   unsigned used_locations = ~SAFE_MASK_FROM_INDEX(max_index);
unsigned double_storage_locations = 0;
 
assert((target_index == MESA_SHADER_VERTEX)
@@ -2936,7 +2937,7 @@ assign_attribute_or_color_locations(void *mem_ctx,
 
if (target_index == MESA_SHADER_VERTEX) {
   unsigned total_attribs_size =
- _mesa_bitcount(used_locations & ((1 << max_index) - 1)) +
+ _mesa_bitcount(used_locations & SAFE_MASK_FROM_INDEX(max_index)) +
  _mesa_bitcount(double_storage_locations);
   if (total_attribs_size > max_index) {
  linker_error(prog,
@@ -3000,7 +3001,7 @@ assign_attribute_or_color_locations(void *mem_ctx,
 */
if (target_index == MESA_SHADER_VERTEX) {
   unsigned total_attribs_size =
- _mesa_bitcount(used_locations & ((1 << max_index) - 1)) +
+ _mesa_bitcount(used_locations & SAFE_MASK_FROM_INDEX(max_index)) +
  _mesa_bitcount(double_storage_locations);
   if (total_attribs_size > max_index) {
  linker_error(prog,

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Mesa (master): nir: Silence unused parameter warnings

[Ian Romanick]

Module: Mesa
Branch: master
Commit: fd2f4f507fe863567045b9a60c7fca71d73fcd8b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fd2f4f507fe863567045b9a60c7fca71d73fcd8b

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Thu Jan  4 15:28:30 2018 -0800

nir: Silence unused parameter warnings

In file included from src/compiler/nir/nir_opt_algebraic.c:4:0:
src/compiler/nir/nir_search_helpers.h: In function ‘is_not_const’:
src/compiler/nir/nir_search_helpers.h:118:59: warning: unused parameter
‘num_components’ [-Wunused-parameter]
 is_not_const(nir_alu_instr *instr, unsigned src, unsigned num_components,
   ^~
src/compiler/nir/nir_search_helpers.h:119:29: warning: unused parameter
‘swizzle ’ [-Wunused-parameter]
  const uint8_t *swizzle)
 ^~~

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Alejandro Piñeiro <apinhe...@igalia.com>

---

 src/compiler/nir/nir_search_helpers.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/compiler/nir/nir_search_helpers.h 
b/src/compiler/nir/nir_search_helpers.h
index 200f2471f8..2e3bd137d6 100644
--- a/src/compiler/nir/nir_search_helpers.h
+++ b/src/compiler/nir/nir_search_helpers.h
@@ -115,8 +115,8 @@ is_zero_to_one(nir_alu_instr *instr, unsigned src, unsigned 
num_components,
 }
 
 static inline bool
-is_not_const(nir_alu_instr *instr, unsigned src, unsigned num_components,
- const uint8_t *swizzle)
+is_not_const(nir_alu_instr *instr, unsigned src, UNUSED unsigned 
num_components,
+ UNUSED const uint8_t *swizzle)
 {
nir_const_value *val = nir_src_as_const_value(instr->src[src].src);
 

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Mesa (master): glsl: Don't handle visit_stop in several ::accept methods

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 702dc43f7eda025103df8adaf9a57067f8f56f87
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=702dc43f7eda025103df8adaf9a57067f8f56f87

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Fri Jan  5 18:19:42 2018 -0800

glsl: Don't handle visit_stop in several ::accept methods

All cases where the result could be non-visit_continue would have
already returned.

CID: 401351, 1224465, 1224466
Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Alejandro Piñeiro <apinhe...@igalia.com>

---

 src/compiler/glsl/ir_hv_accept.cpp | 9 ++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/src/compiler/glsl/ir_hv_accept.cpp 
b/src/compiler/glsl/ir_hv_accept.cpp
index bf3f3d4f04..f04a5b6fd1 100644
--- a/src/compiler/glsl/ir_hv_accept.cpp
+++ b/src/compiler/glsl/ir_hv_accept.cpp
@@ -230,7 +230,8 @@ ir_texture::accept(ir_hierarchical_visitor *v)
   break;
}
 
-   return (s == visit_stop) ? s : v->visit_leave(this);
+   assert(s == visit_continue);
+   return v->visit_leave(this);
 }
 
 
@@ -414,7 +415,8 @@ ir_emit_vertex::accept(ir_hierarchical_visitor *v)
if (s != visit_continue)
   return (s == visit_continue_with_parent) ? visit_continue : s;
 
-   return (s == visit_stop) ? s : v->visit_leave(this);
+   assert(s == visit_continue);
+   return v->visit_leave(this);
 }
 
 
@@ -429,7 +431,8 @@ ir_end_primitive::accept(ir_hierarchical_visitor *v)
if (s != visit_continue)
   return (s == visit_continue_with_parent) ? visit_continue : s;
 
-   return (s == visit_stop) ? s : v->visit_leave(this);
+   assert(s == visit_continue);
+   return v->visit_leave(this);
 }
 
 ir_visitor_status

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Mesa (master): glsl/linker: Mark no locations as invalid instead of marking all locations

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 0c9df36157aca1e725f037e5adc54100aa387bd3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0c9df36157aca1e725f037e5adc54100aa387bd3

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Fri Jan  5 18:40:21 2018 -0800

glsl/linker: Mark no locations as invalid instead of marking all locations

If max_index were ever 32, the linker would have marked all 32
locations as invalid instead of marking none of them as invalid.  It's
a good thing the maximum value actually set by any driver for
MaxAttribs is 16.

Found by inspection while investigating CID 1369628.

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Alejandro Piñeiro <apinhe...@igalia.com>

---

 src/compiler/glsl/linker.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/compiler/glsl/linker.cpp b/src/compiler/glsl/linker.cpp
index 6f9680aae7..d1f10eeecd 100644
--- a/src/compiler/glsl/linker.cpp
+++ b/src/compiler/glsl/linker.cpp
@@ -2583,7 +2583,7 @@ assign_attribute_or_color_locations(void *mem_ctx,
/* Mark invalid locations as being used.
 */
unsigned used_locations = (max_index >= 32)
-  ? ~0 : ~((1 << max_index) - 1);
+  ? 0 : ~((1 << max_index) - 1);
unsigned double_storage_locations = 0;
 
assert((target_index == MESA_SHADER_VERTEX)

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Mesa (master): meta/blit: Don't restore state of the temporary texture

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 9de64d0baa0d4404721aa09fd665252b759a8f28
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9de64d0baa0d4404721aa09fd665252b759a8f28

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Tue Jan 12 17:39:54 2016 -0800

meta/blit: Don't restore state of the temporary texture

It's about to be destroyed, so there's no point.

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Tapani Pälli <tapani.pa...@intel.com>

---

 src/mesa/drivers/common/meta_blit.c | 48 +
 1 file changed, 27 insertions(+), 21 deletions(-)

diff --git a/src/mesa/drivers/common/meta_blit.c 
b/src/mesa/drivers/common/meta_blit.c
index 6322b64696..66714b1ea5 100644
--- a/src/mesa/drivers/common/meta_blit.c
+++ b/src/mesa/drivers/common/meta_blit.c
@@ -841,30 +841,36 @@ _mesa_meta_fb_tex_blit_end(struct gl_context *ctx, GLenum 
target,
struct gl_texture_object *const texObj =
   _mesa_get_current_tex_object(ctx, target);
 
-   /* Restore texture object state, the texture binding will
-* be restored by _mesa_meta_end().
-*
-* If the target restricts values for base level or max level, we assume
-* that the original values were valid.
-*/
-   if (blit->baseLevelSave != texObj->BaseLevel)
-  _mesa_texture_parameteriv(ctx, texObj, GL_TEXTURE_BASE_LEVEL,
->baseLevelSave, false);
-
-   if (blit->maxLevelSave != texObj->MaxLevel)
-  _mesa_texture_parameteriv(ctx, texObj, GL_TEXTURE_MAX_LEVEL,
->maxLevelSave, false);
+   /* Either there is no temporary texture or the temporary texture is bound. 
*/
+   assert(blit->tempTex == 0 || texObj->Name == blit->tempTex);
 
-   /* If ARB_stencil_texturing is not supported, the mode won't have changed. 
*/
-   if (texObj->StencilSampling != blit->stencilSamplingSave) {
-  /* GLint so the compiler won't complain about type signedness mismatch
-   * in the call to _mesa_texture_parameteriv below.
+   /* Restore texture object state, the texture binding will be restored by
+* _mesa_meta_end().  If the texture is the temporary texture that is about
+* to be destroyed, don't bother restoring its state.
+*/
+   if (blit->tempTex == 0) {
+  /* If the target restricts values for base level or max level, we assume
+   * that the original values were valid.
*/
-  const GLint param = blit->stencilSamplingSave ?
- GL_STENCIL_INDEX : GL_DEPTH_COMPONENT;
+  if (blit->baseLevelSave != texObj->BaseLevel)
+ _mesa_texture_parameteriv(ctx, texObj, GL_TEXTURE_BASE_LEVEL,
+   >baseLevelSave, false);
+
+  if (blit->maxLevelSave != texObj->MaxLevel)
+ _mesa_texture_parameteriv(ctx, texObj, GL_TEXTURE_MAX_LEVEL,
+   >maxLevelSave, false);
+
+  /* If ARB_stencil_texturing is not supported, the mode won't have 
changed. */
+  if (texObj->StencilSampling != blit->stencilSamplingSave) {
+ /* GLint so the compiler won't complain about type signedness mismatch
+  * in the call to _mesa_texture_parameteriv below.
+  */
+ const GLint param = blit->stencilSamplingSave ?
+GL_STENCIL_INDEX : GL_DEPTH_COMPONENT;
 
-  _mesa_texture_parameteriv(ctx, texObj, GL_DEPTH_STENCIL_TEXTURE_MODE,
-, false);
+ _mesa_texture_parameteriv(ctx, texObj, GL_DEPTH_STENCIL_TEXTURE_MODE,
+   , false);
+  }
}
 
_mesa_bind_sampler(ctx, ctx->Texture.CurrentUnit, blit->samp_obj_save);

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Mesa (master): meta: Don't pollute the texture namespace

[Ian Romanick]

Module: Mesa
Branch: master
Commit: bd32d4d0671777d9b7d6e3a592abb67563a8063c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bd32d4d0671777d9b7d6e3a592abb67563a8063c

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Tue Jan 19 17:43:05 2016 -0800

meta: Don't pollute the texture namespace

tl;dr: For many types of GL object, we can *NEVER* use the Gen function.

In OpenGL ES (all versions!) and OpenGL compatibility profile,
applications don't have to call Gen functions.  The GL spec is very
clear about how you can mix-and-match generated names and non-generated
names: you can use any name you want for a particular object type until
you call the Gen function for that object type.

Here's the problem scenario:

 - Application calls a meta function that generates a name.  The first
   Gen will probably return 1.

 - Application decides to use the same name for an object of the same
   type without calling Gen.  Many demo programs use names 1, 2, 3,
   etc. without calling Gen.

 - Application calls the meta function again, and the meta function
   replaces the data.  The application's data is lost, and the app
   fails.  Have fun debugging that.

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92363
Reviewed-by: Tapani Pälli <tapani.pa...@intel.com>

---

 src/mesa/drivers/common/meta.c  | 21 ++---
 src/mesa/drivers/common/meta_blit.c | 18 --
 2 files changed, 10 insertions(+), 29 deletions(-)

diff --git a/src/mesa/drivers/common/meta.c b/src/mesa/drivers/common/meta.c
index 55d803fd5b..f4830ec28a 100644
--- a/src/mesa/drivers/common/meta.c
+++ b/src/mesa/drivers/common/meta.c
@@ -98,7 +98,8 @@ meta_clear(struct gl_context *ctx, GLbitfield buffers, bool 
glsl);
 static struct blit_shader *
 choose_blit_shader(GLenum target, struct blit_shader_table *table);
 
-static void cleanup_temp_texture(struct temp_texture *tex);
+static void cleanup_temp_texture(struct gl_context *ctx,
+ struct temp_texture *tex);
 static void meta_glsl_clear_cleanup(struct gl_context *ctx,
 struct clear_state *clear);
 static void meta_decompress_cleanup(struct gl_context *ctx,
@@ -418,7 +419,7 @@ _mesa_meta_free(struct gl_context *ctx)
_mesa_meta_glsl_blit_cleanup(ctx, >Meta->Blit);
meta_glsl_clear_cleanup(ctx, >Meta->Clear);
_mesa_meta_glsl_generate_mipmap_cleanup(ctx, >Meta->Mipmap);
-   cleanup_temp_texture(>Meta->TempTex);
+   cleanup_temp_texture(ctx, >Meta->TempTex);
meta_decompress_cleanup(ctx, >Meta->Decompress);
meta_drawpix_cleanup(ctx, >Meta->DrawPix);
if (old_context)
@@ -1228,8 +1229,6 @@ invert_z(GLfloat normZ)
 static void
 init_temp_texture(struct gl_context *ctx, struct temp_texture *tex)
 {
-   GLuint texObj;
-
/* prefer texture rectangle */
if (_mesa_is_desktop_gl(ctx) && ctx->Extensions.NV_texture_rectangle) {
   tex->Target = GL_TEXTURE_RECTANGLE;
@@ -1245,21 +1244,13 @@ init_temp_texture(struct gl_context *ctx, struct 
temp_texture *tex)
tex->MinSize = 16;  /* 16 x 16 at least */
assert(tex->MaxSize > 0);
 
-   _mesa_CreateTextures(tex->Target, 1, );
-   tex->tex_obj = NULL;
-
-   if (texObj == 0)
-  return;
-
-   tex->tex_obj = _mesa_lookup_texture(ctx, texObj);
+   tex->tex_obj = ctx->Driver.NewTextureObject(ctx, 0xDEADBEEF, tex->Target);
 }
 
 static void
-cleanup_temp_texture(struct temp_texture *tex)
+cleanup_temp_texture(struct gl_context *ctx, struct temp_texture *tex)
 {
-   if (tex->tex_obj == NULL)
- return;
-   _mesa_DeleteTextures(1, >tex_obj->Name);
+   _mesa_delete_nameless_texture(ctx, tex->tex_obj);
tex->tex_obj = NULL;
 }
 
diff --git a/src/mesa/drivers/common/meta_blit.c 
b/src/mesa/drivers/common/meta_blit.c
index 95dfa64c05..496ef285d0 100644
--- a/src/mesa/drivers/common/meta_blit.c
+++ b/src/mesa/drivers/common/meta_blit.c
@@ -879,9 +879,7 @@ _mesa_meta_fb_tex_blit_end(struct gl_context *ctx, GLenum 
target,
_mesa_bind_sampler(ctx, ctx->Texture.CurrentUnit, blit->samp_obj_save);
_mesa_reference_sampler_object(ctx, >samp_obj_save, NULL);
_mesa_reference_sampler_object(ctx, >samp_obj, NULL);
-
-   if (blit->temp_tex_obj)
-  _mesa_DeleteTextures(1, >temp_tex_obj->Name);
+   _mesa_delete_nameless_texture(ctx, blit->temp_tex_obj);
 }
 
 struct gl_texture_object *
@@ -890,20 +888,14 @@ _mesa_meta_texture_object_from_renderbuffer(struct 
gl_context *ctx,
 {
struct gl_texture_image *texImage;
struct gl_texture_object *texObj;
-   GLuint tempTex;
const GLenum target = rb->NumSamples > 1
   ? GL_TEXTURE_2D_MULTISAMPLE : GL_TEXTURE_2D;
 
-   tempTex = 0;
-   _mesa_CreateTextures(target, 1, );
-   if (tempTex == 0)
-  return NULL;
-
-   texObj = _mesa_lookup_texture(ctx, tempTe

Mesa (master): meta/blit: Use _mesa_bind_texture instead of _mesa_BindTexture

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 05f4be96418b23abb3dc23666d5fa200696b1d4e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=05f4be96418b23abb3dc23666d5fa200696b1d4e

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Wed Jan 13 01:25:59 2016 -0800

meta/blit: Use _mesa_bind_texture instead of _mesa_BindTexture

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Tapani Pälli <tapani.pa...@intel.com>

---

 src/mesa/drivers/common/meta_blit.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/drivers/common/meta_blit.c 
b/src/mesa/drivers/common/meta_blit.c
index ee48582944..ea0bd3fead 100644
--- a/src/mesa/drivers/common/meta_blit.c
+++ b/src/mesa/drivers/common/meta_blit.c
@@ -937,7 +937,7 @@ _mesa_meta_setup_sampler(struct gl_context *ctx,
   samp_obj->WrapR);
 
/* Prepare src texture state */
-   _mesa_BindTexture(target, texObj->Name);
+   _mesa_bind_texture(ctx, target, texObj);
if (target != GL_TEXTURE_RECTANGLE_ARB) {
   _mesa_texture_parameteriv(ctx, texObj, GL_TEXTURE_BASE_LEVEL,
 (GLint *) , false);

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Mesa (master): mesa: Fold _mesa_record_error into its only caller

[Ian Romanick]

Module: Mesa
Branch: master
Commit: d80be517750ba5e89432f962175bf996a6f52ce0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d80be517750ba5e89432f962175bf996a6f52ce0

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Tue Dec 12 09:05:46 2017 -0800

mesa: Fold _mesa_record_error into its only caller

Also, the comment on _mesa_record_error was wrong.
dd_function_table::Error was not called because that function does not
exist.

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Tapani Pälli <tapani.pa...@intel.com>

---

 src/mesa/main/context.c | 25 -
 src/mesa/main/context.h |  4 
 src/mesa/main/errors.c  |  3 ++-
 3 files changed, 2 insertions(+), 30 deletions(-)

diff --git a/src/mesa/main/context.c b/src/mesa/main/context.c
index 3fa9f69f88..53261fea51 100644
--- a/src/mesa/main/context.c
+++ b/src/mesa/main/context.c
@@ -1829,31 +1829,6 @@ _mesa_get_dispatch(struct gl_context *ctx)
 /** \name Miscellaneous functions */
 /**/
 /*@{*/
-
-/**
- * Record an error.
- *
- * \param ctx GL context.
- * \param error error code.
- *
- * Records the given error code and call the driver's dd_function_table::Error
- * function if defined.
- *
- * \sa
- * This is called via _mesa_error().
- */
-void
-_mesa_record_error(struct gl_context *ctx, GLenum error)
-{
-   if (!ctx)
-  return;
-
-   if (ctx->ErrorValue == GL_NO_ERROR) {
-  ctx->ErrorValue = error;
-   }
-}
-
-
 /**
  * Flush commands.
  */
diff --git a/src/mesa/main/context.h b/src/mesa/main/context.h
index 309d25cf3b..17fb86c323 100644
--- a/src/mesa/main/context.h
+++ b/src/mesa/main/context.h
@@ -154,10 +154,6 @@ _mesa_set_context_lost_dispatch(struct gl_context *ctx);
 /*@{*/
 
 extern void
-_mesa_record_error( struct gl_context *ctx, GLenum error );
-
-
-extern void
 _mesa_flush(struct gl_context *ctx);
 
 extern void GLAPIENTRY
diff --git a/src/mesa/main/errors.c b/src/mesa/main/errors.c
index 35a2f66c31..a968791362 100644
--- a/src/mesa/main/errors.c
+++ b/src/mesa/main/errors.c
@@ -327,7 +327,8 @@ _mesa_error( struct gl_context *ctx, GLenum error, const 
char *fmtString, ... )
}
 
/* Set the GL context error state for glGetError. */
-   _mesa_record_error(ctx, error);
+   if (ctx->ErrorValue == GL_NO_ERROR)
+  ctx->ErrorValue = error;
 }
 
 void

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Mesa (master): meta/blit: Check the values instead of the target before restoring

[Ian Romanick]

Module: Mesa
Branch: master
Commit: a232df15235ca0e7d4c36762cfb5b51038d71849
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a232df15235ca0e7d4c36762cfb5b51038d71849

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Tue Jan 12 17:37:02 2016 -0800

meta/blit: Check the values instead of the target before restoring

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Tapani Pälli <tapani.pa...@intel.com>

---

 src/mesa/drivers/common/meta_blit.c | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/common/meta_blit.c 
b/src/mesa/drivers/common/meta_blit.c
index 7adad469ac..6322b64696 100644
--- a/src/mesa/drivers/common/meta_blit.c
+++ b/src/mesa/drivers/common/meta_blit.c
@@ -843,13 +843,17 @@ _mesa_meta_fb_tex_blit_end(struct gl_context *ctx, GLenum 
target,
 
/* Restore texture object state, the texture binding will
 * be restored by _mesa_meta_end().
+*
+* If the target restricts values for base level or max level, we assume
+* that the original values were valid.
 */
-   if (target != GL_TEXTURE_RECTANGLE_ARB) {
+   if (blit->baseLevelSave != texObj->BaseLevel)
   _mesa_texture_parameteriv(ctx, texObj, GL_TEXTURE_BASE_LEVEL,
 >baseLevelSave, false);
+
+   if (blit->maxLevelSave != texObj->MaxLevel)
   _mesa_texture_parameteriv(ctx, texObj, GL_TEXTURE_MAX_LEVEL,
 >maxLevelSave, false);
-   }
 
/* If ARB_stencil_texturing is not supported, the mode won't have changed. 
*/
if (texObj->StencilSampling != blit->stencilSamplingSave) {

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Mesa (master): meta: Use _mesa_CreateTextures instead of _mesa_GenTextures

[Ian Romanick]

Module: Mesa
Branch: master
Commit: e0ad314568349e24e5fe44dc6cac8b98a14213d6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e0ad314568349e24e5fe44dc6cac8b98a14213d6

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Tue Jan 19 16:38:20 2016 -0800

meta: Use _mesa_CreateTextures instead of _mesa_GenTextures

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Tapani Pälli <tapani.pa...@intel.com>

---

 src/mesa/drivers/common/meta.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/drivers/common/meta.c b/src/mesa/drivers/common/meta.c
index be490d565b..5bad17d76b 100644
--- a/src/mesa/drivers/common/meta.c
+++ b/src/mesa/drivers/common/meta.c
@@ -1245,7 +1245,7 @@ init_temp_texture(struct gl_context *ctx, struct 
temp_texture *tex)
tex->MinSize = 16;  /* 16 x 16 at least */
assert(tex->MaxSize > 0);
 
-   _mesa_GenTextures(1, );
+   _mesa_CreateTextures(tex->Target, 1, );
tex->tex_obj = NULL;
 
if (texObj == 0)

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Mesa (master): mesa: Add _mesa_bind_texture method

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 594d02892e794b585df31ee75d5c1e2a0e312c25
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=594d02892e794b585df31ee75d5c1e2a0e312c25

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Wed Jan 13 01:20:09 2016 -0800

mesa: Add _mesa_bind_texture method

Light-weight glBindTexture for internal use.

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Tapani Pälli <tapani.pa...@intel.com>

---

 src/mesa/main/texobj.c | 24 +++-
 src/mesa/main/texobj.h |  4 +++-
 2 files changed, 26 insertions(+), 2 deletions(-)

diff --git a/src/mesa/main/texobj.c b/src/mesa/main/texobj.c
index db40598823..5dc5cb8e1a 100644
--- a/src/mesa/main/texobj.c
+++ b/src/mesa/main/texobj.c
@@ -1692,6 +1692,29 @@ bind_texture_object(struct gl_context *ctx, unsigned 
unit,
}
 }
 
+/**
+ * Light-weight bind texture for internal users
+ *
+ * This is really just \c finish_texture_init plus \c bind_texture_object.
+ * This is intended to be used by internal Mesa functions that use
+ * \c _mesa_CreateTexture and need to bind textures (e.g., meta).
+ */
+void
+_mesa_bind_texture(struct gl_context *ctx, GLenum target,
+   struct gl_texture_object *tex_obj)
+{
+   const GLint targetIndex = _mesa_tex_target_to_index(ctx, target);
+
+   assert(targetIndex >= 0 && targetIndex < NUM_TEXTURE_TARGETS);
+
+   if (tex_obj->Target == 0)
+  finish_texture_init(ctx, target, tex_obj, targetIndex);
+
+   assert(tex_obj->Target == target);
+   assert(tex_obj->TargetIndex == targetIndex);
+
+   bind_texture_object(ctx, ctx->Texture.CurrentUnit, tex_obj);
+}
 
 /**
  * Implement glBindTexture().  Do error checking, look-up or create a new
@@ -1764,7 +1787,6 @@ bind_texture(struct gl_context *ctx, GLenum target, 
GLuint texName,
bind_texture_object(ctx, ctx->Texture.CurrentUnit, newTexObj);
 }
 
-
 void GLAPIENTRY
 _mesa_BindTexture_no_error(GLenum target, GLuint texName)
 {
diff --git a/src/mesa/main/texobj.h b/src/mesa/main/texobj.h
index 8dea85303d..f2d78aca0d 100644
--- a/src/mesa/main/texobj.h
+++ b/src/mesa/main/texobj.h
@@ -175,7 +175,9 @@ extern void
 _mesa_delete_nameless_texture(struct gl_context *ctx,
   struct gl_texture_object *texObj);
 
-
+extern void
+_mesa_bind_texture(struct gl_context *ctx, GLenum target,
+   struct gl_texture_object *tex_obj);
 /*@}*/
 
 /**

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Mesa (master): meta/blit: Track source texture using gl_texture_object instead of GL API object handle

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 7609d54e4a891c5d101404c8b291e5f0aebfb926
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7609d54e4a891c5d101404c8b291e5f0aebfb926

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Wed Jan 13 01:22:43 2016 -0800

meta/blit: Track source texture using gl_texture_object instead of GL API 
object handle

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Tapani Pälli <tapani.pa...@intel.com>

---

 src/mesa/drivers/common/meta.h  | 1 +
 src/mesa/drivers/common/meta_blit.c | 1 +
 2 files changed, 2 insertions(+)

diff --git a/src/mesa/drivers/common/meta.h b/src/mesa/drivers/common/meta.h
index a41de8bfea..1b1672e03c 100644
--- a/src/mesa/drivers/common/meta.h
+++ b/src/mesa/drivers/common/meta.h
@@ -312,6 +312,7 @@ struct fb_tex_blit_state
GLint baseLevelSave, maxLevelSave;
struct gl_sampler_object *samp_obj;
struct gl_sampler_object *samp_obj_save;
+   struct gl_texture_object *tex_obj;
GLuint stencilSamplingSave;
GLuint tempTex;
 };
diff --git a/src/mesa/drivers/common/meta_blit.c 
b/src/mesa/drivers/common/meta_blit.c
index d33624d174..27996f9daf 100644
--- a/src/mesa/drivers/common/meta_blit.c
+++ b/src/mesa/drivers/common/meta_blit.c
@@ -694,6 +694,7 @@ blitframebuffer_texture(struct gl_context *ctx,
}
 
target = texObj->Target;
+   fb_tex_blit.tex_obj = texObj;
fb_tex_blit.baseLevelSave = texObj->BaseLevel;
fb_tex_blit.maxLevelSave = texObj->MaxLevel;
fb_tex_blit.stencilSamplingSave = texObj->StencilSampling;

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Mesa (master): Revert "mesa: remove unused _mesa_delete_nameless_texture() "

[Ian Romanick]

Module: Mesa
Branch: master
Commit: e6cef4b0818d014e140f3b17e8603c384066bcf8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e6cef4b0818d014e140f3b17e8603c384066bcf8

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Tue Dec 12 19:41:49 2017 -0800

Revert "mesa: remove unused _mesa_delete_nameless_texture()"

Changes in this series use this function.

This reverts commit 048de9e34a2214371481143cddcaa53f52468c6b.

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Tapani Pälli <tapani.pa...@intel.com>
Cc: Samuel Pitoiset <samuel.pitoi...@gmail.com>
Cc: Timothy Arceri <tarc...@itsqueeze.com>

---

 src/mesa/main/texobj.c | 41 +
 src/mesa/main/texobj.h |  5 +
 2 files changed, 46 insertions(+)

diff --git a/src/mesa/main/texobj.c b/src/mesa/main/texobj.c
index 02c4767788..db40598823 100644
--- a/src/mesa/main/texobj.c
+++ b/src/mesa/main/texobj.c
@@ -1511,6 +1511,47 @@ delete_textures(struct gl_context *ctx, GLsizei n, const 
GLuint *textures)
}
 }
 
+/**
+ * This deletes a texObj without altering the hash table.
+ */
+void
+_mesa_delete_nameless_texture(struct gl_context *ctx,
+  struct gl_texture_object *texObj)
+{
+   if (!texObj)
+  return;
+
+   FLUSH_VERTICES(ctx, 0);
+
+   _mesa_lock_texture(ctx, texObj);
+   {
+  /* Check if texture is bound to any framebuffer objects.
+   * If so, unbind.
+   * See section 4.4.2.3 of GL_EXT_framebuffer_object.
+   */
+  unbind_texobj_from_fbo(ctx, texObj);
+
+  /* Check if this texture is currently bound to any texture units.
+   * If so, unbind it.
+   */
+  unbind_texobj_from_texunits(ctx, texObj);
+
+  /* Check if this texture is currently bound to any shader
+   * image unit.  If so, unbind it.
+   * See section 3.9.X of GL_ARB_shader_image_load_store.
+   */
+  unbind_texobj_from_image_units(ctx, texObj);
+   }
+   _mesa_unlock_texture(ctx, texObj);
+
+   ctx->NewState |= _NEW_TEXTURE_OBJECT;
+
+   /* Unreference the texobj.  If refcount hits zero, the texture
+* will be deleted.
+*/
+   _mesa_reference_texobj(, NULL);
+}
+
 
 void GLAPIENTRY
 _mesa_DeleteTextures_no_error(GLsizei n, const GLuint *textures)
diff --git a/src/mesa/main/texobj.h b/src/mesa/main/texobj.h
index e67ce3ff9d..8dea85303d 100644
--- a/src/mesa/main/texobj.h
+++ b/src/mesa/main/texobj.h
@@ -171,6 +171,11 @@ _mesa_unlock_context_textures( struct gl_context *ctx );
 extern void
 _mesa_lock_context_textures( struct gl_context *ctx );
 
+extern void
+_mesa_delete_nameless_texture(struct gl_context *ctx,
+  struct gl_texture_object *texObj);
+
+
 /*@}*/
 
 /**

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Mesa (master): meta: Track temporary textures using gl_texture_object instead of GL API object handle

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 173e3045a9a176d95be1b4d3fbf7ba0230293842
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=173e3045a9a176d95be1b4d3fbf7ba0230293842

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Thu Jan 14 12:07:02 2016 -0800

meta: Track temporary textures using gl_texture_object instead of GL API object 
handle

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Tapani Pälli <tapani.pa...@intel.com>

---

 src/mesa/drivers/common/meta.c  | 43 ++---
 src/mesa/drivers/common/meta.h  |  2 +-
 src/mesa/drivers/common/meta_blit.c |  8 ---
 3 files changed, 36 insertions(+), 17 deletions(-)

diff --git a/src/mesa/drivers/common/meta.c b/src/mesa/drivers/common/meta.c
index 52d959a710..be490d565b 100644
--- a/src/mesa/drivers/common/meta.c
+++ b/src/mesa/drivers/common/meta.c
@@ -1228,6 +1228,8 @@ invert_z(GLfloat normZ)
 static void
 init_temp_texture(struct gl_context *ctx, struct temp_texture *tex)
 {
+   GLuint texObj;
+
/* prefer texture rectangle */
if (_mesa_is_desktop_gl(ctx) && ctx->Extensions.NV_texture_rectangle) {
   tex->Target = GL_TEXTURE_RECTANGLE;
@@ -1243,16 +1245,22 @@ init_temp_texture(struct gl_context *ctx, struct 
temp_texture *tex)
tex->MinSize = 16;  /* 16 x 16 at least */
assert(tex->MaxSize > 0);
 
-   _mesa_GenTextures(1, >TexObj);
+   _mesa_GenTextures(1, );
+   tex->tex_obj = NULL;
+
+   if (texObj == 0)
+  return;
+
+   tex->tex_obj = _mesa_lookup_texture(ctx, texObj);
 }
 
 static void
 cleanup_temp_texture(struct temp_texture *tex)
 {
-   if (!tex->TexObj)
+   if (tex->tex_obj == NULL)
  return;
-   _mesa_DeleteTextures(1, >TexObj);
-   tex->TexObj = 0;
+   _mesa_DeleteTextures(1, >tex_obj->Name);
+   tex->tex_obj = NULL;
 }
 
 
@@ -1265,7 +1273,7 @@ _mesa_meta_get_temp_texture(struct gl_context *ctx)
 {
struct temp_texture *tex = >Meta->TempTex;
 
-   if (!tex->TexObj) {
+   if (tex->tex_obj == NULL) {
   init_temp_texture(ctx, tex);
}
 
@@ -1283,7 +1291,7 @@ get_bitmap_temp_texture(struct gl_context *ctx)
 {
struct temp_texture *tex = >Meta->Bitmap.Tex;
 
-   if (!tex->TexObj) {
+   if (tex->tex_obj == NULL) {
   init_temp_texture(ctx, tex);
}
 
@@ -1299,7 +1307,7 @@ _mesa_meta_get_temp_depth_texture(struct gl_context *ctx)
 {
struct temp_texture *tex = >Meta->Blit.depthTex;
 
-   if (!tex->TexObj) {
+   if (tex->tex_obj == NULL) {
   init_temp_texture(ctx, tex);
}
 
@@ -1378,9 +1386,11 @@ _mesa_meta_setup_copypix_texture(struct gl_context *ctx,
 {
bool newTex;
 
-   _mesa_BindTexture(tex->Target, tex->TexObj);
-   _mesa_TexParameteri(tex->Target, GL_TEXTURE_MIN_FILTER, filter);
-   _mesa_TexParameteri(tex->Target, GL_TEXTURE_MAG_FILTER, filter);
+   _mesa_BindTexture(tex->Target, tex->tex_obj->Name);
+   _mesa_texture_parameteriv(ctx, tex->tex_obj, GL_TEXTURE_MIN_FILTER,
+ (GLint *) , false);
+   _mesa_texture_parameteriv(ctx, tex->tex_obj, GL_TEXTURE_MAG_FILTER,
+ (GLint *) , false);
_mesa_TexEnvi(GL_TEXTURE_ENV, GL_TEXTURE_ENV_MODE, GL_REPLACE);
 
newTex = _mesa_meta_alloc_texture(tex, width, height, intFormat);
@@ -1422,9 +1432,16 @@ _mesa_meta_setup_drawpix_texture(struct gl_context *ctx,
  GLenum format, GLenum type,
  const GLvoid *pixels)
 {
-   _mesa_BindTexture(tex->Target, tex->TexObj);
-   _mesa_TexParameteri(tex->Target, GL_TEXTURE_MIN_FILTER, GL_NEAREST);
-   _mesa_TexParameteri(tex->Target, GL_TEXTURE_MAG_FILTER, GL_NEAREST);
+   /* GLint so the compiler won't complain about type signedness mismatch in
+* the call to _mesa_texture_parameteriv below.
+*/
+   static const GLint filter = GL_NEAREST;
+
+   _mesa_BindTexture(tex->Target, tex->tex_obj->Name);
+   _mesa_texture_parameteriv(ctx, tex->tex_obj, GL_TEXTURE_MIN_FILTER, ,
+ false);
+   _mesa_texture_parameteriv(ctx, tex->tex_obj, GL_TEXTURE_MAG_FILTER, ,
+ false);
_mesa_TexEnvi(GL_TEXTURE_ENV, GL_TEXTURE_ENV_MODE, GL_REPLACE);
 
/* copy pixel data to texture */
diff --git a/src/mesa/drivers/common/meta.h b/src/mesa/drivers/common/meta.h
index 252b236716..6d5185492d 100644
--- a/src/mesa/drivers/common/meta.h
+++ b/src/mesa/drivers/common/meta.h
@@ -200,7 +200,7 @@ struct save_state
  */
 struct temp_texture
 {
-   GLuint TexObj;
+   struct gl_texture_object *tex_obj;
GLenum Target; /**< GL_TEXTURE_2D or GL_TEXTURE_RECTANGLE */
GLsizei MinSize;   /**< Min texture size to allocate */
GLsizei MaxSize;   /**< Max possible texture size */
diff --git a/src/mesa/drivers/common/meta_blit.c 
b/src/mesa/drivers/common/meta_blit.c
index 0c08109e10

Mesa (master): meta: Use _mesa_bind_texture instead of _mesa_BindTexture

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 5325a34ed78e2ffc3bd3d05fbdb49c8002853a77
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5325a34ed78e2ffc3bd3d05fbdb49c8002853a77

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Tue Jan 19 17:15:08 2016 -0800

meta: Use _mesa_bind_texture instead of _mesa_BindTexture

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Tapani Pälli <tapani.pa...@intel.com>

---

 src/mesa/drivers/common/meta.c | 6 +++---
 src/mesa/drivers/common/meta_generate_mipmap.c | 4 ++--
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/mesa/drivers/common/meta.c b/src/mesa/drivers/common/meta.c
index 5bad17d76b..55d803fd5b 100644
--- a/src/mesa/drivers/common/meta.c
+++ b/src/mesa/drivers/common/meta.c
@@ -1386,7 +1386,7 @@ _mesa_meta_setup_copypix_texture(struct gl_context *ctx,
 {
bool newTex;
 
-   _mesa_BindTexture(tex->Target, tex->tex_obj->Name);
+   _mesa_bind_texture(ctx, tex->Target, tex->tex_obj);
_mesa_texture_parameteriv(ctx, tex->tex_obj, GL_TEXTURE_MIN_FILTER,
  (GLint *) , false);
_mesa_texture_parameteriv(ctx, tex->tex_obj, GL_TEXTURE_MAG_FILTER,
@@ -1437,7 +1437,7 @@ _mesa_meta_setup_drawpix_texture(struct gl_context *ctx,
 */
static const GLint filter = GL_NEAREST;
 
-   _mesa_BindTexture(tex->Target, tex->tex_obj->Name);
+   _mesa_bind_texture(ctx, tex->Target, tex->tex_obj);
_mesa_texture_parameteriv(ctx, tex->tex_obj, GL_TEXTURE_MIN_FILTER, ,
  false);
_mesa_texture_parameteriv(ctx, tex->tex_obj, GL_TEXTURE_MAG_FILTER, ,
@@ -3176,7 +3176,7 @@ decompress_texture_image(struct gl_context *ctx,
_mesa_buffer_sub_data(ctx, decompress->buf_obj, 0, sizeof(verts), verts);
 
/* setup texture state */
-   _mesa_BindTexture(target, texObj->Name);
+   _mesa_bind_texture(ctx, target, texObj);
 
if (!use_glsl_version)
   _mesa_set_enable(ctx, target, GL_TRUE);
diff --git a/src/mesa/drivers/common/meta_generate_mipmap.c 
b/src/mesa/drivers/common/meta_generate_mipmap.c
index 55093e9553..99d0931694 100644
--- a/src/mesa/drivers/common/meta_generate_mipmap.c
+++ b/src/mesa/drivers/common/meta_generate_mipmap.c
@@ -201,10 +201,10 @@ _mesa_meta_GenerateMipmap(struct gl_context *ctx, GLenum 
target,
 
/* We may have been called from glGenerateTextureMipmap with CurrentUnit
 * still set to 0, so we don't know when we can skip binding the texture.
-* Assume that _mesa_BindTexture will be fast if we're rebinding the same
+* Assume that _mesa_bind_texture will be fast if we're rebinding the same
 * texture.
 */
-   _mesa_BindTexture(target, texObj->Name);
+   _mesa_bind_texture(ctx, target, texObj);
 
if (mipmap->samp_obj == NULL) {
   mipmap->samp_obj =  ctx->Driver.NewSamplerObject(ctx, 0xDEADBEEF);

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Mesa (master): meta/blit: Since _mesa_meta_bind_rb_as_tex_image has only one output, return it

[Ian Romanick]

Module: Mesa
Branch: master
Commit: 29a948e06d49ef113014020b74434b1223ba44f2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=29a948e06d49ef113014020b74434b1223ba44f2

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Tue Jan 12 18:21:18 2016 -0800

meta/blit: Since _mesa_meta_bind_rb_as_tex_image has only one output, return it

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Tapani Pälli <tapani.pa...@intel.com>

---

 src/mesa/drivers/common/meta.h  |  5 ++---
 src/mesa/drivers/common/meta_blit.c | 23 ---
 2 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/src/mesa/drivers/common/meta.h b/src/mesa/drivers/common/meta.h
index 128c342fba..a41de8bfea 100644
--- a/src/mesa/drivers/common/meta.h
+++ b/src/mesa/drivers/common/meta.h
@@ -462,10 +462,9 @@ extern void
 _mesa_meta_fb_tex_blit_end(struct gl_context *ctx, GLenum target,
struct fb_tex_blit_state *blit);
 
-extern GLboolean
+extern struct gl_texture_object *
 _mesa_meta_bind_rb_as_tex_image(struct gl_context *ctx,
-struct gl_renderbuffer *rb,
-struct gl_texture_object **texObj);
+struct gl_renderbuffer *rb);
 
 struct gl_sampler_object *
 _mesa_meta_setup_sampler(struct gl_context *ctx,
diff --git a/src/mesa/drivers/common/meta_blit.c 
b/src/mesa/drivers/common/meta_blit.c
index 4e660d2a57..d33624d174 100644
--- a/src/mesa/drivers/common/meta_blit.c
+++ b/src/mesa/drivers/common/meta_blit.c
@@ -640,7 +640,8 @@ blitframebuffer_texture(struct gl_context *ctx,
   srcLevel = readAtt->TextureLevel;
   texObj = readAtt->Texture;
} else if (!readAtt->Texture && ctx->Driver.BindRenderbufferTexImage) {
-  if (!_mesa_meta_bind_rb_as_tex_image(ctx, rb, ))
+  texObj = _mesa_meta_bind_rb_as_tex_image(ctx, rb);
+  if (texObj == NULL)
  return false;
 
   fb_tex_blit.tempTex = texObj->Name;
@@ -882,12 +883,12 @@ _mesa_meta_fb_tex_blit_end(struct gl_context *ctx, GLenum 
target,
   _mesa_DeleteTextures(1, >tempTex);
 }
 
-GLboolean
+struct gl_texture_object *
 _mesa_meta_bind_rb_as_tex_image(struct gl_context *ctx,
-struct gl_renderbuffer *rb,
-struct gl_texture_object **texObj)
+struct gl_renderbuffer *rb)
 {
struct gl_texture_image *texImage;
+   struct gl_texture_object *texObj;
GLuint tempTex;
const GLenum target = rb->NumSamples > 1
   ? GL_TEXTURE_2D_MULTISAMPLE : GL_TEXTURE_2D;
@@ -895,15 +896,15 @@ _mesa_meta_bind_rb_as_tex_image(struct gl_context *ctx,
tempTex = 0;
_mesa_GenTextures(1, );
if (tempTex == 0)
-  return false;
+  return NULL;
 
_mesa_BindTexture(target, tempTex);
-   *texObj = _mesa_lookup_texture(ctx, tempTex);
-   texImage = _mesa_get_tex_image(ctx, *texObj, target, 0);
+   texObj = _mesa_lookup_texture(ctx, tempTex);
+   texImage = _mesa_get_tex_image(ctx, texObj, target, 0);
 
if (!ctx->Driver.BindRenderbufferTexImage(ctx, rb, texImage)) {
   _mesa_DeleteTextures(1, );
-  return false;
+  return NULL;
}
 
if (ctx->Driver.FinishRenderTexture && !rb->NeedsFinishRenderTexture) {
@@ -911,9 +912,9 @@ _mesa_meta_bind_rb_as_tex_image(struct gl_context *ctx,
   ctx->Driver.FinishRenderTexture(ctx, rb);
}
 
-   assert(target == (*texObj)->Target);
-   assert(tempTex == (*texObj)->Name);
-   return true;
+   assert(target == texObj->Target);
+   assert(tempTex == texObj->Name);
+   return texObj;
 }
 
 struct gl_sampler_object *

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Mesa (master): meta/blit: Track temporary texture using gl_texture_object instead of GL API object handle

[Ian Romanick]

Module: Mesa
Branch: master
Commit: c36e3d30169da668e6185fbdd135e1b67297815f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c36e3d30169da668e6185fbdd135e1b67297815f

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Thu Jan 14 11:14:49 2016 -0800

meta/blit: Track temporary texture using gl_texture_object instead of GL API 
object handle

Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Tapani Pälli <tapani.pa...@intel.com>

---

 src/mesa/drivers/common/meta.h  |  2 +-
 src/mesa/drivers/common/meta_blit.c | 12 ++--
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/src/mesa/drivers/common/meta.h b/src/mesa/drivers/common/meta.h
index 863997e9cc..252b236716 100644
--- a/src/mesa/drivers/common/meta.h
+++ b/src/mesa/drivers/common/meta.h
@@ -313,8 +313,8 @@ struct fb_tex_blit_state
struct gl_sampler_object *samp_obj;
struct gl_sampler_object *samp_obj_save;
struct gl_texture_object *tex_obj;
+   struct gl_texture_object *temp_tex_obj;
GLuint stencilSamplingSave;
-   GLuint tempTex;
 };
 
 
diff --git a/src/mesa/drivers/common/meta_blit.c 
b/src/mesa/drivers/common/meta_blit.c
index ea0bd3fead..0c08109e10 100644
--- a/src/mesa/drivers/common/meta_blit.c
+++ b/src/mesa/drivers/common/meta_blit.c
@@ -644,7 +644,7 @@ blitframebuffer_texture(struct gl_context *ctx,
   if (texObj == NULL)
  return false;
 
-  fb_tex_blit.tempTex = texObj->Name;
+  fb_tex_blit.temp_tex_obj = texObj;
 
   srcLevel = 0;
   if (_mesa_is_winsys_fbo(readFb)) {
@@ -834,7 +834,7 @@ _mesa_meta_fb_tex_blit_begin(struct gl_context *ctx,
blit->samp_obj_save = NULL;
_mesa_reference_sampler_object(ctx, >samp_obj_save,
   
ctx->Texture.Unit[ctx->Texture.CurrentUnit].Sampler);
-   blit->tempTex = 0;
+   blit->temp_tex_obj = NULL;
 }
 
 void
@@ -845,13 +845,13 @@ _mesa_meta_fb_tex_blit_end(struct gl_context *ctx, GLenum 
target,
   _mesa_get_current_tex_object(ctx, target);
 
/* Either there is no temporary texture or the temporary texture is bound. 
*/
-   assert(blit->tempTex == 0 || texObj->Name == blit->tempTex);
+   assert(blit->temp_tex_obj == NULL || blit->temp_tex_obj == texObj);
 
/* Restore texture object state, the texture binding will be restored by
 * _mesa_meta_end().  If the texture is the temporary texture that is about
 * to be destroyed, don't bother restoring its state.
 */
-   if (blit->tempTex == 0) {
+   if (blit->temp_tex_obj == NULL) {
   /* If the target restricts values for base level or max level, we assume
* that the original values were valid.
*/
@@ -880,8 +880,8 @@ _mesa_meta_fb_tex_blit_end(struct gl_context *ctx, GLenum 
target,
_mesa_reference_sampler_object(ctx, >samp_obj_save, NULL);
_mesa_reference_sampler_object(ctx, >samp_obj, NULL);
 
-   if (blit->tempTex)
-  _mesa_DeleteTextures(1, >tempTex);
+   if (blit->temp_tex_obj)
+  _mesa_DeleteTextures(1, >temp_tex_obj->Name);
 }
 
 struct gl_texture_object *

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