Module: Mesa Branch: master Commit: 3f074d2f45145dfc75287804ab73fb719521abe2 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3f074d2f45145dfc75287804ab73fb719521abe2
Author: Marek Olšák <marek.ol...@amd.com> Date: Fri Apr 2 14:00:57 2021 -0400 ac/surface: inline and reorder gfx9_surf_flags for better packing Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-pra...@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10083> --- src/amd/common/ac_surface.c | 58 +++++++++++++-------------- src/amd/common/ac_surface.h | 15 ++++--- src/amd/common/ac_surface_modifier_test.c | 6 +-- src/amd/vulkan/radv_device.c | 18 ++++----- src/amd/vulkan/radv_image.c | 22 +++++----- src/amd/vulkan/radv_meta_resolve.c | 4 +- src/gallium/drivers/radeonsi/si_clear.c | 16 ++++---- src/gallium/drivers/radeonsi/si_descriptors.c | 12 +++--- src/gallium/drivers/radeonsi/si_state.c | 24 +++++------ src/gallium/drivers/radeonsi/si_test_blit.c | 4 +- src/gallium/drivers/radeonsi/si_texture.c | 2 +- 11 files changed, 90 insertions(+), 91 deletions(-) diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c index 23ef5381e76..639e1c4fd0e 100644 --- a/src/amd/common/ac_surface.c +++ b/src/amd/common/ac_surface.c @@ -1715,8 +1715,8 @@ static int gfx9_compute_miptree(struct ac_addrlib *addrlib, const struct radeon_ } if (in->flags.stencil) { - surf->u.gfx9.stencil.swizzle_mode = in->swizzleMode; - surf->u.gfx9.stencil.epitch = + surf->u.gfx9.stencil_swizzle_mode = in->swizzleMode; + surf->u.gfx9.stencil_epitch = out.epitchIsHeight ? out.mipChainHeight - 1 : out.mipChainPitch - 1; surf->surf_alignment = MAX2(surf->surf_alignment, out.baseAlign); surf->u.gfx9.stencil_offset = align(surf->surf_size, out.baseAlign); @@ -1724,14 +1724,14 @@ static int gfx9_compute_miptree(struct ac_addrlib *addrlib, const struct radeon_ return 0; } - surf->u.gfx9.surf.swizzle_mode = in->swizzleMode; - surf->u.gfx9.surf.epitch = out.epitchIsHeight ? out.mipChainHeight - 1 : out.mipChainPitch - 1; + surf->u.gfx9.swizzle_mode = in->swizzleMode; + surf->u.gfx9.epitch = out.epitchIsHeight ? out.mipChainHeight - 1 : out.mipChainPitch - 1; /* CMASK fast clear uses these even if FMASK isn't allocated. * FMASK only supports the Z swizzle modes, whose numbers are multiples of 4. */ - surf->u.gfx9.fmask.swizzle_mode = surf->u.gfx9.surf.swizzle_mode & ~0x3; - surf->u.gfx9.fmask.epitch = surf->u.gfx9.surf.epitch; + surf->u.gfx9.fmask_swizzle_mode = surf->u.gfx9.swizzle_mode & ~0x3; + surf->u.gfx9.fmask_epitch = surf->u.gfx9.epitch; surf->u.gfx9.surf_slice_size = out.sliceSize; surf->u.gfx9.surf_pitch = out.pitch; @@ -1740,11 +1740,11 @@ static int gfx9_compute_miptree(struct ac_addrlib *addrlib, const struct radeon_ surf->surf_alignment = out.baseAlign; if (!compressed && surf->blk_w > 1 && out.pitch == out.pixelPitch && - surf->u.gfx9.surf.swizzle_mode == ADDR_SW_LINEAR) { + surf->u.gfx9.swizzle_mode == ADDR_SW_LINEAR) { /* Adjust surf_pitch to be in elements units not in pixels */ surf->u.gfx9.surf_pitch = align(surf->u.gfx9.surf_pitch / surf->blk_w, 256 / surf->bpe); - surf->u.gfx9.surf.epitch = - MAX2(surf->u.gfx9.surf.epitch, surf->u.gfx9.surf_pitch * surf->blk_w - 1); + surf->u.gfx9.epitch = + MAX2(surf->u.gfx9.epitch, surf->u.gfx9.surf_pitch * surf->blk_w - 1); /* The surface is really a surf->bpe bytes per pixel surface even if we * use it as a surf->bpe bytes per element one. * Adjust surf_slice_size and surf_size to reflect the change @@ -2065,8 +2065,8 @@ static int gfx9_compute_miptree(struct ac_addrlib *addrlib, const struct radeon_ if (ret != ADDR_OK) return ret; - surf->u.gfx9.fmask.swizzle_mode = fin.swizzleMode; - surf->u.gfx9.fmask.epitch = fout.pitch - 1; + surf->u.gfx9.fmask_swizzle_mode = fin.swizzleMode; + surf->u.gfx9.fmask_epitch = fout.pitch - 1; surf->fmask_size = fout.fmaskBytes; surf->fmask_alignment = fout.baseAlign; surf->fmask_slice_size = fout.sliceSize; @@ -2124,7 +2124,7 @@ static int gfx9_compute_miptree(struct ac_addrlib *addrlib, const struct radeon_ cin.firstMipIdInTail = out.firstMipIdInTail; if (in->numSamples > 1) - cin.swizzleMode = surf->u.gfx9.fmask.swizzle_mode; + cin.swizzleMode = surf->u.gfx9.fmask_swizzle_mode; else cin.swizzleMode = in->swizzleMode; @@ -2299,7 +2299,7 @@ static int gfx9_compute_surface(struct ac_addrlib *addrlib, const struct radeon_ case RADEON_SURF_MODE_2D: if (surf->flags & RADEON_SURF_IMPORTED || (info->chip_class >= GFX10 && surf->flags & RADEON_SURF_FORCE_SWIZZLE_MODE)) { - AddrSurfInfoIn.swizzleMode = surf->u.gfx9.surf.swizzle_mode; + AddrSurfInfoIn.swizzleMode = surf->u.gfx9.swizzle_mode; break; } @@ -2367,13 +2367,13 @@ static int gfx9_compute_surface(struct ac_addrlib *addrlib, const struct radeon_ return r; } - surf->is_linear = surf->u.gfx9.surf.swizzle_mode == ADDR_SW_LINEAR; + surf->is_linear = surf->u.gfx9.swizzle_mode == ADDR_SW_LINEAR; /* Query whether the surface is displayable. */ /* This is only useful for surfaces that are allocated without SCANOUT. */ BOOL_32 displayable = false; if (!config->is_3d && !config->is_cube) { - r = Addr2IsValidDisplaySwizzleMode(addrlib->handle, surf->u.gfx9.surf.swizzle_mode, + r = Addr2IsValidDisplaySwizzleMode(addrlib->handle, surf->u.gfx9.swizzle_mode, surf->bpe * 8, &displayable); if (r) return r; @@ -2395,7 +2395,7 @@ static int gfx9_compute_surface(struct ac_addrlib *addrlib, const struct radeon_ if (surf->num_dcc_levels) { assert(is_dcc_supported_by_L2(info, surf)); if (AddrSurfInfoIn.flags.color) - assert(is_dcc_supported_by_CB(info, surf->u.gfx9.surf.swizzle_mode)); + assert(is_dcc_supported_by_CB(info, surf->u.gfx9.swizzle_mode)); if (AddrSurfInfoIn.flags.display) { assert(is_dcc_supported_by_DCN(info, config, surf, surf->u.gfx9.dcc.rb_aligned, surf->u.gfx9.dcc.pipe_aligned)); @@ -2425,7 +2425,7 @@ static int gfx9_compute_surface(struct ac_addrlib *addrlib, const struct radeon_ surf->flags &= ~RADEON_SURF_TC_COMPATIBLE_HTILE; } - switch (surf->u.gfx9.surf.swizzle_mode) { + switch (surf->u.gfx9.swizzle_mode) { /* S = standard. */ case ADDR_SW_256B_S: case ADDR_SW_4KB_S: @@ -2621,7 +2621,7 @@ void ac_surface_set_bo_metadata(const struct radeon_info *info, struct radeon_su bool scanout; if (info->chip_class >= GFX9) { - surf->u.gfx9.surf.swizzle_mode = AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE); + surf->u.gfx9.swizzle_mode = AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE); surf->u.gfx9.dcc.independent_64B_blocks = AMDGPU_TILING_GET(tiling_flags, DCC_INDEPENDENT_64B); surf->u.gfx9.dcc.independent_128B_blocks = @@ -2631,7 +2631,7 @@ void ac_surface_set_bo_metadata(const struct radeon_info *info, struct radeon_su surf->u.gfx9.display_dcc_pitch_max = AMDGPU_TILING_GET(tiling_flags, DCC_PITCH_MAX); scanout = AMDGPU_TILING_GET(tiling_flags, SCANOUT); *mode = - surf->u.gfx9.surf.swizzle_mode > 0 ? RADEON_SURF_MODE_2D : RADEON_SURF_MODE_LINEAR_ALIGNED; + surf->u.gfx9.swizzle_mode > 0 ? RADEON_SURF_MODE_2D : RADEON_SURF_MODE_LINEAR_ALIGNED; } else { surf->u.legacy.pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); surf->u.legacy.bankw = 1 << AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); @@ -2668,7 +2668,7 @@ void ac_surface_get_bo_metadata(const struct radeon_info *info, struct radeon_su assert((dcc_offset >> 8) != 0 && (dcc_offset >> 8) < (1 << 24)); } - *tiling_flags |= AMDGPU_TILING_SET(SWIZZLE_MODE, surf->u.gfx9.surf.swizzle_mode); + *tiling_flags |= AMDGPU_TILING_SET(SWIZZLE_MODE, surf->u.gfx9.swizzle_mode); *tiling_flags |= AMDGPU_TILING_SET(DCC_OFFSET_256B, dcc_offset >> 8); *tiling_flags |= AMDGPU_TILING_SET(DCC_PITCH_MAX, surf->u.gfx9.display_dcc_pitch_max); *tiling_flags |= @@ -2859,14 +2859,14 @@ void ac_surface_get_umd_metadata(const struct radeon_info *info, struct radeon_s static uint32_t ac_surface_get_gfx9_pitch_align(struct radeon_surf *surf) { - if (surf->u.gfx9.surf.swizzle_mode == ADDR_SW_LINEAR) + if (surf->u.gfx9.swizzle_mode == ADDR_SW_LINEAR) return 256 / surf->bpe; if (surf->u.gfx9.resource_type == RADEON_RESOURCE_3D) return 1; /* TODO */ unsigned bpe_shift = util_logbase2(surf->bpe) / 2; - switch(surf->u.gfx9.surf.swizzle_mode & ~3) { + switch(surf->u.gfx9.swizzle_mode & ~3) { case ADDR_SW_LINEAR: /* 256B block. */ return 16 >> bpe_shift; case ADDR_SW_4KB_Z: @@ -2907,7 +2907,7 @@ bool ac_surface_override_offset_stride(const struct radeon_info *info, struct ra unsigned slices = surf->surf_size / surf->u.gfx9.surf_slice_size; surf->u.gfx9.surf_pitch = pitch; - surf->u.gfx9.surf.epitch = pitch - 1; + surf->u.gfx9.epitch = pitch - 1; surf->u.gfx9.surf_slice_size = (uint64_t)pitch * surf->u.gfx9.surf_height * surf->bpe; surf->total_size = surf->surf_size = surf->u.gfx9.surf_slice_size * slices; } @@ -3037,8 +3037,8 @@ void ac_surface_print_info(FILE *out, const struct radeon_info *info, "alignment=%u, swmode=%u, epitch=%u, pitch=%u, blk_w=%u, " "blk_h=%u, bpe=%u, flags=0x%"PRIx64"\n", surf->surf_size, surf->u.gfx9.surf_slice_size, - surf->surf_alignment, surf->u.gfx9.surf.swizzle_mode, - surf->u.gfx9.surf.epitch, surf->u.gfx9.surf_pitch, + surf->surf_alignment, surf->u.gfx9.swizzle_mode, + surf->u.gfx9.epitch, surf->u.gfx9.surf_pitch, surf->blk_w, surf->blk_h, surf->bpe, surf->flags); if (surf->fmask_offset) @@ -3046,8 +3046,8 @@ void ac_surface_print_info(FILE *out, const struct radeon_info *info, " FMask: offset=%" PRIu64 ", size=%" PRIu64 ", " "alignment=%u, swmode=%u, epitch=%u\n", surf->fmask_offset, surf->fmask_size, - surf->fmask_alignment, surf->u.gfx9.fmask.swizzle_mode, - surf->u.gfx9.fmask.epitch); + surf->fmask_alignment, surf->u.gfx9.fmask_swizzle_mode, + surf->u.gfx9.fmask_epitch); if (surf->cmask_offset) fprintf(out, @@ -3073,8 +3073,8 @@ void ac_surface_print_info(FILE *out, const struct radeon_info *info, fprintf(out, " Stencil: offset=%" PRIu64 ", swmode=%u, epitch=%u\n", surf->u.gfx9.stencil_offset, - surf->u.gfx9.stencil.swizzle_mode, - surf->u.gfx9.stencil.epitch); + surf->u.gfx9.stencil_swizzle_mode, + surf->u.gfx9.stencil_epitch); } else { fprintf(out, " Surf: size=%" PRIu64 ", alignment=%u, blk_w=%u, blk_h=%u, " diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h index f5a8508d85e..c19cecc8340 100644 --- a/src/amd/common/ac_surface.h +++ b/src/amd/common/ac_surface.h @@ -150,11 +150,6 @@ enum gfx9_resource_type RADEON_RESOURCE_3D, }; -struct gfx9_surf_flags { - uint16_t swizzle_mode; /* tile mode */ - uint16_t epitch; /* (pitch - 1) or (height - 1) */ -}; - struct gfx9_surf_meta_flags { unsigned rb_aligned : 1; /* optimal for RBs */ unsigned pipe_aligned : 1; /* optimal for TC */ @@ -170,9 +165,13 @@ struct gfx9_surf_level { }; struct gfx9_surf_layout { - struct gfx9_surf_flags surf; /* color or depth surface */ - struct gfx9_surf_flags fmask; /* not added to surf_size */ - struct gfx9_surf_flags stencil; /* added to surf_size, use stencil_offset */ + uint8_t swizzle_mode; /* color or depth */ + uint8_t fmask_swizzle_mode; + uint8_t stencil_swizzle_mode; + + uint16_t epitch; /* gfx9 only, not on gfx10 */ + uint16_t fmask_epitch; /* gfx9 only, not on gfx10 */ + uint16_t stencil_epitch; /* gfx9 only, not on gfx10 */ struct gfx9_surf_meta_flags dcc; /* metadata of color */ diff --git a/src/amd/common/ac_surface_modifier_test.c b/src/amd/common/ac_surface_modifier_test.c index 89eece79dcd..3ad38be9136 100644 --- a/src/amd/common/ac_surface_modifier_test.c +++ b/src/amd/common/ac_surface_modifier_test.c @@ -75,7 +75,7 @@ get_addr_from_coord_base(ADDR_HANDLE addrlib, const struct radeon_surf *surf, din.size = sizeof(ADDR2_COMPUTE_DCCINFO_INPUT); dout.size = sizeof(ADDR2_COMPUTE_DCCINFO_OUTPUT); - din.swizzleMode = surf->u.gfx9.surf.swizzle_mode; + din.swizzleMode = surf->u.gfx9.swizzle_mode; din.resourceType = ADDR_RSRC_TEX_2D; din.bpp = util_format_get_blocksizebits(format); din.unalignedWidth = w; @@ -92,7 +92,7 @@ get_addr_from_coord_base(ADDR_HANDLE addrlib, const struct radeon_surf *surf, ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT dcc_input = {0}; dcc_input.size = sizeof(dcc_input); - dcc_input.swizzleMode = surf->u.gfx9.surf.swizzle_mode; + dcc_input.swizzleMode = surf->u.gfx9.swizzle_mode; dcc_input.resourceType = ADDR_RSRC_TEX_2D; dcc_input.bpp = din.bpp; dcc_input.numSlices = 1; @@ -130,7 +130,7 @@ void generate_hash(struct ac_addrlib *ac_addrlib, ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT input = {0}; input.size = sizeof(input); - input.swizzleMode = surf->u.gfx9.surf.swizzle_mode; + input.swizzleMode = surf->u.gfx9.swizzle_mode; input.resourceType = ADDR_RSRC_TEX_2D; input.bpp = util_format_get_blocksizebits(entry->format); input.unalignedWidth = entry->w; diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index 0120a6e05f2..de63bfddec6 100644 --- a/src/amd/vulkan/radv_device.c +++ b/src/amd/vulkan/radv_device.c @@ -6296,8 +6296,8 @@ radv_initialise_color_surface(struct radv_device *device, struct radv_color_buff if (device->physical_device->rad_info.chip_class >= GFX9) { if (device->physical_device->rad_info.chip_class >= GFX10) { - cb->cb_color_attrib3 |= S_028EE0_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) | - S_028EE0_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) | + cb->cb_color_attrib3 |= S_028EE0_COLOR_SW_MODE(surf->u.gfx9.swizzle_mode) | + S_028EE0_FMASK_SW_MODE(surf->u.gfx9.fmask_swizzle_mode) | S_028EE0_CMASK_PIPE_ALIGNED(1) | S_028EE0_DCC_PIPE_ALIGNED(surf->u.gfx9.dcc.pipe_aligned); } else { @@ -6309,11 +6309,11 @@ radv_initialise_color_surface(struct radv_device *device, struct radv_color_buff if (surf->dcc_offset) meta = surf->u.gfx9.dcc; - cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) | - S_028C74_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) | + cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(surf->u.gfx9.swizzle_mode) | + S_028C74_FMASK_SW_MODE(surf->u.gfx9.fmask_swizzle_mode) | S_028C74_RB_ALIGNED(meta.rb_aligned) | S_028C74_PIPE_ALIGNED(meta.pipe_aligned); - cb->cb_mrt_epitch = S_0287A0_EPITCH(surf->u.gfx9.surf.epitch); + cb->cb_mrt_epitch = S_0287A0_EPITCH(surf->u.gfx9.epitch); } cb->cb_color_base += surf->u.gfx9.surf_offset >> 8; @@ -6584,14 +6584,14 @@ radv_initialise_ds_surface(struct radv_device *device, struct radv_ds_buffer_inf ds->db_z_info = S_028038_FORMAT(format) | S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) | - S_028038_SW_MODE(surf->u.gfx9.surf.swizzle_mode) | + S_028038_SW_MODE(surf->u.gfx9.swizzle_mode) | S_028038_MAXMIP(iview->image->info.levels - 1) | S_028038_ZRANGE_PRECISION(1); ds->db_stencil_info = - S_02803C_FORMAT(stencil_format) | S_02803C_SW_MODE(surf->u.gfx9.stencil.swizzle_mode); + S_02803C_FORMAT(stencil_format) | S_02803C_SW_MODE(surf->u.gfx9.stencil_swizzle_mode); if (device->physical_device->rad_info.chip_class == GFX9) { - ds->db_z_info2 = S_028068_EPITCH(surf->u.gfx9.surf.epitch); - ds->db_stencil_info2 = S_02806C_EPITCH(surf->u.gfx9.stencil.epitch); + ds->db_z_info2 = S_028068_EPITCH(surf->u.gfx9.epitch); + ds->db_stencil_info2 = S_02806C_EPITCH(surf->u.gfx9.stencil_epitch); } ds->db_depth_view |= S_028008_MIPID(level); diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c index 94a380d22ed..2811055e82e 100644 --- a/src/amd/vulkan/radv_image.c +++ b/src/amd/vulkan/radv_image.c @@ -379,7 +379,7 @@ radv_patch_surface_from_metadata(struct radv_device *device, struct radeon_surf else surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE); - surface->u.gfx9.surf.swizzle_mode = md->u.gfx9.swizzle_mode; + surface->u.gfx9.swizzle_mode = md->u.gfx9.swizzle_mode; } else { surface->u.legacy.pipe_config = md->u.legacy.pipe_config; surface->u.legacy.bankw = md->u.legacy.bankw; @@ -722,9 +722,9 @@ si_set_mutable_tex_desc_fields(struct radv_device *device, struct radv_image *im state[3] &= C_00A00C_SW_MODE; if (is_stencil) { - state[3] |= S_00A00C_SW_MODE(plane->surface.u.gfx9.stencil.swizzle_mode); + state[3] |= S_00A00C_SW_MODE(plane->surface.u.gfx9.stencil_swizzle_mode); } else { - state[3] |= S_00A00C_SW_MODE(plane->surface.u.gfx9.surf.swizzle_mode); + state[3] |= S_00A00C_SW_MODE(plane->surface.u.gfx9.swizzle_mode); } state[6] &= C_00A018_META_DATA_ADDRESS_LO & C_00A018_META_PIPE_ALIGNED; @@ -751,11 +751,11 @@ si_set_mutable_tex_desc_fields(struct radv_device *device, struct radv_image *im state[4] &= C_008F20_PITCH; if (is_stencil) { - state[3] |= S_008F1C_SW_MODE(plane->surface.u.gfx9.stencil.swizzle_mode); - state[4] |= S_008F20_PITCH(plane->surface.u.gfx9.stencil.epitch); + state[3] |= S_008F1C_SW_MODE(plane->surface.u.gfx9.stencil_swizzle_mode); + state[4] |= S_008F20_PITCH(plane->surface.u.gfx9.stencil_epitch); } else { - state[3] |= S_008F1C_SW_MODE(plane->surface.u.gfx9.surf.swizzle_mode); - state[4] |= S_008F20_PITCH(plane->surface.u.gfx9.surf.epitch); + state[3] |= S_008F1C_SW_MODE(plane->surface.u.gfx9.swizzle_mode); + state[4] |= S_008F20_PITCH(plane->surface.u.gfx9.epitch); } state[5] &= @@ -949,7 +949,7 @@ gfx10_make_texture_descriptor(struct radv_device *device, struct radv_image *ima fmask_state[3] = S_00A00C_DST_SEL_X(V_008F1C_SQ_SEL_X) | S_00A00C_DST_SEL_Y(V_008F1C_SQ_SEL_X) | S_00A00C_DST_SEL_Z(V_008F1C_SQ_SEL_X) | S_00A00C_DST_SEL_W(V_008F1C_SQ_SEL_X) | - S_00A00C_SW_MODE(image->planes[0].surface.u.gfx9.fmask.swizzle_mode) | + S_00A00C_SW_MODE(image->planes[0].surface.u.gfx9.fmask_swizzle_mode) | S_00A00C_TYPE( radv_tex_dim(image->type, view_type, image->info.array_size, 0, false, false)); fmask_state[4] = S_00A010_DEPTH(last_layer) | S_00A010_BASE_ARRAY(first_layer); @@ -1129,9 +1129,9 @@ si_make_texture_descriptor(struct radv_device *device, struct radv_image *image, fmask_state[7] = 0; if (device->physical_device->rad_info.chip_class == GFX9) { - fmask_state[3] |= S_008F1C_SW_MODE(image->planes[0].surface.u.gfx9.fmask.swizzle_mode); + fmask_state[3] |= S_008F1C_SW_MODE(image->planes[0].surface.u.gfx9.fmask_swizzle_mode); fmask_state[4] |= S_008F20_DEPTH(last_layer) | - S_008F20_PITCH(image->planes[0].surface.u.gfx9.fmask.epitch); + S_008F20_PITCH(image->planes[0].surface.u.gfx9.fmask_epitch); fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(1) | S_008F24_META_RB_ALIGNED(1); if (radv_image_is_tc_compat_cmask(image)) { @@ -1214,7 +1214,7 @@ radv_init_metadata(struct radv_device *device, struct radv_image *image, uint64_t dcc_offset = image->offset + (surface->display_dcc_offset ? surface->display_dcc_offset : surface->dcc_offset); - metadata->u.gfx9.swizzle_mode = surface->u.gfx9.surf.swizzle_mode; + metadata->u.gfx9.swizzle_mode = surface->u.gfx9.swizzle_mode; metadata->u.gfx9.dcc_offset_256b = dcc_offset >> 8; metadata->u.gfx9.dcc_pitch_max = surface->u.gfx9.display_dcc_pitch_max; metadata->u.gfx9.dcc_independent_64b_blocks = surface->u.gfx9.dcc.independent_64B_blocks; diff --git a/src/amd/vulkan/radv_meta_resolve.c b/src/amd/vulkan/radv_meta_resolve.c index 3a23f392249..eda31bbedb5 100644 --- a/src/amd/vulkan/radv_meta_resolve.c +++ b/src/amd/vulkan/radv_meta_resolve.c @@ -358,8 +358,8 @@ image_hw_resolve_compat(const struct radv_device *device, struct radv_image *src struct radv_image *dst_image) { if (device->physical_device->rad_info.chip_class >= GFX9) { - return dst_image->planes[0].surface.u.gfx9.surf.swizzle_mode == - src_image->planes[0].surface.u.gfx9.surf.swizzle_mode; + return dst_image->planes[0].surface.u.gfx9.swizzle_mode == + src_image->planes[0].surface.u.gfx9.swizzle_mode; } else { return dst_image->planes[0].surface.micro_tile_mode == src_image->planes[0].surface.micro_tile_mode; diff --git a/src/gallium/drivers/radeonsi/si_clear.c b/src/gallium/drivers/radeonsi/si_clear.c index a74badf1d7c..97c66a27196 100644 --- a/src/gallium/drivers/radeonsi/si_clear.c +++ b/src/gallium/drivers/radeonsi/si_clear.c @@ -329,7 +329,7 @@ static void si_set_optimal_micro_tile_mode(struct si_screen *sscreen, struct si_ if (sscreen->info.chip_class >= GFX9) { /* 4K or larger tiles only. 0 is linear. 1-3 are 256B tiles. */ - assert(tex->surface.u.gfx9.surf.swizzle_mode >= 4); + assert(tex->surface.u.gfx9.swizzle_mode >= 4); /* If you do swizzle_mode % 4, you'll get: * 0 = Depth @@ -339,20 +339,20 @@ static void si_set_optimal_micro_tile_mode(struct si_screen *sscreen, struct si_ * * Depth-sample order isn't allowed: */ - assert(tex->surface.u.gfx9.surf.swizzle_mode % 4 != 0); + assert(tex->surface.u.gfx9.swizzle_mode % 4 != 0); switch (tex->last_msaa_resolve_target_micro_mode) { case RADEON_MICRO_MODE_DISPLAY: - tex->surface.u.gfx9.surf.swizzle_mode &= ~0x3; - tex->surface.u.gfx9.surf.swizzle_mode += 2; /* D */ + tex->surface.u.gfx9.swizzle_mode &= ~0x3; + tex->surface.u.gfx9.swizzle_mode += 2; /* D */ break; case RADEON_MICRO_MODE_STANDARD: - tex->surface.u.gfx9.surf.swizzle_mode &= ~0x3; - tex->surface.u.gfx9.surf.swizzle_mode += 1; /* S */ + tex->surface.u.gfx9.swizzle_mode &= ~0x3; + tex->surface.u.gfx9.swizzle_mode += 1; /* S */ break; case RADEON_MICRO_MODE_RENDER: - tex->surface.u.gfx9.surf.swizzle_mode &= ~0x3; - tex->surface.u.gfx9.surf.swizzle_mode += 3; /* R */ + tex->surface.u.gfx9.swizzle_mode &= ~0x3; + tex->surface.u.gfx9.swizzle_mode += 3; /* R */ break; default: /* depth */ assert(!"unexpected micro mode"); diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c index 0e4dc81de40..2f3642b7d3c 100644 --- a/src/gallium/drivers/radeonsi/si_descriptors.c +++ b/src/gallium/drivers/radeonsi/si_descriptors.c @@ -358,9 +358,9 @@ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen, struct si_texture state[3] &= C_00A00C_SW_MODE; if (is_stencil) { - state[3] |= S_00A00C_SW_MODE(tex->surface.u.gfx9.stencil.swizzle_mode); + state[3] |= S_00A00C_SW_MODE(tex->surface.u.gfx9.stencil_swizzle_mode); } else { - state[3] |= S_00A00C_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode); + state[3] |= S_00A00C_SW_MODE(tex->surface.u.gfx9.swizzle_mode); } state[6] &= C_00A018_META_DATA_ADDRESS_LO & C_00A018_META_PIPE_ALIGNED & @@ -386,10 +386,10 @@ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen, struct si_texture state[4] &= C_008F20_PITCH; if (is_stencil) { - state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.stencil.swizzle_mode); - state[4] |= S_008F20_PITCH(tex->surface.u.gfx9.stencil.epitch); + state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.stencil_swizzle_mode); + state[4] |= S_008F20_PITCH(tex->surface.u.gfx9.stencil_epitch); } else { - uint16_t epitch = tex->surface.u.gfx9.surf.epitch; + uint16_t epitch = tex->surface.u.gfx9.epitch; if (tex->buffer.b.b.format == PIPE_FORMAT_R8G8_R8B8_UNORM && block_width == 1) { /* epitch is patched in ac_surface for sdma/vcn blocks to get @@ -399,7 +399,7 @@ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen, struct si_texture */ epitch = (epitch + 1) / tex->surface.blk_w - 1; } - state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode); + state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.swizzle_mode); state[4] |= S_008F20_PITCH(epitch); } diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 1113e4ad54a..64936b5c52b 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -2466,14 +2466,14 @@ static void si_init_depth_surface(struct si_context *sctx, struct si_surface *su surf->db_stencil_base = (tex->buffer.gpu_address + tex->surface.u.gfx9.stencil_offset) >> 8; z_info = S_028038_FORMAT(format) | S_028038_NUM_SAMPLES(util_logbase2(tex->buffer.b.b.nr_samples)) | - S_028038_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) | + S_028038_SW_MODE(tex->surface.u.gfx9.swizzle_mode) | S_028038_MAXMIP(tex->buffer.b.b.last_level); s_info = S_02803C_FORMAT(stencil_format) | - S_02803C_SW_MODE(tex->surface.u.gfx9.stencil.swizzle_mode); + S_02803C_SW_MODE(tex->surface.u.gfx9.stencil_swizzle_mode); if (sctx->chip_class == GFX9) { - surf->db_z_info2 = S_028068_EPITCH(tex->surface.u.gfx9.surf.epitch); - surf->db_stencil_info2 = S_02806C_EPITCH(tex->surface.u.gfx9.stencil.epitch); + surf->db_z_info2 = S_028068_EPITCH(tex->surface.u.gfx9.epitch); + surf->db_stencil_info2 = S_02806C_EPITCH(tex->surface.u.gfx9.stencil_epitch); } surf->db_depth_view |= S_028008_MIPID(level); surf->db_depth_size = @@ -3051,8 +3051,8 @@ static void si_emit_framebuffer_state(struct si_context *sctx) cb_color_cmask = cb_color_base; cb_color_attrib3 = cb->cb_color_attrib3 | - S_028EE0_COLOR_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) | - S_028EE0_FMASK_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) | + S_028EE0_COLOR_SW_MODE(tex->surface.u.gfx9.swizzle_mode) | + S_028EE0_FMASK_SW_MODE(tex->surface.u.gfx9.fmask_swizzle_mode) | S_028EE0_CMASK_PIPE_ALIGNED(1) | S_028EE0_DCC_PIPE_ALIGNED(tex->surface.u.gfx9.dcc.pipe_aligned); @@ -3096,8 +3096,8 @@ static void si_emit_framebuffer_state(struct si_context *sctx) cb_color_fmask = cb_color_base; if (cb->base.u.tex.level > 0) cb_color_cmask = cb_color_base; - cb_color_attrib |= S_028C74_COLOR_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) | - S_028C74_FMASK_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) | + cb_color_attrib |= S_028C74_COLOR_SW_MODE(tex->surface.u.gfx9.swizzle_mode) | + S_028C74_FMASK_SW_MODE(tex->surface.u.gfx9.fmask_swizzle_mode) | S_028C74_RB_ALIGNED(meta.rb_aligned) | S_028C74_PIPE_ALIGNED(meta.pipe_aligned); @@ -3119,7 +3119,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx) radeon_emit(cs, S_028C98_BASE_256B(cb_dcc_base >> 32)); /* CB_COLOR0_DCC_BASE_EXT */ radeon_set_context_reg(cs, R_0287A0_CB_MRT0_EPITCH + i * 4, - S_0287A0_EPITCH(tex->surface.u.gfx9.surf.epitch)); + S_0287A0_EPITCH(tex->surface.u.gfx9.epitch)); } else { /* Compute mutable surface parameters (GFX6-GFX8). */ const struct legacy_surf_level *level_info = @@ -3891,7 +3891,7 @@ static void gfx10_make_texture_descriptor( fmask_state[3] = S_00A00C_DST_SEL_X(V_008F1C_SQ_SEL_X) | S_00A00C_DST_SEL_Y(V_008F1C_SQ_SEL_X) | S_00A00C_DST_SEL_Z(V_008F1C_SQ_SEL_X) | S_00A00C_DST_SEL_W(V_008F1C_SQ_SEL_X) | - S_00A00C_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) | + S_00A00C_SW_MODE(tex->surface.u.gfx9.fmask_swizzle_mode) | S_00A00C_TYPE(si_tex_dim(screen, tex, target, 0)); fmask_state[4] = S_00A010_DEPTH(last_layer) | S_00A010_BASE_ARRAY(first_layer); fmask_state[5] = 0; @@ -4215,9 +4215,9 @@ static void si_make_texture_descriptor(struct si_screen *screen, struct si_textu fmask_state[7] = 0; if (screen->info.chip_class == GFX9) { - fmask_state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode); + fmask_state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.fmask_swizzle_mode); fmask_state[4] |= - S_008F20_DEPTH(last_layer) | S_008F20_PITCH(tex->surface.u.gfx9.fmask.epitch); + S_008F20_DEPTH(last_layer) | S_008F20_PITCH(tex->surface.u.gfx9.fmask_epitch); fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(1) | S_008F24_META_RB_ALIGNED(1); } else { diff --git a/src/gallium/drivers/radeonsi/si_test_blit.c b/src/gallium/drivers/radeonsi/si_test_blit.c index 7f011e8c4a5..c4351ad5f8a 100644 --- a/src/gallium/drivers/radeonsi/si_test_blit.c +++ b/src/gallium/drivers/radeonsi/si_test_blit.c @@ -121,7 +121,7 @@ static enum pipe_format choose_format() static const char *array_mode_to_string(struct si_screen *sscreen, struct radeon_surf *surf) { if (sscreen->info.chip_class >= GFX9) { - switch (surf->u.gfx9.surf.swizzle_mode) { + switch (surf->u.gfx9.swizzle_mode) { case 0: return " LINEAR"; case 21: @@ -135,7 +135,7 @@ static const char *array_mode_to_string(struct si_screen *sscreen, struct radeon case 27: return "64KB_R_X"; default: - printf("Unhandled swizzle mode = %u\n", surf->u.gfx9.surf.swizzle_mode); + printf("Unhandled swizzle mode = %u\n", surf->u.gfx9.swizzle_mode); return " UNKNOWN"; } } else { diff --git a/src/gallium/drivers/radeonsi/si_texture.c b/src/gallium/drivers/radeonsi/si_texture.c index ce750fe3d90..0980cc55466 100644 --- a/src/gallium/drivers/radeonsi/si_texture.c +++ b/src/gallium/drivers/radeonsi/si_texture.c @@ -256,7 +256,7 @@ static int si_init_surface(struct si_screen *sscreen, struct radeon_surf *surfac flags |= RADEON_SURF_FORCE_SWIZZLE_MODE; if (sscreen->info.chip_class >= GFX10) - surface->u.gfx9.surf.swizzle_mode = ADDR_SW_64KB_R_X; + surface->u.gfx9.swizzle_mode = ADDR_SW_64KB_R_X; } surface->modifier = modifier; _______________________________________________ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
