Module: Mesa Branch: master Commit: f99d5af03b0f97d7a1b7076b2142069770879471 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f99d5af03b0f97d7a1b7076b2142069770879471
Author: Chad Versace <chad.vers...@linux.intel.com> Date: Wed Nov 23 10:06:46 2011 -0800 i965/gen6: Fix GPU hang when using stencil buffer without depth Enable the bit 3DSTATE_DEPTH_BUFFER.Tiled_Surface. From the Sandybridge PRM, Volume 2, Part 1, Section 7.5.5.1.1 3DSTATE_DEPTH_BUFFER, Bit 1.27 Tiled Surface: [DevGT+]: This field must be set to TRUE. Fixes GPU hangs on the following Piglit tests: hiz-stencil-test-fbo-d0-s8 hiz-stencil-read-fbo-d0-s8 Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> Signed-off-by: Chad Versace <chad.vers...@linux.intel.com> --- src/mesa/drivers/dri/i965/brw_misc_state.c | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c index 17da460..cb1405c 100644 --- a/src/mesa/drivers/dri/i965/brw_misc_state.c +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c @@ -278,6 +278,10 @@ static void emit_depthbuffer(struct brw_context *brw) * * [DevGT]: This field must be set to the same value (enabled or * disabled) as Hierarchical Depth Buffer Enable + * + * The tiled bit must be set. From the Sandybridge PRM, Volume 2, Part 1, + * Section 7.5.5.1.1 3DSTATE_DEPTH_BUFFER, Bit 1.27 Tiled Surface: + * [DevGT+]: This field must be set to TRUE. */ struct intel_region *region = stencil_irb->mt->region; @@ -290,6 +294,7 @@ static void emit_depthbuffer(struct brw_context *brw) (1 << 21) | /* separate stencil enable */ (1 << 22) | /* hiz enable */ (BRW_TILEWALK_YMAJOR << 26) | + (1 << 27) | /* tiled surface */ (BRW_SURFACE_2D << 29)); OUT_BATCH(0); OUT_BATCH(((region->width - 1) << 6) | _______________________________________________ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit