Module: Mesa
Branch: master
Commit: b3aa18dfd6fd343b45c1138e545d1130046bcb91
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b3aa18dfd6fd343b45c1138e545d1130046bcb91
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Tue Mar 27 17:56:44 2018 +0100
intel: genxml: add preemption control instructions
Helpful to debug kernel workaround batchbuffers.
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phill...@intel.com>
---
src/intel/genxml/gen10.xml | 7 +++++++
src/intel/genxml/gen11.xml | 7 +++++++
src/intel/genxml/gen8.xml | 6 ++++++
src/intel/genxml/gen9.xml | 6 ++++++
4 files changed, 26 insertions(+)
diff --git a/src/intel/genxml/gen10.xml b/src/intel/genxml/gen10.xml
index aeb9966759..bd914ad10e 100644
--- a/src/intel/genxml/gen10.xml
+++ b/src/intel/genxml/gen10.xml
@@ -2824,6 +2824,13 @@
<field name="MI Command Opcode" start="23" end="28" type="uint"
default="5"/>
</instruction>
+ <instruction name="MI_ARB_ON_OFF" bias="1" length="1">
+ <field name="Command Type" start="29" end="31" type="uint" default="0"/>
+ <field name="MI Command Opcode" start="23" end="28" type="uint"
default="8"/>
+ <field name="Allow Lite Restore" start="1" end="1" type="bool"/>
+ <field name="Arbitration Enable" start="0" end="0" type="bool"
default="1"/>
+ </instruction>
+
<instruction name="MI_ATOMIC" bias="2" length="3">
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint"
default="47"/>
diff --git a/src/intel/genxml/gen11.xml b/src/intel/genxml/gen11.xml
index 6ca0e785ba..cb3212620f 100644
--- a/src/intel/genxml/gen11.xml
+++ b/src/intel/genxml/gen11.xml
@@ -2788,6 +2788,13 @@
<field name="MI Command Opcode" start="23" end="28" type="uint"
default="5"/>
</instruction>
+ <instruction name="MI_ARB_ON_OFF" bias="1" length="1">
+ <field name="Command Type" start="29" end="31" type="uint" default="0"/>
+ <field name="MI Command Opcode" start="23" end="28" type="uint"
default="8"/>
+ <field name="Allow Lite Restore" start="1" end="1" type="bool"/>
+ <field name="Arbitration Enable" start="0" end="0" type="bool"
default="1"/>
+ </instruction>
+
<instruction name="MI_ATOMIC" bias="2" length="3">
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint"
default="47"/>
diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml
index 71626c15cd..28fbdfdf09 100644
--- a/src/intel/genxml/gen8.xml
+++ b/src/intel/genxml/gen8.xml
@@ -2509,6 +2509,12 @@
<field name="MI Command Opcode" start="23" end="28" type="uint"
default="5"/>
</instruction>
+ <instruction name="MI_ARB_ON_OFF" bias="1" length="1">
+ <field name="Command Type" start="29" end="31" type="uint" default="0"/>
+ <field name="MI Command Opcode" start="23" end="28" type="uint"
default="8"/>
+ <field name="Arbitration Enable" start="0" end="0" type="bool"
default="1"/>
+ </instruction>
+
<instruction name="MI_ATOMIC" bias="2" length="3">
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint"
default="47"/>
diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml
index c32f2c3162..0912b6f7fe 100644
--- a/src/intel/genxml/gen9.xml
+++ b/src/intel/genxml/gen9.xml
@@ -2752,6 +2752,12 @@
<field name="MI Command Opcode" start="23" end="28" type="uint"
default="5"/>
</instruction>
+ <instruction name="MI_ARB_ON_OFF" bias="1" length="1">
+ <field name="Command Type" start="29" end="31" type="uint" default="0"/>
+ <field name="MI Command Opcode" start="23" end="28" type="uint"
default="8"/>
+ <field name="Arbitration Enable" start="0" end="0" type="bool"
default="1"/>
+ </instruction>
+
<instruction name="MI_ATOMIC" bias="2" length="3">
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint"
default="47"/>
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