Module: Mesa Branch: master Commit: fd21ee8b52fb9416b16c63fd34c699b1301ce30c URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=fd21ee8b52fb9416b16c63fd34c699b1301ce30c
Author: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> Date: Fri Oct 18 01:21:29 2019 +0200 radv: Fix single stage constant flush with merged shaders. e.g. a VERTEX only flush with tess on Vega should look at the TCS to see which bits are needed. CC: <mesa-sta...@lists.freedesktop.org> Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1953 Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> --- src/amd/vulkan/radv_cmd_buffer.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 1e5e2834135..01a0787dcf5 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -2313,14 +2313,15 @@ radv_flush_constants(struct radv_cmd_buffer *cmd_buffer, return; radv_foreach_stage(stage, stages) { - if (!pipeline->shaders[stage]) + shader = radv_get_shader(pipeline, stage); + if (!shader) continue; - need_push_constants |= pipeline->shaders[stage]->info.loads_push_constants; - need_push_constants |= pipeline->shaders[stage]->info.loads_dynamic_offsets; + need_push_constants |= shader->info.loads_push_constants; + need_push_constants |= shader->info.loads_dynamic_offsets; - uint8_t base = pipeline->shaders[stage]->info.base_inline_push_consts; - uint8_t count = pipeline->shaders[stage]->info.num_inline_push_consts; + uint8_t base = shader->info.base_inline_push_consts; + uint8_t count = shader->info.num_inline_push_consts; radv_emit_inline_push_consts(cmd_buffer, pipeline, stage, AC_UD_INLINE_PUSH_CONSTANTS, _______________________________________________ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
