Module: Mesa
Branch: master
Commit: cf8a11c1baccebbd6dda38da8639e1a6eeccd7c7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cf8a11c1baccebbd6dda38da8639e1a6eeccd7c7
Author: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
Date: Tue Jan 31 21:25:41 2017 +0100
radv: Pass draw index to shader.
Signed-off-by: Bas Nieuwenhuizen <ba...@google.com>
Reviewed-by: Dave Airlie <airl...@redhat.com>
Reviewed-by: Edward O'Callaghan <funfunc...@folklore1984.net>
---
src/amd/vulkan/radv_cmd_buffer.c | 14 +++++++++-----
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 091d970..97c6b63 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -2174,15 +2174,16 @@ void radv_CmdDraw(
RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
radv_cmd_buffer_flush_state(cmd_buffer);
- MAYBE_UNUSED unsigned cdw_max =
radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 9);
+ MAYBE_UNUSED unsigned cdw_max =
radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 10);
struct ac_userdata_info *loc =
radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
AC_UD_VS_BASE_VERTEX_START_INSTANCE);
if (loc->sgpr_idx != -1) {
uint32_t base_reg =
shader_stage_to_user_data_0(MESA_SHADER_VERTEX,
radv_pipeline_has_gs(cmd_buffer->state.pipeline));
- radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx
* 4, 2);
+ radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx
* 4, 3);
radeon_emit(cmd_buffer->cs, firstVertex);
radeon_emit(cmd_buffer->cs, firstInstance);
+ radeon_emit(cmd_buffer->cs, 0);
}
radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
radeon_emit(cmd_buffer->cs, instanceCount);
@@ -2225,7 +2226,7 @@ void radv_CmdDrawIndexed(
radv_cmd_buffer_flush_state(cmd_buffer);
radv_emit_primitive_reset_index(cmd_buffer);
- MAYBE_UNUSED unsigned cdw_max =
radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 14);
+ MAYBE_UNUSED unsigned cdw_max =
radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 15);
radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
@@ -2234,9 +2235,10 @@ void radv_CmdDrawIndexed(
AC_UD_VS_BASE_VERTEX_START_INSTANCE);
if (loc->sgpr_idx != -1) {
uint32_t base_reg =
shader_stage_to_user_data_0(MESA_SHADER_VERTEX,
radv_pipeline_has_gs(cmd_buffer->state.pipeline));
- radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx
* 4, 2);
+ radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx
* 4, 3);
radeon_emit(cmd_buffer->cs, vertexOffset);
radeon_emit(cmd_buffer->cs, firstInstance);
+ radeon_emit(cmd_buffer->cs, 0);
}
radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
radeon_emit(cmd_buffer->cs, instanceCount);
@@ -2298,7 +2300,9 @@ radv_emit_indirect_draw(struct radv_cmd_buffer
*cmd_buffer,
radeon_emit(cs, 0);
radeon_emit(cs, ((base_reg + loc->sgpr_idx * 4) - SI_SH_REG_OFFSET) >>
2);
radeon_emit(cs, ((base_reg + (loc->sgpr_idx + 1) * 4) -
SI_SH_REG_OFFSET) >> 2);
- radeon_emit(cs, S_2C3_COUNT_INDIRECT_ENABLE(!!count_va)); /* draw_index
and count_indirect enable */
+ radeon_emit(cs, (((base_reg + (loc->sgpr_idx + 2) * 4) -
SI_SH_REG_OFFSET) >> 2) |
+ S_2C3_DRAW_INDEX_ENABLE(1) |
+ S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
radeon_emit(cs, draw_count); /* count */
radeon_emit(cs, count_va); /* count_addr */
radeon_emit(cs, count_va >> 32);
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